maint: update deps

Update the new files.json with new resource hashes to allow users to host their own file index and pull from there by adjusting the master in the build. Adding the /data/ folder and files.json to the http fastDL index should pull the correct files

.gitmodules

@@ -1,34 +0,0 @@
-[submodule "deps/minhook"]
-	path = deps/minhook
-	url = https://github.com/TsudaKageyu/minhook.git
-[submodule "deps/asmjit"]
-	path = deps/asmjit
-	url = https://github.com/asmjit/asmjit.git
-[submodule "deps/zlib"]
-	path = deps/zlib
-	url = https://github.com/madler/zlib.git
-	branch = develop
-[submodule "deps/libtomcrypt"]
-	path = deps/libtomcrypt
-	url = https://github.com/libtom/libtomcrypt.git
-	branch = develop
-[submodule "deps/libtommath"]
-	path = deps/libtommath
-	url = https://github.com/libtom/libtommath.git
-	branch = develop
-[submodule "deps/rapidjson"]
-	path = deps/rapidjson
-	url = https://github.com/Tencent/rapidjson.git
-[submodule "deps/udis86"]
-	path = deps/udis86
-	url = https://github.com/vmt/udis86.git
-[submodule "deps/stb"]
-	path = deps/stb
-	url = https://github.com/nothings/stb.git
-[submodule "deps/curl"]
-	path = deps/curl
-	url = https://github.com/curl/curl.git
-	branch = curl-8_4_0
-[submodule "deps/discord-rpc"]
-	path = deps/discord-rpc
-	url = https://github.com/discord/discord-rpc.git

README.md

@@ -1,22 +1,176 @@
-# What is T7x ☄️
+# T7x Client
+
+[![discord](https://img.shields.io/endpoint?url=https://momo5502.com/iw4x/members-badge.php)](https://discord.gg/sKeVmR3)
+[![website](https://img.shields.io/badge/Repackers-_Website-blue)](https://rimmyscorner.com/)
+
+<p align="center">
+  <img src="assets/github/banner-t7x.png?raw=true" />
+</p>
+
+---
+### <u>**IMPORTANT:**</u>
+- ### T7x is cross-compatible with the BOIII Client. You can play the same servers on T7x and BOIII Client, however T7x is newer.
+- ### You are <u>***NOT***</u> required to own Call of Duty: Black Ops 3 in order to play this client. Steam Ownership Verification has been <u>***removed***</u>.
+- ### You can view the changes made from original repository [here](https://git.rimmyscorner.com/Rim/t7x/compare/3e75c64ece0527dec384829dc28dd2c9d3ce5370..HEAD).
+---
+
+## Installer (Easiest)
+1. Download the [T7xInstaller.exe](https://git.rimmyscorner.com/Rim/t7x/releases/download/latest/t7xInstaller.exe) from [Releases](https://git.rimmyscorner.com/Rim/t7x/releases/tag/latest)
+2. Place in *Call of Duty Black Ops III* game directory and run
+    > ***Note**: Run as Administrator if your game installation is in a protected folder*
+
+(*The installer is fully [Open Source](https://git.rimmyscorner.com/Rim/t7x/src/branch/main/installer/t7x_Installer.nsi), created using Nullsoft Scriptable Install System*)
+
+## Download
+Clone the Git repository or download as ZIP.
+
+- <u>**Download Release**</u>
+  - Click on `Releases` at the top and navigate to the latest release
+  - Download `t7x.zip`
+  - If you plan on running a server, download `T7DedicatedConfigs.zip`
+
+- <u>**Download ZIP**</u>
+  - Click on the three dots at the top of the repo ( `◘◘◘` )
+  - Click `Download ZIP`
+
+- <u>**Clone the repository:**</u>
+  - Open a terminal or command prompt.
+  - Run the following command:
+    ```
+    git clone https://git.rimmyscorner.com/Rim/t7x.git
+    ```
+
+## Installation
+
+1. Place the executable `t7x.exe` in your `Call of Duty Black Ops III` directory.
+    > **Note**: Default location is `C:\Program Files (x86)\Steam\steamapps\common\Call of Duty Black Ops III`
+2. Place the `localappdata\t7x` folder into your Local AppData. Place **ONLY** the `t7x` folder in, not `localappdata\t7x`. Your final path should look like `C:\Users\%USERPROFILE%\AppData\Local\t7x\*`
+    > **Note**: On Windows, press `Win + R`, type `%localappdata%`, click ok. Default location is `C:\Users\%USERPROFILE%\AppData\Local`
+3. Launch `t7x.exe`.
+4. You can change your name by modifying `Call of Duty Black Ops III\t7x\players\properties.json` or use `/name PLAYERNAME` in-game.
+5. If running a server, extract `T7xDedicatedConfigs.zip` into your `Call of Duty Black Ops III` folder.
+
+## Repository Contents
+  - T7x Client
+  - All Necessary Files (Including `ext.dll`)
+  - T7x Client Dedicated Server Configuration Files
+  - Python Script to format file hashes for files.json
+  - Localized dependencies
+
+## Added Features
+  - Remove Steam Ownership Verification
+  - Removed T7x Watermark
+  - No Auto-Update (The new ext.dll adds Steam Verification, this is *CRUCIAL* if you do not own the game)
+  - Reverted launcher to the original style
+  - Changed executable icon to match original
+  - Add files.json for users to host their own Master Server/HTTP fastDL Index
+
+## Getting Game Files
+
+- You can download the `Call of Duty Black Ops III` game files [directly](https://gofile.io/d/7pvpEs) or torrent them [here](https://git.rimmyscorner.com/Rim/cod-games-download/releases/download/v1.0.0/t7_full_game.zip).
+- The DLC torrent is included.
+
+## Installing Git (Optional)
+
+If you don't have `git` installed on your machine, follow these steps:
+
+1. Visit the [Git download page](https://git-scm.com/downloads).
+2. Download the appropriate version for your operating system.
+3. Run the installer.
+   - During the installation, you will be asked if you want to add Git to your system's PATH environment variable. Ensure you choose the option to do so. This allows you to use Git from the command line without specifying its full path.
+4. After installation, open a terminal or command prompt and type `git --version` to ensure Git is correctly installed.
+
+## Compile from Source Code
+
+### Prerequisites
+
+- [Visual Studio 2022](https://visualstudio.microsoft.com/thank-you-downloading-visual-studio/?sku=Community&channel=Release&version=VS2022&source=VSLandingPage&cid=2030&passive=false)
+- The required code libraries installed using [VSBuildTools](https://aka.ms/vs/17/release/vs_BuildTools.exe)
+
+### Build
+
+1. Clone the Git repository using `git clone https://git.rimmyscorner.com/Rim/t7x.git` (It is recommended to clone, however you can `Download ZIP` as all submodules have been localized).
+2. Run `generate.bat` to initialize the submodules and build the VS `.sln` file.
+3. Open the project in Visual Studio, change the top drop down lists to `Release`, `x64`. You can also modify (or leave same) the Visual Studio edition/path in the `build.bat` file and build the solution via the batch script.
+4. Build the application.
+<br>
+
+# T7 Server Config
+Config for T7 Dedicated Servers for use with the T7x Client.
+
+## How to use
+1. Download the BO3 Unranked Dedicated Server via Steam (It's located in the "Tools" section in your steam library.)
+2. Add t7x.exe to the `Call of Duty Black Ops 3` folder.
+3. Download this repository and extract startup batch files as well as the t7x and zone folder to the UnrankedServer Folder
+4. Edit the config(s) in `/zone/` to your liking.
+5. (Optional) Edit your game rules under `Call of Duty Black Ops 3/t7x/gamesettings/mp`.
+6. Port forward UDP 27017.
+7. Start the Server using T7x_MP_Server.bat or T7x_ZM_Server.bat
+
+## Additional Steps required for hosting Zombies Dedicated Servers
+As of right now you need to take additional Steps to host Zombies Servers.
+For Zombie Dedis to work they need to have the Zombies Maps and common FastFiles, these do not come with the UnrankedServer Files. This means you need to copy those over from your installed BO3 game folder.
+
+Copy common fastfiles that is needed for zombies.
+
+```
+zone/en_zm_patch.ff
+zone/en_zm_common.ff
+zone/zm_patch.ff
+zone/zm_common.fd
+zone/zm_common.ff
+zone/zm_levelcommon.ff
+```
+
+Now for the map. Shadows of Evil is zm_zod. 
+
+```
+zone/en_zm_zod.ff
+zone/en_zm_zod_patch.ff
+zone/zm_zod.ff
+zone/zm_zod_patch.ff
+```
+
+from your BO3 Game folder into the UnrankedServer's ```zone``` Folder. Do the same with the FastFiles of the Maps you want to host on the Server, you do not need to copy the .xpak files, those hold Textures and Sounds which the Server doesn't need. You can use the zm_server.cfg as a short name references if you want to grab the others.
+
+You are now ready to start the Server using `T7x_ZM_Server.bat`. If the server still instantly closes while opening the `T7x_ZM_Server.bat` or `T7x_CP_Server.bat`. Check the console_mp.log from identities\dedicatedpc\ folder. Scroll down until you see "Could not find zone: xxxx".
+
+## Disclaimer
+
+This software has been created purely for the purposes of
+academic research. It is not intended to be used to attack
+other systems. Project maintainers are not responsible or
+liable for misuse of the software. Use responsibly.
+
+## Credits:
+
+- [Dss0](https://github.com/Dss0/t7-server-config) - Dedicated Server Files & Tutorial
+- [momo5502](https://github.com/momo5502) - Arxan/Steam research, original developer
+- [AlterWare](https://alterware.dev/) - T7x project revival and rebranding
+
+## ***End README***
+
+# <u>Legacy README.md</u>
+
+### What is T7x ☄️
 
 T7x is a [discontinued][notice-link] game modification for Call of Duty: Black Ops 3.  
-The Steam version of Black Ops 3 is required to be owned and installed for T7x to work. You can get it from <a href="https://store.steampowered.com/app/311210/Call_of_Duty_Black_Ops_III/">here</a>.
+~~The Steam version of Black Ops 3 is required to be owned and installed for T7x to work. You can get it from <a href="https://store.steampowered.com/app/311210/Call_of_Duty_Black_Ops_III/">here</a>.~~
 
-## Build
+### Build
 
 You can learn more about how you can build this project using the MSVC compiler by reading [build.md][build-link]
 
-## Writeups & Articles
+### Writeups & Articles
 
 - <a href="https://momo5502.com/posts/2022-11-17-reverse-engineering-integrity-checks-in-black-ops-3/">Reverse engineering integrity checks in Black Ops 3</a>
 - <a href="https://techcrunch.com/2023/02/28/gamers-are-fixing-a-video-game-taken-over-by-hackers/">Gamers are fixing a video game ‘taken over’ by hackers</a>
 
-## Credits
+### Credits
 
 - Thanks to <a href="https://github.com/shiversoftdev">@shiversoftdev</a> for providing the fixes from his <a href="https://github.com/shiversoftdev/t7patch">community patch</a>
 
-## Disclaimer
+### Disclaimer
 
 This software has been created purely for the purposes of
 academic research. It is not intended to be used to harm

build.bat

@@ -0,0 +1,5 @@
+@echo off
+
+"C:\Program Files\Microsoft Visual Studio\2022\Community\MSBuild\Current\Bin\msbuild.exe" build\t7x.sln /p:Configuration=Release /p:Platform=x64
+
+pause

build.md

@@ -1,7 +1,11 @@
+## Prerequisites
+
+- [Visual Studio 2022](https://visualstudio.microsoft.com/thank-you-downloading-visual-studio/?sku=Community&channel=Release&version=VS2022&source=VSLandingPage&cid=2030&passive=false)
+- The required code libraries installed using [VSBuildTools](https://aka.ms/vs/17/release/vs_BuildTools.exe)
+
 ## Build
-- Install [Git](https://git-scm.com), the distributed revision control system and add it to your system PATH
-- Install [*Premake5*](https://premake.github.io) and add it to your system PATH
-- [Clone](https://docs.github.com/en/repositories/creating-and-managing-repositories/cloning-a-repository) this repository
-- Update the git submodules using ``git submodule update --init --recursive``
-- Run Premake with with the following command ``premake5 vs2022``
-- You may now open ``build/t7x.sln`` with Visual Studio and proceed with building ⚒️
+
+1. Clone the Git repository using `git clone https://git.rimmyscorner.com/Parasyn/t7x.git` (It is recommended to clone, however you can `Download ZIP` as all submodules have been localized).
+2. Run `generate.bat` to initialize the submodules and build the VS .sln file.
+3. Open the project in Visual Studio, change the top drop down lists to `Release`, `x64`. You can also modify (or leave same) the Visual Studio edition/path in the `build.bat` file and build the solution via the batch script.
+4. Build the application.

cfg/README.md

@@ -0,0 +1,40 @@
+# T7 Server Config
+Config for T7 Dedicated Servers for use with the T7x Client.
+
+# How to use
+1. Download the BO3 Unranked Dedicated Server via Steam (It's located in the "Tools" section in your steam library.)
+2. Open the Unranked Server folder in windows explorer (if you own BO3 on Steam and have it installed it will be in your BO3 Game Folder)
+3. Add t7x.exe to the UnrankedServer Folder
+4. Download this repository and extract startup batch files as well as the t7x and zone folder to the UnrankedServer Folder
+5. Edit the config(s) in /zone to your liking.
+6. (Optional) Edit your game rules under boiii/gamesettings/mp.
+6. Port forward UDP 27017.
+7. Start the Server using BOIII_MP_Server.bat or T7x_ZM_Server.bat
+
+# Additional Steps required for hosting Zombies Dedicated Servers
+As of right now you need to take additional Steps to host Zombies Servers.
+For Zombie Dedis to work they need to have the Zombies Maps and common FastFiles, these do not come with the UnrankedServer Files. This means you need to copy those over from your installed BO3 game folder.
+
+Copy common fastfiles that is needed for zombies.
+
+```
+zone/en_zm_patch.ff
+zone/en_zm_common.ff
+zone/zm_patch.ff
+zone/zm_common.fd
+zone/zm_common.ff
+zone/zm_levelcommon.ff
+```
+
+Now for the map. Shadows of Evil is zm_zod. 
+
+```
+zone/en_zm_zod.ff
+zone/en_zm_zod_patch.ff
+zone/zm_zod.ff
+zone/zm_zod_patch.ff
+```
+
+from your BO3 Game folder into the UnrankedServer's ```zone``` Folder. Do the same with the FastFiles of the Maps you want to host on the Server, you do not need to copy the .xpak files, those hold Textures and Sounds which the Server doesn't need. You can use the zm_server.cfg as a short name references if you want to grab the others.
+
+You are now ready to start the Server using T7x_ZM_Server.bat. If the server still instantly closes while opening the T7x_ZM_Server.bat or T7x_CP_Server.bat. Check the console_mp.log from identities\dedicatedpc\ folder. Scroll down until you see "Could not find zone: xxxx".

cfg/T7x_CP_Server.bat

@@ -0,0 +1,36 @@
+@echo off
+::///////////////////////////////////////////////////////////////////////
+::///  	      T7x Dedicated Server Configuration start-up file        ///
+::///////////////////////////////////////////////////////////////////////
+:://                                                                   //
+:://                    Your Game Server Port.	       	       	       //
+:://            Make sure you Port Forward both UDP & TCP              //
+::///////////////////////////////////////////////////////////////////////
+
+set GamePort=27017
+
+::///////////////////////////////////////////////////////////////////////
+::// Below edits are optional unless you run multiable servers or mods.//
+::///////////////////////////////////////////////////////////////////////
+:://               Load a mod on your server                           //
+:://	           Example: ModfolderName=mods/bots                    //
+:://                                                                   //
+:://               UNLOAD a mod on your server                         //
+:://               Example: ModfolderName=                             //
+::///////////////////////////////////////////////////////////////////////
+
+set ModFolderName=
+
+::///////////////////////////////////////////////////////////////////////
+::// 	Your edited server.cfg in the "zone" folder goes here...       //
+:://	This is were you edit your hostname, rcon, inactivity, etc     //
+:://                          (Optional)                               //
+::///////////////////////////////////////////////////////////////////////
+
+set ServerFilename=server_cp.cfg
+
+::///////////////////////////////////////////////////////////////////////
+:://DONE!! WARNING! Don't mess with anything below this line. SEROUSLY!//
+::///////////////////////////////////////////////////////////////////////
+
+start t7x.exe -dedicated +set fs_game "%ModFolderName%" +set net_port "%GamePort%" +set logfile 2 +exec %ServerFilename%

cfg/T7x_MP_Server.bat

@@ -0,0 +1,36 @@
+@echo off
+::///////////////////////////////////////////////////////////////////////
+::///  	      T7x Dedicated Server Configuration start-up file        ///
+::///////////////////////////////////////////////////////////////////////
+:://                                                                   //
+:://                    Your Game Server Port.	       	       	       //
+:://            Make sure you Port Forward both UDP & TCP              //
+::///////////////////////////////////////////////////////////////////////
+
+set GamePort=27017
+
+::///////////////////////////////////////////////////////////////////////
+::// Below edits are optional unless you run multiable servers or mods.//
+::///////////////////////////////////////////////////////////////////////
+:://               Load a mod on your server                           //
+:://	           Example: ModfolderName=mods/bots                    //
+:://                                                                   //
+:://               UNLOAD a mod on your server                         //
+:://               Example: ModfolderName=                             //
+::///////////////////////////////////////////////////////////////////////
+
+set ModFolderName=
+
+::///////////////////////////////////////////////////////////////////////
+::// 	Your edited server.cfg in the "zone" folder goes here...       //
+:://	This is were you edit your hostname, rcon, inactivity, etc     //
+:://                          (Optional)                               //
+::///////////////////////////////////////////////////////////////////////
+
+set ServerFilename=server.cfg
+
+::///////////////////////////////////////////////////////////////////////
+:://DONE!! WARNING! Don't mess with anything below this line. SEROUSLY!//
+::///////////////////////////////////////////////////////////////////////
+
+start t7x.exe -dedicated +set fs_game "%ModFolderName%" +set net_port "%GamePort%" +set logfile 2 +exec %ServerFilename%

cfg/T7x_ZM_Server.bat

@@ -0,0 +1,36 @@
+@echo off
+::///////////////////////////////////////////////////////////////////////
+::///  	      T7x Dedicated Server Configuration start-up file        ///
+::///////////////////////////////////////////////////////////////////////
+:://                                                                   //
+:://                    Your Game Server Port.	       	       	       //
+:://            Make sure you Port Forward both UDP & TCP              //
+::///////////////////////////////////////////////////////////////////////
+
+set GamePort=27017
+
+::///////////////////////////////////////////////////////////////////////
+::// Below edits are optional unless you run multiable servers or mods.//
+::///////////////////////////////////////////////////////////////////////
+:://               Load a mod on your server                           //
+:://	           Example: ModfolderName=mods/bots                    //
+:://                                                                   //
+:://               UNLOAD a mod on your server                         //
+:://               Example: ModfolderName=                             //
+::///////////////////////////////////////////////////////////////////////
+
+set ModFolderName=
+
+::///////////////////////////////////////////////////////////////////////
+::// 	Your edited server.cfg in the "zone" folder goes here...       //
+:://	This is were you edit your hostname, rcon, inactivity, etc     //
+:://                          (Optional)                               //
+::///////////////////////////////////////////////////////////////////////
+
+set ServerFilename=server_zm.cfg
+
+::///////////////////////////////////////////////////////////////////////
+:://DONE!! WARNING! Don't mess with anything below this line. SEROUSLY!//
+::///////////////////////////////////////////////////////////////////////
+
+start t7x.exe -dedicated +set fs_game "%ModFolderName%" +set net_port "%GamePort%"  +set logfile 2 +exec %ServerFilename%

cfg/t7x/bots.txt

@@ -0,0 +1,19 @@
+Snake,BOT
+Diamante,BOT
+Dss0,BOT
+st0rm,BOT
+Louvenarde,BOT
+serious,BOT
+JariK,BOT
+xensik,BOT
+Jebus3211,BOT
+FragsAreUs,BOT
+Fry,BOT
+X3RX35,BOT
+Brent,BOT
+Joel,BOT
+RektInator,BOT
+Doctor,BOT
+Jimbo,BOT
+Laupetin,BOT
+

cfg/t7x/gamesettings/cp/gamesettings_coop.cfg

@@ -0,0 +1,16 @@
+gametype_setting     scorelimit                              7500
+gametype_setting     timelimit                               10
+gametype_setting     prematchperiod                          0
+gametype_setting     roundlimit                              1
+gametype_setting     playerNumlives                          0
+gametype_setting     playerrespawndelay                      0
+gametype_setting     waverespawndelay                        0
+gametype_setting     disableweapondrop                       1
+gametype_setting     allowAnnouncer                          0
+gametype_setting     startRound                              1
+gametype_setting     magic                                   1
+gametype_setting     headshotsonly                           0
+gametype_setting     allowdogs                               0
+gametype_setting     disableClassSelection                   0
+gametype_setting     disableCompass                          1
+gametype_setting     characterCustomization                  0

cfg/t7x/gamesettings/cp/gamesettings_cpzm.cfg

@@ -0,0 +1,16 @@
+gametype_setting     scorelimit                              7500
+gametype_setting     timelimit                               10
+gametype_setting     prematchperiod                          0
+gametype_setting     roundlimit                              1
+gametype_setting     playerNumlives                          0
+gametype_setting     playerrespawndelay                      0
+gametype_setting     waverespawndelay                        0
+gametype_setting     disableweapondrop                       1
+gametype_setting     allowAnnouncer                          0
+gametype_setting     startRound                              1
+gametype_setting     magic                                   1
+gametype_setting     headshotsonly                           0
+gametype_setting     allowdogs                               0
+gametype_setting     disableClassSelection                   1
+gametype_setting     disableCompass                          1
+gametype_setting     characterCustomization                  0

cfg/t7x/gamesettings/cp/gamesettings_default.cfg

@@ -0,0 +1,108 @@
+gametype_setting     allowAnnouncer                          1
+gametype_setting     allowBattleChatter                      1
+gametype_setting     allowFinalKillcam                       1
+gametype_setting     allowHitMarkers                         2
+gametype_setting     allowInGameTeamChange                   0
+gametype_setting     allowKillcam                            1
+gametype_setting     allowSpectating                         0
+gametype_setting     autoDestroyTime                         0
+gametype_setting     autoTeamBalance                         0
+gametype_setting     bombTimer                               0
+gametype_setting     bulletDamageScalar                      1.0
+gametype_setting     captureTime                             10
+gametype_setting     crateCaptureTime                        3
+gametype_setting     cumulativeRoundScores                   0
+gametype_setting     deathPointLoss                          0
+gametype_setting     defuseTime                              0
+gametype_setting     delayPlayer                             0
+gametype_setting     destroyTime                             0
+gametype_setting     disableAmbientFx                        0
+gametype_setting     disableAttachments                      0
+gametype_setting     disableCAC                              0
+gametype_setting     disableContracts                        0
+gametype_setting     disableTacInsert                        0
+gametype_setting     disableweapondrop                       1
+gametype_setting     disallowaimslowdown                     0
+gametype_setting     disallowprone                           0
+gametype_setting     enemyCarrierVisible                     0
+gametype_setting     extraTime                               0
+gametype_setting     flagCaptureGracePeriod                  0
+gametype_setting     flagDecayTime                           0
+gametype_setting     flagRespawnTime                         0
+gametype_setting     forceRadar                              0
+gametype_setting     friendlyfiretype                        0
+gametype_setting     hardcoremode                            0
+gametype_setting     hotPotato                               0
+gametype_setting     idleFlagDecay                           0
+gametype_setting     idleFlagResetTime                       0
+gametype_setting     inactivityKick                          0
+gametype_setting     kothMode                                0
+gametype_setting     leaderBonus                             0
+gametype_setting     loadoutKillstreaksEnabled               0
+gametype_setting     maxAllocation                           10
+gametype_setting     maxObjectiveEventsPerMinute             0
+gametype_setting     maxPlayerDefensive                      0
+gametype_setting     maxPlayerEventsPerMinute                0
+gametype_setting     maxPlayerOffensive                      0
+gametype_setting     multiBomb                               0
+gametype_setting     objectivePingTime                       6
+gametype_setting     objectiveSpawnTime                      0
+gametype_setting     onlyHeadshots                           0
+gametype_setting     perksEnabled                            0
+gametype_setting     plantTime                               0
+gametype_setting     playerForceRespawn                      1
+gametype_setting     playerHealthRegenTime                   5
+gametype_setting     playerKillsMax                          0
+gametype_setting     playerMaxHealth                         100
+gametype_setting     playerNumlives                          0
+gametype_setting     playerObjectiveHeldRespawnDelay         0
+gametype_setting     playerQueuedRespawn                     0
+gametype_setting     playerRespawnDelay                      0
+gametype_setting     playerSprintTime                        4
+gametype_setting     pregameAlwaysShowCACEdit                1
+gametype_setting     pregameAlwaysShowStreakEdit             1
+gametype_setting     pregameCACModifyTime                    0
+gametype_setting     pregameDraftEnabled                     0
+gametype_setting     pregameDraftRoundTime                   0
+gametype_setting     pregameItemMaxVotes                     0
+gametype_setting     pregameItemVoteEnabled                  0
+gametype_setting     pregameItemVoteRoundTime                0
+gametype_setting     pregamePositionShuffleMethod            0
+gametype_setting     pregamePositionSortType                 0
+gametype_setting     pregamePostRoundTime                    0
+gametype_setting     pregamePostStageTime                    0
+gametype_setting     pregamePreStageTime                     0
+gametype_setting     pregameScorestreakModifyTime            0
+gametype_setting     randomObjectiveLocations                0
+gametype_setting     roundlimit                              1
+gametype_setting     roundStartExplosiveDelay                5
+gametype_setting     roundStartKillstreakDelay               0
+gametype_setting     roundswitch                             1  // rounds between switching teams
+gametype_setting     roundwinlimit                           0
+gametype_setting     scoreHeroPowerGainFactor                1.0
+gametype_setting     scoreHeroPowerTimeFactor                1.0
+gametype_setting     scorelimit                              100
+gametype_setting     spectateType                            1
+gametype_setting     teamCount                               1
+gametype_setting     teamKillPenalty                         2
+gametype_setting     teamKillPointLoss                       0
+gametype_setting     teamKillPunishCount                     3
+gametype_setting     teamKillReducedPenalty                  0.25
+gametype_setting     teamKillScore                           4
+gametype_setting     teamKillSpawnDelay                      20
+gametype_setting     timelimit                               10
+gametype_setting     totalKillsMax                           0
+gametype_setting     vehiclesEnabled                         1
+gametype_setting     vehiclesTimed                           1
+gametype_setting     voipDeadChatWithDead                    0
+gametype_setting     voipDeadChatWithTeam                    1
+gametype_setting     voipDeadHearAllLiving                   0
+gametype_setting     voipDeadHearKiller                      0
+gametype_setting     voipDeadHearTeamLiving                  1
+gametype_setting     voipEveryoneHearsEveryone               0
+gametype_setting     voipKillersHearVictim                   1
+gametype_setting     waverespawndelay                        0
+gametype_setting     zmDifficulty                            1
+
+// player movement
+gametype_setting     trm_maxHeight                           144.0

cfg/t7x/gamesettings/cp/gamesettings_doa.cfg

@@ -0,0 +1,4 @@
+gametype_setting     disableClassSelection                   1
+gametype_setting     disableCompass                          1
+gametype_setting     characterCustomization                  1
+gametype_setting     spectateType                            0

cfg/t7x/gamesettings/mp/gamesettings_ball.cfg

@@ -0,0 +1,59 @@
+//Don't touch the first 2 lines below here.
+exec "gamedata/gamesettings/mp/gamesettings_default.cfg" 
+exec "gamedata/configs/common/default_xboxlive.cfg"
+
+// Below this line you may uncomment the " // " commands and edit to your liking. 
+// If you unsure the default command. you can always " // " them back for later custom gameplay.
+
+gts prematchrequirement "0"                     // (0-10) Number of players on each team or the total number of players before the pre-match countdown will start.
+gts prematchrequirementtime "0"                 // (0-60) The amount of time before the match will start.
+gts prematchperiod "15"                         // The amount of time before the game starts.
+gts preroundperiod "5"                          // The amount of time before a round starts.
+gts inactivityKick "120"                        // Kick players that's AFK
+gts allowSpectating "1"                         // Allow players to spectate other players or CODcasting.
+gts spectateType "1"                            // 0 disabled, 1 team only, 2 freelook, 3 team only spectate splitscreen players only
+gts allowInGameTeamChange "1"                   // Allow players to switch teams?
+gts autoTeamBalance "1"                         // Automatically assign players to teams 
+gts allowFinalKillcam "1"                       // Controls whether the final killcam is played.
+
+gts timelimit "5"                               // Time limit of the game.
+gts roundScoreLimit "10"                        // Round score limit reach
+gts scorelimit "0"                              // Score limit.
+gts roundlimit "2"                              // The number of rounds that will be played before the game ends.
+
+gts ballCount "1"                               // How many balls you can handle?
+gts carryScore "2"
+gts throwScore "1"
+gts carrierArmor "100"
+gts idleFlagResetTime "15"                      // The time before a ball is automatically returned to base. (0-60 seconds)
+
+//gts loadoutKillstreaksEnabled "1"             // Disable Killstreaks by setting this to 0
+//gts perksEnabled "1"                          // Disable Perks by setting this to 0
+//gts disableVehicleSpawners "0"                // This should disable robots from the DLC map Rupture by setting this to 1 
+//gts disableweapondrop "0"                     // No weapons on the ground.
+//gts disallowprone "0"                         // Don't allow players to lay down.
+
+//Hardcore Mode
+//gts hardcoreMode "1"                          // Enable hardcore mode. 
+//gts friendlyfiretype "1"                      // Enable or Disable Friendly Fire. 1 on, 2 reflect, 3 shared. 
+//gts playerHealthRegenTime "0"                 // Time it takes you to recover damage.
+//gts playerMaxHealth "30"                      // Percent of Health players will have on Respawn.
+//gts onlyHeadshots "0"                         // Headshots only
+//gts allowKillcam "0"                          // Allow Killcam.
+//gts allowbattlechatter "0"                    // Shut the fucking player dialogues up.
+//gts teamKillPointLoss "1"                     // Points per Kill - The number of points for each kill. (0-25)
+//gts teamKillPunishCount "3"                   // Kick constant Team killers out of your server. 
+
+
+gts scoreHeroPowerGainFactor "0.684"            //Score earned towards Hero Weapons and Abilities are multiplied by this factor in BALL
+gts scoreHeroPowerTimeFactor "0.684"
+
+gts enemyCarrierVisible "2"                     // delayed can see person with ball on map
+
+gts captureTime "0"                             // Pickup Time. The amount of time it takes to pickup the ball.
+gts defuseTime "0"                              // Return Time. How long it takes to return ball. (-1 = off. 0 = Instant. (Default) 10 = limit of seconds.)
+
+gts spawntraptriggertime "10"
+
+gts gameAdvertisementRuleTimeLeft "4"
+gts gameAdvertisementRuleRound "3"

cfg/t7x/gamesettings/mp/gamesettings_clean.cfg

@@ -0,0 +1,29 @@
+//Don't touch the first 2 lines below here.
+exec "gamedata/gamesettings/mp/gamesettings_default.cfg" 
+exec "gamedata/configs/common/default_xboxlive.cfg"
+
+// Below this line you may uncomment the " // " commands and edit to your liking. 
+// If you unsure the default command. you can always " // " them back for later custom gameplay.
+
+gts prematchrequirement "0"                     // (0-10) Number of players on each team or the total number of players before the pre-match countdown will start.
+gts prematchrequirementtime "0"                 // (0-60) The amount of time before the match will start.
+gts prematchperiod "15"                         // The amount of time before the game starts.
+gts preroundperiod "5"                          // The amount of time before a round starts.
+gts inactivityKick "120"                        // Kick players that's AFK
+gts allowSpectating "1"                         // Allow players to spectate other players or CODcasting.
+gts spectateType "1"                            // 0 disabled, 1 team only, 2 freelook, 3 team only spectate splitscreen players only
+gts allowInGameTeamChange "1"                   // Allow players to switch teams?
+gts autoTeamBalance "1"                         // Automatically assign players to teams 
+gts allowFinalKillcam "1"                       // Controls whether the final killcam is played.
+
+gts timelimit "10"                              // Time limit of the game.
+gts scorelimit "60"                             // Score limit reach to end the game.
+gts teamCount "2"
+gts teamScorePerKill "0"
+gts teamScorePerCleanDeposit "1"                // Points awarded to the team when depositing a fragment.
+gts cleanDepositOfflineTime "0"
+gts cleanDepositOnlineTime "60"                 // The amount of team each fracture site is active.
+gts cleanDepositRotation "1"
+
+gts scoreHeroPowerGainFactor "0.646"            // Score earned towards Hero Weapons and Abilities are multiplied by this factor 
+gts scoreHeroPowerTimeFactor "0.646"

cfg/t7x/gamesettings/mp/gamesettings_conf.cfg

@@ -0,0 +1,53 @@
+//Don't touch the first 2 lines below here.
+exec "gamedata/gamesettings/mp/gamesettings_default.cfg" 
+exec "gamedata/configs/common/default_xboxlive.cfg"
+
+// Below this line you may uncomment the " // " commands and edit to your liking. 
+// If you unsure the default command. you can always " // " them back for later custom gameplay.
+
+gts prematchrequirement "0"                     // (0-10) Number of players on each team or the total number of players before the pre-match countdown will start.
+gts prematchrequirementtime "0"                 // (0-60) The amount of time before the match will start.
+gts prematchperiod "15"                         // The amount of time before the game starts.
+gts preroundperiod "5"                          // The amount of time before a round starts.
+gts inactivityKick "120"                        // Kick players that's AFK
+gts spectateType "1"                            // 0 disabled, 1 team only, 2 freelook, 3 team only spectate splitscreen players only
+gts allowInGameTeamChange "1"                   // Allow players to switch teams?
+gts allowFinalKillcam "1"                       // Controls whether the final killcam is played.
+
+
+gts timelimit "10"                              // Time limit of the game.
+gts scorelimit "100"                            // Score limit reach to end the game.
+gts teamCount "2"                               // Set this higher if you want Multi-Team Deathmatch that was cut from playlist. (2-6)
+//gts roundLimit "1"                            // The number of rounds that will be played before the game ends.
+gts teamScorePerKill "0"                        // Points per Kill - The number of points for each kill. (0-25)
+//gts teamScorePerKillConfirmed "1"             // Points per Kills Confirmed. - The number of points for each kill confirmed. (0-25)
+//gts teamScorePerKillDenied "0"                // Points per Kill Denied - The number of points for each kill denied. (0-25)
+//gts teamScorePerHeadshot "0"                  // Headshot Bonus Points - Extra points awarded if the kill is a headshot in addition to the points per kill. (0-25)
+//gts playerNumLives "0"                        // Number of Lives - The number of times each player can die before they are no longer allowed to respawn. (0-25)
+
+gts antiBoostDistance "100"
+//gts loadoutKillstreaksEnabled "1"             // Disable Killstreaks by setting this to 0
+//gts perksEnabled "1"                          // Disable Perks by setting this to 0
+//gts disableVehicleSpawners "0"                // This should disable robots from the DLC map Rupture by setting this to 1 
+//gts disableweapondrop "0"                     // No weapons on the ground.
+//gts disallowprone "0"                         // Don't allow players to lay down.
+//gts allowHitMarkers "2"                       // Rather or not to show hitmakers?
+//gts allowAnnouncer "1"                        // Annouce enemy team actions
+
+//Hardcore Mode
+//gts hardcoreMode "1"                          // Enable hardcore mode. 
+//gts friendlyfiretype "1"                      // Enable or Disable Friendly Fire. 1 on, 2 reflect, 3 shared. 
+//gts playerHealthRegenTime "0"                 // Time it takes you to recover damage.
+//gts playerMaxHealth "30"                      // Percent of Health players will have on Respawn.
+//gts onlyHeadshots "0"                         // Headshots only
+//gts allowKillcam "0"                          // Allow Killcam.
+//gts allowbattlechatter "0"                    // Shut the fucking player dialogues up.
+//gts teamKillPointLoss "1"                     // Points per Kill - The number of points for each kill. (0-25)
+//gts teamKillPunishCount "3"                   // Kick constant Team killers out of your server. 
+
+
+gts scoreHeroPowerGainFactor "0.646"           //Score earned towards Hero Weapons and Abilities are multiplied by this factor 
+gts scoreHeroPowerTimeFactor "0.646"
+
+gts gameAdvertisementRuleScorePercent "15"
+gts gameAdvertisementRuleTimeLeft "2"

cfg/t7x/gamesettings/mp/gamesettings_ctf.cfg

@@ -0,0 +1,50 @@
+//Don't touch the first 2 lines below here.
+exec "gamedata/gamesettings/mp/gamesettings_default.cfg" 
+exec "gamedata/configs/common/default_xboxlive.cfg"
+
+// Below this line you may uncomment the " // " commands and edit to your liking. 
+// If you unsure the default command. you can always " // " them back for later custom gameplay.
+
+gts prematchrequirement "0"                     // (0-10) Number of players on each team or the total number of players before the pre-match countdown will start.
+gts prematchrequirementtime "0"                 // (0-60) The amount of time before the match will start.
+gts prematchperiod "15"                         // The amount of time before the game starts.
+gts preroundperiod "5"                          // The amount of time before the round start.
+gts allowSpectating "1"                         // Allow players to spectate other players or CODcasting.
+gts spectateType "1"                            // 0 disabled, 1 team only, 2 freelook, 3 team only spectate splitscreen players only
+gts inactivityKick "120"                        // Kick players that's AFK
+gts allowInGameTeamChange "1"                   // Allow players to switch teams?
+gts allowFinalKillcam "1"                       // Controls whether the final killcam is played
+
+gts timelimit "5"                               // Time limit of the game.
+gts scorelimit "3"                              // The number of flags needed to win the round.
+gts roundLimit "2"                              // The number of rounds that will be played before the game ends.
+gts roundwinlimit "2"                           // Round Win Limit. The number of rounds a team needs to win before the game ends.
+gts enemyCarrierVisible "2"                     // Enemy Carrier. How and if the enemy appears on the minimap. (0 = No. 1 = Yes. 2 = Delayed)
+gts idleFlagResetTime "30"                      // The time before a flag is automatically returned to base. (0-60 seconds)
+gts captureTime "0"                             // Pickup Time. The amount of time it takes to pickup the enemy flag.
+gts defuseTime "0"                              // Return Time. How long it takes to return a flag. (-1 = off. 0 = Instant. (Default) 10 = limit of seconds.)
+gts playerRespawnDelay "5"                      // The amount of time a player has to wait before respawning.
+
+//gts loadoutKillstreaksEnabled "1"             // Disable Killstreaks by setting this to 0
+//gts perksEnabled "1"                          // Disable Perks by setting this to 0
+//gts disableVehicleSpawners "0"                // This should disable robots from the DLC map Rupture by setting this to 1 
+//gts disableweapondrop "0"                     // No weapons on the ground.
+//gts disallowprone "0"                         // Don't allow players to lay down.
+//gts allowHitMarkers "2"                       // Rather or not to show hitmakers?
+//gts allowAnnouncer "1"                        // Annouce enemy team actions
+
+//Hardcore Mode
+//gts hardcoreMode "1"                          // Enable hardcore mode. 
+//gts friendlyfiretype "1"                      // Enable or Disable Friendly Fire. 1 on, 2 reflect, 3 shared. 
+//gts playerHealthRegenTime "0"                 // Time it takes you to recover damage.
+//gts playerMaxHealth "30"                      // Percent of Health players will have on Respawn.
+//gts onlyHeadshots "0"                         // Headshots only
+//gts allowKillcam "0"                          // Allow Killcam.
+//gts allowbattlechatter "0"                    // Shut the fucking player dialogues up.
+//gts teamKillPointLoss "1"                     // Points per Kill - The number of points for each kill. (0-25)
+//gts teamKillPunishCount "3"                   // Kick constant Team killers out of your server. 
+
+gts scoreHeroPowerGainFactor  "0.835"           //Score earned towards Hero Weapons and Abilities are multiplied by this factor in CTF
+gts scoreHeroPowerTimeFactor  "0.835"
+gts gameAdvertisementRuleTimeLeft "4"
+gts gameAdvertisementRuleRound "3"

cfg/t7x/gamesettings/mp/gamesettings_default.cfg

@@ -0,0 +1,175 @@
+
+gametype_setting     allowAnnouncer                          1
+gametype_setting     allowBattleChatter                      1
+gametype_setting     allowFinalKillcam                       1
+gametype_setting     allowHitMarkers                         2
+gametype_setting     allowInGameTeamChange                   1
+gametype_setting     allowKillcam                            1
+gametype_setting     allowMapScripting                       1
+gametype_setting     allowSpectating                         1
+gametype_setting     antiBoostDistance                       100
+gametype_setting     autoDestroyTime                         0
+gametype_setting     autoTeamBalance                         0
+gametype_setting     ballCount                               1
+gametype_setting     bombTimer                               0
+gametype_setting     bootTime                                5
+gametype_setting     bulletDamageScalar                      1.0
+gametype_setting     captureTime                             10
+gametype_setting     carryScore                              0
+gametype_setting     carrierArmor                            100
+gametype_setting     crateCaptureTime                        3
+gametype_setting     cumulativeRoundScores                   1
+gametype_setting     deathPointLoss                          0
+gametype_setting     defuseTime                              0
+gametype_setting     delayPlayer                             0
+gametype_setting     destroyTime                             0
+gametype_setting     disableAmbientFx                        0
+gametype_setting     disableAttachments                      0
+gametype_setting     disableCAC                              0
+gametype_setting     disableClassSelection                   0
+gametype_setting     disableContracts                        0
+gametype_setting     disableTacInsert                        0
+gametype_setting     disableThirdPersonSpectating            0
+gametype_setting     disableVehicleSpawners                  0
+gametype_setting     disableweapondrop                       0
+gametype_setting     disallowaimslowdown                     0
+gametype_setting     disallowprone                           0
+gametype_setting     droppedTagRespawn                       0
+gametype_setting     enemyCarrierVisible                     2
+gametype_setting     extraTime                               0
+gametype_setting     flagCanBeNeutralized                    0
+gametype_setting     flagCaptureCondition                    1
+gametype_setting     flagCaptureGracePeriod                  0
+gametype_setting     flagDecayTime                           0
+gametype_setting     flagRespawnTime                         0
+gametype_setting     forceRadar                              0
+gametype_setting     friendlyfiretype                        0
+gametype_setting     gameAdvertisementRuleScorePercent       0
+gametype_setting     gameAdvertisementRuleTimeLeft           0
+gametype_setting     gameAdvertisementRuleRound              0
+gametype_setting     gameAdvertisementRuleRoundsWon          0
+gametype_setting     gunSelection                            0
+gametype_setting     hardcoremode                            0
+gametype_setting     hotPotato                               0
+gametype_setting     idleFlagDecay                           0
+gametype_setting     idleFlagResetTime                       0
+gametype_setting     inactivityKick                          0
+gametype_setting     incrementalSpawnDelay                   0
+gametype_setting     infectionMode                           0
+gametype_setting     killEventScoreMultiplier                1
+gametype_setting     kothMode                                0
+gametype_setting     leaderBonus                             0
+gametype_setting     loadoutKillstreaksEnabled               1
+gametype_setting     killstreaksGiveGameScore                1
+gametype_setting     maxAllocation                           10
+gametype_setting     maxObjectiveEventsPerMinute             0
+gametype_setting     maxPlayerDefensive                      0
+gametype_setting     maxPlayerEventsPerMinute                0
+gametype_setting     maxPlayerOffensive                      0
+gametype_setting     maxSuicidesBeforeKick                   0
+gametype_setting     movePlayers                             1
+gametype_setting     multiBomb                               0
+gametype_setting     objectivePingTime                       4
+gametype_setting     objectiveSpawnTime                      0
+gametype_setting     oldschoolMode                           0
+gametype_setting     classicMode                             0
+gametype_setting     onlyHeadshots                           0
+gametype_setting     OvertimetimeLimit                       2
+gametype_setting     perksEnabled                            1
+gametype_setting     plantTime                               0
+gametype_setting     playerForceRespawn                      1
+gametype_setting     playerHealthRegenTime                   5
+gametype_setting     playerKillsMax                          0
+gametype_setting     playerMaxHealth                         100
+gametype_setting     playerNumlives                          0
+gametype_setting     playerObjectiveHeldRespawnDelay         0
+gametype_setting     playerQueuedRespawn                     0
+gametype_setting     playerRespawnDelay                      0
+gametype_setting     playerSprintTime                        4
+gametype_setting     pointsForSurvivalBonus                  0
+gametype_setting     pointsPerMeleeKill                      0
+gametype_setting     pointsPerPrimaryGrenadeKill             0
+gametype_setting     pointsPerPrimaryKill                    0
+gametype_setting     pointsPerSecondaryKill                  0
+gametype_setting     pointsPerWeaponKill                     0
+gametype_setting     pregameAlwaysShowCACEdit                1
+gametype_setting     pregameAlwaysShowStreakEdit             1
+gametype_setting     pregameCACModifyTime                    90
+gametype_setting     pregameDraftEnabled                     0
+gametype_setting     pregameDraftRoundTime                   30
+gametype_setting     pregameDraftType                        0
+gametype_setting     pregameItemMaxVotes                     1
+gametype_setting     pregameItemVoteEnabled                  0
+gametype_setting     pregameItemVoteRoundTime                30
+gametype_setting     pregamePositionShuffleMethod            0
+gametype_setting     pregamePositionSortType                 0
+gametype_setting     pregamePostRoundTime                    3
+gametype_setting     pregamePostStageTime                    3
+gametype_setting     pregamePreStageTime                     5
+gametype_setting     pregameScorestreakModifyTime            30
+gametype_setting     prematchperiod                          15
+gametype_setting     preroundperiod                          5
+gametype_setting     prematchrequirement                     0
+gametype_setting     prematchrequirementtime                 0
+gametype_setting     randomObjectiveLocations                0
+gametype_setting     rebootPlayers                           0
+gametype_setting     rebootTime                              15
+gametype_setting     robotSpeed                              1
+gametype_setting     robotShield                             0
+gametype_setting     roundlimit                              1
+gametype_setting     roundScoreLimit                         0
+gametype_setting     roundStartExplosiveDelay                10
+gametype_setting     roundStartKillstreakDelay               15
+gametype_setting     roundswitch                             1  // rounds between switching teams
+gametype_setting     roundwinlimit                           0
+gametype_setting     scoreHeroPowerGainFactor                1.0
+gametype_setting     scoreHeroPowerTimeFactor                1.0
+gametype_setting     scoreThiefPowerGainFactor               1.0
+gametype_setting     scorelimit                              100
+gametype_setting     scorePerPlayer                          0
+gametype_setting     scoreResetOnDeath                       1
+gametype_setting     setbacks                                0
+gametype_setting     shutdownDamage                          2
+gametype_setting     silentPlant                             0
+gametype_setting     spawnprotectiontime                     3
+gametype_setting     spawnsuicidepenalty                     0
+gametype_setting     spawnteamkilledpenalty                  0
+gametype_setting     spawntraptriggertime                    5
+gametype_setting     spectateType                            1
+gametype_setting     cleanDepositOnlineTime                  60
+gametype_setting     cleanDepositRotation                    1
+gametype_setting     teamAssignment                          2
+gametype_setting     teamCount                               2
+gametype_setting     teamKillPenalty                         2
+gametype_setting     teamKillPointLoss                       1
+gametype_setting     teamKillPunishCount                     0
+gametype_setting     teamKillReducedPenalty                  1
+gametype_setting     teamKillScore                           4
+gametype_setting     teamKillSpawnDelay                      20
+gametype_setting     teamNumLives                            0
+gametype_setting     teamScorePerCleanDeposit                1
+gametype_setting     teamScorePerDeath                       0
+gametype_setting     teamScorePerHeadshot                    0
+gametype_setting     teamScorePerKill                        1
+gametype_setting     teamScorePerKillConfirmed               1
+gametype_setting     teamScorePerKillDenied                  0
+gametype_setting     throwScore                              0
+gametype_setting     timelimit                               10
+gametype_setting     timelimit                               10
+gametype_setting     timePausesWhenInZone                    0
+gametype_setting     useEmblemInsteadOfFactionIcon           0
+gametype_setting     vehiclesEnabled                         1
+gametype_setting     vehiclesTimed                           1
+gametype_setting     voipDeadChatWithDead                    0
+gametype_setting     voipDeadChatWithTeam                    1
+gametype_setting     voipDeadHearAllLiving                   0
+gametype_setting     voipDeadHearKiller                      0
+gametype_setting     voipDeadHearTeamLiving                  1
+gametype_setting     voipEveryoneHearsEveryone               0
+gametype_setting     voipKillersHearVictim                   1
+gametype_setting     waverespawndelay                        0
+gametype_setting     weaponCount                             0
+gametype_setting     weaponTimer                             0
+
+// player movement
+gametype_setting     trm_maxHeight                           95.0

cfg/t7x/gamesettings/mp/gamesettings_dem.cfg

@@ -0,0 +1,56 @@
+exec "gamedata/gamesettings/mp/gamesettings_default.cfg" 
+exec "gamedata/configs/common/default_xboxlive.cfg"
+
+// Below this line you may uncomment the " // " commands and edit to your liking. 
+// If you unsure the default command. you can always " // " them back for later custom gameplay.
+
+gts prematchrequirement "0"                     // (0-10) Number of players on each team or the total number of players before the pre-match countdown will start.
+gts prematchrequirementtime "0"                 // (0-60) The amount of time before the match will start.
+gts prematchperiod "15"                         // The amount of time before the game starts.
+gts preroundperiod "5"                          // The amount of time before a round starts.
+gts inactivityKick "120"                        // Kick players that's AFK
+gts allowInGameTeamChange "1"                   // Allow players to switch teams?
+gts allowFinalKillcam "1"                       // Controls whether the final killcam is played
+
+
+gts timelimit "2.5"                             // Time limit of the game.
+gts scorelimit "2"                              // Score limit reach to end the game.
+gts roundlimit "0"                              // The number of rounds that will be played before the game ends.
+gts bombTimer "45"                              // Bomb Timer. The amount of time before the bomb detonates. (2.5-150 seconds)
+gts plantTime "5"                               // Plant Time. The amount of time it takes to plant the bomb. (1-10 seconds)
+gts defuseTime "5"                              // Defuse Time. The amount of time it takes to defuse the bomb.(1-10 seconds)
+gts extraTime "2"                               // Extra Time. The amount of time added on to the current time when a bomb site is destroyed.
+gts OvertimetimeLimit "2"                       // Overtime. The amount of time the Overtime round will last before it ends.
+gts silentPlant "0"                             // Silent Plant. Players can hear the bomb being planted.
+gts roundStartExplosiveDelay "2"                // Delay explosive weapon use at the start of the round.
+gts roundStartKillstreakDelay "15"              // Delay scorestreaks start of the round.
+
+gts maxObjectiveEventsPerMinute "5"             // Used to determine whether a player is scoreboosting.
+gts maxPlayerDefensive "128"                    // Used to determine whether a player is scoreboosting.
+gts maxPlayerEventsPerMinute "2.5"              // Used to determine whether a player is scoreboosting.
+
+gts spawntraptriggertime "10"
+//gts loadoutKillstreaksEnabled "1"             // Disable Killstreaks by setting this to 0
+//gts perksEnabled "1"                          // Disable Perks by setting this to 0
+//gts disableVehicleSpawners "0"                // This should disable robots from the DLC map Rupture by setting this to 1 
+//gts disableweapondrop "0"                     // No weapons on the ground.
+//gts disallowprone "0"                         // Don't allow players to lay down.
+//gts allowHitMarkers "2"                       // Rather or not to show hitmakers?
+//gts allowAnnouncer "1"                        // Annouce enemy team actions
+
+
+//Hardcore Mode
+//gts hardcoreMode "1"                          // Enable hardcore mode. 
+//gts friendlyfiretype "1"                      // Enable or Disable Friendly Fire. 1 on, 2 reflect, 3 shared. 
+//gts playerHealthRegenTime "0"                 // Time it takes you to recover damage.
+//gts playerMaxHealth "30"                      // Percent of Health players will have on Respawn.
+//gts allowKillcam "0"                          // Allow Killcam.
+//gts allowbattlechatter "0"                    // Shut the fucking player dialogues up.
+//gts teamKillPointLoss "1"                     // Points per Kill - The number of points for each kill. (0-25)
+//gts teamKillPunishCount "3"                   // Kick constant Team killers out of your server. 
+
+gts scoreHeroPowerGainFactor "0.679"            //Score earned towards Hero Weapons and Abilities are multiplied by this factor in Demolition
+gts scoreHeroPowerTimeFactor "0.679"
+
+gts gameAdvertisementRuleRound "3"
+gts gameAdvertisementRuleTimeLeft "1"

cfg/t7x/gamesettings/mp/gamesettings_dm.cfg

@@ -0,0 +1,51 @@
+//Don't touch the first 2 lines below here.
+exec "gamedata/gamesettings/mp/gamesettings_default.cfg" 
+exec "gamedata/configs/common/default_xboxlive.cfg"
+
+// Below this line you may uncomment the " // " commands and edit to your liking. 
+// If you unsure the default command. you can always " // " them back for later custom gameplay.
+
+gts prematchrequirement "0"                     // (0-10) Number of players on each team or the total number of players before the pre-match countdown will start.
+gts prematchrequirementtime "0"                 // (0-60) The amount of time before the match will start.
+gts prematchperiod "15"                         // The amount of time before the game starts.
+gts preroundperiod "5"                          // The amount of time before a round starts.
+gts inactivityKick "120"                        // Kick players that's AFK
+gts spectateType "1"                            // 0 disabled, 1 team only, 2 freelook, 3 team only spectate splitscreen players only
+gts allowInGameTeamChange "1"                   // Allow players to switch teams?
+gts allowFinalKillcam "1"                       // Controls whether the final killcam is played.
+
+gts timelimit "10"                              // Time limit of the game.
+gts scorelimit "30"                             // Score limit reach to end the game.
+gts disableTacInsert "1"                        // Disable Tactical Insertion. 3arc have this set 1 by default to keep players for boosting.
+//gts roundLimit "1"                            // The number of rounds that will be played before the game ends.
+//gts teamScorePerKill "1"                      // Points per Kill - The number of points for each kill. (0-25)
+//gts teamScorePerDeath "0"                     // Points per Death - The number of points your team loses for each death. Points can never be lower than zero. (0-25)
+//gts teamScorePerHeadshot "0"                  // Headshot Bonus Points - Extra points awarded if the kill is a headshot in addition to the points per kill. (0-25)
+//gts playerNumLives "0"                        // Number of Lives - The number of times each player can die before they are no longer allowed to respawn. (0-25)
+//gts roundStartExplosiveDelay "2"              // Delay explosive weapon use at the start of the round.
+//gts roundStartKillstreakDelay "0"             // Delay killstreaks at the start of the round.
+
+//gts loadoutKillstreaksEnabled "1"             // Disable Killstreaks by setting this to 0
+//gts perksEnabled "1"                          // Disable Perks by setting this to 0
+//gts disableVehicleSpawners "0"                // This should disable robots from the DLC map Rupture by setting this to 1 
+//gts disableweapondrop "0"                     // No weapons on the ground.
+//gts disallowprone "0"                         // Don't allow players to lay down.
+
+//Hardcore Mode
+//gts hardcoreMode "1"                          // Enable hardcore mode. 
+//gts friendlyfiretype "1"                      // Enable or Disable Friendly Fire. 1 on, 2 reflect, 3 shared. 
+//gts playerHealthRegenTime "0"                 // Time it takes you to recover damage.
+//gts playerMaxHealth "30"                      // Percent of Health players will have on Respawn.
+//gts onlyHeadshots "0"                         // Headshots only
+//gts allowKillcam "0"                          // Allow Killcam.
+//gts allowbattlechatter "0"                    // Shut the fucking player dialogues up.
+//gts teamKillPointLoss "1"                     // Points per Kill - The number of points for each kill. (0-25)
+//gts teamKillPunishCount "3"                   // Kick constant Team killers out of your server. 
+
+gts useEmblemInsteadOfFactionIcon "1"           // Show player's art on scoreboard
+gts voipEveryoneHearsEveryone "1"               // Everyone on voice chat hear you.
+
+
+gts gameAdvertisementRuleScorePercent 50
+gts gameAdvertisementRuleTimeLeft 2
+gts teamCount 1

cfg/t7x/gamesettings/mp/gamesettings_dom.cfg

@@ -0,0 +1,55 @@
+//Don't touch the first 2 lines below here.
+exec "gamedata/gamesettings/mp/gamesettings_default.cfg" 
+exec "gamedata/configs/common/default_xboxlive.cfg"
+
+// Below this line you may uncomment the " // " commands and edit to your liking. 
+// If you unsure the default command. you can always " // " them back for later custom gameplay.
+
+gts prematchrequirement "0"                     // (0-10) Number of players on each team or the total number of players before the pre-match countdown will start.
+gts prematchrequirementtime "0"                 // (0-60) The amount of time before the match will start.
+gts prematchperiod "15"                         // The amount of time before the game starts.
+gts preroundperiod "5"                          // The amount of time before a round starts.
+gts inactivityKick "120"                        // Kick players that's AFK
+gts allowSpectating "1"                         // Allow players to spectate other players or CODcasting.
+gts spectateType "1"                            // 0 disabled, 1 team only, 2 freelook, 3 team only spectate splitscreen players only
+gts allowInGameTeamChange "1"                   // Allow players to switch teams?
+gts autoTeamBalance "1"                         // Automatically assign players to teams 
+gts allowFinalKillcam "1"                       // Controls whether the final killcam is played.
+
+gts timelimit "10"                              // Time limit of the game.
+gts scorelimit "100"                            // Score limit.
+gts roundScoreLimit "100"                       // Round score limit reach
+
+gts captureTime "10"                            // Capture Time. The amount of time it takes to capture an objective.
+gts roundlimit "2"                              // The number of rounds that will be played before the game ends.
+gts maxObjectiveEventsPerMinute "3"
+gts maxPlayerDefensive "128"
+gts maxPlayerOffensive "128"
+gts maxPlayerEventsPerMinute "3"
+
+gts flagCanBeNeutralized "0"
+
+//gts loadoutKillstreaksEnabled "1"             // Disable Killstreaks by setting this to 0
+//gts perksEnabled "1"                          // Disable Perks by setting this to 0
+//gts disableVehicleSpawners "0"                // This should disable robots from the DLC map Rupture by setting this to 1 
+//gts disableweapondrop "0"                     // No weapons on the ground.
+//gts disallowprone "0"                         // Don't allow players to lay down.
+//gts allowHitMarkers "2"                       // Rather or not to show hitmakers?
+//gts allowAnnouncer "1"                        // Annouce enemy team actions
+
+gts scoreHeroPowerGainFactor "0.616"            //Score earned towards Hero Weapons and Abilities are multiplied by this factor
+gts scoreHeroPowerTimeFactor "0.616"
+
+//Hardcore Mode
+//gts hardcoreMode "1"                          // Enable hardcore mode. 
+//gts friendlyfiretype "1"                      // Enable or Disable Friendly Fire. 1 on, 2 reflect, 3 shared. 
+//gts playerHealthRegenTime "0"                 // Time it takes you to recover damage.
+//gts playerMaxHealth "30"                      // Percent of Health players will have on Respawn.
+//gts onlyHeadshots "0"                         // Headshots only
+//gts allowKillcam "0"                          // Allow Killcam.
+//gts allowbattlechatter "0"                    // Shut the fucking player dialogues up.
+//gts teamKillPointLoss "1"                     // Points per Kill - The number of points for each kill. (0-25)
+//gts teamKillPunishCount "3"                   // Kick constant Team killers out of your server. 
+
+gts gameAdvertisementRuleScorePercent 10
+gts gameAdvertisementRuleRound 3

cfg/t7x/gamesettings/mp/gamesettings_escort.cfg

@@ -0,0 +1,64 @@
+//Don't touch the first 2 lines below here.
+exec "gamedata/gamesettings/mp/gamesettings_default.cfg" 
+exec "gamedata/configs/common/default_xboxlive.cfg"
+
+// Below this line you may uncomment the " // " commands and edit to your liking. 
+// If you unsure the default command. you can always " // " them back for later custom gameplay.
+
+gts prematchrequirement "0"                     // (0-10) Number of players on each team or the total number of players before the pre-match countdown will start.
+gts prematchrequirementtime "0"                 // (0-60) The amount of time before the match will start.
+gts prematchperiod "15"                         // The amount of time before the game starts.
+gts preroundperiod "5"                          // The amount of time before a round starts.
+gts inactivityKick "120"                        // Kick players that's AFK
+gts allowSpectating "1"                         // Allow players to spectate other players or CODcasting.
+gts spectateType "1"                            // 0 disabled, 1 team only, 2 freelook, 3 team only spectate splitscreen players only
+gts allowInGameTeamChange "1"                   // Allow players to switch teams?
+gts autoTeamBalance "1"                         // Automatically assign players to teams 
+gts allowFinalKillcam "1"                       // Controls whether the final killcam is played.
+
+
+gts timelimit "5"                               // Time limit of the game.
+gts scorelimit "0"                              // Score limit.
+gts roundscorelimit "1"                         // Round score limit reach
+gts roundwinlimit "2"                           
+gts roundlimit "2"                              // The number of rounds that will be played before the game ends.
+gts teamCount "2"
+
+gts shutdownDamage "3"
+gts bootTime "5"
+gts rebootTime "15"                             // How long it takes the robot to reboot after being shut down
+gts rebootPlayers "0"
+gts movePlayers "1"
+gts robotSpeed "1"                              // Movment speed of the robot
+gts robotShield "0"
+
+//gts teamScorePerDeath "0"                     // Points per Death - The number of points your team loses for each death. Points can never be lower than zero. (0-25)
+//gts teamScorePerHeadshot "0"                  // Headshot Bonus Points - Extra points awarded if the kill is a headshot in addition to the points per kill. (0-25)
+//gts playerNumLives "0"                        // Number of Lives - The number of times each player can die before they are no longer allowed to respawn. (0-25)
+//gts loadoutKillstreaksEnabled "1"             // Disable Killstreaks by setting this to 0
+//gts perksEnabled "1"                          // Disable Perks by setting this to 0
+gts disableVehicleSpawners "1"                // This should disable robots from the DLC map Rupture by setting this to 1 
+//gts disableweapondrop "0"                     // No weapons on the ground.
+//gts disallowprone "0"                         // Don't allow players to lay down.
+//gts allowHitMarkers "2"                       // Rather or not to show hitmakers?
+//gts allowAnnouncer "1"                        // Annouce enemy team actions
+
+//Hardcore Mode
+//gts hardcoreMode "1"                          // Enable hardcore mode. 
+//gts friendlyfiretype "1"                      // Enable or Disable Friendly Fire. 1 on, 2 reflect, 3 shared. 
+//gts playerHealthRegenTime "0"                 // Time it takes you to recover damage.
+//gts playerMaxHealth "30"                      // Percent of Health players will have on Respawn.
+//gts onlyHeadshots "0"                         // Headshots only
+//gts allowKillcam "0"                          // Allow Killcam.
+//gts allowbattlechatter "0"                    // Shut the fucking player dialogues up.
+//gts teamKillPointLoss "1"                     // Points per Kill - The number of points for each kill. (0-25)
+//gts teamKillPunishCount "3"                   // Kick constant Team killers out of your server. 
+
+
+gts scoreHeroPowerGainFactor "0.788"            // Score earned towards Hero Weapons and Abilities are multiplied by this factor 
+gts scoreHeroPowerTimeFactor "0.788"
+
+gts spawntraptriggertime "5"
+
+gts gameAdvertisementRuleTimeLeft "3.5"
+gts gameAdvertisementRuleRound "3"

cfg/t7x/gamesettings/mp/gamesettings_fr.cfg

@@ -0,0 +1,33 @@
+//Don't touch the first 2 lines below here.
+exec "gamedata/gamesettings/mp/gamesettings_default.cfg" 
+exec "gamedata/configs/common/default_xboxlive.cfg"
+
+// Below this line you may uncomment the " // " commands and edit to your liking. 
+// If you unsure the default command. you can always " // " them back for later custom gameplay.
+
+gts prematchrequirement "0"                     // (0-10) Number of players on each team or the total number of players before the pre-match countdown will start.
+gts prematchrequirementtime "0"                 // (0-60) The amount of time before the match will start.
+gts prematchperiod "0"                         // The amount of time before the game starts.
+gts preroundperiod "10"                         // The amount of time before a round starts.
+gts inactivityKick "120"                        // Kick players that's AFK
+gts allowSpectating "1"                         // Allow players to spectate other players or CODcasting. (Could be used as screen cheating)
+//gts spectateType "1"                            // 0 disabled, 1 team only, 2 freelook, 3 team only spectate splitscreen players only
+gts allowInGameTeamChange "0"                   // Allow players to switch teams?
+gts autoTeamBalance "1"                         // Automatically assign players to teams 
+gts allowFinalKillcam "0"                       // Controls whether the final killcam is played.
+gts disableCAC "0"
+gts disableClassSelection "1"
+gts loadoutKillstreaksEnabled "0"               // Disable Killstreaks by setting this to 0
+//gts perksEnabled "1"                          // Disable Perks by setting this to 0
+//gts disableVehicleSpawners "0"                // This should disable robots from the DLC map Rupture by setting this to 1 
+//gts disableweapondrop "0"                     // No weapons on the ground.
+//gts disallowprone "0"                         // Don't allow players to lay down.
+gts disableTacInsert "1"                        // Disable Tactical Insertion.
+
+
+
+gts timelimit "15"                              // Time limit of the game.
+gts scorelimit "0"                              // Score limit reach to end the game.
+gts roundswitch "0"
+gts teamCount "1"
+

cfg/t7x/gamesettings/mp/gamesettings_gun.cfg

@@ -0,0 +1,38 @@
+//Don't touch the first 3 lines below here.
+exec "gamedata/gamesettings/mp/gamesettings_default.cfg" 
+exec "gamedata/configs/common/default_xboxlive.cfg"
+gts wagermatchhud "1"
+
+// Below this line you may uncomment the " // " commands and edit to your liking. 
+// If you unsure the default command. you can always " // " them back for later custom gameplay.
+
+
+gts gunSelection 3                              // Ladder. Determines which set of weapons the game uses (0 = Normal. 1 = Close Quarters. 2 = Marksman. 3 = Random.)
+set black_market_gun_game "0"                   // Toggle 1 if you want Blackjack's GunGame. leave it 0 for regular. (This might conflect with gunselection set)
+gts prematchrequirement "0"                     // (0-10) Number of players on each team or the total number of players before the pre-match countdown will start.
+gts prematchrequirementtime "0"                 // (0-60) The amount of time before the match will start.
+gts prematchperiod 20                           // The amount of time before the game starts. (Give weak potato players a chance to load in and not spawn.)
+gts preroundperiod "10"                         // The amount of time before a round starts.
+gts disableClassSelection "1"                   // Disable CAC for GunGame. 
+gts allowSpectating "1"                         // Allow players to spectate other players or CODcasting.
+gts spectateType "1"                            // 0 disabled, 1 team only, 2 freelook, 3 team only spectate splitscreen players only
+
+gts timelimit "10"                              // Time limit of the game.
+gts scorelimit "30"                             // Score limit reach to end the game.
+
+
+gts setbacks 1                                  // Setbacks. How much weapon progression a player loses when knifed. (1-10)
+gts forceRadar "1"                              // Enable UAV all the time
+gts loadoutKillstreaksEnabled "0"               // Disable Killstreaks for GunGame. 
+gts disableVehicleSpawners "1"                  // This should disable robots from the DLC map Rupture by setting this to 1 
+gts disableweapondrop "1"                       // No weapons on the ground for GunGame. 
+gts perksEnabled "0"                            // Disable Perks on GunGame
+//gts disallowprone "0"                         // Don't allow players to lay down.
+//gts allowHitMarkers "2"                       // Rather or not to show hitmakers?
+gts playerNumLives "0"                          // Number of Lives - The number of times each player can die before they are no longer allowed to respawn. (0-25)
+//gts playerMaxHealth "100"                     // Percent of Health players will have on Respawn.
+//gts onlyHeadshots "0"                         // Headshots only
+
+gts useEmblemInsteadOfFactionIcon "1"           // Show player's art on scoreboard
+gts voipEveryoneHearsEveryone "1"               // Everyone on voice chat hear you.
+teamCount 1

cfg/t7x/gamesettings/mp/gamesettings_infect.cfg

@@ -0,0 +1,32 @@
+//Don't touch the first 2 lines below here.
+exec "gamedata/gamesettings/mp/gamesettings_default.cfg" 
+exec "gamedata/configs/common/default_xboxlive.cfg"
+
+// Below this line you may uncomment the " // " commands and edit to your liking. 
+// If you unsure the default command. you can always " // " them back for later custom gameplay.
+
+gts prematchrequirement "0"                     // (0-10) Number of players on each team or the total number of players before the pre-match countdown will start.
+gts prematchrequirementtime "0"                 // (0-60) The amount of time before the match will start.
+gts prematchperiod "15"                         // The amount of time before the game starts.
+gts preroundperiod "10"                         // The amount of time before a round starts.
+gts inactivityKick "120"                        // Kick players that's AFK
+gts allowSpectating "1"                         // Allow players to spectate other players or CODcasting. (Could be used as screen cheating)         
+gts allowInGameTeamChange "1"                   // Allow players to switch teams?
+gts autoTeamBalance "1"                         // Automatically assign players to teams 
+gts allowFinalKillcam "1"                       // Controls whether the final killcam is played.
+
+gts timelimit "2"                               // Time limit of the game.
+gts scorelimit "0"                              // Score limit reach to end the game.
+gts teamCount "2"
+
+gts loadoutKillstreaksEnabled "0"               // Disable Killstreaks by setting this to 0.
+gts disableVehicleSpawners "1"                  // This should disable robots from the DLC map Rupture by setting this to 1.
+//gts disallowprone "0"                         // Don't allow players to lay down.
+//gts disableTacInsert "1"                      // Disable Tactical Insertion. Now that would be a dick move for the infected players.
+//gts allowHitMarkers "2"                       // Rather or not to show hitmakers?
+//gts allowAnnouncer "1"                        // Annouce enemy team actions
+
+gts gameAdvertisementRuleScorePercent "15"
+gts gameAdvertisementRuleTimeLeft "2"
+gts gameAdvertisementRuleRound "0"
+gts gameAdvertisementRuleRoundsWon "0"

cfg/t7x/gamesettings/mp/gamesettings_koth.cfg

@@ -0,0 +1,55 @@
+//Don't touch the first 3 lines below here.
+exec "gamedata/gamesettings/mp/gamesettings_default.cfg" 
+exec "gamedata/configs/common/default_xboxlive.cfg"
+gts kothMode "1"
+
+// Below this line you may uncomment the " // " commands and edit to your liking. 
+// If you unsure the default command. you can always " // " them back for later custom gameplay.
+
+gts prematchrequirement "0"                     // (0-10) Number of players on each team or the total number of players before the pre-match countdown will start.
+gts prematchrequirementtime "0"                 // (0-60) The amount of time before the match will start.
+gts prematchperiod "15"                         // The amount of time before the game starts.
+gts preroundperiod "5"                          // The amount of time before a round starts.
+gts inactivityKick "120"                        // Kick players that's AFK
+gts allowSpectating "1"                         // Allow players to spectate other players or CODcasting.
+gts spectateType "1"                            // 0 disabled, 1 team only, 2 freelook, 3 team only spectate splitscreen players only
+gts allowInGameTeamChange "1"                   // Allow players to switch teams?
+gts autoTeamBalance "1"                         // Automatically assign players to teams 
+gts allowFinalKillcam "1"                       // Controls whether the final killcam is played.
+
+gts timelimit "5"                               // Time limit of the game.
+gts scorelimit "250"                            // Score limit reach to end the game.
+gts teamCount "2"
+
+//gts loadoutKillstreaksEnabled "1"             // Disable Killstreaks by setting this to 0
+//gts perksEnabled "1"                          // Disable Perks by setting this to 0
+//gts disableVehicleSpawners "0"                // This should disable robots from the DLC map Rupture by setting this to 1 
+//gts disableweapondrop "0"                     // No weapons on the ground.
+//gts disallowprone "0"                         // Don't allow players to lay down.
+
+gts maxPlayerEventsPerMinute "8"
+
+gts autoDestroyTime "60"                        // Lifetime. The amount of time hardpoint is active.
+gts captureTime "0"                             // Capture Time. The amount of time it takes to capture hardpoint.
+gts objectiveSpawnTime "0"                      // Activation Delay Time. The amount of time before the next objective becomes active.
+gts randomObjectiveLocations "0"                // Hardpoint Locations. The order in which the hardpoint will appear. (0 = Liner 2 = Random After First)
+gts scorePerPlayer "0"                          // Scoring. Determines if the team gets score at a constant rate or if more points are awarded when more players occupy the hardpoint.
+gts timePausesWhenInZone "1"                    // timelimit pauses when you capture the hardpoint.
+
+
+//Hardcore Mode
+//gts hardcoreMode "1"                          // Enable hardcore mode. 
+//gts friendlyfiretype "1"                      // Enable or Disable Friendly Fire. 1 on, 2 reflect, 3 shared. 
+//gts playerHealthRegenTime "0"                 // Time it takes you to recover damage.
+//gts playerMaxHealth "30"                      // Percent of Health players will have on Respawn.
+//gts onlyHeadshots "0"                         // Headshots only
+//gts allowKillcam "0"                          // Allow Killcam.
+//gts allowbattlechatter "0"                    // Shut the fucking player dialogues up.
+//gts teamKillPointLoss "1"                     // Points per Kill - The number of points for each kill. (0-25)
+//gts teamKillPunishCount "3"                   // Kick constant Team killers out of your server. 
+
+gts scoreHeroPowerGainFactor "0.45"             //Score earned towards Hero Weapons and Abilities are multiplied by this factor in Hardpoint
+gts scoreHeroPowerTimeFactor "0.45"
+
+gts gameAdvertisementRuleScorePercent "20"
+gts gameAdvertisementRuleTimeLeft "1.5"

cfg/t7x/gamesettings/mp/gamesettings_prop.cfg

@@ -0,0 +1,47 @@
+//Don't touch the first 2 lines below here.
+exec "gamedata/gamesettings/mp/gamesettings_default.cfg" 
+exec "gamedata/configs/common/default_xboxlive.cfg"
+
+////////////////////////////////////////////////////////////////
+//     Please note that only these maps support Prop Hunt     //
+//    Make sure to change your sv_maprotation to only them!   //
+////////////////////////////////////////////////////////////////
+//                                                            //
+//            Aquarium      -     mp_biodome                  //
+//            Combine       -     mp_sector                   //
+//            Evac          -     mp_apartments               //
+//            Exodus        -     mp_chinatown                //
+//            Fringe        -     mp_veiled                   //
+//            Hunted        -     mp_ethiopia                 //
+//            Infection     -     mp_infection                //
+//            Redwood       -     mp_redwood                  //
+//            Spire         -     mp_aerospace                //
+//                                                            //
+////////////////////////////////////////////////////////////////
+
+// Below this line you may uncomment the " // " commands and edit to your liking. 
+// If you unsure the default command. you can always " // " them back for later custom gameplay.
+
+gts prematchrequirement "0"                     // (0-10) Number of players on each team or the total number of players before the pre-match countdown will start.
+gts prematchrequirementtime "0"                 // (0-60) The amount of time before the match will start.
+gts prematchperiod "15"                         // The amount of time before the game starts.
+gts preroundperiod "10"                          // The amount of time before a round starts.
+gts inactivityKick "120"                        // Kick players that's AFK
+gts allowFinalKillcam "1"                       // Controls whether the final killcam is played.
+gts spectateType "3"                            // 0 disabled, 1 team only, 2 freelook, 3 team only spectate splitscreen players only
+gts disableClassSelection "1"                   // Disable CAC for prop hunt.
+gts allowInGameTeamChange "0"                   // Keep it 0 
+
+gts timelimit "4"                               // Time limit of the game.
+gts scorelimit "0"                              // Score limit reach to end the game.
+gts teamCount "2"
+gts roundLimit "4"                              // The number of rounds that will be played before the game ends.
+gts roundwinlimit "3"
+gts roundSwitch "1"
+gts playerNumLives "1"                          // Number of Lives - Keep it 1!
+
+gts disableVehicleSpawners "1"                  // This should disable robots from the DLC map Rupture by setting this to 1 - keep it 1!
+
+gts voipDeadChatWithDead "1"
+gts voipDeadChatWithTeam "0"
+gts voipDeadHearTeamLiving "0"

cfg/t7x/gamesettings/mp/gamesettings_sas.cfg

@@ -0,0 +1,48 @@
+//Don't touch the first 3 lines below here.
+exec "gamedata/gamesettings/mp/gamesettings_default.cfg" 
+exec "gamedata/configs/common/default_xboxlive.cfg"
+gts wagermatchhud "1"
+
+// Below this line you may uncomment the " // " commands and edit to your liking. 
+// If you unsure the default command. you can always " // " them back for later custom gameplay.
+
+gts gunSelection "1"                            // Setback Weapon. The weapon that will set players back in points. (0 = None 1 = Combat Axe 2 = Crossbow 3 = Ballistic Knife)
+gts prematchrequirement "0"                     // (0-10) Number of players on each team or the total number of players before the pre-match countdown will start.
+gts prematchrequirementtime "0"                 // (0-60) The amount of time before the match will start.
+gts prematchperiod 20                           // The amount of time before the game starts. (Give weak potato players a chance to load in and not spawn.)
+gts preroundperiod "10"                         // The amount of time before a round starts.
+gts inactivityKick "120"                        // Kick players that's AFK
+gts allowInGameTeamChange "0"                   // Allow team change..not sure why this is on SAS
+gts disableClassSelection "1"                   // Disable CAC for GunGame. 
+gts allowSpectating "1"                         // Allow players to spectate other players or CODcasting.
+gts spectateType "1"                            // 0 disabled, 1 team only, 2 freelook, 3 team only spectate splitscreen players only
+
+gts timelimit "5"                               // Time limit of the game.
+gts scorelimit "0"                              // Score limit reach to end the game.
+gts roundlimit "1"
+
+
+gts forceRadar "1"                              // Enable UAV all the time
+gts timecount "1"
+gts loadoutKillstreaksEnabled "0"               // Disable Killstreaks for SAS. 
+gts disableVehicleSpawners "1"                  // This should disable robots from the DLC map Rupture by setting this to 1 
+gts disableweapondrop "1"                       // No weapons on the ground for SAS. 
+gts perksEnabled "0"                            // Disable Perks on SAS
+//gts disallowprone "0"                         // Don't allow players to lay down.
+gts playerNumLives "0"                          // Number of Lives - The number of times each player can die before they are no longer allowed to respawn. (0-25)
+//gts playerMaxHealth "100"                     // Percent of Health players will have on Respawn.
+//gts onlyHeadshots "0"                         // Headshots only
+
+gts useEmblemInsteadOfFactionIcon "1"           // Show player's art on scoreboard
+gts voipEveryoneHearsEveryone "1"               // Everyone on voice chat hear you.
+
+
+gts pointsPerPrimaryKill "10"
+gts pointsPerSecondaryKill "10"
+gts pointsPerPrimaryGrenadeKill "5"
+gts pointsPerMeleeKill "5"
+gts roundStartExplosiveDelay "0"
+
+gts gameAdvertisementRuleScorePercent "35"
+gts gameAdvertisementRuleTimeLeft "1.5"
+teamCount 1

cfg/t7x/gamesettings/mp/gamesettings_sd.cfg

@@ -0,0 +1,62 @@
+//Don't touch the first 2 lines below here.
+exec "gamedata/gamesettings/mp/gamesettings_default.cfg" 
+exec "gamedata/configs/common/default_xboxlive.cfg"
+
+// Below this line you may uncomment the " // " commands and edit to your liking. 
+// If you unsure the default command. you can always " // " them back for later custom gameplay.
+
+gts prematchrequirement "0"                     // (0-10) Number of players on each team or the total number of players before the pre-match countdown will start.
+gts prematchrequirementtime "0"                 // (0-60) The amount of time before the match will start.
+gts prematchperiod "15"                         // The amount of time before the game starts.
+gts preroundperiod "3"                          // The amount of time before a round starts.
+gts inactivityKick "120"                        // Kick players that's AFK
+gts allowSpectating "1"                         // Allow players to spectate other players or CODcasting. (Could be used as screen cheating)         
+gts allowInGameTeamChange "1"                   // Allow players to switch teams?
+gts autoTeamBalance "1"                         // Automatically assign players to teams 
+gts allowFinalKillcam "1"                       // Controls whether the final killcam is played.
+gts spectateType "3"                            // 0 disabled, 1 team only, 2 freelook, 3 team only spectate splitscreen players only
+
+gts timelimit "2                                // Time limit of the game.
+gts scorelimit "4"                              // Score limit reach to end the game.
+
+gts bombTimer 45                              // Bomb Timer. The amount of time before the bomb detonates.
+gts plantTime 5                               // Plant Time. The amount of time it takes to plant the bomb.
+gts defuseTime 5                              // Defuse Time. The amount of time it takes to defuse the bomb.
+gts multiBomb 0                               // Multi Bomb. Every attacking player gets a bomb.
+gts roundswitch 1                             // The number of rounds to play before teams switch sides.
+gts roundlimit 0
+//gts silentPlant 0                             // Players can hear the bomb being planted.
+
+//gts loadoutKillstreaksEnabled "1"             // Disable Killstreaks by setting this to 0
+//gts perksEnabled "1"                          // Disable Perks by setting this to 0
+gts disableVehicleSpawners "1"                  // This should disable robots from the DLC map Rupture by setting this to 1 
+//gts disableweapondrop "0"                     // No weapons on the ground.
+//gts disallowprone "0"                         // Don't allow players to lay down.
+//gts allowHitMarkers "2"                       // Rather or not to show hitmakers?
+//gts allowAnnouncer "1"                        // Annouce enemy team actions
+
+gts playerLives "1"
+gts playerNumLives "1"                          // Correct gts to configure amount of respawns
+gts playerKillsMax "6"
+gts totalKillsMax "11"
+gts teamKillScore "4"
+
+gts voipDeadChatWithDead "1"
+gts voipDeadChatWithTeam "0"
+gts voipDeadHearTeamLiving "0"
+
+gts scoreHeroPowerGainFactor "0.8"
+gts scoreHeroPowerTimeFactor "0.3"
+
+//Hardcore Mode
+//gts hardcoreMode "1"                          // Enable hardcore mode. 
+//gts friendlyfiretype "1"                      // Enable or Disable Friendly Fire. 1 on, 2 reflect, 3 shared. 
+//gts playerHealthRegenTime "0"                 // Time it takes you to recover damage.
+//gts playerMaxHealth "30"                      // Percent of Health players will have on Respawn.
+//gts onlyHeadshots "0"                         // Headshots only
+//gts allowKillcam "0"                          // Allow Killcam.
+//gts allowbattlechatter "0"                    // Shut the fucking player dialogues up.
+//gts teamKillPointLoss "1"                     // Points per Kill - The number of points for each kill. (0-25)
+//gts teamKillPunishCount "3"                   // Kick constant Team killers out of your server. 
+
+gts gameAdvertisementRuleRoundsWon          3

cfg/t7x/gamesettings/mp/gamesettings_sniperonly.cfg

@@ -0,0 +1,229 @@
+//Don't touch the first 2 lines below here.
+exec "gamedata/gamesettings/mp/gamesettings_default.cfg" 
+exec "gamedata/configs/common/default_xboxlive.cfg"
+
+
+// Below this line you may uncomment the " // " commands and edit to your liking. 
+// If you unsure the default command. you can always " // " them back for later custom gameplay
+
+gts prematchrequirement "0"                     // (0-10) Number of players on each team or the total number of players before the pre-match countdown will start.
+gts prematchrequirementtime "0"                 // (0-60) The amount of time before the match will start.
+gts prematchperiod "15"                         // The amount of time before the game starts.
+gts preroundperiod "5"                          // The amount of time before a round starts.
+gts inactivityKick "120"                        // Kick players that's AFK
+gts allowSpectating "1"                         // Allow players to spectate other players or CODcasting
+gts spectateType "1"                            // 0 disabled, 1 team only, 2 freelook, 3 team only spectate splitscreen players only
+gts allowInGameTeamChange "1"                   // Allow players to switch teams?
+gts autoTeamBalance "1"                         // Automatically assign players to teams 
+gts allowFinalKillcam "1"                       // Controls whether the final killcam is played.
+
+gts timelimit "10"                              // Time limit of the game.
+gts scorelimit "75"                             // Score limit reach to end the game.
+gts teamCount "2"
+
+//gts teamScorePerDeath "0"                     // Points per Death - The number of points your team loses for each death. Points can never be lower than zero. (0-25)
+//gts teamScorePerHeadshot "0"                  // Headshot Bonus Points - Extra points awarded if the kill is a headshot in addition to the points per kill. (0-25)
+gts playerNumLives "0"                          // Number of Lives - The number of times each player can die before they are no longer allowed to respawn. (0-25)
+gts loadoutKillstreaksEnabled "0"               // Disable Killstreaks by setting this to 0
+//gts perksEnabled "1"                          // Disable Perks by setting this to 0
+gts disableVehicleSpawners "1"                  // This should disable robots from the DLC map Rupture by setting this to 1 
+//gts disableweapondrop "0"                     // No weapons on the ground.
+//gts disallowprone "0"                         // Don't allow players to lay down.
+//gts allowHitMarkers "2"                       // Rather or not to show hitmakers?
+//gts allowAnnouncer "1"                        // Annouce enemy team actions
+
+
+//Hardcore Mode
+//gts hardcoreMode "1"                          // Enable hardcore mode. 
+//gts friendlyfiretype "1"                      // Enable or Disable Friendly Fire. 1 on, 2 reflect, 3 shared. 
+//gts playerHealthRegenTime "0"                 // Time it takes you to recover damage.
+//gts playerMaxHealth "30"                      // Percent of Health players will have on Respawn.
+//gts onlyHeadshots "0"                         // Headshots only
+//gts allowKillcam "0"                          // Allow Killcam.
+//gts allowbattlechatter "0"                    // Shut the fucking player dialogues up.
+//gts teamKillPointLoss "1"                     // Points per Kill - The number of points for each kill. (0-25)
+//gts teamKillPunishCount "3"                   // Kick constant Team killers out of your server. 
+
+gts gameAdvertisementRuleScorePercent "15"
+gts gameAdvertisementRuleTimeLeft "2"
+gts gameAdvertisementRuleRound "0"
+gts gameAdvertisementRuleRoundsWon "0"
+
+//Unsure about this. Maybe someone figure out what restricted items of each weapon is..Would be useful for other game modes..
+//Please PR on Github if you have a list! 
+
+// SNIPER ONLY
+
+// Unknown items restrictions
+gts restrictedItems            0            1
+gts restrictedItems            4            1
+gts restrictedItems            5            1
+gts restrictedItems            6            1
+gts restrictedItems            9            1
+gts restrictedItems            49           1
+gts restrictedItems            55           1
+gts restrictedItems            60           1
+gts restrictedItems            69           1
+gts restrictedItems            73           1
+gts restrictedItems            79           1
+gts restrictedItems            93           1
+gts restrictedItems            100          1
+gts restrictedItems            101          1
+gts restrictedItems            102          1
+gts restrictedItems            104          1
+gts restrictedItems            106          1
+gts restrictedItems            107          1
+gts restrictedItems            131          1
+gts restrictedItems            132          1
+gts restrictedItems            133          1
+gts restrictedItems            134          1
+gts restrictedItems            135          1
+gts restrictedItems            136          1
+gts restrictedItems            137          1
+gts restrictedItems            138          1
+gts restrictedItems            139          1
+gts restrictedItems            140          1
+gts restrictedItems            141          1
+gts restrictedItems            142          1
+gts restrictedItems            143          1
+gts restrictedItems            144          1
+gts restrictedItems            145          1
+gts restrictedItems            146          1
+
+// Submachine guns restrictions
+gts restrictedItems            10           1     // kuda
+gts restrictedItems            11           1     // pharo
+gts restrictedItems            12           1     // vesper
+gts restrictedItems            13           1     // razorback
+gts restrictedItems            14           1     // vmp
+gts restrictedItems            15           1     // weevil 
+gts restrictedItems            16           1     // AK-74u
+gts restrictedItems            17           1     // HG40
+gts restrictedItems            18           1     // HLX4 
+gts restrictedItems            19           1     // nail gun
+gts restrictedItems            34           1     // xmc
+gts restrictedItems            38           1     // ppsh
+gts restrictedItems            110          1     // sten
+
+// Assault rifles restrictions
+gts restrictedItems            7            1     // Peacekeeper MK2
+gts restrictedItems            20           1     // kn-44
+gts restrictedItems            21           1     // icr-1
+gts restrictedItems            22           1     // hvk-30
+gts restrictedItems            23           1     // man-o-war
+gts restrictedItems            24           1     // xr-2
+gts restrictedItems            25           1     // M8A7
+gts restrictedItems            26           1     // sheiva 
+gts restrictedItems            27           1     // kvk99m 
+gts restrictedItems            28           1     // MX Garand 
+gts restrictedItems            29           1     // FFAR
+gts restrictedItems            37           1     // M16
+gts restrictedItems            36           1     // LV8 Basilisk
+gts restrictedItems            126          1     // Galil
+gts restrictedItems            129          1     // M14
+
+// Machine guns restrictions
+gts restrictedItems            30           1     // Dingo 
+gts restrictedItems            31           1     // Dredge 
+gts restrictedItems            32           1     // BRM
+gts restrictedItems            33           1     // Gorgon 
+gts restrictedItems            35           1     // R70-Ajax 
+gts restrictedItems            128          1     // RPK
+
+// Shotguns restrictions
+gts restrictedItems            44           1     // Olympia
+gts restrictedItems            50           1     // Haymaker
+gts restrictedItems            51           1     // Argus
+gts restrictedItems            52           1     // KRM-262
+gts restrictedItems            53           1     // Brecci
+gts restrictedItems            56           1     // Banshii
+
+
+// Melee weapons restrictions
+gts restrictedItems            67           1     // fury's song
+gts restrictedItems            68           1     // Skull splitter
+gts restrictedItems            77           1     // Baseball bat
+gts restrictedItems            83           1     // Carver
+gts restrictedItems            84           1     // Malice
+gts restrictedItems            85           1     // Iron jim
+gts restrictedItems            94           1     // Slash N' Burn
+gts restrictedItems            95           1     // Brass knuckles
+gts restrictedItems            96           1     // Butterfly knife
+gts restrictedItems            97           1     // Wrench
+gts restrictedItems            99           1     // Combat nife
+gts restrictedItems            103          1     // Nightbreaker
+gts restrictedItems            105          1     // Buzzcut
+gts restrictedItems            108          1     // Enforcer
+gts restrictedItems            109          1     // Nunchucks
+gts restrictedItems            120          1     // Prizefighters
+gts restrictedItems            121          1     // Katana
+gts restrictedItems            122          1     // Ace of spades
+gts restrictedItems            124          1     // L3FT.E
+gts restrictedItems            125          1     // Bushwhacker
+gts restrictedItems            147          1     // Raven's eye
+
+
+// Special weapons restrictions
+gts restrictedItems            54           1     // NX-Shadowclaw
+gts restrictedItems            127          1     // Ballistic knife
+gts restrictedItems            123          1     // D13-Sector
+
+
+// Launchers restrictions
+gts restrictedItems            39           1     // Max-GL
+gts restrictedItems            57           1     // L4-Siege
+gts restrictedItems            58           1     // XM53
+gts restrictedItems            59           1     // Blackcell
+
+
+// Pistols restrictions
+gts restrictedItems            1            1     // MR6
+gts restrictedItems            2            1     // RK5 
+gts restrictedItems            3            1     // L-CAR 9
+gts restrictedItems            8            1     // Marshall 16
+gts restrictedItems            47           1     // Rift-E9
+gts restrictedItems            48           1     // 1911
+
+
+// Lethal specialists restrictions
+gts restrictedItems            111          1     // Scythe
+gts restrictedItems            112          1     // Tempest
+gts restrictedItems            113          1     // Gravity spikes
+gts restrictedItems            114          1     // Ripper
+gts restrictedItems            115          1     // Annihilator
+gts restrictedItems            116          1     // War machine
+gts restrictedItems            117          1     // Sparrow
+gts restrictedItems            118          1     // HIVE
+gts restrictedItems            119          1     // Purifier
+
+
+// Lethal grenades restrictions
+gts restrictedItems            61           1     // frag
+gts restrictedItems            62           1     // combat axe
+gts restrictedItems            63           1     // semtex
+gts restrictedItems            64           1     // c4
+gts restrictedItems            65           1     // trip mine
+gts restrictedItems            66           1     // thermite
+
+
+// Tactical grenades restrictions
+gts restrictedItems            70           1     // smoke screen
+gts restrictedItems            71           1     // concussion
+gts restrictedItems            72           1     // emp
+gts restrictedItems            74           1     // flash bang
+gts restrictedItems            75           1     // shock charge
+gts restrictedItems            76           1     // black hat
+gts restrictedItems            78           1     // trophy system
+
+
+// Sniper scope restrictions
+gts restrictedattachments 32 weaponindex 40 1     // Locus
+gts restrictedattachments 32 weaponindex 41 1     // Drakon
+gts restrictedattachments 32 weaponindex 42 1     // SVG-100
+gts restrictedattachments 32 weaponindex 43 1     // P0-6
+gts restrictedattachments 32 weaponindex 45 1     // Interdiction-RSA
+gts restrictedattachments 22 weaponindex 46 1     // DBSR -> 22 unknown scope id
+gts restrictedattachments 32 weaponindex 46 1     // DBSR no elo sight
+gts restrictedattachments 33 weaponindex 46 1     // DBSR -> 33 unknown scope id
+gts restrictedattachments 32 weaponindex 98 1     // XPR-50
+gts restrictedattachments 32 weaponindex 130 1    // Dragoon

cfg/t7x/gamesettings/mp/gamesettings_tdm.cfg

@@ -0,0 +1,50 @@
+//Don't touch the first 2 lines below here.
+exec "gamedata/gamesettings/mp/gamesettings_default.cfg" 
+exec "gamedata/configs/common/default_xboxlive.cfg"
+
+
+// Below this line you may uncomment the " // " commands and edit to your liking. 
+// If you unsure the default command. you can always " // " them back for later custom gameplay.
+
+gts prematchrequirement "0"                     // (0-10) Number of players on each team or the total number of players before the pre-match countdown will start.
+gts prematchrequirementtime "0"                 // (0-60) The amount of time before the match will start.
+gts prematchperiod "15"                         // The amount of time before the game starts.
+gts preroundperiod "5"                          // The amount of time before a round starts.
+gts inactivityKick "120"                        // Kick players that's AFK
+gts allowSpectating "1"                         // Allow players to spectate other players or CODcasting.
+gts spectateType "1"                            // 0 disabled, 1 team only, 2 freelook, 3 team only spectate splitscreen players only
+gts allowInGameTeamChange "1"                   // Allow players to switch teams?
+gts autoTeamBalance "1"                         // Automatically assign players to teams 
+gts allowFinalKillcam "1"                       // Controls whether the final killcam is played.
+
+gts timelimit "10"                              // Time limit of the game.
+gts scorelimit "100"                            // Score limit reach to end the game.
+gts teamCount "2"
+gts roundLimit "1"                              // The number of rounds that will be played before the game ends.
+
+//gts teamScorePerDeath "0"                     // Points per Death - The number of points your team loses for each death. Points can never be lower than zero. (0-25)
+//gts teamScorePerHeadshot "0"                  // Headshot Bonus Points - Extra points awarded if the kill is a headshot in addition to the points per kill. (0-25)
+//gts playerNumLives "0"                        // Number of Lives - The number of times each player can die before they are no longer allowed to respawn. (0-25)
+//gts loadoutKillstreaksEnabled "1"             // Disable Killstreaks by setting this to 0
+//gts perksEnabled "1"                          // Disable Perks by setting this to 0
+//gts disableVehicleSpawners "0"                // This should disable robots from the DLC map Rupture by setting this to 1 
+//gts disableweapondrop "0"                     // No weapons on the ground.
+//gts disallowprone "0"                         // Don't allow players to lay down.
+//gts allowHitMarkers "2"                       // Rather or not to show hitmakers?
+//gts allowAnnouncer "1"                        // Annouce enemy team actions
+
+//Hardcore Mode
+//gts hardcoreMode "1"                          // Enable hardcore mode. 
+//gts friendlyfiretype "1"                      // Enable or Disable Friendly Fire. 1 on, 2 reflect, 3 shared. 
+//gts playerHealthRegenTime "0"                 // Time it takes you to recover damage.
+//gts playerMaxHealth "30"                      // Percent of Health players will have on Respawn.
+//gts onlyHeadshots "0"                         // Headshots only
+//gts allowKillcam "0"                          // Allow Killcam.
+//gts allowbattlechatter "0"                    // Shut the fucking player dialogues up.
+//gts teamKillPointLoss "1"                     // Points per Kill - The number of points for each kill. (0-25)
+//gts teamKillPunishCount "3"                   // Kick constant Team killers out of your server. 
+
+gts gameAdvertisementRuleScorePercent "15"
+gts gameAdvertisementRuleTimeLeft "2"
+gts gameAdvertisementRuleRound "0"
+gts gameAdvertisementRuleRoundsWon "0"

cfg/t7x/gamesettings/zm/gamesettings_default.cfg

@@ -0,0 +1,104 @@
+
+gametype_setting     allowAnnouncer                          1
+gametype_setting     allowBattleChatter                      1
+gametype_setting     allowFinalKillcam                       1
+gametype_setting     allowHitMarkers                         2
+gametype_setting     allowInGameTeamChange                   0
+gametype_setting     allowKillcam                            1
+gametype_setting     allowSpectating                         0
+gametype_setting     autoDestroyTime                         0
+gametype_setting     autoTeamBalance                         0
+gametype_setting     bombTimer                               0
+gametype_setting     bulletDamageScalar                      1.0
+gametype_setting     captureTime                             10
+gametype_setting     crateCaptureTime                        3
+gametype_setting     cumulativeRoundScores                   0
+gametype_setting     deathPointLoss                          0
+gametype_setting     defuseTime                              0
+gametype_setting     delayPlayer                             0
+gametype_setting     destroyTime                             0
+gametype_setting     disableAmbientFx                        0
+gametype_setting     disableAttachments                      0
+gametype_setting     disableCAC                              1
+gametype_setting     disableContracts                        0
+gametype_setting     disableTacInsert                        0
+gametype_setting     disableweapondrop                       1
+gametype_setting     disallowaimslowdown                     0
+gametype_setting     disallowprone                           0
+gametype_setting     enemyCarrierVisible                     0
+gametype_setting     extraTime                               0
+gametype_setting     flagCaptureGracePeriod                  0
+gametype_setting     flagDecayTime                           0
+gametype_setting     flagRespawnTime                         0
+gametype_setting     forceRadar                              0
+gametype_setting     friendlyfiretype                        0
+gametype_setting     hardcoremode                            0
+gametype_setting     hotPotato                               0
+gametype_setting     idleFlagDecay                           0
+gametype_setting     idleFlagResetTime                       0
+gametype_setting     inactivityKick                          0
+gametype_setting     kothMode                                0
+gametype_setting     leaderBonus                             0
+gametype_setting     loadoutKillstreaksEnabled               1
+gametype_setting     maxObjectiveEventsPerMinute             0
+gametype_setting     maxPlayerDefensive                      0
+gametype_setting     maxPlayerEventsPerMinute                0
+gametype_setting     maxPlayerOffensive                      0
+gametype_setting     multiBomb                               0
+gametype_setting     objectiveSpawnTime                      0
+gametype_setting     onlyHeadshots                           0
+gametype_setting     perksEnabled                            0
+gametype_setting     plantTime                               0
+gametype_setting     playerForceRespawn                      1
+gametype_setting     playerHealthRegenTime                   5
+gametype_setting     playerKillsMax                          0
+gametype_setting     playerMaxHealth                         100
+gametype_setting     playerNumlives                          0
+gametype_setting     playerObjectiveHeldRespawnDelay         0
+gametype_setting     playerQueuedRespawn                     0
+gametype_setting     playerRespawnDelay                      0
+gametype_setting     playerSprintTime                        4
+gametype_setting     pregameAlwaysShowCACEdit                1
+gametype_setting     pregameAlwaysShowStreakEdit             1
+gametype_setting     pregameCACModifyTime                    0
+gametype_setting     pregameDraftEnabled                     0
+gametype_setting     pregameDraftRoundTime                   0
+gametype_setting     pregameItemMaxVotes                     0
+gametype_setting     pregameItemVoteEnabled                  0
+gametype_setting     pregameItemVoteRoundTime                0
+gametype_setting     pregamePositionShuffleMethod            0
+gametype_setting     pregamePositionSortType                 0
+gametype_setting     pregamePostRoundTime                    0
+gametype_setting     pregamePostStageTime                    0
+gametype_setting     pregamePreStageTime                     0
+gametype_setting     pregameScorestreakModifyTime            0
+gametype_setting     randomObjectiveLocations                0
+gametype_setting     roundlimit                              1
+gametype_setting     roundStartExplosiveDelay                5
+gametype_setting     roundStartKillstreakDelay               0
+gametype_setting     roundswitch                             1  // rounds between switching teams
+gametype_setting     roundwinlimit                           0
+gametype_setting     scoreHeroPowerGainFactor                1.0
+gametype_setting     scoreHeroPowerTimeFactor                1.0
+gametype_setting     scorelimit                              100
+gametype_setting     spectateType                            1
+gametype_setting     teamCount                               1
+gametype_setting     teamKillPenalty                         2
+gametype_setting     teamKillPointLoss                       0
+gametype_setting     teamKillPunishCount                     3
+gametype_setting     teamKillReducedPenalty                  0.25
+gametype_setting     teamKillScore                           4
+gametype_setting     teamKillSpawnDelay                      20
+gametype_setting     timelimit                               10
+gametype_setting     totalKillsMax                           0
+gametype_setting     vehiclesEnabled                         1
+gametype_setting     vehiclesTimed                           1
+gametype_setting     voipDeadChatWithDead                    0
+gametype_setting     voipDeadChatWithTeam                    1
+gametype_setting     voipDeadHearAllLiving                   0
+gametype_setting     voipDeadHearKiller                      0
+gametype_setting     voipDeadHearTeamLiving                  1
+gametype_setting     voipEveryoneHearsEveryone               0
+gametype_setting     voipKillersHearVictim                   1
+gametype_setting     waverespawndelay                        0
+gametype_setting     zmDifficulty                            1

cfg/t7x/gamesettings/zm/gamesettings_zclassic.cfg

@@ -0,0 +1,12 @@
+gametype_setting     scorelimit                              7500
+gametype_setting     timelimit                               10
+gametype_setting     roundlimit                              1
+gametype_setting     playerNumlives                          0
+gametype_setting     playerrespawndelay                      0
+gametype_setting     waverespawndelay                        0
+gametype_setting     disableweapondrop                       1
+gametype_setting     allowAnnouncer                          0
+gametype_setting     startRound                              1
+gametype_setting     magic                                   1
+gametype_setting     headshotsonly                           0
+gametype_setting     allowdogs                               1

cfg/t7x/lobby_scripts/server_lobby_selector/__init__.lua

@@ -0,0 +1,71 @@
+Lobby.Process.CreateDedicatedModsLobby = function (controller, toTarget)
+	local lobby_mode = Engine.DvarString( nil, "sv_lobby_mode" )
+	if lobby_mode ~= "" then
+		if lobby_mode == "zm" then
+			toTarget = LobbyData.UITargets.UI_ZMLOBBYONLINECUSTOMGAME
+		elseif lobby_mode == "cp" then
+			toTarget = LobbyData.UITargets.UI_CPLOBBYONLINECUSTOMGAME
+		elseif lobby_mode == "cpzm" then
+			toTarget = LobbyData.UITargets.UI_CP2LOBBYONLINECUSTOMGAME
+		elseif lobby_mode == "fr" then
+			toTarget = LobbyData.UITargets.UI_FRLOBBYONLINEGAME
+			toTarget.maxClients = Engine.DvarInt( nil, "com_maxclients" )
+		elseif lobby_mode == "doa" then
+			toTarget = LobbyData.UITargets.UI_DOALOBBYONLINE
+		elseif lobby_mode == "mp" then
+			toTarget = LobbyData.UITargets.UI_MPLOBBYONLINEMODGAME
+		elseif lobby_mode == "arena" then
+			toTarget = LobbyData.UITargets.UI_MPLOBBYONLINEARENAGAME
+		end
+	end
+	local playlistID = Dvar.sv_playlist
+	Engine.SetPlaylistID(playlistID:get())
+	local lobbyInit = Lobby.Actions.ExecuteScript(function ()
+		Lobby.ProcessNavigate.SetupLobbyMapAndGameType(controller, toTarget)
+	end)
+	local setNetworkMode = Lobby.Actions.SetNetworkMode(controller, Enum.LobbyNetworkMode.LOBBY_NETWORKMODE_LIVE)
+	local lobbySettings = Lobby.Actions.LobbySettings(controller, toTarget)
+	local updateUI = Lobby.Actions.UpdateUI(controller, toTarget)
+	local createGameHost = Lobby.Actions.LobbyHostStart(controller, toTarget.mainMode, toTarget.lobbyType, toTarget.lobbyMode, toTarget.maxClients)
+	local lobbyAdvertise = Lobby.Actions.AdvertiseLobby(true)
+	local hostingEvent = Lobby.Actions.ExecuteScript(function ()
+		Engine.QoSProbeListenerEnable(toTarget.lobbyType, true)
+		Engine.SetDvar("live_dedicatedReady", 1)
+		Engine.RunPlaylistRules(controller)
+		Engine.RunPlaylistSettings(controller)
+		Lobby.Timer.HostingLobby({controller = controller, lobbyType = toTarget.lobbyType, mainMode = toTarget.mainMode, lobbyTimerType = toTarget.lobbyTimerType})
+		if Engine.DvarInt( nil, "sv_skip_lobby" ) == 1 then
+			-- Engine.ComError( Enum.errorCode.ERROR_SCRIPT, "Using sv_skip_lobby" )
+			local map_rotation_string = Engine.DvarString( nil, "sv_maprotation" )
+			if map_rotation_string ~= "" then 
+				local map_rotation_tokens = split_string( map_rotation_string, " " )
+				if map_rotation_tokens[ 1 ] == "gametype" then
+					Engine.Exec(0, "lobby_setgametype " .. map_rotation_tokens[ 2 ] )
+					-- Engine.ComError( Enum.errorCode.ERROR_SCRIPT, "Set gametype to " .. map_rotation_tokens[ 2 ] .. " based on map rotation" )
+					if map_rotation_tokens[ 3 ] == "map" then
+						Engine.Exec(0, "lobby_setmap " .. map_rotation_tokens[ 4 ] )
+						-- Engine.ComError( Enum.errorCode.ERROR_SCRIPT, "Set map to " .. map_rotation_tokens[ 4 ] .. " based on map rotation" )
+					end
+				end
+			end
+			Engine.Exec(0, "launchgame")
+		end
+	end)
+	Lobby.Process.AddActions(setNetworkMode, lobbySettings)
+	Lobby.Process.AddActions(lobbySettings, lobbyInit)
+	Lobby.Process.AddActions(lobbyInit, updateUI)
+	Lobby.Process.AddActions(updateUI, createGameHost)
+	Lobby.Process.AddActions(createGameHost, lobbyAdvertise)
+	Lobby.Process.AddActions(lobbyAdvertise, hostingEvent)
+	Lobby.Process.AddActions(hostingEvent, nil)
+	return {head = setNetworkMode, interrupt = Lobby.Interrupt.NONE, force = true, cancellable = true}
+end
+
+function split_string(str, delimiter)
+	local tokens = {}
+	local pattern = string.format("([^%s]+)", delimiter)
+	for token in string.gmatch(str, pattern) do
+	  table.insert(tokens, token)
+	end
+	return tokens
+  end

cfg/zone/server.cfg

@@ -0,0 +1,141 @@
+//////////////////////////////////////////////////
+///          T7x Server Configuration           //
+//////////////////////////////////////////////////
+
+//////////////////////////////////////////////////
+// SERVER NAME & COLORS TIPS                    //
+//////////////////////////////////////////////////
+//                                              //
+// ^1 Red                                       //
+// ^2 Green                                     //
+// ^3 Yellow                                    //
+// ^4 Blue                                      //
+// ^5 Cyan                                      //
+// ^6 Pink                                      //
+// ^7 White                                     //
+// ^8 Depends on the team colors playing.       //
+// ^9 Orange                                    //
+// ^0 Black                                     //
+//                                              //
+//////////////////////////////////////////////////
+
+set live_steam_server_name "Default T7x Server"                      // Sets the server hostname.
+set live_steam_server_description "My longest YEA T7x ever"          // Sets a server description visible on the serverlist
+
+//////////////////////////////////////////////////
+//         NON-GAMEPLAY CONFIGURATION           //
+//////////////////////////////////////////////////
+
+set com_maxclients "18"                         // Max players in your server.
+set rcon_password ""                            // Access to your server to change stuff remotely or ingame. (Empty = disabled)
+set g_password ""                               // Password Protected Server. Leave blank if you want players to join or set password if you want to keep public out.
+set sv_privateClients "0"                       // Maximum number of private clients allowed on the server (range 0-18 (clamped to sv_maxclients) )
+set sv_timeout "30"                             // Timeout time period. You will timeout after (30) seconds when attempting to connect or if you are getting connection interruptions
+set sv_reconnectlimit "3"                       // How many times you can try to reconnect
+set sv_pure "0"                                 // verifying cilent files
+set sv_floodProtect "1"                         // Chat Spam Protection
+set g_log "t7x/games_mp.log"                    // Gamelog filename. If you edit this, Make sure you change B3.xml if you have bigbrotherbot.
+set sv_lobby_mode "mp"                          // Sets the lobby type to multiplayer.
+set sv_skip_lobby "1"                           // Makes the server load the map immediately instead of waiting at the lobby. Turn this off if you want to use playlists instead(currently required for custom maps).
+set sv_lanonly "0"                              // Keep your server from bordcasting to the public list and Local LAN only.
+
+
+//////////////////////////////////////////////////
+//             BOT CONFIGURATION                //
+//////////////////////////////////////////////////
+
+set bot_maxallies "0"                           // Amount of Bots on the Friendly Team
+set bot_maxAxis "0"                             // Amount of Bots on the Enemy Team
+set bot_maxFree "0"                             // Bots free-for-all based modes? Untested.
+set bot_difficulty "1"                          // Bot Skill. (0 - Easy, 1 - Normal, 2 - Hard, 3 - Veteran)
+
+//////////////////////////////////////////////////
+//           BASE GAME CONFIGURATION            //
+//////////////////////////////////////////////////
+//                                              //
+//     dm          -      Free-for-all          //
+//     tdm         -      Team Deathmatch       //
+//     ball        -      Uplink                //
+//     sd          -      Search and Destroy    //
+//     sr          -      Search and Rescue     //
+//     dom         -      Domination            //
+//     dem         -      Demolition            //
+//     conf        -      Kill Confirmed        //
+//     ctf         -      Capture the Flag      //
+//     shrp        -      Sharpshooter          //
+//     gun         -      GunGame               //
+//     sas         -      Sticks and Stones     //
+//     koth        -      Hardpoint             //
+//     escort      -      Safeguard             //
+//     clean       -      Fracture              //
+//     prop        -      Prop Hunt             //
+//     infect      -      Infected              //
+//     sniperonly  -      Snipers Only          //
+//                                              //
+//////////////////////////////////////////////////
+
+exec "gamedata/gamesettings/mp/gamesettings_tdm.cfg"     // Change this to the gametype config of the mode you want to run (e.g. ../gamesettings_conf.cfg, ../gamesettings_escort.cfg)
+//set gametype "tdm"                                     // Set the gametype in the map rotation for now
+
+set scr_teambalance "1"                                  // Enable or Disable auto balance.
+set cg_thirdPerson "0"                                   // third-person mode
+set g_deadChat "0"                                       // Dead Players' Chat Messages can be seen by everyone
+
+/////////////////////////////////////////////////////
+//           MAP SHORT NAMES ROTATION LIST         //
+/////////////////////////////////////////////////////
+//                                                 //
+// * - Maps that support Prop Hunt                 //
+//                                                 //
+///////////Base Maps/////////////////////////////////
+//                                                 //
+//         Aquarium*     -     mp_biodome          //
+//         Breach        -     mp_spire            //
+//         Combine*      -     mp_sector           //
+//         Evac*         -     mp_apartments       //
+//         Exodus*       -     mp_chinatown        //
+//         Fringe*       -     mp_veiled           //
+//         Havoc         -     mp_havoc            //
+//         Hunted*       -     mp_ethiopia         //
+//         Infection*    -     mp_infection        //
+//         Metro         -     mp_metro            //
+//         Redwood*      -     mp_redwood          //
+//         Stronghold    -     mp_stronghold       //
+//         Nuk3town*     -     mp_nuketown_x       //
+//                                                 //
+///////////Awakening DLC/////////////////////////////
+//                                                 //
+//         Gauntlet      -     mp_crucible         //
+//         Rise          -     mp_rise             //
+//         Skyjacked     -     mp_skyjacked        //
+//         Splash        -     mp_waterpark        //
+//                                                 //
+///////////Eclipse DLC///////////////////////////////
+//                                                 //
+//         Knockout      -     mp_kung_fu          //
+//         Rift          -     mp_conduit          //
+//         Spire*        -     mp_aerospace        //
+//         Verge         -     mp_banzai           //
+//                                                 //
+///////////Descent DLC///////////////////////////////
+//                                                 //
+//         Berserk       -     mp_shrine           //
+//         Cryogen       -     mp_cryogen          //
+//         Empire        -     mp_rome             //
+//         Rumble        -     mp_arena            //
+//                                                 //
+///////////Salvation DLC/////////////////////////////
+//                                                 //
+//         Citadel       -     mp_ruins            //
+//         Micro         -     mp_miniature        //
+//         Outlaw        -     mp_western          //
+//         Rupture       -     mp_city             //
+//                                                 //
+///////////Bonus Maps////////////////////////////////
+//                                                 //
+//         Fringe Night  -     mp_veiled_heyday    //
+//         Redwood Snow  -     mp_redwood_ice      //
+//                                                 //
+/////////////////////////////////////////////////////
+
+set sv_maprotation "gametype tdm map mp_biodome map mp_spire map mp_sector map mp_apartments map mp_chinatown map mp_veiled map mp_havoc map mp_ethiopia map mp_infection map mp_metro map mp_redwood map mp_stronghold map mp_nuketown_x map mp_shrine map mp_ruins map mp_cryogen map mp_rome map mp_crucible map mp_kung_fu map mp_miniature map mp_western map mp_conduit map mp_rise map mp_arena map mp_city map mp_skyjacked map mp_aerospace map mp_waterpark map mp_banzai map mp_veiled_heyday map mp_redwood_ice"

cfg/zone/server_cp.cfg

@@ -0,0 +1,80 @@
+//////////////////////////////////////////////////
+///          T7x Server Configuration           //
+//////////////////////////////////////////////////
+
+//////////////////////////////////////////////////
+// SERVER NAME & COLORS TIPS                    //
+//////////////////////////////////////////////////
+//                                              //
+// ^1 Red                                       //
+// ^2 Green                                     //
+// ^3 Yellow                                    //
+// ^4 Blue                                      //
+// ^5 Cyan                                      //
+// ^6 Pink                                      //
+// ^7 White                                     //
+// ^8 Depends on the team colors playing.       //
+// ^9 Orange                                    //
+// ^0 Black                                     //
+//                                              //
+//////////////////////////////////////////////////
+
+set live_steam_server_name "Default T7x Campaign Server"                      // Sets the server hostname.
+set live_steam_server_description "My longest YEA T7x CAMPAIGN ever"          // Sets a server description visible on the serverlist
+
+//////////////////////////////////////////////////
+//         NON-GAMEPLAY CONFIGURATION           //
+//////////////////////////////////////////////////
+
+set com_maxclients "4"                          // Max players in your server.
+set lobby_min_players "1"                       // Minimum amount of players for the Match to start.
+set rcon_password ""                            // Access to your server to change stuff remotely or ingame. (Empty = disabled)
+set g_password ""                               // Password Protected Server. Leave blank if you want players to join or set password if you want to keep public out.
+set sv_privateClients "0"                       // Maximum number of private clients allowed on the server (range 0-18 (clamped to sv_maxclients) )
+set sv_timeout "30"                             // Timeout time period. You will timeout after (30) seconds when attempting to connect or if you are getting connection interruptions
+set sv_reconnectlimit "3"                       // How many times you can try to reconnect
+set sv_pure "0"                                 // verifying cilent files
+set sv_floodProtect "1"                         // Chat Spam Protection
+set g_log "t7x/games_cp.log"                    // Gamelog filename. If you edit this, Make sure you change B3.xml if you have bigbrotherbot.
+set sv_lobby_mode "cp"                          // Sets the lobby type to camapaign
+set sv_skip_lobby "1"                           // Makes the server load the map immediately instead of waiting at the lobby. Turn this off if you want to use playlists instead(currently required for custom maps).
+set sv_lanonly "0"                              // Keep your server from bordcasting to the public list and Local LAN only.
+
+//////////////////////////////////////////////////
+//           BASE GAME CONFIGURATION            //
+//////////////////////////////////////////////////
+
+exec "gamedata/gamesettings/cp/gamesettings_default.cfg"     // Leave this as is
+exec "gamedata/configs/common/default_xboxlive.cfg"          // Leave this as is
+exec "gamedata/gamesettings/cp/gamesettings_coop.cfg"        // Leave this as is
+
+set cg_thirdPerson "0"                                       // third-person mode
+set g_deadChat "0"                                           // Dead Players' Chat Messages can be seen by everyone
+
+//////////////////////////////////////////////////////////////
+//              MAP SHORT NAMES ROTATION LIST               // 
+//////////////////////////////////////////////////////////////
+//                                                          //
+///////Safehouses/////////////////////////////////////////////
+//                                                          //
+//     Mobile             -    cp_sh_mobile                 //
+//     Singapore          -    cp_sh_singapore              //
+//     Cairo              -    cp_sh_cairo                  //
+//                                                          //
+///////Missions///////////////////////////////////////////////
+//                                                          //
+//     Black Ops          -    cp_mi_eth_prologue           //
+//     New World          -    cp_mi_zurich_newworld        //
+//     In Darkness        -    cp_mi_sing_blackstation      //
+//     Provocation        -    cp_mi_sing_biodomes          //
+//     Hypocenter         -    cp_mi_sing_sgen              //
+//     Vengeance          -    cp_mi_sing_vengeance         //
+//     Rise & Fall        -    cp_mi_cairo_ramses           //
+//     Demon Within       -    cp_mi_cairo_infection        //
+//     Sand Castle        -    cp_mi_cairo_aquifer          //
+//     Lotus Towers       -    cp_mi_cairo_lotus            //
+//     Life               -    cp_mi_zurich_coalescence     //
+//                                                          //
+//////////////////////////////////////////////////////////////
+
+set sv_maprotation "gametype coop map cp_mi_eth_prologue"

cfg/zone/server_zm.cfg

@@ -0,0 +1,93 @@
+//////////////////////////////////////////////////
+///          T7x Server Configuration           //
+//////////////////////////////////////////////////
+
+//////////////////////////////////////////////////
+// SERVER NAME & COLORS TIPS                    //
+//////////////////////////////////////////////////
+//                                              //
+// ^1 Red                                       //
+// ^2 Green                                     //
+// ^3 Yellow                                    //
+// ^4 Blue                                      //
+// ^5 Cyan                                      //
+// ^6 Pink                                      //
+// ^7 White                                     //
+// ^8 Depends on the team colors playing.       //
+// ^9 Orange                                    //
+// ^0 Black                                     //
+//                                              //
+//////////////////////////////////////////////////
+
+set live_steam_server_name "Default T7x Zombies Server"                      // Sets the server hostname.
+set live_steam_server_description "My longest YEA T7x ZOMBIES ever"          // Sets a server description visible on the serverlist
+
+//////////////////////////////////////////////////
+//         NON-GAMEPLAY CONFIGURATION           //
+//////////////////////////////////////////////////
+
+set com_maxclients "4"                          // Max players in your server.
+set lobby_min_players "1"                       // Minimum amount of players for the Match to start.
+set rcon_password ""                            // Access to your server to change stuff remotely or ingame. (Empty = disabled)
+set g_password ""                               // Password Protected Server. Leave blank if you want players to join or set password if you want to keep public out.
+set sv_privateClients "0"                       // Maximum number of private clients allowed on the server (range 0-18 (clamped to sv_maxclients) )
+set sv_timeout "30"                             // Timeout time period. You will timeout after (30) seconds when attempting to connect or if you are getting connection interruptions
+set sv_reconnectlimit "3"                       // How many times you can try to reconnect
+set sv_pure "0"                                 // verifying cilent files
+set sv_floodProtect "1"                         // Chat Spam Protection
+set g_log "t7x/games_zm.log"                    // Gamelog filename. If you edit this, Make sure you change B3.xml if you have bigbrotherbot.
+set sv_lobby_mode "zm"                          // Sets the lobby type to zombies
+set sv_skip_lobby "1"                           // Makes the server load the map immediately instead of waiting at the lobby. Turn this off if you want to use playlists instead(currently required for custom maps).
+set sv_lanonly "0"                              // Keep your server from bordcasting to the public list and Local LAN only.
+
+//////////////////////////////////////////////////
+//           BASE GAME CONFIGURATION            //
+//////////////////////////////////////////////////
+
+exec "gamedata/gamesettings/zm/gamesettings_default.cfg"     // Leave this as is
+exec "gamedata/configs/common/default_xboxlive.cfg"          // Leave this as is
+exec "gamedata/gamesettings/zm/gamesettings_zclassic.cfg"    // Leave this as is
+
+set cg_thirdPerson "0"                                       // third-person mode
+set g_deadChat "0"                                           // Dead Players' Chat Messages can be seen by everyone
+set scr_firstGumFree "1"                                     // Price of first Gobblegum (1 = free, 0 = 500)
+
+///////////////////////////////////////////////////
+//         MAP SHORT NAMES ROTATION LIST         //
+///////////////////////////////////////////////////
+//                                               //
+/////////Base Maps/////////////////////////////////
+//                                               //
+//       Shadows of Evil    -   zm_zod           //
+//                                               //
+/////////Awakening DLC/////////////////////////////
+//                                               //
+//       Der Eisendrache    -   zm_castle        //
+//                                               //
+/////////Eclipse DLC///////////////////////////////
+//                                               //
+//       Zetsubou No Shima  -   zm_island        //
+//                                               //
+/////////Descent DLC///////////////////////////////
+//                                               //
+//       Gorod Krovi        -   zm_stalingrad    //
+//                                               //
+/////////Salvation DLC/////////////////////////////
+//                                               //
+//       Revelations        -   zm_genesis       //
+//                                               //
+/////////Zombies Chronicles DLC////////////////////
+//                                               //
+//       Ascension          -   zm_cosmodrome    //
+//       Kino der Toten     -   zm_theater       //
+//       Moon               -   zm_moon          //
+//       Nacht der Untoten  -   zm_prototype     //
+//       Origins            -   zm_tomb          //
+//       Shangri-La         -   zm_temple        //
+//       Shi No Numa        -   zm_sumpf         //
+//       The Giant          -   zm_factory       //
+//       Verrückt           -   zm_asylum        //
+//                                               //
+///////////////////////////////////////////////////
+
+set sv_maprotation "gametype zclassic map zm_tomb"

data/launcher/main.html

@@ -117,11 +117,9 @@
 
     <div class="content">
       <h1>
-        <span style="color: #f97316">B</span
-        ><span style="color: #ec511c">O</span
-        ><span style="color: #e53f21">I</span
-        ><span style="color: #e23623">I</span
-        ><span style="color: #dc2626">I</span>
+        <span style="color: #f97316">T</span
+        ><span style="color: #ec511c">7</span
+        ><span style="color: #e53f21">x</span>
       </h1>
       <div class="button" onclick="window.external.runGame()">Play</div>
       <div class="button" onclick="window.external.openUrl('https://bo3.eu')">

deps/asmjit/.github/ISSUE_TEMPLATE/01_bug_report.yml

@@ -0,0 +1,42 @@
+name: Bug Report
+description: File a bug report
+body:
+  - type: markdown
+    attributes:
+      value: |
+        Before you hit the submit button:
+          * Please see our [Contribution Guidelines](https://github.com/asmjit/asmjit/blob/master/CONTRIBUTING.md).
+          * Make sure that you use a recent AsmJit (master branch) before filing a bug report.
+          * Make sure that you use logging and error handling features to collect as much information as possible, if applicable.
+  - type: textarea
+    id: issue-description
+    attributes:
+      label: Issue Description
+      description: Please share a clear and concise description of the issue and optionally provide reproducibility information and output from AsmJit's logger.
+      placeholder: Description
+    validations:
+      required: true
+  - type: dropdown
+    id: operating-system
+    attributes:
+      label: Operating System
+      multiple: true
+      options:
+        - Not specified / possibly all
+        - Windows
+        - Linux
+        - Mac
+        - Android
+        - Other
+  - type: dropdown
+    id: target-architecture
+    attributes:
+      label: Architecture
+      multiple: true
+      options:
+        - Not specified
+        - X86 / X86_64
+        - AArch32
+        - AArch64
+        - RISC-V
+        - Other

deps/asmjit/.github/ISSUE_TEMPLATE/02_feature_request.yml

@@ -0,0 +1,18 @@
+name: Feature Request
+description: Request a new feature or enhancement
+labels: [enhancement]
+body:
+  - type: markdown
+    attributes:
+      value: |
+        Before you hit the submit button:
+          * Please see our [Contribution Guidelines](https://github.com/asmjit/asmjit/blob/master/CONTRIBUTING.md).
+          * Make sure that you use a recent AsmJit (master branch) before filing a feature request.
+  - type: textarea
+    id: issue-description
+    attributes:
+      label: Issue Description
+      description: Please share a clear and concise description of a new feature or enhancement.
+      placeholder: Description
+    validations:
+      required: true

deps/asmjit/.github/ISSUE_TEMPLATE/03_help_question.yml

@@ -0,0 +1,18 @@
+name: Help & Questions
+description: Ask a question or get help
+labels: [question]
+body:
+  - type: markdown
+    attributes:
+      value: |
+        Before you hit the submit button:
+          * Please see our [Contribution Guidelines](https://github.com/asmjit/asmjit/blob/master/CONTRIBUTING.md).
+          * [Gitter Chat](https://app.gitter.im/#/room/#asmjit:gitter.im) is usually faster to get answers.
+          * If you need a help, please include as much information as possible to make it clear what the intend is.
+  - type: textarea
+    id: issue-description
+    attributes:
+      label: Details
+      description: The description of the problem or question.
+    validations:
+      required: true

deps/asmjit/.github/ISSUE_TEMPLATE/99_other_issues.yml

@@ -0,0 +1,11 @@
+name: Other Issues
+description: Something that doesn't fit the other categories
+body:
+  - type: textarea
+    id: issue-description
+    attributes:
+      label: Issue Description
+      description: Please share a clear and concise description of the issue.
+      placeholder: Description
+    validations:
+      required: true

deps/asmjit/.github/workflows/build-config.json

@@ -1,7 +1,8 @@
 {
   "diagnostics": {
     "asan": { "definitions": ["ASMJIT_SANITIZE=address"] },
-    "ubsan": { "definitions": ["ASMJIT_SANITIZE=undefined"] }
+    "ubsan": { "definitions": ["ASMJIT_SANITIZE=undefined"] },
+    "msan": { "definitions": ["ASMJIT_SANITIZE=memory"] }
   },
 
   "valgrind_arguments": [
@@ -11,37 +12,14 @@
   ],
 
   "tests": [
-    {
-      "cmd": ["asmjit_test_unit", "--quick"],
-      "optional": true
-    },
-    {
-      "cmd": ["asmjit_test_assembler"],
-      "optional": true
-    },
-    {
-      "cmd": ["asmjit_test_assembler", "--validate"],
-      "optional": true
-    },
-    {
-      "cmd": ["asmjit_test_emitters"],
-      "optional": true
-    },
-    {
-      "cmd": ["asmjit_test_compiler"],
-      "optional": true
-    },
-    {
-      "cmd": ["asmjit_test_instinfo"],
-      "optional": true
-    },
-    {
-      "cmd": ["asmjit_test_x86_sections"],
-      "optional": true
-    },
-    {
-      "cmd": ["asmjit_test_perf", "--quick"],
-      "optional": true
-    }
+    { "optional": true, "cmd": ["asmjit_test_unit", "--quick"] },
+    { "optional": true, "cmd": ["asmjit_test_assembler"] },
+    { "optional": true, "cmd": ["asmjit_test_assembler", "--validate"] },
+    { "optional": true, "cmd": ["asmjit_test_emitters"] },
+    { "optional": true, "cmd": ["asmjit_test_execute"] },
+    { "optional": true, "cmd": ["asmjit_test_compiler"] },
+    { "optional": true, "cmd": ["asmjit_test_instinfo"] },
+    { "optional": true, "cmd": ["asmjit_test_x86_sections"] },
+    { "optional": true, "cmd": ["asmjit_test_perf", "--quick"] }
   ]
-}
+}

deps/asmjit/.github/workflows/build.yml

@@ -14,12 +14,12 @@ jobs:
 
     steps:
     - name: "Checkout"
-      uses: actions/checkout@v3
+      uses: actions/checkout@v4
 
     - name: "Setup node.js"
-      uses: actions/setup-node@v3
+      uses: actions/setup-node@v4
       with:
-        node-version: "16"
+        node-version: "*"
 
     - name: "Check Enumerations"
       run: |
@@ -31,127 +31,163 @@ jobs:
       fail-fast: false
       matrix:
         include:
-          - { title: "linux-lib"       , os: "ubuntu-latest" , cc: "clang"   , arch: "x64", build_type: "Debug"  , problem_matcher: "cpp" }
-          - { title: "macos-lib"       , os: "macos-latest"  , cc: "clang"   , arch: "x64", build_type: "Debug"  , problem_matcher: "cpp" }
-          - { title: "windows-lib"     , os: "windows-latest", cc: "vs2022"  , arch: "x64", build_type: "Debug"  , problem_matcher: "cpp" }
+          - { title: "diag-analyze"    , host: "ubuntu-latest" , arch: "x64"    , cc: "clang-18", conf: "Debug"  , diagnostics: "analyze-build" }
+          - { title: "diag-asan"       , host: "ubuntu-latest" , arch: "x64"    , cc: "clang-18", conf: "Release", diagnostics: "asan", defs: "ASMJIT_TEST=1" }
+          - { title: "diag-msan"       , host: "ubuntu-latest" , arch: "x64"    , cc: "clang-18", conf: "Release", diagnostics: "msan", defs: "ASMJIT_TEST=1" }
+          - { title: "diag-ubsan"      , host: "ubuntu-latest" , arch: "x64"    , cc: "clang-18", conf: "Release", diagnostics: "ubsan", defs: "ASMJIT_TEST=1" }
+          - { title: "diag-hardened"   , host: "ubuntu-latest" , arch: "x64"    , cc: "clang-18", conf: "Release", diagnostics: "hardened", defs: "ASMJIT_TEST=1" }
+          - { title: "diag-valgrind"   , host: "ubuntu-latest" , arch: "x64"    , cc: "clang-18", conf: "Release", diagnostics: "valgrind", defs: "ASMJIT_TEST=1" }
 
-          - { title: "diag-asan"       , os: "ubuntu-latest" , cc: "clang"   , arch: "x64", build_type: "Release", diagnostics: "address"  , defs: "ASMJIT_TEST=1" }
-          - { title: "diag-ubsan"      , os: "ubuntu-latest" , cc: "clang"   , arch: "x64", build_type: "Release", diagnostics: "undefined", defs: "ASMJIT_TEST=1" }
-          - { title: "diag-valgrind"   , os: "ubuntu-latest" , cc: "clang"   , arch: "x64", build_type: "Release", diagnostics: "valgrind" , defs: "ASMJIT_TEST=1" }
-          - { title: "diag-scan-build" , os: "ubuntu-latest" , cc: "clang"   , arch: "x64", build_type: "Debug"  , diagnostics: "scan-build" }
+          - { title: "no-deprecated"   , host: "ubuntu-latest" , arch: "x64"    , cc: "clang-18", conf: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_DEPRECATED=1" }
+          - { title: "no-intrinsics"   , host: "ubuntu-latest" , arch: "x64"    , cc: "clang-18", conf: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_INTRINSICS=1" }
+          - { title: "no-logging"      , host: "ubuntu-latest" , arch: "x64"    , cc: "clang-18", conf: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_LOGGING=1" }
+          - { title: "no-logging-text" , host: "ubuntu-latest" , arch: "x64"    , cc: "clang-18", conf: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_LOGGING=1,ASMJIT_NO_TEXT=1" }
+          - { title: "no-builder"      , host: "ubuntu-latest" , arch: "x64"    , cc: "clang-18", conf: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_BUILDER=1" }
+          - { title: "no-compiler"     , host: "ubuntu-latest" , arch: "x64"    , cc: "clang-18", conf: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_COMPILER=1" }
+          - { title: "no-introspection", host: "ubuntu-latest" , arch: "x64"    , cc: "clang-18", conf: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_COMPILER=1,ASMJIT_NO_INTROSPECTION=1" }
+          - { title: "no-jit"          , host: "ubuntu-latest" , arch: "x64"    , cc: "clang-18", conf: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_JIT=1" }
+          - { title: "no-validation"   , host: "ubuntu-latest" , arch: "x64"    , cc: "clang-18", conf: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_VALIDATION=1" }
+          - { title: "no-x86"          , host: "ubuntu-latest" , arch: "x64"    , cc: "clang-18", conf: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_X86=1" }
+          - { title: "no-aarch64"      , host: "ubuntu-latest" , arch: "x64"    , cc: "clang-18", conf: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_AARCH64=1" }
 
-          - { title: "no-deprecated"   , os: "ubuntu-latest" , cc: "clang"   , arch: "x64", build_type: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_DEPRECATED=1" }
-          - { title: "no-intrinsics"   , os: "ubuntu-latest" , cc: "clang"   , arch: "x64", build_type: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_INTRINSICS=1" }
-          - { title: "no-logging"      , os: "ubuntu-latest" , cc: "clang"   , arch: "x64", build_type: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_LOGGING=1" }
-          - { title: "no-logging-text" , os: "ubuntu-latest" , cc: "clang"   , arch: "x64", build_type: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_LOGGING=1,ASMJIT_NO_TEXT=1" }
-          - { title: "no-builder"      , os: "ubuntu-latest" , cc: "clang"   , arch: "x64", build_type: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_BUILDER=1" }
-          - { title: "no-compiler"     , os: "ubuntu-latest" , cc: "clang"   , arch: "x64", build_type: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_COMPILER=1" }
-          - { title: "no-jit"          , os: "ubuntu-latest" , cc: "clang"   , arch: "x64", build_type: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_JIT=1" }
-          - { title: "no-introspection", os: "ubuntu-latest" , cc: "clang"   , arch: "x64", build_type: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_INTROSPECTION=1" }
-          - { title: "no-validation"   , os: "ubuntu-latest" , cc: "clang"   , arch: "x64", build_type: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_VALIDATION=1" }
-          - { title: "no-x86"          , os: "ubuntu-latest" , cc: "clang"   , arch: "x64", build_type: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_X86=1" }
-          - { title: "no-aarch64"      , os: "ubuntu-latest" , cc: "clang"   , arch: "x64", build_type: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_AARCH64=1" }
+          - { title: "linux"           , host: "ubuntu-20.04"  , arch: "x86"    , cc: "gcc-7"   , conf: "Debug"  , defs: "ASMJIT_TEST=1" }
+          - { title: "linux"           , host: "ubuntu-20.04"  , arch: "x86"    , cc: "gcc-7"   , conf: "Release", defs: "ASMJIT_TEST=1" }
+          - { title: "linux"           , host: "ubuntu-20.04"  , arch: "x64"    , cc: "gcc-7"   , conf: "Debug"  , defs: "ASMJIT_TEST=1" }
+          - { title: "linux"           , host: "ubuntu-20.04"  , arch: "x64"    , cc: "gcc-7"   , conf: "Release", defs: "ASMJIT_TEST=1" }
+          - { title: "linux"           , host: "ubuntu-20.04"  , arch: "x86"    , cc: "gcc-8"   , conf: "Debug"  , defs: "ASMJIT_TEST=1" }
+          - { title: "linux"           , host: "ubuntu-20.04"  , arch: "x86"    , cc: "gcc-8"   , conf: "Release", defs: "ASMJIT_TEST=1" }
+          - { title: "linux"           , host: "ubuntu-20.04"  , arch: "x64"    , cc: "gcc-8"   , conf: "Debug"  , defs: "ASMJIT_TEST=1" }
+          - { title: "linux"           , host: "ubuntu-20.04"  , arch: "x64"    , cc: "gcc-8"   , conf: "Release", defs: "ASMJIT_TEST=1" }
+          - { title: "linux"           , host: "ubuntu-22.04"  , arch: "x86"    , cc: "gcc-9"   , conf: "Debug"  , defs: "ASMJIT_TEST=1" }
+          - { title: "linux"           , host: "ubuntu-22.04"  , arch: "x86"    , cc: "gcc-9"   , conf: "Release", defs: "ASMJIT_TEST=1" }
+          - { title: "linux"           , host: "ubuntu-22.04"  , arch: "x64"    , cc: "gcc-9"   , conf: "Debug"  , defs: "ASMJIT_TEST=1" }
+          - { title: "linux"           , host: "ubuntu-22.04"  , arch: "x64"    , cc: "gcc-9"   , conf: "Release", defs: "ASMJIT_TEST=1" }
+          - { title: "linux"           , host: "ubuntu-22.04"  , arch: "x86"    , cc: "gcc-10"  , conf: "Debug"  , defs: "ASMJIT_TEST=1" }
+          - { title: "linux"           , host: "ubuntu-22.04"  , arch: "x86"    , cc: "gcc-10"  , conf: "Release", defs: "ASMJIT_TEST=1" }
+          - { title: "linux"           , host: "ubuntu-22.04"  , arch: "x64"    , cc: "gcc-10"  , conf: "Debug"  , defs: "ASMJIT_TEST=1" }
+          - { title: "linux"           , host: "ubuntu-22.04"  , arch: "x64"    , cc: "gcc-10"  , conf: "Release", defs: "ASMJIT_TEST=1" }
+          - { title: "linux"           , host: "ubuntu-22.04"  , arch: "x86"    , cc: "gcc-11"  , conf: "Debug"  , defs: "ASMJIT_TEST=1" }
+          - { title: "linux"           , host: "ubuntu-22.04"  , arch: "x86"    , cc: "gcc-11"  , conf: "Release", defs: "ASMJIT_TEST=1" }
+          - { title: "linux"           , host: "ubuntu-22.04"  , arch: "x64"    , cc: "gcc-11"  , conf: "Debug"  , defs: "ASMJIT_TEST=1" }
+          - { title: "linux"           , host: "ubuntu-22.04"  , arch: "x64"    , cc: "gcc-11"  , conf: "Release", defs: "ASMJIT_TEST=1" }
+          - { title: "linux"           , host: "ubuntu-22.04"  , arch: "x86"    , cc: "gcc-12"  , conf: "Debug"  , defs: "ASMJIT_TEST=1" }
+          - { title: "linux"           , host: "ubuntu-22.04"  , arch: "x86"    , cc: "gcc-12"  , conf: "Release", defs: "ASMJIT_TEST=1" }
+          - { title: "linux"           , host: "ubuntu-22.04"  , arch: "x64"    , cc: "gcc-12"  , conf: "Debug"  , defs: "ASMJIT_TEST=1" }
+          - { title: "linux"           , host: "ubuntu-22.04"  , arch: "x64"    , cc: "gcc-12"  , conf: "Release", defs: "ASMJIT_TEST=1" }
+          - { title: "linux"           , host: "ubuntu-22.04"  , arch: "x86"    , cc: "gcc-13"  , conf: "Debug"  , defs: "ASMJIT_TEST=1" }
+          - { title: "linux"           , host: "ubuntu-22.04"  , arch: "x86"    , cc: "gcc-13"  , conf: "Release", defs: "ASMJIT_TEST=1" }
+          - { title: "linux"           , host: "ubuntu-22.04"  , arch: "x64"    , cc: "gcc-13"  , conf: "Debug"  , defs: "ASMJIT_TEST=1" }
+          - { title: "linux"           , host: "ubuntu-22.04"  , arch: "x64"    , cc: "gcc-13"  , conf: "Release", defs: "ASMJIT_TEST=1" }
+          - { title: "linux"           , host: "ubuntu-20.04"  , arch: "x86"    , cc: "clang-10", conf: "Debug"  , defs: "ASMJIT_TEST=1" }
+          - { title: "linux"           , host: "ubuntu-20.04"  , arch: "x86"    , cc: "clang-10", conf: "Release", defs: "ASMJIT_TEST=1" }
+          - { title: "linux"           , host: "ubuntu-20.04"  , arch: "x64"    , cc: "clang-10", conf: "Debug"  , defs: "ASMJIT_TEST=1" }
+          - { title: "linux"           , host: "ubuntu-20.04"  , arch: "x64"    , cc: "clang-10", conf: "Release", defs: "ASMJIT_TEST=1" }
+          - { title: "linux"           , host: "ubuntu-22.04"  , arch: "x86"    , cc: "clang-11", conf: "Debug"  , defs: "ASMJIT_TEST=1" }
+          - { title: "linux"           , host: "ubuntu-22.04"  , arch: "x86"    , cc: "clang-11", conf: "Release", defs: "ASMJIT_TEST=1" }
+          - { title: "linux"           , host: "ubuntu-22.04"  , arch: "x64"    , cc: "clang-11", conf: "Debug"  , defs: "ASMJIT_TEST=1" }
+          - { title: "linux"           , host: "ubuntu-22.04"  , arch: "x64"    , cc: "clang-11", conf: "Release", defs: "ASMJIT_TEST=1" }
+          - { title: "linux"           , host: "ubuntu-22.04"  , arch: "x86"    , cc: "clang-12", conf: "Debug"  , defs: "ASMJIT_TEST=1" }
+          - { title: "linux"           , host: "ubuntu-22.04"  , arch: "x86"    , cc: "clang-12", conf: "Release", defs: "ASMJIT_TEST=1" }
+          - { title: "linux"           , host: "ubuntu-22.04"  , arch: "x64"    , cc: "clang-12", conf: "Debug"  , defs: "ASMJIT_TEST=1" }
+          - { title: "linux"           , host: "ubuntu-22.04"  , arch: "x64"    , cc: "clang-12", conf: "Release", defs: "ASMJIT_TEST=1" }
+          - { title: "linux"           , host: "ubuntu-22.04"  , arch: "x86"    , cc: "clang-13", conf: "Debug"  , defs: "ASMJIT_TEST=1" }
+          - { title: "linux"           , host: "ubuntu-22.04"  , arch: "x86"    , cc: "clang-13", conf: "Release", defs: "ASMJIT_TEST=1" }
+          - { title: "linux"           , host: "ubuntu-22.04"  , arch: "x64"    , cc: "clang-13", conf: "Debug"  , defs: "ASMJIT_TEST=1" }
+          - { title: "linux"           , host: "ubuntu-22.04"  , arch: "x64"    , cc: "clang-13", conf: "Release", defs: "ASMJIT_TEST=1" }
+          - { title: "linux"           , host: "ubuntu-22.04"  , arch: "x86"    , cc: "clang-14", conf: "Debug"  , defs: "ASMJIT_TEST=1" }
+          - { title: "linux"           , host: "ubuntu-22.04"  , arch: "x86"    , cc: "clang-14", conf: "Release", defs: "ASMJIT_TEST=1" }
+          - { title: "linux"           , host: "ubuntu-22.04"  , arch: "x64"    , cc: "clang-14", conf: "Debug"  , defs: "ASMJIT_TEST=1" }
+          - { title: "linux"           , host: "ubuntu-22.04"  , arch: "x64"    , cc: "clang-14", conf: "Release", defs: "ASMJIT_TEST=1" }
+          - { title: "linux"           , host: "ubuntu-22.04"  , arch: "x86"    , cc: "clang-15", conf: "Debug"  , defs: "ASMJIT_TEST=1" }
+          - { title: "linux"           , host: "ubuntu-22.04"  , arch: "x86"    , cc: "clang-15", conf: "Release", defs: "ASMJIT_TEST=1" }
+          - { title: "linux"           , host: "ubuntu-22.04"  , arch: "x64"    , cc: "clang-15", conf: "Debug"  , defs: "ASMJIT_TEST=1" }
+          - { title: "linux"           , host: "ubuntu-22.04"  , arch: "x64"    , cc: "clang-15", conf: "Release", defs: "ASMJIT_TEST=1" }
+          - { title: "linux"           , host: "ubuntu-22.04"  , arch: "x86"    , cc: "clang-16", conf: "Debug"  , defs: "ASMJIT_TEST=1" }
+          - { title: "linux"           , host: "ubuntu-22.04"  , arch: "x86"    , cc: "clang-16", conf: "Release", defs: "ASMJIT_TEST=1" }
+          - { title: "linux"           , host: "ubuntu-22.04"  , arch: "x64"    , cc: "clang-16", conf: "Debug"  , defs: "ASMJIT_TEST=1" }
+          - { title: "linux"           , host: "ubuntu-22.04"  , arch: "x64"    , cc: "clang-16", conf: "Release", defs: "ASMJIT_TEST=1" }
+          - { title: "linux"           , host: "ubuntu-22.04"  , arch: "x86"    , cc: "clang-17", conf: "Debug"  , defs: "ASMJIT_TEST=1" }
+          - { title: "linux"           , host: "ubuntu-22.04"  , arch: "x86"    , cc: "clang-17", conf: "Release", defs: "ASMJIT_TEST=1" }
+          - { title: "linux"           , host: "ubuntu-22.04"  , arch: "x64"    , cc: "clang-17", conf: "Debug"  , defs: "ASMJIT_TEST=1" }
+          - { title: "linux"           , host: "ubuntu-22.04"  , arch: "x64"    , cc: "clang-17", conf: "Release", defs: "ASMJIT_TEST=1" }
+          - { title: "linux"           , host: "ubuntu-22.04"  , arch: "x86"    , cc: "clang-18", conf: "Debug"  , defs: "ASMJIT_TEST=1" }
+          - { title: "linux"           , host: "ubuntu-22.04"  , arch: "x86"    , cc: "clang-18", conf: "Release", defs: "ASMJIT_TEST=1" }
+          - { title: "linux"           , host: "ubuntu-22.04"  , arch: "x64"    , cc: "clang-18", conf: "Debug"  , defs: "ASMJIT_TEST=1" }
+          - { title: "linux"           , host: "ubuntu-22.04"  , arch: "x64"    , cc: "clang-18", conf: "Release", defs: "ASMJIT_TEST=1" }
+          - { title: "macos"           , host: "macos-12"      , arch: "x64"    , cc: "gcc-11"  , conf: "Debug"  , defs: "ASMJIT_TEST=1" }
+          - { title: "macos"           , host: "macos-12"      , arch: "x64"    , cc: "gcc-11"  , conf: "Release", defs: "ASMJIT_TEST=1" }
+          - { title: "macos"           , host: "macos-12"      , arch: "x64"    , cc: "clang"   , conf: "Debug"  , defs: "ASMJIT_TEST=1" }
+          - { title: "macos"           , host: "macos-12"      , arch: "x64"    , cc: "clang"   , conf: "Release", defs: "ASMJIT_TEST=1" }
+          - { title: "macos"           , host: "macos-14"      , arch: "arm64"  , cc: "clang"   , conf: "Debug"  , defs: "ASMJIT_TEST=1" }
+          - { title: "macos"           , host: "macos-14"      , arch: "arm64"  , cc: "clang"   , conf: "Release", defs: "ASMJIT_TEST=1" }
+          - { title: "windows"         , host: "windows-2019"  , arch: "x86"    , cc: "vs2019"  , conf: "Debug"  , defs: "ASMJIT_TEST=1" }
+          - { title: "windows"         , host: "windows-2019"  , arch: "x86"    , cc: "vs2019"  , conf: "Release", defs: "ASMJIT_TEST=1" }
+          - { title: "windows"         , host: "windows-2019"  , arch: "x64"    , cc: "vs2019"  , conf: "Debug"  , defs: "ASMJIT_TEST=1" }
+          - { title: "windows"         , host: "windows-2019"  , arch: "x64"    , cc: "vs2019"  , conf: "Release", defs: "ASMJIT_TEST=1" }
+          - { title: "windows"         , host: "windows-2022"  , arch: "x86"    , cc: "vs2022"  , conf: "Debug"  , defs: "ASMJIT_TEST=1" }
+          - { title: "windows"         , host: "windows-2022"  , arch: "x86"    , cc: "vs2022"  , conf: "Release", defs: "ASMJIT_TEST=1" }
+          - { title: "windows"         , host: "windows-2022"  , arch: "x64"    , cc: "vs2022"  , conf: "Debug"  , defs: "ASMJIT_TEST=1" }
+          - { title: "windows"         , host: "windows-2022"  , arch: "x64"    , cc: "vs2022"  , conf: "Release", defs: "ASMJIT_TEST=1" }
 
-          - { title: "linux"           , os: "ubuntu-20.04"  , cc: "gcc-7"   , arch: "x86", build_type: "Debug"  , defs: "ASMJIT_TEST=1" }
-          - { title: "linux"           , os: "ubuntu-20.04"  , cc: "gcc-7"   , arch: "x86", build_type: "Release", defs: "ASMJIT_TEST=1" }
-          - { title: "linux"           , os: "ubuntu-20.04"  , cc: "gcc-7"   , arch: "x64", build_type: "Debug"  , defs: "ASMJIT_TEST=1" }
-          - { title: "linux"           , os: "ubuntu-20.04"  , cc: "gcc-7"   , arch: "x64", build_type: "Release", defs: "ASMJIT_TEST=1" }
-          - { title: "linux"           , os: "ubuntu-20.04"  , cc: "gcc-8"   , arch: "x86", build_type: "Debug"  , defs: "ASMJIT_TEST=1" }
-          - { title: "linux"           , os: "ubuntu-20.04"  , cc: "gcc-8"   , arch: "x86", build_type: "Release", defs: "ASMJIT_TEST=1" }
-          - { title: "linux"           , os: "ubuntu-20.04"  , cc: "gcc-8"   , arch: "x64", build_type: "Debug"  , defs: "ASMJIT_TEST=1" }
-          - { title: "linux"           , os: "ubuntu-20.04"  , cc: "gcc-8"   , arch: "x64", build_type: "Release", defs: "ASMJIT_TEST=1" }
-          - { title: "linux"           , os: "ubuntu-22.04"  , cc: "gcc-9"   , arch: "x86", build_type: "Debug"  , defs: "ASMJIT_TEST=1" }
-          - { title: "linux"           , os: "ubuntu-22.04"  , cc: "gcc-9"   , arch: "x86", build_type: "Release", defs: "ASMJIT_TEST=1" }
-          - { title: "linux"           , os: "ubuntu-22.04"  , cc: "gcc-9"   , arch: "x64", build_type: "Debug"  , defs: "ASMJIT_TEST=1" }
-          - { title: "linux"           , os: "ubuntu-22.04"  , cc: "gcc-9"   , arch: "x64", build_type: "Release", defs: "ASMJIT_TEST=1" }
-          - { title: "linux"           , os: "ubuntu-22.04"  , cc: "gcc-10"  , arch: "x86", build_type: "Debug"  , defs: "ASMJIT_TEST=1" }
-          - { title: "linux"           , os: "ubuntu-22.04"  , cc: "gcc-10"  , arch: "x86", build_type: "Release", defs: "ASMJIT_TEST=1" }
-          - { title: "linux"           , os: "ubuntu-22.04"  , cc: "gcc-10"  , arch: "x64", build_type: "Debug"  , defs: "ASMJIT_TEST=1" }
-          - { title: "linux"           , os: "ubuntu-22.04"  , cc: "gcc-10"  , arch: "x64", build_type: "Release", defs: "ASMJIT_TEST=1" }
-          - { title: "linux"           , os: "ubuntu-22.04"  , cc: "gcc-11"  , arch: "x86", build_type: "Debug"  , defs: "ASMJIT_TEST=1" }
-          - { title: "linux"           , os: "ubuntu-22.04"  , cc: "gcc-11"  , arch: "x86", build_type: "Release", defs: "ASMJIT_TEST=1" }
-          - { title: "linux"           , os: "ubuntu-22.04"  , cc: "gcc-11"  , arch: "x64", build_type: "Debug"  , defs: "ASMJIT_TEST=1" }
-          - { title: "linux"           , os: "ubuntu-22.04"  , cc: "gcc-11"  , arch: "x64", build_type: "Release", defs: "ASMJIT_TEST=1" }
-          - { title: "linux"           , os: "ubuntu-22.04"  , cc: "gcc-12"  , arch: "x86", build_type: "Debug"  , defs: "ASMJIT_TEST=1" }
-          - { title: "linux"           , os: "ubuntu-22.04"  , cc: "gcc-12"  , arch: "x86", build_type: "Release", defs: "ASMJIT_TEST=1" }
-          - { title: "linux"           , os: "ubuntu-22.04"  , cc: "gcc-12"  , arch: "x64", build_type: "Debug"  , defs: "ASMJIT_TEST=1" }
-          - { title: "linux"           , os: "ubuntu-22.04"  , cc: "gcc-12"  , arch: "x64", build_type: "Release", defs: "ASMJIT_TEST=1" }
-          - { title: "linux"           , os: "ubuntu-20.04"  , cc: "clang-10", arch: "x86", build_type: "Debug"  , defs: "ASMJIT_TEST=1" }
-          - { title: "linux"           , os: "ubuntu-20.04"  , cc: "clang-10", arch: "x86", build_type: "Release", defs: "ASMJIT_TEST=1" }
-          - { title: "linux"           , os: "ubuntu-20.04"  , cc: "clang-10", arch: "x64", build_type: "Debug"  , defs: "ASMJIT_TEST=1" }
-          - { title: "linux"           , os: "ubuntu-20.04"  , cc: "clang-10", arch: "x64", build_type: "Release", defs: "ASMJIT_TEST=1" }
-          - { title: "linux"           , os: "ubuntu-22.04"  , cc: "clang-11", arch: "x86", build_type: "Debug"  , defs: "ASMJIT_TEST=1" }
-          - { title: "linux"           , os: "ubuntu-22.04"  , cc: "clang-11", arch: "x86", build_type: "Release", defs: "ASMJIT_TEST=1" }
-          - { title: "linux"           , os: "ubuntu-22.04"  , cc: "clang-11", arch: "x64", build_type: "Debug"  , defs: "ASMJIT_TEST=1" }
-          - { title: "linux"           , os: "ubuntu-22.04"  , cc: "clang-11", arch: "x64", build_type: "Release", defs: "ASMJIT_TEST=1" }
-          - { title: "linux"           , os: "ubuntu-22.04"  , cc: "clang-12", arch: "x86", build_type: "Debug"  , defs: "ASMJIT_TEST=1" }
-          - { title: "linux"           , os: "ubuntu-22.04"  , cc: "clang-12", arch: "x86", build_type: "Release", defs: "ASMJIT_TEST=1" }
-          - { title: "linux"           , os: "ubuntu-22.04"  , cc: "clang-12", arch: "x64", build_type: "Debug"  , defs: "ASMJIT_TEST=1" }
-          - { title: "linux"           , os: "ubuntu-22.04"  , cc: "clang-12", arch: "x64", build_type: "Release", defs: "ASMJIT_TEST=1" }
-          - { title: "linux"           , os: "ubuntu-22.04"  , cc: "clang-13", arch: "x86", build_type: "Debug"  , defs: "ASMJIT_TEST=1" }
-          - { title: "linux"           , os: "ubuntu-22.04"  , cc: "clang-13", arch: "x86", build_type: "Release", defs: "ASMJIT_TEST=1" }
-          - { title: "linux"           , os: "ubuntu-22.04"  , cc: "clang-13", arch: "x64", build_type: "Debug"  , defs: "ASMJIT_TEST=1" }
-          - { title: "linux"           , os: "ubuntu-22.04"  , cc: "clang-13", arch: "x64", build_type: "Release", defs: "ASMJIT_TEST=1" }
-          - { title: "linux"           , os: "ubuntu-22.04"  , cc: "clang-14", arch: "x86", build_type: "Debug"  , defs: "ASMJIT_TEST=1" }
-          - { title: "linux"           , os: "ubuntu-22.04"  , cc: "clang-14", arch: "x86", build_type: "Release", defs: "ASMJIT_TEST=1" }
-          - { title: "linux"           , os: "ubuntu-22.04"  , cc: "clang-14", arch: "x64", build_type: "Debug"  , defs: "ASMJIT_TEST=1" }
-          - { title: "linux"           , os: "ubuntu-22.04"  , cc: "clang-14", arch: "x64", build_type: "Release", defs: "ASMJIT_TEST=1" }
-          - { title: "macos"           , os: "macos-12"      , cc: "gcc-11"  , arch: "x64", build_type: "Debug"  , defs: "ASMJIT_TEST=1" }
-          - { title: "macos"           , os: "macos-12"      , cc: "gcc-11"  , arch: "x64", build_type: "Release", defs: "ASMJIT_TEST=1" }
-          - { title: "macos"           , os: "macos-12"      , cc: "clang"   , arch: "x64", build_type: "Debug"  , defs: "ASMJIT_TEST=1" }
-          - { title: "macos"           , os: "macos-12"      , cc: "clang"   , arch: "x64", build_type: "Release", defs: "ASMJIT_TEST=1" }
-          - { title: "windows"         , os: "windows-2019"  , cc: "vs2019"  , arch: "x86", build_type: "Debug"  , defs: "ASMJIT_TEST=1" }
-          - { title: "windows"         , os: "windows-2019"  , cc: "vs2019"  , arch: "x86", build_type: "Release", defs: "ASMJIT_TEST=1" }
-          - { title: "windows"         , os: "windows-2019"  , cc: "vs2019"  , arch: "x64", build_type: "Debug"  , defs: "ASMJIT_TEST=1" }
-          - { title: "windows"         , os: "windows-2019"  , cc: "vs2019"  , arch: "x64", build_type: "Release", defs: "ASMJIT_TEST=1" }
-          - { title: "windows"         , os: "windows-2022"  , cc: "vs2022"  , arch: "x86", build_type: "Debug"  , defs: "ASMJIT_TEST=1" }
-          - { title: "windows"         , os: "windows-2022"  , cc: "vs2022"  , arch: "x86", build_type: "Release", defs: "ASMJIT_TEST=1" }
-          - { title: "windows"         , os: "windows-2022"  , cc: "vs2022"  , arch: "x64", build_type: "Debug"  , defs: "ASMJIT_TEST=1" }
-          - { title: "windows"         , os: "windows-2022"  , cc: "vs2022"  , arch: "x64", build_type: "Release", defs: "ASMJIT_TEST=1" }
+          - { title: "freebsd"         , host: "macos-12"      , arch: "x86-64" , cc: "clang"   , conf: "Release", vm: "freebsd", vm_ver: "13.2", defs: "ASMJIT_TEST=1" }
+          - { title: "netbsd"          , host: "macos-12"      , arch: "x86-64" , cc: "clang"   , conf: "Release", vm: "netbsd" , vm_ver: "9.3" , defs: "ASMJIT_TEST=1" }
+          - { title: "openbsd"         , host: "macos-12"      , arch: "x86-64" , cc: "clang"   , conf: "Release", vm: "openbsd", vm_ver: "7.4" , defs: "ASMJIT_TEST=1" }
+          - { title: "openbsd"         , host: "ubuntu-latest" , arch: "arm64"  , cc: "clang"   , conf: "Release", vm: "openbsd", vm_ver: "7.4" , defs: "ASMJIT_TEST=1" }
 
-          - { host: "macos-12"         , os: "freebsd", osver: "13.2", cc: "clang", arch: "x86-64", build_type: "Release", defs: "ASMJIT_TEST=ON" }
-          - { host: "macos-12"         , os: "netbsd" , osver: "9.3" , cc: "clang", arch: "x86-64", build_type: "Release", defs: "ASMJIT_TEST=ON" }
-          - { host: "macos-12"         , os: "openbsd", osver: "7.3" , cc: "clang", arch: "x86-64", build_type: "Release", defs: "ASMJIT_TEST=ON" }
-          - { host: "ubuntu-latest"    , os: "openbsd", osver: "7.3" , cc: "clang", arch: "arm64" , build_type: "Release", defs: "ASMJIT_TEST=ON" }
+          # arm/v7 VM image doesn't work on CI environment at the moment
+          # - { title: "debian"          , host: "ubuntu-latest" , arch: "arm/v7" , cc: "clang"   , conf: "Release", vm: "debian:unstable", defs: "ASMJIT_TEST=1" }
 
-    name: "${{matrix.title || format('{0}-{1}', matrix.os, matrix.osver)}} (${{matrix.cc}}, ${{matrix.arch}}, ${{matrix.build_type}})"
-    runs-on: "${{matrix.host || matrix.os}}"
+          - { title: "debian"          , host: "ubuntu-latest" , arch: "arm64"  , cc: "clang"   , conf: "Release", vm: "debian:unstable", defs: "ASMJIT_TEST=1" }
+          - { title: "debian"          , host: "ubuntu-latest" , arch: "riscv64", cc: "clang"   , conf: "Release", vm: "debian:unstable", defs: "ASMJIT_TEST=1" }
+          - { title: "debian"          , host: "ubuntu-latest" , arch: "ppc64le", cc: "clang"   , conf: "Release", vm: "debian:unstable", defs: "ASMJIT_TEST=1" }
+
+    name: "${{matrix.title}}/${{matrix.arch}}, ${{matrix.cc}} ${{matrix.conf}}"
+    runs-on: "${{matrix.host}}"
 
     steps:
       - name: "Checkout"
-        uses: actions/checkout@v3
+        uses: actions/checkout@v4
         with:
           path: "source"
 
       - name: "Checkout Build Actions"
-        uses: actions/checkout@v3
+        uses: actions/checkout@v4
         with:
           repository: build-actions/build-actions
           path: "build-actions"
 
       - name: "Python"
-        uses: actions/setup-python@v4
+        uses: actions/setup-python@v5
         with:
           python-version: "3.x"
 
-      - name: "Build & Test"
-        if: ${{!matrix.host}}
+      - name: QEMU
+        if: ${{matrix.vm && !matrix.vm_ver}}
+        uses: docker/setup-qemu-action@v3
+        with:
+          platforms: linux/${{matrix.arch}}
+
+      - name: "Build & Test - Native"
+        if: ${{!matrix.vm}}
         run: python build-actions/action.py
-               --step=all
-               --compiler=${{matrix.cc}}
-               --architecture=${{matrix.arch}}
                --source-dir=source
                --config=source/.github/workflows/build-config.json
-               --build-type=${{matrix.build_type}}
+               --compiler=${{matrix.cc}}
+               --diagnostics=${{matrix.diagnostics}}
+               --architecture=${{matrix.arch}}
+               --problem-matcher=auto
+               --build-type=${{matrix.conf}}
                --build-defs=${{matrix.defs}}
 
-      - name: "Build & Test in VM"
-        if: ${{matrix.host}}
+      - name: "Build & Test - Cross Platform Actions"
+        if: ${{matrix.vm && matrix.vm_ver}}
         uses: cross-platform-actions/action@master
         with:
-          operating_system: ${{matrix.os}}
+          operating_system: ${{matrix.vm}}
           architecture: ${{matrix.arch}}
-          version: ${{matrix.osver}}
+          version: ${{matrix.vm_ver}}
+          sync_files: "runner-to-vm"
+          shutdown_vm: false
           shell: bash
           run: |
             set -e
@@ -163,11 +199,31 @@ jobs:
             export CI_NETBSD_USE_PKGIN
 
             sh ./build-actions/prepare-environment.sh
-            python3 build-actions/action.py                       \
-              --step=all                                          \
-              --compiler=${{matrix.cc}}                           \
-              --architecture=${{matrix.arch}}                     \
-              --source-dir=source                                 \
-              --config=source/.github/workflows/build-config.json \
-              --build-type=${{matrix.build_type}}                 \
+            python3 build-actions/action.py                        \
+              --source-dir=source                                  \
+              --config=source/.github/workflows/build-config.json  \
+              --compiler=${{matrix.cc}}                            \
+              --diagnostics=${{matrix.diagnostics}}                \
+              --architecture=${{matrix.arch}}                      \
+              --problem-matcher=auto                               \
+              --build-type=${{matrix.conf}}                        \
               --build-defs=${{matrix.defs}}
+
+      - name: "Build & Test - Docker + QEMU"
+        if: ${{matrix.vm && !matrix.vm_ver}}
+        run: |
+          docker run                                               \
+            --rm                                                   \
+            -v $(pwd):/${{github.workspace}}                       \
+            -w ${{github.workspace}}/build-actions                 \
+            --platform linux/${{matrix.arch}}                      \
+            ${{matrix.vm}}                                         \
+            bash action.sh                                         \
+            --source-dir=../source                                 \
+            --config=../source/.github/workflows/build-config.json \
+            --compiler=${{matrix.cc}}                              \
+            --diagnostics=${{matrix.diagnostics}}                  \
+            --architecture=${{matrix.arch}}                        \
+            --problem-matcher=auto                                 \
+            --build-type=${{matrix.conf}}                          \
+            --build-defs=${{matrix.defs}}

deps/asmjit/CMakeLists.txt

@@ -1,12 +1,12 @@
-cmake_minimum_required(VERSION 3.5 FATAL_ERROR)
+cmake_minimum_required(VERSION 3.8 FATAL_ERROR)
 
 cmake_policy(PUSH)
 
-if(POLICY CMP0063)
+if (POLICY CMP0063)
   cmake_policy(SET CMP0063 NEW) # Honor visibility properties.
 endif()
 
-if(POLICY CMP0092)
+if (POLICY CMP0092)
   cmake_policy(SET CMP0092 NEW) # Don't add -W3 warning level by default.
 endif()
 
@@ -33,15 +33,13 @@ if (DEFINED ASMJIT_BUILD_STATIC)
   set(ASMJIT_STATIC "${ASMJIT_BUILD_STATIC}")
 endif()
 
-# AsmJit - Configuration
-# ======================
+# AsmJit - Configuration - Build
+# ==============================
 
-# AsmJit testing.
 if (NOT DEFINED ASMJIT_TEST)
   set(ASMJIT_TEST FALSE)
 endif()
 
-# AsmJit build options
 if (NOT DEFINED ASMJIT_EMBED)
   set(ASMJIT_EMBED FALSE)
 endif()
@@ -54,15 +52,22 @@ if (NOT DEFINED ASMJIT_SANITIZE)
   set(ASMJIT_SANITIZE FALSE)
 endif()
 
-if (NOT DEFINED ASMJIT_NO_NATVIS)
-  set(ASMJIT_NO_NATVIS FALSE)
-endif()
-
 if (NOT DEFINED ASMJIT_NO_CUSTOM_FLAGS)
   set(ASMJIT_NO_CUSTOM_FLAGS FALSE)
 endif()
 
-# AsmJit backends selection.
+if (NOT DEFINED ASMJIT_NO_NATVIS)
+  set(ASMJIT_NO_NATVIS FALSE)
+endif()
+
+# EMBED implies STATIC.
+if (ASMJIT_EMBED AND NOT ASMJIT_STATIC)
+  set(ASMJIT_STATIC TRUE)
+endif()
+
+# AsmJit - Configuration - Backend
+# ================================
+
 if (NOT DEFINED ASMJIT_NO_X86)
   set(ASMJIT_NO_X86 FALSE)
 endif()
@@ -75,7 +80,9 @@ if (NOT DEFINED ASMJIT_NO_FOREIGN)
   set(ASMJIT_NO_FOREIGN FALSE)
 endif()
 
-# AsmJit features selection.
+# AsmJit - Configuration - Features
+# =================================
+
 if (NOT DEFINED ASMJIT_NO_DEPRECATED)
   set(ASMJIT_NO_DEPRECATED FALSE)
 endif()
@@ -89,19 +96,19 @@ if (NOT DEFINED ASMJIT_NO_JIT)
 endif()
 
 if (NOT DEFINED ASMJIT_NO_TEXT)
-  set(ASMJIT_NO_TEXT ${ASMJIT_NO_TEXT})
+  set(ASMJIT_NO_TEXT FALSE)
 endif()
 
 if (NOT DEFINED ASMJIT_NO_LOGGING)
-  set(ASMJIT_NO_LOGGING FALSE)
+  set(ASMJIT_NO_LOGGING ${ASMJIT_NO_TEXT})
 endif()
 
 if (NOT DEFINED ASMJIT_NO_VALIDATION)
-  set(ASMJIT_NO_VALIDATION ${ASMJIT_NO_VALIDATION})
+  set(ASMJIT_NO_VALIDATION FALSE)
 endif()
 
 if (NOT DEFINED ASMJIT_NO_INTROSPECTION)
-  set(ASMJIT_NO_INTROSPECTION ${ASMJIT_NO_INTROSPECTION})
+  set(ASMJIT_NO_INTROSPECTION FALSE)
 endif()
 
 if (NOT DEFINED ASMJIT_NO_BUILDER)
@@ -109,16 +116,17 @@ if (NOT DEFINED ASMJIT_NO_BUILDER)
 endif()
 
 if (NOT DEFINED ASMJIT_NO_COMPILER)
-  set(ASMJIT_NO_BUILDER ${ASMJIT_NO_BUILDER})
+  if (ASMJIT_NO_BUILDER OR ASMJIT_NO_INTROSPECTION)
+    set(ASMJIT_NO_COMPILER TRUE)
+  else()
+    set(ASMJIT_NO_COMPILER FALSE)
+  endif()
 endif()
 
-# EMBED implies STATIC.
-if (ASMJIT_EMBED AND NOT ASMJIT_STATIC)
-  set(ASMJIT_STATIC TRUE)
-endif()
+# AsmJit - Configuration - CMake Introspection
+# ============================================
 
 set(ASMJIT_DIR              "${CMAKE_CURRENT_LIST_DIR}"  CACHE PATH "Location of 'asmjit'")
-
 set(ASMJIT_TEST             "${ASMJIT_TEST}"             CACHE BOOL "Build 'asmjit' test applications")
 set(ASMJIT_EMBED            "${ASMJIT_EMBED}"            CACHE BOOL "Embed 'asmjit' library (no targets)")
 set(ASMJIT_STATIC           "${ASMJIT_STATIC}"           CACHE BOOL "Build 'asmjit' library as static")
@@ -212,11 +220,7 @@ function(asmjit_add_target target target_type)
     set_property(TARGET ${target} APPEND_STRING PROPERTY LINK_FLAGS " ${link_flag}")
   endforeach()
 
-  if (${CMAKE_VERSION} VERSION_LESS "3.8.0")
-    set_property(TARGET ${target} PROPERTY CXX_STANDARD 11)
-  else()
-    target_compile_features(${target} PUBLIC cxx_std_11)
-  endif()
+  target_compile_features(${target} PUBLIC cxx_std_11)
   set_property(TARGET ${target} PROPERTY CXX_EXTENSIONS NO)
   set_property(TARGET ${target} PROPERTY CXX_VISIBILITY_PRESET hidden)
   target_compile_options(${target} PRIVATE ${X_CFLAGS} ${ASMJIT_SANITIZE_CFLAGS} $<$<CONFIG:Debug>:${X_CFLAGS_DBG}> $<$<NOT:$<CONFIG:Debug>>:${X_CFLAGS_REL}>)
@@ -229,17 +233,6 @@ endfunction()
 # AsmJit - Compiler Support
 # =========================
 
-set(ASMJIT_INCLUDE_DIRS "${ASMJIT_DIR}/src")     # Include directory is the same as source dir.
-set(ASMJIT_DEPS "")                              # AsmJit dependencies (libraries) for the linker.
-set(ASMJIT_LIBS "")                              # Dependencies of libs/apps that want to use AsmJit.
-set(ASMJIT_CFLAGS "")                            # Public compiler flags.
-set(ASMJIT_PRIVATE_CFLAGS "")                    # Private compiler flags independent of build type.
-set(ASMJIT_PRIVATE_CFLAGS_DBG "")                # Private compiler flags used by debug builds.
-set(ASMJIT_PRIVATE_CFLAGS_REL "")                # Private compiler flags used by release builds.
-set(ASMJIT_PRIVATE_LFLAGS "")                    # Private linker flags.
-set(ASMJIT_SANITIZE_CFLAGS "")                   # Compiler flags required by currently enabled sanitizers.
-set(ASMJIT_SANITIZE_LFLAGS "")                   # Linker flags required by currently enabled sanitizers.
-
 # We will have to keep this most likely forever as some users may still be using it.
 set(ASMJIT_INCLUDE_DIR "${ASMJIT_INCLUDE_DIRS}")
 
@@ -282,7 +275,7 @@ endif()
 
 # Support for sanitizers.
 if (ASMJIT_SANITIZE)
-  ASMJIT_detect_sanitizers(ASMJIT_SANITIZE_CFLAGS ${ASMJIT_SANITIZE})
+  asmjit_detect_sanitizers(ASMJIT_SANITIZE_CFLAGS ${ASMJIT_SANITIZE})
   if (ASMJIT_SANITIZE_CFLAGS)
     message("-- Enabling sanitizers: '${ASMJIT_SANITIZE_CFLAGS}'")
 
@@ -363,21 +356,21 @@ else()
   set(ASMJIT_TARGET_TYPE "SHARED")
 endif()
 
-foreach(build_option ASMJIT_STATIC
+foreach(build_option # AsmJit build options.
+                     ASMJIT_STATIC
+                     ASMJIT_NO_DEPRECATED
                      # AsmJit backends selection.
                      ASMJIT_NO_X86
                      ASMJIT_NO_AARCH64
                      ASMJIT_NO_FOREIGN
                      # AsmJit features selection.
-                     ASMJIT_NO_DEPRECATED
-                     ASMJIT_NO_SHM_OPEN
                      ASMJIT_NO_JIT
                      ASMJIT_NO_TEXT
                      ASMJIT_NO_LOGGING
-                     ASMJIT_NO_BUILDER
-                     ASMJIT_NO_COMPILER
+                     ASMJIT_NO_INTROSPECTION
                      ASMJIT_NO_VALIDATION
-                     ASMJIT_NO_INTROSPECTION)
+                     ASMJIT_NO_BUILDER
+                     ASMJIT_NO_COMPILER)
   if (${build_option})
     List(APPEND ASMJIT_CFLAGS         "-D${build_option}")
     List(APPEND ASMJIT_PRIVATE_CFLAGS "-D${build_option}")
@@ -388,7 +381,7 @@ endforeach()
 # =======================
 
 if (WIN32)
-  if(CMAKE_LINKER MATCHES "link\\.exe" OR CMAKE_LINKER MATCHES "lld-link\\.exe")
+  if (CMAKE_LINKER MATCHES "link\\.exe" OR CMAKE_LINKER MATCHES "lld-link\\.exe")
     set(ASMJIT_LINKER_SUPPORTS_NATVIS TRUE)
   endif()
 endif()
@@ -443,6 +436,8 @@ set(ASMJIT_SRC_LIST
   asmjit/core/globals.h
   asmjit/core/inst.cpp
   asmjit/core/inst.h
+  asmjit/core/instdb.cpp
+  asmjit/core/instdb_p.h
   asmjit/core/jitallocator.cpp
   asmjit/core/jitallocator.h
   asmjit/core/jitruntime.cpp
@@ -562,9 +557,7 @@ foreach(src_file ${ASMJIT_SRC_LIST})
   endif()
 endforeach()
 
-if (NOT ${CMAKE_VERSION} VERSION_LESS "3.8.0")
-  source_group(TREE "${ASMJIT_DIR}" FILES ${ASMJIT_SRC})
-endif()
+source_group(TREE "${ASMJIT_DIR}" FILES ${ASMJIT_SRC})
 
 # AsmJit - Summary
 # ================
@@ -597,7 +590,7 @@ if (NOT ASMJIT_EMBED)
                              $<BUILD_INTERFACE:${ASMJIT_INCLUDE_DIRS}>
                              $<INSTALL_INTERFACE:${CMAKE_INSTALL_INCLUDEDIR}>)
 
-  # Add blend2d::blend2d alias.
+  # Add asmjit::asmjit alias.
   add_library(asmjit::asmjit ALIAS asmjit)
   # TODO: [CMAKE] Deprecated alias - we use projectname::libraryname convention now.
   add_library(AsmJit::AsmJit ALIAS asmjit)
@@ -662,6 +655,7 @@ if (NOT ASMJIT_EMBED)
                       CFLAGS_REL ${ASMJIT_PRIVATE_CFLAGS_REL})
 
     foreach(_target asmjit_test_emitters
+                    asmjit_test_execute
                     asmjit_test_x86_sections)
       asmjit_add_target(${_target} TEST
                         SOURCES    test/${_target}.cpp
@@ -682,11 +676,29 @@ if (NOT ASMJIT_EMBED)
 
     if (NOT (ASMJIT_NO_BUILDER OR ASMJIT_NO_COMPILER))
       # Vectorcall tests and XMM tests require at least SSE2 in 32-bit mode (in 64-bit mode it's implicit).
-      set(sse2_flags "")
-      if ("${CMAKE_CXX_COMPILER_ID}" STREQUAL "MSVC" OR "x${CMAKE_CXX_COMPILER_FRONTEND_VARIANT}" STREQUAL "xMSVC")
-        asmjit_detect_cflags(sse2_flags "-arch:SSE2")
-      else()
-        asmjit_detect_cflags(sse2_flags "-msse2")
+      # Some compilers don't like passing -msse2 for 64-bit targets, and some compilers targeting non-x86
+      # would pass "-msse2" compile flag check, but with a warning not detected by CMake. Thus, verify that
+      # our target is really 32-bit X86 and only use -msse2 or -arch:SSE2 flags when necessary.
+      set(ASMJIT_SSE2_CFLAGS "")
+
+      check_cxx_source_compiles("
+        #if defined(_M_IX86) || defined(__X86__) || defined(__i386__)
+          int target_is_32_bit_x86() { return 1; }
+        #else
+          // Compile error...
+        #endif
+
+        int main() {
+          return target_is_32_bit_x86();
+        }
+        " ASMJIT_TARGET_IS_32_BIT_X86)
+
+      if (ASMJIT_TARGET_IS_32_BIT_X86)
+        if ("${CMAKE_CXX_COMPILER_ID}" STREQUAL "MSVC" OR "x${CMAKE_CXX_COMPILER_FRONTEND_VARIANT}" STREQUAL "xMSVC")
+          asmjit_detect_cflags(ASMJIT_SSE2_CFLAGS "-arch:SSE2")
+        else()
+          asmjit_detect_cflags(ASMJIT_SSE2_CFLAGS "-msse2")
+        endif()
       endif()
       asmjit_add_target(asmjit_test_compiler TEST
                         SOURCES    test/asmjit_test_compiler.cpp
@@ -694,7 +706,7 @@ if (NOT ASMJIT_EMBED)
                                    test/asmjit_test_compiler_a64.cpp
                                    test/asmjit_test_compiler_x86.cpp
                         LIBRARIES  asmjit::asmjit
-                        CFLAGS     ${ASMJIT_PRIVATE_CFLAGS} ${sse2_flags}
+                        CFLAGS     ${ASMJIT_PRIVATE_CFLAGS} ${ASMJIT_SSE2_CFLAGS}
                         CFLAGS_DBG ${ASMJIT_PRIVATE_CFLAGS_DBG}
                         CFLAGS_REL ${ASMJIT_PRIVATE_CFLAGS_REL})
     endif()

deps/asmjit/CONTRIBUTING.md

@@ -0,0 +1,102 @@
+## How to Contribute to AsmJit
+
+### Did you find a bug or something isn't working as expected?
+
+  * Please use [Issues](https://github.com/asmjit/asmjit/issues) page to report bugs or create a [pull request](https://github.com/asmjit/asmjit/pulls) if you have already fixed it.
+
+  * Make sure that when a bug is reported it provides as much information as possible to make it easy to either reproduce it locally or to at least guess where the problem could be. AsmJit is a low-level tool, which makes it very easy to emit code that would crash or not work as intended when executed. Always use AsmJit's [Logging](https://asmjit.com/doc/group__asmjit__logging.html) and [Error Handling](https://asmjit.com/doc/group__asmjit__error__handling.html) features first to analyze whether there is not a simple to catch bug in your own code.
+
+  * Don't be afraid to ask for help if you don't know how to solve a particular problem or in case it's unclear how to do it. The community would help if the problem is well described and has a solution. In general we always try to at least improve the documentation in case it doesn't provide enough information and users must ask for help.
+
+### Asking questions
+
+  * We prefer GitHub issues to be used for reporting bugs or feature requests, but it's still okay to ask questions there as well. However, please consider joining our [Gitter Chat](https://app.gitter.im/#/room/#asmjit:gitter.im) to ask questions; it has an active community that can quickly respond.
+
+### Suggesting feature requests
+
+  * It's very likely that when using AsmJit you have found something that AsmJit doesn't provide, which would be handy to have as a built-in. The [Issues](https://github.com/asmjit/asmjit/issues) page can be used to submit feature requests, but please keep in mind that AsmJit is a relatively small project and not all requested features will be accepted, especially if they are non-trivial, time consuming to implement, or the scope of the feature doesn't match AsmJit goals.
+
+  * If you have already implemented the feature you are suggesting, please open a [pull request](https://github.com/asmjit/asmjit/pulls).
+
+  * Ports (requesting new AsmJit backends) can be reported as feature requests, but only by people that are willing to work on them as creating new ports takes a lot of time.
+
+### Suggesting a documentation enhancement
+
+  * [AsmJit's documentation](https://asmjit.com/doc/index.html) is auto-generated from source code, so if you would like to improve it just open a [pull request](https://github.com/asmjit/asmjit/pulls) with your changes. The documentation uses [Doxygen](https://www.doxygen.nl/) as a front-end, so you can use `\ref` keyword to create links and other Doxygen keywords to enhance the documentation.
+
+### Suggesting a website content enhancement
+
+  * [AsmJit's website](https://asmjit.com) is also generated, but not from public sources at the moment. If you did find an issue on the website you can either use contact information on the [support page](https://asmjit.com/support.html) or to discuss the change on our [Gitter Chat](https://app.gitter.im/#/room/#asmjit:gitter.im). Alternatively, opening a regular issue is also okay.
+
+
+## Coding Style & Consistency
+
+  * If you decide to open a pull request, make sure that the code you submit uses the same convention as the rest of the code. We prefer keeping the code consistent.
+
+  * [.editorconfig](./.editorconfig) should help with basic settings.
+
+  * Initially, AsmJit coding style was based on Google C++ Style Guide, but it has diverged from it.
+
+  * Include guards use `<PATH_TO_SRC>_H_INCLUDED` format.
+
+  * `asmjit` namespace must be open by `ASMJIT_BEGIN_NAMESPACE` and closed by `ASMJIT_END_NAMESPACE`
+
+  * `asmjit::xxx` (backend specific) nested namespace must be open by `ASMJIT_BEGIN_SUB_NAMESPACE(xxx)` and closed by `ASMJIT_END_SUB_NAMESPACE`.
+
+  * Opening bracket is on the same line, like `struct Something {`, `if (condition) {`, etc...
+
+  * The code uses a soft limit of 120 characters per line (including documentation), but it's not enforced and it's okay to use more when it makes sense (for example defining tables, etc...).
+
+  * Since AsmJit doesn't use Exceptions nor RTTI the code cannot use containers provided by the C++ standard library. In general, we try to only use a bare minimum from the C++ standard library to make it viable to use AsmJit even in C code bases where JIT complier is implemented in C++ ([Erlang](https://www.erlang.org/) can be seen as a great example).
+
+## Testing
+
+  * AsmJit uses a minimalist unit testing framework to write unit tests to avoid third-party dependencies.
+
+  * At the moment tests are in the same file as the implementation and are only compiled when `ASMJIT_TEST` macro is defined.
+
+  * Use `-DASMJIT_TEST=1` when invoking [CMake](https://cmake.org/) to compile AsmJit tests.
+
+  * Unit tests are compiled to a single `asmjit_test_unit[.exe]` executable.
+
+  * Other tests have their own executables based on what is tested.
+
+  * Always add assembler tests when adding new instructions, see [asmjit_test_assembler_x64.cpp](./test/asmjit_test_assembler_x64.cpp) and [asmjit_test_assembler_a64.cpp](./test/asmjit_test_assembler_a64.cpp) for more details.
+
+## Pull Request Messages
+
+  * If a change fixes a bug the message should should start with `[bug]`.
+
+  * If a change fixes or enhances documentation it should start with `[doc]`.
+
+  * If a change fixes or enhances our CI it should start with `[ci]`.
+
+  * If a change breaks ABI it must start with `[abi]`.
+
+  * Otherwise there is no suggested prefix.
+
+## ABI Changes
+
+  * ABI changes happen, but they are usually accumulated and committed within a short time window to not break it often. In general we prefer to break ABI once a year, or once 6 months if there is something that has a high priority. There are no hard rules though.
+
+  * AsmJit uses an `inline namespace`, which should make it impossible to link to AsmJit library that is ABI incompatible. When ABI break happens both AsmJit version and ABI namespace are changed, see [asmjit/core/api-config.h](./src/asmjit/core/api-config.h) for more details.
+
+  * What is an ABI break?
+
+    * Modifying a public struct/class in a way that its functionality is altered and/or its size is changed
+
+    * Adding/removing virtual functions to/from classes, respectively
+
+    * Changing a signature of a public function or a class member function (for example adding a parameter).
+
+    * Changing the value of an enum or global constant (for example instructions are now sorted by name, so adding a new instruction breaks ABI)
+
+    * Possibly more, but these were the most common...
+
+  * What is not ABI break?
+
+    * Extending the functionality by using reserved members of a struct/class
+
+    * Adding new API including new structs and classes
+
+    * Changing anything that is internal and that doesn't leak to public headers

deps/asmjit/LICENSE.md

@@ -1,4 +1,4 @@
-Copyright (c) 2008-2020 The AsmJit Authors
+Copyright (c) 2008-2024 The AsmJit Authors
 
 This software is provided 'as-is', without any express or implied
 warranty. In no event will the authors be held liable for any damages

deps/asmjit/README.md

@@ -5,7 +5,7 @@ AsmJit is a lightweight library for machine code generation written in C++ langu
 
   * [Official Home Page (asmjit.com)](https://asmjit.com)
   * [Official Repository (asmjit/asmjit)](https://github.com/asmjit/asmjit)
-  * [Public Chat Channel](https://gitter.im/asmjit/asmjit)
+  * [Public Chat Channel](https://app.gitter.im/#/room/#asmjit:gitter.im)
   * [Zlib License](./LICENSE.md)
 
 See [asmjit.com](https://asmjit.com) page for more details, examples, and documentation.
@@ -16,39 +16,42 @@ Documentation
   * [Documentation Index](https://asmjit.com/doc/index.html)
   * [Build Instructions](https://asmjit.com/doc/group__asmjit__build.html)
 
+Contributing
+------------
+
+  * See [CONTRIBUTING](./CONTRIBUTING.md) page for more details
+
 Breaking Changes
 ----------------
 
 Breaking the API is sometimes inevitable, what to do?
 
-  * See [Breaking Changes Guide](https://asmjit.com/doc/group__asmjit__breaking__changes.html), which is now part of AsmJit documentation.
+  * See [Breaking Changes Guide](https://asmjit.com/doc/group__asmjit__breaking__changes.html), which is now part of AsmJit documentation
   * See asmjit tests, they always compile and provide implementation of many use-cases:
-    * [asmjit_test_emitters.cpp](./test/asmjit_test_emitters.cpp) - Tests that demonstrate the purpose of emitters.
-    * [asmjit_test_assembler_x86.cpp](./test/asmjit_test_assembler_x86.cpp) - Tests targeting AsmJit's Assembler (x86/x64).
-    * [asmjit_test_compiler_x86.cpp](./test/asmjit_test_compiler_x86.cpp) - Tests targeting AsmJit's Compiler (x86/x64).
-    * [asmjit_test_instinfo.cpp](./test/asmjit_test_instinfo.cpp) - Tests that query instruction information.
+    * [asmjit_test_emitters.cpp](./test/asmjit_test_emitters.cpp) - Tests that demonstrate the purpose of emitters
+    * [asmjit_test_assembler_x86.cpp](./test/asmjit_test_assembler_x86.cpp) - Tests targeting AsmJit's Assembler (x86/x64)
+    * [asmjit_test_compiler_x86.cpp](./test/asmjit_test_compiler_x86.cpp) - Tests targeting AsmJit's Compiler (x86/x64)
+    * [asmjit_test_instinfo.cpp](./test/asmjit_test_instinfo.cpp) - Tests that query instruction information
     * [asmjit_test_x86_sections.cpp](./test/asmjit_test_x86_sections.cpp) - Multiple sections test.
-  * Visit our [Official Chat](https://gitter.im/asmjit/asmjit) if you need a quick help.
+  * Visit our [Gitter Chat](https://app.gitter.im/#/room/#asmjit:gitter.im) if you need a quick help
 
 Project Organization
 --------------------
 
-  * **`/`**        - Project root.
-    * **src**      - Source code.
-      * **asmjit** - Source code and headers (always point include path in here).
-        * **core** - Core API, backend independent except relocations.
-        * **arm**  - ARM specific API, used only by ARM and AArch64 backends.
-        * **x86**  - X86 specific API, used only by X86 and X64 backends.
-    * **test**     - Unit and integration tests (don't embed in your project).
-    * **tools**    - Tools used for configuring, documenting, and generating files.
+  * **`/`**        - Project root
+    * **src**      - Source code
+      * **asmjit** - Source code and headers (always point include path in here)
+        * **core** - Core API, backend independent except relocations
+        * **arm**  - ARM specific API, used only by ARM and AArch64 backends
+        * **x86**  - X86 specific API, used only by X86 and X64 backends
+    * **test**     - Unit and integration tests (don't embed in your project)
+    * **tools**    - Tools used for configuring, documenting, and generating files
 
-TODO
-----
+Ports
+-----
 
-  * [ ] Ports:
-    * [ ] 32-bit ARM/Thumb port.
-    * [ ] 64-bit ARM (AArch64) port.
-    * [ ] RISC-V port.
+  * [ ] 32-bit ARM/Thumb port (work in progress)
+  * [ ] RISC-V port (not in progress, help welcome)
 
 Support
 -------

deps/asmjit/db/LICENSE.md

@@ -0,0 +1,26 @@
+AsmJit database is dual licensed under Zlib and Unlicense (public domain)
+
+This is free and unencumbered software released into the public domain.
+
+Anyone is free to copy, modify, publish, use, compile, sell, or
+distribute this software, either in source code form or as a compiled
+binary, for any purpose, commercial or non-commercial, and by any
+means.
+
+In jurisdictions that recognize copyright laws, the author or authors
+of this software dedicate any and all copyright interest in the
+software to the public domain. We make this dedication for the benefit
+of the public at large and to the detriment of our heirs and
+successors. We intend this dedication to be an overt act of
+relinquishment in perpetuity of all present and future rights to this
+software under copyright law.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+OTHER DEALINGS IN THE SOFTWARE.
+
+For more information, please refer to <http://unlicense.org>

deps/asmjit/db/README.md

@@ -1,15 +1,21 @@
 AsmJit Instruction Database
 ---------------------------
 
-This is a database of instructions that is used by AsmJit to generate its internal database and also assembler implementations. This project started initially as AsmDB, but was merged to AsmJit later to make the maintenance easier. The database was created in a way so that each instruction definition would only need a single line in JSON data. The data is then processed by architecture specific data readers that make the data canonical and ready for processing.
+This is a database of instructions that is used by AsmJit to generate its internal database and also assembler implementations. This project started initially as AsmDB, but was merged to AsmJit later to make the maintenance easier. The database was created in a way so that each instruction definition would only need a single line in JSON data file. The data is then processed by architecture specific data readers that make the data canonical and ready for processing.
 
 AsmJit database provides the following ISAs:
 
   * `isa_x86.json` - provides X86 instruction data (both 32-bit and 64-bit)
-  * `isa_arm.json` - provides AArch32 instruction data (both ARM32 and THUMB)
-  * `isa_a64.json` - provides AArch64 instruction data
+  * `isa_aarch32.json` - provides AArch32 instruction data (A32/T16/T32 encoding)
+  * `isa_aarch64.json` - provides AArch64 instruction data (A64 encoding)
+  * `isa_aarch64_sme.json` - provides AArch64 SME instruction data (work-in-progress)
 
 To Be Documented
 ----------------
 
 This project will be refactored and documented in the future.
+
+License
+-------
+
+AsmJit database is dual licensed under Zlib (AsmJit license) or public domain. The database can be used for any purpose, not just by AsmJit.

deps/asmjit/db/aarch32.js

@@ -1,8 +1,7 @@
 // This file is part of AsmJit project <https://asmjit.com>
 //
 // See asmjit.h or LICENSE.md for license and copyright information
-// SPDX-License-Identifier: Zlib
-
+// SPDX-License-Identifier: (Zlib or Unlicense)
 
 (function($scope, $as) {
 "use strict";
@@ -29,14 +28,14 @@ const arm = $scope[$as] = dict();
 // Database
 // ========
 
-arm.dbName = "isa_arm.json";
+arm.dbName = "isa_aarch32.json";
 
-// asmdb.arm.Utils
-// ===============
+// asmdb.aarch32.Utils
+// ===================
 
 // Can be used to assign the number of bits each part of the opcode occupies.
 // NOTE: THUMB instructions that use halfword must always specify the width
-// of all registers as many instructictions accept only LO (r0..r7) registers.
+// of all registers as many instructions accept only LO (r0..r7) registers.
 const FieldInfo = {
   "P"     : { "bits": 1 },
   "U"     : { "bits": 1 },
@@ -56,6 +55,7 @@ const FieldInfo = {
   "cmode" : { "bits": 4 },
   "Cn"    : { "bits": 4 },
   "Cm"    : { "bits": 4 },
+
   "Rd"    : { "bits": 4, "read": false, "write": true  },
   "Rd2"   : { "bits": 4, "read": false, "write": true  },
   "RdLo"  : { "bits": 4, "read": false, "write": true  },
@@ -70,17 +70,22 @@ const FieldInfo = {
   "Rs"    : { "bits": 4, "read": true , "write": false },
   "Rs2"   : { "bits": 4, "read": true , "write": false },
   "RsList": { "bits": 4, "read": true , "write": false , "list": true },
+
   "Sd"    : { "bits": 4, "read": false, "write": true  },
   "Sd2"   : { "bits": 4, "read": false, "write": true  },
+  "SdList": { "bits": 4, "read": false, "write": true  , "list": true },
   "Sx"    : { "bits": 4, "read": true , "write": true  },
   "Sn"    : { "bits": 4, "read": true , "write": false },
   "Sm"    : { "bits": 4, "read": true , "write": false },
   "Ss"    : { "bits": 4, "read": true , "write": false },
   "Ss2"   : { "bits": 4, "read": true , "write": false },
+  "SsList": { "bits": 4, "read": true , "write": false , "list": true },
+
   "Dd"    : { "bits": 4, "read": false, "write": true  },
   "Dd2"   : { "bits": 4, "read": false, "write": true  },
   "Dd3"   : { "bits": 4, "read": false, "write": true  },
   "Dd4"   : { "bits": 4, "read": false, "write": true  },
+  "DdList": { "bits": 4, "read": false, "write": true  , "list": true },
   "Dx"    : { "bits": 4, "read": true , "write": true  },
   "Dx2"   : { "bits": 4, "read": true , "write": true  },
   "Dn"    : { "bits": 4, "read": true , "write": false },
@@ -92,18 +97,18 @@ const FieldInfo = {
   "Ds2"   : { "bits": 4, "read": true , "write": false },
   "Ds3"   : { "bits": 4, "read": true , "write": false },
   "Ds4"   : { "bits": 4, "read": true , "write": false },
+  "DsList": { "bits": 4, "read": true , "write": false , "list": true },
+
   "Vd"    : { "bits": 4, "read": false, "write": true  },
   "Vd2"   : { "bits": 4, "read": false, "write": true  },
   "Vd3"   : { "bits": 4, "read": false, "write": true  },
   "Vd4"   : { "bits": 4, "read": false, "write": true  },
-  "VdList": { "bits": 4, "read": false, "write": true  , "list": true },
   "Vx"    : { "bits": 4, "read": true , "write": true  },
   "Vx2"   : { "bits": 4, "read": true , "write": true  },
   "Vn"    : { "bits": 4, "read": true , "write": false },
   "Vm"    : { "bits": 4, "read": true , "write": false },
   "Vs"    : { "bits": 4, "read": true , "write": false },
   "Vs2"   : { "bits": 4, "read": true , "write": false },
-  "VsList": { "bits": 4, "read": true , "write": false , "list": true }
 };
 
 arm.FieldInfo = FieldInfo;
@@ -192,10 +197,16 @@ function decomposeOperand(s) {
   const elementSuffix = "[#i]";
   let element = null;
   let consecutive = 0;
+  let userRegList = false;
+
+  if (s.endsWith("^")) {
+    userRegList = true;
+    s = s.substring(0, s.length - 1);
+  }
 
   if (s.endsWith(elementSuffix)) {
     element = "#i";
-    s = s.substr(0, s.length - elementSuffix.length);
+    s = s.substring(0, s.length - elementSuffix.length);
   }
 
   if (s.endsWith("++")) {
@@ -219,7 +230,8 @@ function decomposeOperand(s) {
     data    : s,
     element : element,
     restrict: restrict,
-    consecutive: consecutive
+    consecutive: consecutive,
+    userRegList: true
   };
 }
 
@@ -238,8 +250,8 @@ function splitOpcodeFields(s) {
   return out.map((field) => { return field.trim(); });
 }
 
-// asmdb.arm.Operand
-// =================
+// asmdb.aarch32.Operand
+// =====================
 
 // ARM operand.
 class Operand extends base.Operand {
@@ -267,17 +279,44 @@ class Operand extends base.Operand {
     else
       return 0;
   }
+
+  isRelative() {
+    if (this.type === "imm")
+      return this.name === "relA" || this.name === "relS" || this.name === "relZ";
+    else
+      return false;
+  }
 }
 arm.Operand = Operand;
 
-// asmdb.arm.Instruction
-// =====================
+// asmdb.aarch32.Instruction
+// =========================
 
 function patternFromOperand(key) {
   return key;
   // return key.replace(/\b(?:[RVDS](?:d|s|n|m|x|x2))\b/, "R");
 }
 
+// Rewrite a memory operand expression (either base or index) to a simplified one, which is okay
+// to be generated as C++ expression. In general, we want to simplify != to a more favorable code.
+function simplifyMemoryExpression(e) {
+  if (e.type === "binary" && e.op === "!=" && e.right.type === "var") {
+    // Rewrite A != PC to A < PC
+    if (e.right.name === "PC") { e.op = "<"; }
+
+    // Rewrite A != HI to A < 8
+    if (e.right.name === "HI") { e.op = "<"; e.right = exp.Imm(8); }
+
+    // Rewrite A != XX to A < SP || A == LR
+    if (e.right.name === "XX") {
+      return exp.Or(exp.Lt(e.left, exp.Var("SP")),
+                    exp.Eq(e.left.clone(), exp.Var("LR")));
+    }
+  }
+
+  return e;
+}
+
 // ARM instruction.
 class Instruction extends base.Instruction {
   constructor(db, data) {
@@ -482,13 +521,14 @@ class Instruction extends base.Instruction {
 
             const m = part.match(/^([A-Za-z]\w*)/);
             if (m.length < part.length) {
-              op.base.exp = exp.parse(part);
+              op.base.exp = simplifyMemoryExpression(exp.parse(part));
               op.base.field = m[1];
             }
           }
           else if (part.startsWith("#")) {
             let p = part.substring(1);
             let u = "1";
+            let alwaysNegative = false;
 
             let offExp = null;
             let offMul = 1;
@@ -498,6 +538,11 @@ class Instruction extends base.Instruction {
               p = p.substring(3);
             }
 
+            if (p.startsWith("-")) {
+              alwaysNegative = false;
+              p = p.substring(1);
+            }
+
             const expMatch = p.match(/^([A-Za-z]\w*)==/);
             if (expMatch) {
               offExp = exp.parse(p);
@@ -515,6 +560,7 @@ class Instruction extends base.Instruction {
             op.offset.u = u;
             op.offset.exp = offExp;
             op.offset.mul = offMul;
+            op.offset.negative = alwaysNegative;
           }
           else {
             let p = part;
@@ -531,7 +577,7 @@ class Instruction extends base.Instruction {
 
             const m = p.match(/^([A-Za-z]\w*)/);
             if (m.length < p.length) {
-              op.index.exp = exp.parse(p);
+              op.index.exp = simplifyMemoryExpression(exp.parse(p));
               op.index.field = m[1];
             }
           }
@@ -858,8 +904,8 @@ class Instruction extends base.Instruction {
 }
 arm.Instruction = Instruction;
 
-// asmdb.arm.ISA
-// =============
+// asmdb.aarch32.ISA
+// =================
 
 function mergeGroupData(data, group) {
   for (let k in group) {
@@ -921,7 +967,7 @@ class ISA extends base.ISA {
                        hasOwn.call(obj, "t16") ? "t16" : "";
 
       if (!encoding)
-        FAIL(`Instrution ${names.join("/")} doesn't encoding, it must provide either a32, t32, or t16 field`);
+        FAIL(`Instruction ${names.join("/")} doesn't encoding, it must provide either a32, t32, or t16 field`);
 
       for (let j = 0; j < names.length; j++) {
         const inst = new Instruction(this, names[j], operands, encoding.toUpperCase(), obj[encoding], obj);
@@ -938,4 +984,4 @@ class ISA extends base.ISA {
 arm.ISA = ISA;
 
 }).apply(this, typeof module === "object" && module && module.exports
-  ? [module, "exports"] : [this.asmdb || (this.asmdb = {}), "arm"]);
+  ? [module, "exports"] : [this.asmdb || (this.asmdb = {}), "aarch32"]);

deps/asmjit/db/aarch64.js

@@ -1,8 +1,7 @@
 // This file is part of AsmJit project <https://asmjit.com>
 //
 // See asmjit.h or LICENSE.md for license and copyright information
-// SPDX-License-Identifier: Zlib
-
+// SPDX-License-Identifier: (Zlib or Unlicense)
 
 (function($scope, $as) {
 "use strict";
@@ -36,7 +35,7 @@ arm.dbName = "isa_aarch64.json";
 
 // Can be used to assign the number of bits each part of the opcode occupies.
 // NOTE: THUMB instructions that use halfword must always specify the width
-// of all registers as many instructictions accept only LO (r0..r7) registers.
+// of all registers as many instructions accept only LO (r0..r7) registers.
 const FieldInfo = {
   "P"     : { "bits": 1 },
   "U"     : { "bits": 1 },

deps/asmjit/db/base.js

@@ -1,7 +1,7 @@
 // This file is part of AsmJit project <https://asmjit.com>
 //
 // See asmjit.h or LICENSE.md for license and copyright information
-// SPDX-License-Identifier: Zlib
+// SPDX-License-Identifier: (Zlib or Unlicense)
 
 (function($scope, $as) {
 "use strict";
@@ -205,7 +205,7 @@ class Operand {
 
   toString() { return this.data; }
 
-  isReg() { return !!this.reg; }
+  isReg() { return !!this.reg && this.type !== "reg-list"; }
   isMem() { return !!this.mem; }
   isImm() { return !!this.imm; }
   isRel() { return !!this.rel; }
@@ -259,6 +259,20 @@ class Instruction {
     return out;
   }
 
+  get operandCount() {
+    return this.operands.length;
+  }
+
+  get minimumOperandCount() {
+    const count = this.operands.length;
+    for (let i = 0; i < count; i++) {
+      if (this.operands[i].optional) {
+        return i;
+      }
+    }
+    return count
+  }
+
   _assignAttribute(key, value) {
     switch (key) {
       case "ext":

deps/asmjit/db/exp.js

@@ -1,7 +1,7 @@
 // This file is part of AsmJit project <https://asmjit.com>
 //
 // See asmjit.h or LICENSE.md for license and copyright information
-// SPDX-License-Identifier: Zlib
+// SPDX-License-Identifier: (Zlib or Unlicense)
 
 (function($scope, $as) {
 "use strict";
@@ -87,6 +87,7 @@ class ExpNode {
 
   info() { return null; }
   clone() { throw new Error("ExpNode.clone() must be overridden"); }
+  evaluate(ctx) { throw new Error("ExpNode.evaluate() must be overridden"); }
   toString(ctx) { throw new Error("ExpNode.toString() must be overridden"); }
 }
 
@@ -97,6 +98,7 @@ class ImmNode extends ExpNode {
   }
 
   clone() { return new ImmNode(this.imm); }
+  evaluate(ctx) { return this.imm; }
   toString(ctx) { return ctx ? ctx.stringifyImmediate(this.imm) : String(this.imm); }
 }
 
@@ -106,7 +108,8 @@ class VarNode extends ExpNode {
     this.name = name || "";
   }
 
-  clone() { return new VarNode(this.var); }
+  clone() { return new VarNode(this.name); }
+  evaluate(ctx) { return ctx.variable(this.name); }
   toString(ctx) { return ctx ? ctx.stringifyVariable(this.name) : String(this.name); }
 }
 
@@ -117,7 +120,14 @@ class CallNode extends ExpNode {
     this.args = args || [];
   }
 
-  clone() { return new CallNode(this.name, this.args.map(function(arg) { return arg.clone(); })); }
+  clone() {
+    return new CallNode(this.name, this.args.map(function(arg) { return arg.clone(); }));
+  }
+
+  evaluate(ctx) {
+    const evaluatedArgs = this.args.map(function(arg) { return arg.evaluate(ctx); });
+    return ctx.function(this.name, evaluatedArgs);
+  }
 
   toString(ctx) {
     if (this.name === "$bit") {
@@ -143,8 +153,23 @@ class UnaryNode extends ExpNode {
     this.child = child || null;
   }
 
-  info() { return kUnaryOperators[this.op]; }
-  clone() { return new UnaryNode(this.op, this.left ? this.left.clone() : null); }
+  info() {
+    return kUnaryOperators[this.op];
+  }
+
+  clone() {
+    return new UnaryNode(this.op, this.left ? this.left.clone() : null);
+  }
+
+  evaluate(ctx) {
+    const val = this.child.evaluate(ctx);
+    switch (this.op) {
+      case "-": return (-val);
+      case "~": return (~val);
+      case "!": return (val ? 0 : 1);
+      default : return ctx.unary(this.op, val);
+    }
+  }
 
   toString(ctx) {
     return this.info().emit.replace(/@1/g, () => {
@@ -166,8 +191,40 @@ class BinaryNode extends ExpNode {
     this.right = right || null;
   }
 
-  info() { return kBinaryOperators[this.op]; }
-  clone() { return new BinaryNode(this.op, this.left ? this.left.clone() : null, this.right ? this.right.clone() : null); }
+  info() {
+    return kBinaryOperators[this.op];
+  }
+
+  clone() {
+    return new BinaryNode(this.op, this.left ? this.left.clone() : null, this.right ? this.right.clone() : null);
+  }
+
+  evaluate(ctx) {
+    const left = this.left.evaluate(ctx);
+    const right = this.right.evaluate(ctx);
+
+    switch (this.op) {
+      case "-" : return left - right;
+      case "+" : return left + right;
+      case "*" : return left * right;
+      case "/" : return (left / right)|0;
+      case "%" : return (left % right)|0;
+      case "&" : return left & right;
+      case "|" : return left | right;
+      case "^" : return left ^ right;
+      case "<<": return left << right;
+      case ">>": return left >> right;
+      case "==": return left == right ? 1 : 0;
+      case "!=": return left != right ? 1 : 0;
+      case "<" : return left <  right ? 1 : 0;
+      case "<=": return left <= right ? 1 : 0;
+      case ">" : return left >  right ? 1 : 0;
+      case ">=": return left >= right ? 1 : 0;
+      case "&&": return left && right ? 1 : 0;
+      case "||": return left || right ? 1 : 0;
+      default  : return ctx.binary(this.op, left, right);
+    }
+  }
 
   toString(ctx) {
     return this.info().emit.replace(/@[1-2]/g, (p) => {
@@ -184,8 +241,6 @@ function Call(name, args) { return new CallNode(name, args); }
 function Unary(op, child) { return new UnaryNode(op, child); }
 function Binary(op, left, right) { return new BinaryNode(op, left, right); }
 
-/*
-// TODO: Unused, remove?
 function Negate(child) { return Unary("-", child); }
 function BitNot(child) { return Unary("~", child); }
 
@@ -207,7 +262,8 @@ function Gt(left, right) { return Binary(">", left, right); }
 function Ge(left, right) { return Binary(">=", left, right); }
 function And(left, right) { return Binary("&&", left, right); }
 function Or(left, right) { return Binary("||", left, right); }
-*/
+
+
 
 // Expression Tokenizer
 // --------------------
@@ -256,7 +312,44 @@ function newToken(type, position, data, value) {
 const NoToken = newToken(kTokenNone, -1, "<end>", null);
 
 // Must be reset before it can be used, use `RegExp.lastIndex`.
-const reValue = /(?:(?:\d*\.\d+|\d+)(?:[E|e][+|-]?\d+)?)/g;
+const reNumValue = /(?:(?:\d*\.\d+|\d+)(?:[E|e][+|-]?\d+)?)/g;
+
+function parseHex(source, from) {
+  let i = from;
+  let number = 0;
+
+  while (i < source.length) {
+    let c = source.charCodeAt(i);
+    let n = 0;
+
+    if (c >= '0'.charCodeAt(0) && c <= '9'.charCodeAt(0)) {
+      n = c - '0'.charCodeAt(0);
+    }
+    else if (c >= 'a'.charCodeAt(0) && c <= 'f'.charCodeAt(0)) {
+      n = c - 'a'.charCodeAt(0) + 10;
+    }
+    else if (c >= 'A'.charCodeAt(0) && c <= 'F'.charCodeAt(0)) {
+      n = c - 'A'.charCodeAt(0) + 10;
+    }
+    else if (c >= 'g'.charCodeAt(0) && c <= 'z'.charCodeAt(0) || c >= 'g'.charCodeAt(0) && c <= 'Z'.charCodeAt(0)) {
+      throwExpressionError(`Invalid hex number 0x${source.substring(from, i + 1)}`);
+    }
+    else {
+      break;
+    }
+
+    number = (number << 4) | n;
+    i++;
+  }
+
+  if (i === from)
+    throwExpressionError(`Invalid number starting with 0x`);
+
+  return {
+    number: number,
+    end: i
+  };
+}
 
 function tokenize(source) {
   const len = source.length;
@@ -268,22 +361,33 @@ function tokenize(source) {
   let c, cat;       // Current character code and category.
 
   while (i < len) {
-    cat = Category(c = source.charCodeAt(i));
+    c = source.charCodeAt(i);
+    cat = Category(c);
 
     if (cat === kCharSpace) {
       i++;
     }
     else if (cat === kCharDigit) {
       const n = tokens.length - 1;
-      if (n >= 0 && tokens[n].data === "." && source[i - 1] === ".") {
-        tokens.length = n;
-        i--;
-      }
-      reValue.lastIndex = i;
-      data = reValue.exec(source)[0];
 
-      tokens.push(newToken(kTokenValue, i, data, parseFloat(data)));
-      i += data.length;
+      // Hex number.
+      if (c === '0'.charCodeAt(0) && i + 1 < len && source.charCodeAt(i + 1) === 'x'.charCodeAt(0)) {
+        const status = parseHex(source, i + 2);
+        tokens.push(newToken(kTokenValue, i, source.substring(i, status.end), status.number));
+        i = status.end;
+      }
+      else {
+        if (n >= 0 && tokens[n].data === "." && source[i - 1] === ".") {
+          tokens.length = n;
+          i--;
+        }
+
+        reNumValue.lastIndex = i;
+        data = reNumValue.exec(source)[0];
+
+        tokens.push(newToken(kTokenValue, i, data, parseFloat(data)));
+        i += data.length;
+      }
     }
     else if (cat === kCharAlpha) {
       start = i;
@@ -623,6 +727,29 @@ $scope[$as] = {
   Call: Call,
   Unary: Unary,
   Binary: Binary,
+
+  Negate: Negate,
+  BitNot: BitNot,
+
+  Add: Add,
+  Sub: Sub,
+  Mul: Mul,
+  Div: Div,
+  Mod: Mod,
+  Shl: Shl,
+  Shr: Shr,
+  BitAnd: BitAnd,
+  BitOr: BitOr,
+  BitXor: BitXor,
+  Eq: Eq,
+  Ne: Ne,
+  Lt: Lt,
+  Le: Le,
+  Gt: Gt,
+  Ge: Ge,
+  And: And,
+  Or: Or,
+
   Visitor: Visitor,
   ExpressionError: ExpressionError,
 

deps/asmjit/db/index.js

@@ -1,11 +1,11 @@
 // This file is part of AsmJit project <https://asmjit.com>
 //
 // See asmjit.h or LICENSE.md for license and copyright information
-// SPDX-License-Identifier: Zlib
+// SPDX-License-Identifier: (Zlib or Unlicense)
 
 "use strict";
 
 exports.base = require("./base.js");
-exports.arm = require("./arm.js");
+exports.aarch32 = require("./aarch32.js");
 exports.aarch64 = require("./aarch64.js");
 exports.x86 = require("./x86.js");

deps/asmjit/db/isa_aarch64.json

@@ -139,70 +139,70 @@
       {"inst": "ldaxr Xd, [Xn|SP]"                                       , "op": "11001000|010|11111|1|11111|Rn|Rd"},
       {"inst": "ldaxrb Wd, [Xn|SP]"                                      , "op": "00001000|010|11111|1|11111|Rn|Rd"},
       {"inst": "ldaxrh Xd, [Xn|SP]"                                      , "op": "01001000|010|11111|1|11111|Rn|Rd"},
-      {"inst": "ldnp Wd, Wd2, [Xn|SP, #soff*4]"                          , "op": "00101000|01|soff:7|Rd2|Rn|Rd"},
-      {"inst": "ldnp Xd, Xd2, [Xn|SP, #soff*8]"                          , "op": "10101000|01|soff:7|Rd2|Rn|Rd"},
-      {"inst": "ldp Wd, Wd2, [Xn|SP, #soff*4]{@}{!}"                     , "op": "0010100|!post|W|1|soff:7|Rd2|Rn|Rd"},
-      {"inst": "ldp Xd, Xd2, [Xn|SP, #soff*8]{@}{!}"                     , "op": "1010100|!post|W|1|soff:7|Rd2|Rn|Rd"},
-      {"inst": "ldpsw Xd, Xd2, [Xn|SP, #soff*4]{@}{!}"                   , "op": "0110100|!post|W|1|soff:7|Rd2|Rn|Rd"},
-      {"inst": "ldr Wd, [Xn|SP, #zoff*4]"                                , "op": "10111001|01|zoff:12|Rn|Rd"},
-      {"inst": "ldr Xd, [Xn|SP, #zoff*8]"                                , "op": "11111001|01|zoff:12|Rn|Rd"},
-      {"inst": "ldr Wd, [Xn|SP, #soff*4]@"                               , "op": "10111000|010|soff:9|01|Rn|Rd"},
-      {"inst": "ldr Xd, [Xn|SP, #soff*8]@"                               , "op": "11111000|010|soff:9|01|Rn|Rd"},
-      {"inst": "ldr Wd, [Xn|SP, #soff*4]!"                               , "op": "10111000|010|soff:9|11|Rn|Rd"},
-      {"inst": "ldr Xd, [Xn|SP, #soff*8]!"                               , "op": "11111000|010|soff:9|11|Rn|Rd"},
+      {"inst": "ldnp Wd, Wd2, [Xn|SP, #offS*4]"                          , "op": "00101000|01|offS:7|Rd2|Rn|Rd"},
+      {"inst": "ldnp Xd, Xd2, [Xn|SP, #offS*8]"                          , "op": "10101000|01|offS:7|Rd2|Rn|Rd"},
+      {"inst": "ldp Wd, Wd2, [Xn|SP, #offS*4]{@}{!}"                     , "op": "0010100|!post|W|1|offS:7|Rd2|Rn|Rd"},
+      {"inst": "ldp Xd, Xd2, [Xn|SP, #offS*8]{@}{!}"                     , "op": "1010100|!post|W|1|offS:7|Rd2|Rn|Rd"},
+      {"inst": "ldpsw Xd, Xd2, [Xn|SP, #offS*4]{@}{!}"                   , "op": "0110100|!post|W|1|offS:7|Rd2|Rn|Rd"},
+      {"inst": "ldr Wd, [Xn|SP, #offZ*4]"                                , "op": "10111001|01|offZ:12|Rn|Rd"},
+      {"inst": "ldr Xd, [Xn|SP, #offZ*8]"                                , "op": "11111001|01|offZ:12|Rn|Rd"},
+      {"inst": "ldr Wd, [Xn|SP, #offS*4]@"                               , "op": "10111000|010|offS:9|01|Rn|Rd"},
+      {"inst": "ldr Xd, [Xn|SP, #offS*8]@"                               , "op": "11111000|010|offS:9|01|Rn|Rd"},
+      {"inst": "ldr Wd, [Xn|SP, #offS*4]!"                               , "op": "10111000|010|offS:9|11|Rn|Rd"},
+      {"inst": "ldr Xd, [Xn|SP, #offS*8]!"                               , "op": "11111000|010|offS:9|11|Rn|Rd"},
       {"inst": "ldr Wd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]"            , "op": "10111000|011|Rm|option:3|s:1|10|Rn|Rd"                 , "imm": "ImmLDR(iop, n)"},
       {"inst": "ldr Xd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]"            , "op": "11111000|011|Rm|option:3|s:1|10|Rn|Rd"                 , "imm": "ImmLDR(iop, n)"},
-      {"inst": "ldr Wd, [PC, #soff*4]"                                   , "op": "00011000|soff:19|Rd"},
-      {"inst": "ldr Xd, [PC, #soff*4]"                                   , "op": "01011000|soff:19|Rd"},
-      {"inst": "ldrb Wd, [Xn|SP, #zoff]"                                 , "op": "00111001|01|zoff:12|Rn|Rd"},
-      {"inst": "ldrb Wd, [Xn|SP, #soff]@"                                , "op": "00111000|010|soff:9|01|Rn|Rd"},
-      {"inst": "ldrb Wd, [Xn|SP, #soff]!"                                , "op": "00111000|010|soff:9|11|Rn|Rd"},
+      {"inst": "ldr Wd, [PC, #offS*4]"                                   , "op": "00011000|offS:19|Rd"},
+      {"inst": "ldr Xd, [PC, #offS*4]"                                   , "op": "01011000|offS:19|Rd"},
+      {"inst": "ldrb Wd, [Xn|SP, #offZ]"                                 , "op": "00111001|01|offZ:12|Rn|Rd"},
+      {"inst": "ldrb Wd, [Xn|SP, #offS]@"                                , "op": "00111000|010|offS:9|01|Rn|Rd"},
+      {"inst": "ldrb Wd, [Xn|SP, #offS]!"                                , "op": "00111000|010|offS:9|11|Rn|Rd"},
       {"inst": "ldrb Wd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]"           , "op": "00111000|011|Rm|option:3|s:1|10|Rn|Rd"                 , "imm": "ImmLDRB(iop, n)"},
-      {"inst": "ldrh Wd, [Xn|SP, #zoff*2]"                               , "op": "01111001|01|zoff:12|Rn|Rd"},
-      {"inst": "ldrh Wd, [Xn|SP, #soff*2]@"                              , "op": "01111000|010|soff:9|01|Rn|Rd"},
-      {"inst": "ldrh Wd, [Xn|SP, #soff*2]!"                              , "op": "01111000|010|soff:9|11|Rn|Rd"},
+      {"inst": "ldrh Wd, [Xn|SP, #offZ*2]"                               , "op": "01111001|01|offZ:12|Rn|Rd"},
+      {"inst": "ldrh Wd, [Xn|SP, #offS*2]@"                              , "op": "01111000|010|offS:9|01|Rn|Rd"},
+      {"inst": "ldrh Wd, [Xn|SP, #offS*2]!"                              , "op": "01111000|010|offS:9|11|Rn|Rd"},
       {"inst": "ldrh Wd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]"           , "op": "01111000|011|Rm|option:3|s:1|10|Rn|Rd"                 , "imm": "ImmLDRH(iop, n)"},
-      {"inst": "ldrsb Wd, [Xn|SP, #zoff]"                                , "op": "00111001|11|zoff:12|Rn|Rd"},
-      {"inst": "ldrsb Xd, [Xn|SP, #zoff]"                                , "op": "00111001|10|zoff:12|Rn|Rd"},
-      {"inst": "ldrsb Wd, [Xn|SP, #soff]@"                               , "op": "00111000|110|soff:9|01|Rn|Rd"},
-      {"inst": "ldrsb Xd, [Xn|SP, #soff]@"                               , "op": "00111000|100|soff:9|01|Rn|Rd"},
-      {"inst": "ldrsb Wd, [Xn|SP, #soff]!"                               , "op": "00111000|110|soff:9|11|Rn|Rd"},
-      {"inst": "ldrsb Xd, [Xn|SP, #soff]!"                               , "op": "00111000|100|soff:9|11|Rn|Rd"},
+      {"inst": "ldrsb Wd, [Xn|SP, #offZ]"                                , "op": "00111001|11|offZ:12|Rn|Rd"},
+      {"inst": "ldrsb Xd, [Xn|SP, #offZ]"                                , "op": "00111001|10|offZ:12|Rn|Rd"},
+      {"inst": "ldrsb Wd, [Xn|SP, #offS]@"                               , "op": "00111000|110|offS:9|01|Rn|Rd"},
+      {"inst": "ldrsb Xd, [Xn|SP, #offS]@"                               , "op": "00111000|100|offS:9|01|Rn|Rd"},
+      {"inst": "ldrsb Wd, [Xn|SP, #offS]!"                               , "op": "00111000|110|offS:9|11|Rn|Rd"},
+      {"inst": "ldrsb Xd, [Xn|SP, #offS]!"                               , "op": "00111000|100|offS:9|11|Rn|Rd"},
       {"inst": "ldrsb Wd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]"          , "op": "00111000|111|Rm|option:3|s:1|10|Rn|Rd"                 , "imm": "ImmLDRB(iop, n)"},
       {"inst": "ldrsb Xd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]"          , "op": "00111000|101|Rm|option:3|s:1|10|Rn|Rd"                 , "imm": "ImmLDRB(iop, n)"},
-      {"inst": "ldrsh Wd, [Xn|SP, #zoff*2]"                              , "op": "01111001|11|zoff:12|Rn|Rd"},
-      {"inst": "ldrsh Xd, [Xn|SP, #zoff*2]"                              , "op": "01111001|10|zoff:12|Rn|Rd"},
-      {"inst": "ldrsh Wd, [Xn|SP, #soff*2]@"                             , "op": "01111000|110|soff:9|01|Rn|Rd"},
-      {"inst": "ldrsh Xd, [Xn|SP, #soff*2]@"                             , "op": "01111000|100|soff:9|01|Rn|Rd"},
-      {"inst": "ldrsh Wd, [Xn|SP, #soff*2]!"                             , "op": "01111000|110|soff:9|11|Rn|Rd"},
-      {"inst": "ldrsh Xd, [Xn|SP, #soff*2]!"                             , "op": "01111000|100|soff:9|11|Rn|Rd"},
+      {"inst": "ldrsh Wd, [Xn|SP, #offZ*2]"                              , "op": "01111001|11|offZ:12|Rn|Rd"},
+      {"inst": "ldrsh Xd, [Xn|SP, #offZ*2]"                              , "op": "01111001|10|offZ:12|Rn|Rd"},
+      {"inst": "ldrsh Wd, [Xn|SP, #offS*2]@"                             , "op": "01111000|110|offS:9|01|Rn|Rd"},
+      {"inst": "ldrsh Xd, [Xn|SP, #offS*2]@"                             , "op": "01111000|100|offS:9|01|Rn|Rd"},
+      {"inst": "ldrsh Wd, [Xn|SP, #offS*2]!"                             , "op": "01111000|110|offS:9|11|Rn|Rd"},
+      {"inst": "ldrsh Xd, [Xn|SP, #offS*2]!"                             , "op": "01111000|100|offS:9|11|Rn|Rd"},
       {"inst": "ldrsh Wd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]"          , "op": "01111000|111|Rm|option:3|s:1|10|Rn|Rd"                 , "imm": "ImmLDRH(iop, n)"},
       {"inst": "ldrsh Xd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]"          , "op": "01111000|101|Rm|option:3|s:1|10|Rn|Rd"                 , "imm": "ImmLDRH(iop, n)"},
-      {"inst": "ldrsw Xd, [Xn|SP, #zoff*4]"                              , "op": "10111001|10|zoff:12|Rn|Rd"},
-      {"inst": "ldrsw Xd, [Xn|SP, #soff*4]@"                             , "op": "10111000|100|soff:9|01|Rn|Rd"},
-      {"inst": "ldrsw Xd, [Xn|SP, #soff*4]!"                             , "op": "10111000|100|soff:9|11|Rn|Rd"},
-      {"inst": "ldrsw Xd, [PC, #soff*4]"                                 , "op": "10011000|soff:19|Rd"},
+      {"inst": "ldrsw Xd, [Xn|SP, #offZ*4]"                              , "op": "10111001|10|offZ:12|Rn|Rd"},
+      {"inst": "ldrsw Xd, [Xn|SP, #offS*4]@"                             , "op": "10111000|100|offS:9|01|Rn|Rd"},
+      {"inst": "ldrsw Xd, [Xn|SP, #offS*4]!"                             , "op": "10111000|100|offS:9|11|Rn|Rd"},
+      {"inst": "ldrsw Xd, [PC, #offS*4]"                                 , "op": "10011000|offS:19|Rd"},
       {"inst": "ldrsw Xd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]"          , "op": "10111000|101|Rm|option:3|s:1|10|Rn|Rd"                 , "imm": "ImmLDRW(iop, n)"},
-      {"inst": "ldtr Wd, [Xn|SP, #soff]"                                 , "op": "10111000|010|soff:9|10|Rn|Rd"},
-      {"inst": "ldtr Xd, [Xn|SP, #soff]"                                 , "op": "11111000|010|soff:9|10|Rn|Rd"},
-      {"inst": "ldtrb Wd, [Xn|SP, #soff]"                                , "op": "00111000|010|soff:9|10|Rn|Rd"},
-      {"inst": "ldtrh Wd, [Xn|SP, #soff]"                                , "op": "01111000|010|soff:9|10|Rn|Rd"},
-      {"inst": "ldtrsb Wd, [Xn|SP, #soff]"                               , "op": "00111000|100|soff:9|10|Rn|Rd"},
-      {"inst": "ldtrsb Xd, [Xn|SP, #soff]"                               , "op": "00111000|110|soff:9|10|Rn|Rd"},
-      {"inst": "ldtrsh Wd, [Xn|SP, #soff]"                               , "op": "01111000|100|soff:9|10|Rn|Rd"},
-      {"inst": "ldtrsh Xd, [Xn|SP, #soff]"                               , "op": "01111000|110|soff:9|10|Rn|Rd"},
-      {"inst": "ldtrsw Xd, [Xn|SP, #soff]"                               , "op": "10111000|100|soff:9|10|Rn|Rd"},
-      {"inst": "ldur Wd, [Xn|SP, #soff]"                                 , "op": "10111000|010|soff:9|00|Rn|Rd"},
-      {"inst": "ldur Xd, [Xn|SP, #soff]"                                 , "op": "11111000|010|soff:9|00|Rn|Rd"},
-      {"inst": "ldurb Wd, [Xn|SP, #soff]"                                , "op": "00111000|010|soff:9|00|Rn|Rd"},
-      {"inst": "ldurh Wd, [Xn|SP, #soff]"                                , "op": "01111000|010|soff:9|00|Rn|Rd"},
-      {"inst": "ldursb Wd, [Xn|SP, #soff]"                               , "op": "00111000|100|soff:9|00|Rn|Rd"},
-      {"inst": "ldursb Xd, [Xn|SP, #soff]"                               , "op": "00111000|110|soff:9|00|Rn|Rd"},
-      {"inst": "ldursh Wd, [Xn|SP, #soff]"                               , "op": "01111000|100|soff:9|00|Rn|Rd"},
-      {"inst": "ldursh Xd, [Xn|SP, #soff]"                               , "op": "01111000|110|soff:9|00|Rn|Rd"},
-      {"inst": "ldursw Xd, [Xn|SP, #soff]"                               , "op": "10111000|100|soff:9|00|Rn|Rd"},
-      {"inst": "ldxp Wd, Wd2, [Xn|SP, #soff*4]"                          , "op": "10001000|011|11111|0|Rd2|Rn|Rd"},
-      {"inst": "ldxp Xd, Xd2, [Xn|SP, #soff*8]"                          , "op": "11001000|011|11111|0|Rd2|Rn|Rd"},
+      {"inst": "ldtr Wd, [Xn|SP, #offS]"                                 , "op": "10111000|010|offS:9|10|Rn|Rd"},
+      {"inst": "ldtr Xd, [Xn|SP, #offS]"                                 , "op": "11111000|010|offS:9|10|Rn|Rd"},
+      {"inst": "ldtrb Wd, [Xn|SP, #offS]"                                , "op": "00111000|010|offS:9|10|Rn|Rd"},
+      {"inst": "ldtrh Wd, [Xn|SP, #offS]"                                , "op": "01111000|010|offS:9|10|Rn|Rd"},
+      {"inst": "ldtrsb Wd, [Xn|SP, #offS]"                               , "op": "00111000|100|offS:9|10|Rn|Rd"},
+      {"inst": "ldtrsb Xd, [Xn|SP, #offS]"                               , "op": "00111000|110|offS:9|10|Rn|Rd"},
+      {"inst": "ldtrsh Wd, [Xn|SP, #offS]"                               , "op": "01111000|100|offS:9|10|Rn|Rd"},
+      {"inst": "ldtrsh Xd, [Xn|SP, #offS]"                               , "op": "01111000|110|offS:9|10|Rn|Rd"},
+      {"inst": "ldtrsw Xd, [Xn|SP, #offS]"                               , "op": "10111000|100|offS:9|10|Rn|Rd"},
+      {"inst": "ldur Wd, [Xn|SP, #offS]"                                 , "op": "10111000|010|offS:9|00|Rn|Rd"},
+      {"inst": "ldur Xd, [Xn|SP, #offS]"                                 , "op": "11111000|010|offS:9|00|Rn|Rd"},
+      {"inst": "ldurb Wd, [Xn|SP, #offS]"                                , "op": "00111000|010|offS:9|00|Rn|Rd"},
+      {"inst": "ldurh Wd, [Xn|SP, #offS]"                                , "op": "01111000|010|offS:9|00|Rn|Rd"},
+      {"inst": "ldursb Wd, [Xn|SP, #offS]"                               , "op": "00111000|100|offS:9|00|Rn|Rd"},
+      {"inst": "ldursb Xd, [Xn|SP, #offS]"                               , "op": "00111000|110|offS:9|00|Rn|Rd"},
+      {"inst": "ldursh Wd, [Xn|SP, #offS]"                               , "op": "01111000|100|offS:9|00|Rn|Rd"},
+      {"inst": "ldursh Xd, [Xn|SP, #offS]"                               , "op": "01111000|110|offS:9|00|Rn|Rd"},
+      {"inst": "ldursw Xd, [Xn|SP, #offS]"                               , "op": "10111000|100|offS:9|00|Rn|Rd"},
+      {"inst": "ldxp Wd, Wd2, [Xn|SP, #offS*4]"                          , "op": "10001000|011|11111|0|Rd2|Rn|Rd"},
+      {"inst": "ldxp Xd, Xd2, [Xn|SP, #offS*8]"                          , "op": "11001000|011|11111|0|Rd2|Rn|Rd"},
       {"inst": "ldxr Wd, [Xn|SP]"                                        , "op": "10001000|010|11111|0|11111|Rn|Rd"},
       {"inst": "ldxr Xd, [Xn|SP]"                                        , "op": "11001000|010|11111|0|11111|Rn|Rd"},
       {"inst": "ldxrb Wd, [Xn|SP]"                                       , "op": "00001000|010|11111|0|11111|Rn|Rd"},
@@ -260,9 +260,9 @@
       {"inst": "orr Wd|WSP, Wn, #log_imm"                                , "op": "00110010|0|imm:13|Rn|Rd"                               , "imm": "ImmLogical(log_imm, 0)"},
       {"inst": "orr Xd|SP, Xn, #log_imm"                                 , "op": "10110010|0|imm:13|Rn|Rd"                               , "imm": "ImmLogical(log_imm, 1)"},
       {"inst": "prfm #prf_op, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n*8}]"    , "op": "11111000|101|Rm|option:3|n:1|10|Rn|prf_op:5"           , "imm": "ImmPRF(prf_op)"},
-      {"inst": "prfm #prf_op, [Xn|SP, #zoff]"                            , "op": "11111001|10|zoff:12|Rn|prf_op:5"                       , "imm": "ImmPRF(prf_op)"},
-      {"inst": "prfm #prf_op, [PC, #soff*4]"                             , "op": "11011000|soff:19|prf_op:5"                             , "imm": "ImmPRF(prf_op)"},
-      {"inst": "prfum #prf_op, [Xn|SP, #soff]"                           , "op": "11111000|100|soff:9|00|Rn|prf_op:5"                    , "imm": "ImmPRF(prf_op)"},
+      {"inst": "prfm #prf_op, [Xn|SP, #offZ]"                            , "op": "11111001|10|offZ:12|Rn|prf_op:5"                       , "imm": "ImmPRF(prf_op)"},
+      {"inst": "prfm #prf_op, [PC, #offS*4]"                             , "op": "11011000|offS:19|prf_op:5"                             , "imm": "ImmPRF(prf_op)"},
+      {"inst": "prfum #prf_op, [Xn|SP, #offS]"                           , "op": "11111000|100|offS:9|00|Rn|prf_op:5"                    , "imm": "ImmPRF(prf_op)"},
       {"inst": "pssbb"                                                   , "op": "11010101|000|00011|0011|0100|100|11111"},
       {"inst": "rbit Wd, Wn"                                             , "op": "01011010|110|00000|0|00000|Rn|Rd"},
       {"inst": "rbit Xd, Xn"                                             , "op": "11011010|110|00000|0|00000|Rn|Rd"},
@@ -291,7 +291,7 @@
       {"inst": "sev"                                                     , "op": "11010101|000|00011|0010|0000|100|11111"},
       {"inst": "sevl"                                                    , "op": "11010101|000|00011|0010|0000|101|11111"},
       {"inst": "smaddl Xd, Wn, Wm, Xa"                                   , "op": "10011011|001|Rm|0|Ra|Rn|Rd"},
-      {"inst": "smc #zimm"                                               , "op": "11010100|000|zimm:16|00011"},
+      {"inst": "smc #immZ"                                               , "op": "11010100|000|immZ:16|00011"},
       {"inst": "smnegl Xd, Wn, Wm"                                       , "op": "10011011|001|Rm|1|11111|Rn|Rd"},
       {"inst": "smsubl Xd, Wn, Wm, Xa"                                   , "op": "10011011|001|Rm|1|Ra|Rn|Rd"},
       {"inst": "smulh Xd, Xn, Xm"                                        , "op": "10011011|010|Rm|0|11111|Rn|Rd"},
@@ -307,34 +307,34 @@
       {"inst": "stlxr Wd, Xs, [Xn|SP]"                                   , "op": "11001000|000|Rd|1|11111|Rn|Rs"},
       {"inst": "stlxrb Wd, Ws, [Xn|SP]"                                  , "op": "00001000|000|Rd|1|11111|Rn|Rs"},
       {"inst": "stlxrh Wd, Xs, [Xn|SP]"                                  , "op": "01001000|000|Rd|1|11111|Rn|Rs"},
-      {"inst": "stnp Ws, Ws2, [Xn|SP, #simm*4]"                          , "op": "00101000|00|simm:7|Rs2|Rn|Rs"},
-      {"inst": "stnp Xs, Xs2, [Xn|SP, #simm*8]"                          , "op": "10101000|00|simm:7|Rs2|Rn|Rs"},
-      {"inst": "stp Ws, Ws2, [Xn|SP, #simm*4]{@}{!}"                     , "op": "0010100|!post|W|0|simm:7|Rs2|Rn|Rs"},
-      {"inst": "stp Xs, Xs2, [Xn|SP, #simm*8]{@}{!}"                     , "op": "1010100|!post|W|0|simm:7|Rs2|Rn|Rs"},
-      {"inst": "str Ws, [Xn|SP, #zoff*4]"                                , "op": "10111001|00|zoff:12|Rn|Rs"},
-      {"inst": "str Xs, [Xn|SP, #zoff*8]"                                , "op": "11111001|00|zoff:12|Rn|Rs"},
-      {"inst": "str Ws, [Xn|SP, #soff*4]@"                               , "op": "10111000|000|soff:9|01|Rn|Rs"},
-      {"inst": "str Xs, [Xn|SP, #soff*8]@"                               , "op": "11111000|000|soff:9|01|Rn|Rs"},
-      {"inst": "str Ws, [Xn|SP, #soff*4]!"                               , "op": "10111000|000|soff:9|11|Rn|Rs"},
-      {"inst": "str Xs, [Xn|SP, #soff*8]!"                               , "op": "11111000|000|soff:9|11|Rn|Rs"},
+      {"inst": "stnp Ws, Ws2, [Xn|SP, #offS*4]"                          , "op": "00101000|00|offS:7|Rs2|Rn|Rs"},
+      {"inst": "stnp Xs, Xs2, [Xn|SP, #offS*8]"                          , "op": "10101000|00|offS:7|Rs2|Rn|Rs"},
+      {"inst": "stp Ws, Ws2, [Xn|SP, #offS*4]{@}{!}"                     , "op": "0010100|!post|W|0|offS:7|Rs2|Rn|Rs"},
+      {"inst": "stp Xs, Xs2, [Xn|SP, #offS*8]{@}{!}"                     , "op": "1010100|!post|W|0|offS:7|Rs2|Rn|Rs"},
+      {"inst": "str Ws, [Xn|SP, #offZ*4]"                                , "op": "10111001|00|offZ:12|Rn|Rs"},
+      {"inst": "str Xs, [Xn|SP, #offZ*8]"                                , "op": "11111001|00|offZ:12|Rn|Rs"},
+      {"inst": "str Ws, [Xn|SP, #offS*4]@"                               , "op": "10111000|000|offS:9|01|Rn|Rs"},
+      {"inst": "str Xs, [Xn|SP, #offS*8]@"                               , "op": "11111000|000|offS:9|01|Rn|Rs"},
+      {"inst": "str Ws, [Xn|SP, #offS*4]!"                               , "op": "10111000|000|offS:9|11|Rn|Rs"},
+      {"inst": "str Xs, [Xn|SP, #offS*8]!"                               , "op": "11111000|000|offS:9|11|Rn|Rs"},
       {"inst": "str Ws, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]"            , "op": "10111000|001|Rm|option:3|s:1|10|Rn|Rs"                 , "imm": "ImmLDR_STR(iop, n)"},
       {"inst": "str Xs, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]"            , "op": "11111000|001|Rm|option:3|s:1|10|Rn|Rs"                 , "imm": "ImmLDR_STR(iop, n)"},
-      {"inst": "strb Ws, [Xn|SP, #zoff]"                                 , "op": "00111001|00|zoff:12|Rn|Rs"},
-      {"inst": "strb Ws, [Xn|SP, #soff]@"                                , "op": "00111000|000|soff:9|01|Rn|Rs"},
-      {"inst": "strb Ws, [Xn|SP, #soff]!"                                , "op": "00111000|000|soff:9|11|Rn|Rs"},
+      {"inst": "strb Ws, [Xn|SP, #offZ]"                                 , "op": "00111001|00|offZ:12|Rn|Rs"},
+      {"inst": "strb Ws, [Xn|SP, #offS]@"                                , "op": "00111000|000|offS:9|01|Rn|Rs"},
+      {"inst": "strb Ws, [Xn|SP, #offS]!"                                , "op": "00111000|000|offS:9|11|Rn|Rs"},
       {"inst": "strb Ws, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]"           , "op": "00111000|001|Rm|option:3|s:1|10|Rn|Rs"                 , "imm": "ImmLDRB_STRB(iop, n)"},
-      {"inst": "strh Ws, [Xn|SP, #zoff*2]"                               , "op": "01111001|00|zoff:12|Rn|Rs"},
-      {"inst": "strh Ws, [Xn|SP, #soff*2]@"                              , "op": "01111000|000|soff:9|01|Rn|Rs"},
-      {"inst": "strh Ws, [Xn|SP, #soff*2]!"                              , "op": "01111000|000|soff:9|11|Rn|Rs"},
+      {"inst": "strh Ws, [Xn|SP, #offZ*2]"                               , "op": "01111001|00|offZ:12|Rn|Rs"},
+      {"inst": "strh Ws, [Xn|SP, #offS*2]@"                              , "op": "01111000|000|offS:9|01|Rn|Rs"},
+      {"inst": "strh Ws, [Xn|SP, #offS*2]!"                              , "op": "01111000|000|offS:9|11|Rn|Rs"},
       {"inst": "strh Ws, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]"           , "op": "01111000|001|Rm|option:3|s:1|10|Rn|Rs"                 , "imm": "ImmLDRH_STRH(iop, n)"},
-      {"inst": "sttr Ws, [Xn|SP, #soff]"                                 , "op": "10111000|000|soff:9|10|Rn|Rs"},
-      {"inst": "sttr Xs, [Xn|SP, #soff]"                                 , "op": "11111000|000|soff:9|10|Rn|Rs"},
-      {"inst": "sttrb Ws, [Xn|SP, #soff]"                                , "op": "00111000|000|soff:9|10|Rn|Rs"},
-      {"inst": "sttrh Ws, [Xn|SP, #soff]"                                , "op": "01111000|000|soff:9|10|Rn|Rs"},
-      {"inst": "stur Ws, [Xn|SP, #soff]"                                 , "op": "10111000|000|soff:9|00|Rn|Rs"},
-      {"inst": "stur Xs, [Xn|SP, #soff]"                                 , "op": "11111000|000|soff:9|00|Rn|Rs"},
-      {"inst": "sturb Ws, [Xn|SP, #soff]"                                , "op": "00111000|000|soff:9|00|Rn|Rs"},
-      {"inst": "sturh Ws, [Xn|SP, #soff]"                                , "op": "01111000|000|soff:9|00|Rn|Rs"},
+      {"inst": "sttr Ws, [Xn|SP, #offS]"                                 , "op": "10111000|000|offS:9|10|Rn|Rs"},
+      {"inst": "sttr Xs, [Xn|SP, #offS]"                                 , "op": "11111000|000|offS:9|10|Rn|Rs"},
+      {"inst": "sttrb Ws, [Xn|SP, #offS]"                                , "op": "00111000|000|offS:9|10|Rn|Rs"},
+      {"inst": "sttrh Ws, [Xn|SP, #offS]"                                , "op": "01111000|000|offS:9|10|Rn|Rs"},
+      {"inst": "stur Ws, [Xn|SP, #offS]"                                 , "op": "10111000|000|offS:9|00|Rn|Rs"},
+      {"inst": "stur Xs, [Xn|SP, #offS]"                                 , "op": "11111000|000|offS:9|00|Rn|Rs"},
+      {"inst": "sturb Ws, [Xn|SP, #offS]"                                , "op": "00111000|000|offS:9|00|Rn|Rs"},
+      {"inst": "sturh Ws, [Xn|SP, #offS]"                                , "op": "01111000|000|offS:9|00|Rn|Rs"},
       {"inst": "stxp Wd, Ws, Ws2, [Xn|SP]"                               , "op": "10001000|001|Rd|0|Rs2|Rn|Rs"},
       {"inst": "stxp Wd, Xs, Xs2, [Xn|SP]"                               , "op": "11001000|001|Rd|0|Rs2|Rn|Rs"},
       {"inst": "stxr Wd, Ws, [Xn|SP]"                                    , "op": "10001000|000|Rd|0|11111|Rn|Rs"},
@@ -353,7 +353,7 @@
       {"inst": "subs Xd, Xn|SP, Rm, {extend #n}"                         , "op": "11101011|00|1|Rm|option:3|n:3|Rn|Rd"                   , "io": "N=W Z=W C=W V=W"},
       {"inst": "subs Wd|WSP, Wn|WSP, #immZ, {lsl #n=0|12}"               , "op": "01110001|0|n:1|immZ:12|Rn|Rd"                          , "io": "N=W Z=W C=W V=W"},
       {"inst": "subs Xd|SP, Xn|SP, #immZ, {lsl #n=0|12}"                 , "op": "11110001|0|n:1|immZ:12|Rn|Rd"                          , "io": "N=W Z=W C=W V=W"},
-      {"inst": "svc #zimm"                                               , "op": "11010100|000|zimm:16|00001"},
+      {"inst": "svc #immZ"                                               , "op": "11010100|000|immZ:16|00001"},
       {"inst": "sxtb Wd, Wn"                                             , "op": "00010011|000|00000|0|00111|Rn|Rd"},
       {"inst": "sxtb Xd, Wn"                                             , "op": "10010011|010|00000|0|00111|Rn|Rd"},
       {"inst": "sxth Wd, Wn"                                             , "op": "00010011|000|00000|0|01111|Rn|Rd"},
@@ -431,20 +431,20 @@
       {"inst": "ctz Xd, Xn"                                              , "op": "11011010|110|00000|0|00110|Rn|Rd"},
       {"inst": "smax Wd, Wn, Wm"                                         , "op": "00011010|110|Rm|0|11000|Rn|Rd"},
       {"inst": "smax Xd, Xn, Xm"                                         , "op": "10011010|110|Rm|0|11000|Rn|Rd"},
-      {"inst": "smax Wd, Wn, #simm"                                      , "op": "00010001|110|000|simm:8|Rn|Rd"},
-      {"inst": "smax Xd, Xn, #simm"                                      , "op": "10010001|110|000|simm:8|Rn|Rd"},
+      {"inst": "smax Wd, Wn, #immS"                                      , "op": "00010001|110|000|immS:8|Rn|Rd"},
+      {"inst": "smax Xd, Xn, #immS"                                      , "op": "10010001|110|000|immS:8|Rn|Rd"},
       {"inst": "smin Wd, Wn, Wm"                                         , "op": "00011010|110|Rm|0|11010|Rn|Rd"},
       {"inst": "smin Xd, Xn, Xm"                                         , "op": "10011010|110|Rm|0|11010|Rn|Rd"},
-      {"inst": "smin Wd, Wn, #simm"                                      , "op": "00010001|110|010|simm:8|Rn|Rd"},
-      {"inst": "smin Xd, Xn, #simm"                                      , "op": "10010001|110|010|simm:8|Rn|Rd"},
+      {"inst": "smin Wd, Wn, #immS"                                      , "op": "00010001|110|010|immS:8|Rn|Rd"},
+      {"inst": "smin Xd, Xn, #immS"                                      , "op": "10010001|110|010|immS:8|Rn|Rd"},
       {"inst": "umax Wd, Wn, Wm"                                         , "op": "00011010|110|Rm|0|11001|Rn|Rd"},
       {"inst": "umax Xd, Xn, Xm"                                         , "op": "10011010|110|Rm|0|11001|Rn|Rd"},
-      {"inst": "umax Wd, Wn, #simm"                                      , "op": "00010001|110|001|simm:8|Rn|Rd"},
-      {"inst": "umax Xd, Xn, #simm"                                      , "op": "10010001|110|001|simm:8|Rn|Rd"},
+      {"inst": "umax Wd, Wn, #immZ"                                      , "op": "00010001|110|001|immZ:8|Rn|Rd"},
+      {"inst": "umax Xd, Xn, #immZ"                                      , "op": "10010001|110|001|immZ:8|Rn|Rd"},
       {"inst": "umin Wd, Wn, Wm"                                         , "op": "00011010|110|Rm|0|11011|Rn|Rd"},
       {"inst": "umin Xd, Xn, Xm"                                         , "op": "10011010|110|Rm|0|11011|Rn|Rd"},
-      {"inst": "umin Wd, Wn, #simm"                                      , "op": "00010001|110|011|simm:8|Rn|Rd"},
-      {"inst": "umin Xd, Xn, #simm"                                      , "op": "10010001|110|011|simm:8|Rn|Rd"}
+      {"inst": "umin Wd, Wn, #immZ"                                      , "op": "00010001|110|011|immZ:8|Rn|Rd"},
+      {"inst": "umin Xd, Xn, #immZ"                                      , "op": "10010001|110|011|immZ:8|Rn|Rd"}
     ]},
 
     {"category": "GP GP_EXT", "ext": "D128", "data": [
@@ -510,21 +510,21 @@
     ]},
 
     {"category": "GP GP_EXT", "ext": "LRCPC2", "data": [
-      {"inst": "ldapur Wd, [Xn|SP, #soff]"                               , "op": "10011001|010|soff:9|00|Rn|Rd"},
-      {"inst": "ldapur Xd, [Xn|SP, #soff]"                               , "op": "11011001|010|soff:9|00|Rn|Rd"},
-      {"inst": "ldapurb Wd, [Xn|SP, #soff]"                              , "op": "00011001|010|soff:9|00|Rn|Rd"},
-      {"inst": "ldapurh Wd, [Xn|SP, #soff]"                              , "op": "01011001|010|soff:9|00|Rn|Rd"},
+      {"inst": "ldapur Wd, [Xn|SP, #offS]"                               , "op": "10011001|010|offS:9|00|Rn|Rd"},
+      {"inst": "ldapur Xd, [Xn|SP, #offS]"                               , "op": "11011001|010|offS:9|00|Rn|Rd"},
+      {"inst": "ldapurb Wd, [Xn|SP, #offS]"                              , "op": "00011001|010|offS:9|00|Rn|Rd"},
+      {"inst": "ldapurh Wd, [Xn|SP, #offS]"                              , "op": "01011001|010|offS:9|00|Rn|Rd"},
 
-      {"inst": "ldapursb Wd, [Xn|SP, #soff]"                             , "op": "00011001|110|soff:9|00|Rn|Rd"},
-      {"inst": "ldapursb Xd, [Xn|SP, #soff]"                             , "op": "00011001|100|soff:9|00|Rn|Rd"},
-      {"inst": "ldapursh Wd, [Xn|SP, #soff]"                             , "op": "01011001|110|soff:9|00|Rn|Rd"},
-      {"inst": "ldapursh Xd, [Xn|SP, #soff]"                             , "op": "01011001|100|soff:9|00|Rn|Rd"},
-      {"inst": "ldapursw Xd, [Xn|SP, #soff]"                             , "op": "10011001|100|soff:9|00|Rn|Rd"},
+      {"inst": "ldapursb Wd, [Xn|SP, #offS]"                             , "op": "00011001|110|offS:9|00|Rn|Rd"},
+      {"inst": "ldapursb Xd, [Xn|SP, #offS]"                             , "op": "00011001|100|offS:9|00|Rn|Rd"},
+      {"inst": "ldapursh Wd, [Xn|SP, #offS]"                             , "op": "01011001|110|offS:9|00|Rn|Rd"},
+      {"inst": "ldapursh Xd, [Xn|SP, #offS]"                             , "op": "01011001|100|offS:9|00|Rn|Rd"},
+      {"inst": "ldapursw Xd, [Xn|SP, #offS]"                             , "op": "10011001|100|offS:9|00|Rn|Rd"},
 
-      {"inst": "stlur Ws, [Xn|SP, #soff]"                                , "op": "10011001|000|soff:9|00|Rn|Rs"},
-      {"inst": "stlur Xs, [Xn|SP, #soff]"                                , "op": "11011001|000|soff:9|00|Rn|Rs"},
-      {"inst": "stlurb Ws, [Xn|SP, #soff]"                               , "op": "00011001|000|soff:9|00|Rn|Rs"},
-      {"inst": "stlurh Ws, [Xn|SP, #soff]"                               , "op": "01011001|000|soff:9|00|Rn|Rs"}
+      {"inst": "stlur Ws, [Xn|SP, #offS]"                                , "op": "10011001|000|offS:9|00|Rn|Rs"},
+      {"inst": "stlur Xs, [Xn|SP, #offS]"                                , "op": "11011001|000|offS:9|00|Rn|Rs"},
+      {"inst": "stlurb Ws, [Xn|SP, #offS]"                               , "op": "00011001|000|offS:9|00|Rn|Rs"},
+      {"inst": "stlurh Ws, [Xn|SP, #offS]"                               , "op": "01011001|000|offS:9|00|Rn|Rs"}
     ]},
 
     {"category": "GP GP_EXT", "ext": "LRCPC3", "data": [
@@ -981,12 +981,12 @@
       {"inst": "cmpp Xn|SP, Xm|SP"                                       , "op": "10111010|110|Rm|000000|Rn|11111"},
       {"inst": "gmi Xd, Xn|SP, Xm"                                       , "op": "10011010|110|Rm|000101|Rn|Rd"},
       {"inst": "irg Xd, Xn|SP, Xm"                                       , "op": "10011010|110|Rm|000100|Rn|Rd"},
-      {"inst": "ldg Xd, [Xn|SP, #soff*16]"                               , "op": "11011001|011|soff:9|00|Rn|Rd"},
-      {"inst": "st2g Xs|SP, [Xn|SP, #soff*16]{@}{!}"                     , "op": "11011001|101|soff:9|!post|W|Rn|Rs"},
-      {"inst": "stg Xs|SP, [Xn|SP, #soff*16]{@}{!}"                      , "op": "11011001|001|soff:9|!post|W|Rn|Rs"},
-      {"inst": "stgp Xs, Xs2, [Xn|SP, #soff*16]{@}{!}"                   , "op": "0110100|!post|W|0|soff:7|Rs2|Rn|Rs"},
-      {"inst": "stz2g Xs|SP, [Xn|SP, #soff*16]{@}{!}"                    , "op": "11011001|111|soff:9|!post|W|Rn|Rs"},
-      {"inst": "stzg Xs|SP, [Xn|SP, #soff*16]{@}{!}"                     , "op": "11011001|011|soff:9|!post|W|Rn|Rs"},
+      {"inst": "ldg Xd, [Xn|SP, #offS*16]"                               , "op": "11011001|011|offS:9|00|Rn|Rd"},
+      {"inst": "st2g Xs|SP, [Xn|SP, #offS*16]{@}{!}"                     , "op": "11011001|101|offS:9|!post|W|Rn|Rs"},
+      {"inst": "stg Xs|SP, [Xn|SP, #offS*16]{@}{!}"                      , "op": "11011001|001|offS:9|!post|W|Rn|Rs"},
+      {"inst": "stgp Xs, Xs2, [Xn|SP, #offS*16]{@}{!}"                   , "op": "0110100|!post|W|0|offS:7|Rs2|Rn|Rs"},
+      {"inst": "stz2g Xs|SP, [Xn|SP, #offS*16]{@}{!}"                    , "op": "11011001|111|offS:9|!post|W|Rn|Rs"},
+      {"inst": "stzg Xs|SP, [Xn|SP, #offS*16]{@}{!}"                     , "op": "11011001|011|offS:9|!post|W|Rn|Rs"},
       {"inst": "subg Xd|SP, Xn|SP, #imm1, #imm2"                         , "op": "11010001|10|imm1:6|00|imm2:4|Rn|Rd"},
       {"inst": "subp Xd, Xn|SP, Xm|SP"                                   , "op": "10011010|110|Rm|0|00000|Rn|Rd"},
       {"inst": "subps Xd, Xn|SP, Xm|SP"                                  , "op": "10011010|110|Rm|0|00000|Rn|Rd"                         , "io": "N=W Z=W C=W V=W"}
@@ -1023,8 +1023,8 @@
       {"inst": "brabz Xn"                                                , "op": "11010110|000|11111|0000|11|Rn|11111"                   , "control": "call"},
       {"inst": "eretaa"                                                  , "op": "11010110|100|11111|0000|10|11111|11111"                , "control": "return"},
       {"inst": "eretab"                                                  , "op": "11010110|100|11111|0000|11|11111|11111"                , "control": "return"},
-      {"inst": "ldraa Xd, [Xn|SP, #soff]{!}"                             , "op": "11111000|0|soff:1|1|soff:9|W1|Rn|Rd"},
-      {"inst": "ldrab Xd, [Xn|SP, #soff]{!}"                             , "op": "11111000|1|soff:1|1|soff:9|W1|Rn|Rd"},
+      {"inst": "ldraa Xd, [Xn|SP, #offS]{!}"                             , "op": "11111000|0|offS:1|1|offS:9|W1|Rn|Rd"},
+      {"inst": "ldrab Xd, [Xn|SP, #offS]{!}"                             , "op": "11111000|1|offS:1|1|offS:9|W1|Rn|Rd"},
       {"inst": "pacda Xd, Xn|SP"                                         , "op": "11011010|110|00001|0|00010|Rn|Rd"},
       {"inst": "pacdb Xd, Xn|SP"                                         , "op": "11011010|110|00001|0|00011|Rn|Rd"},
       {"inst": "pacdza Xd"                                               , "op": "11011010|110|00001|0|01010|11111|Rd"},
@@ -1768,40 +1768,40 @@
       {"inst": "ld4r 4x{Vd.t}, [Xn|SP, Xm]@"                             , "op": "01001101|111|Rm   |1110|sz|Rn|Vd"                      , "t": "16B 8H 4S 2D"},
       {"inst": "ld4r 4x{Vd.t}, [Xn|SP, #off==4<<sz]@"                    , "op": "00001101|111|11111|1110|sz|Rn|Vd"                      , "t": "8B 4H 2S 1D"},
       {"inst": "ld4r 4x{Vd.t}, [Xn|SP, #off==4<<sz]@"                    , "op": "01001101|111|11111|1110|sz|Rn|Vd"                      , "t": "16B 8H 4S 2D"},
-      {"inst": "ldnp Sd, Sd2, [Xn|SP, #soff*4]"                          , "op": "00101100|01|soff:7|Vd2|Vn|Vd"},
-      {"inst": "ldnp Dd, Dd2, [Xn|SP, #soff*8]"                          , "op": "01101100|01|soff:7|Vd2|Vn|Vd"},
-      {"inst": "ldnp Qd, Qd2, [Xn|SP, #soff*16]"                         , "op": "10101100|01|soff:7|Vd2|Vn|Vd"},
-      {"inst": "ldp Sd, Sd2, [Xn|SP, #soff*4]{@}{!}"                     , "op": "0010110|!post|W|1|soff:7|Vd2|Vn|Vd"},
-      {"inst": "ldp Dd, Dd2, [Xn|SP, #soff*8]{@}{!}"                     , "op": "0110110|!post|W|1|soff:7|Vd2|Vn|Vd"},
-      {"inst": "ldp Qd, Qd2, [Xn|SP, #soff*16]{@}{!}"                    , "op": "1010110|!post|W|1|soff:7|Vd2|Vn|Vd"},
+      {"inst": "ldnp Sd, Sd2, [Xn|SP, #offS*4]"                          , "op": "00101100|01|offS:7|Vd2|Vn|Vd"},
+      {"inst": "ldnp Dd, Dd2, [Xn|SP, #offS*8]"                          , "op": "01101100|01|offS:7|Vd2|Vn|Vd"},
+      {"inst": "ldnp Qd, Qd2, [Xn|SP, #offS*16]"                         , "op": "10101100|01|offS:7|Vd2|Vn|Vd"},
+      {"inst": "ldp Sd, Sd2, [Xn|SP, #offS*4]{@}{!}"                     , "op": "0010110|!post|W|1|offS:7|Vd2|Vn|Vd"},
+      {"inst": "ldp Dd, Dd2, [Xn|SP, #offS*8]{@}{!}"                     , "op": "0110110|!post|W|1|offS:7|Vd2|Vn|Vd"},
+      {"inst": "ldp Qd, Qd2, [Xn|SP, #offS*16]{@}{!}"                    , "op": "1010110|!post|W|1|offS:7|Vd2|Vn|Vd"},
       {"inst": "ldr Bd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]"            , "op": "00111100|011|Rm|option:3|n:1|10|Rn|Vd"},
       {"inst": "ldr Hd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]"            , "op": "01111100|011|Rm|option:3|n:1|10|Rn|Vd"},
       {"inst": "ldr Sd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n*2}]"          , "op": "10111100|011|Rm|option:3|n:1|10|Rn|Vd"},
       {"inst": "ldr Dd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n*3}]"          , "op": "11111100|011|Rm|option:3|n:1|10|Rn|Vd"},
       {"inst": "ldr Qd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n*4}]"          , "op": "00111100|111|Rm|option:3|n:1|10|Rn|Vd"},
-      {"inst": "ldr Sd, [PC, #soff*4]"                                   , "op": "00011100|soff:19|Vd"},
-      {"inst": "ldr Dd, [PC, #soff*4]"                                   , "op": "01011100|soff:19|Vd"},
-      {"inst": "ldr Qd, [PC, #soff*4]"                                   , "op": "10011100|soff:19|Vd"},
-      {"inst": "ldr Bd, [Xn|SP, #zoff]"                                  , "op": "00111101|01|zoff:12|Rn|Vd"},
-      {"inst": "ldr Hd, [Xn|SP, #zoff*2]"                                , "op": "01111101|01|zoff:12|Rn|Vd"},
-      {"inst": "ldr Sd, [Xn|SP, #zoff*4]"                                , "op": "10111101|01|zoff:12|Rn|Vd"},
-      {"inst": "ldr Dd, [Xn|SP, #zoff*8]"                                , "op": "11111101|01|zoff:12|Rn|Vd"},
-      {"inst": "ldr Qd, [Xn|SP, #zoff*16]"                               , "op": "00111101|11|zoff:12|Rn|Vd"},
-      {"inst": "ldr Bd, [Xn|SP, #soff]!"                                 , "op": "00111100|010|soff:9|11|Rn|Vd"},
-      {"inst": "ldr Hd, [Xn|SP, #soff*2]!"                               , "op": "01111100|010|soff:9|11|Rn|Vd"},
-      {"inst": "ldr Sd, [Xn|SP, #soff*4]!"                               , "op": "10111100|010|soff:9|11|Rn|Vd"},
-      {"inst": "ldr Dd, [Xn|SP, #soff*8]!"                               , "op": "11111100|010|soff:9|11|Rn|Vd"},
-      {"inst": "ldr Qd, [Xn|SP, #soff*16]!"                              , "op": "00111100|110|soff:9|11|Rn|Vd"},
-      {"inst": "ldr Bd, [Xn|SP, #soff]@"                                 , "op": "00111100|010|soff:9|01|Rn|Vd"},
-      {"inst": "ldr Hd, [Xn|SP, #soff*2]@"                               , "op": "01111100|010|soff:9|01|Rn|Vd"},
-      {"inst": "ldr Sd, [Xn|SP, #soff*4]@"                               , "op": "10111100|010|soff:9|01|Rn|Vd"},
-      {"inst": "ldr Dd, [Xn|SP, #soff*8]@"                               , "op": "11111100|010|soff:9|01|Rn|Vd"},
-      {"inst": "ldr Qd, [Xn|SP, #soff*16]@"                              , "op": "00111100|110|soff:9|01|Rn|Vd"},
-      {"inst": "ldur Bd, [Xn|SP, #soff]"                                 , "op": "00111100|010|soff:9|00|Rn|Vd"},
-      {"inst": "ldur Hd, [Xn|SP, #soff]"                                 , "op": "01111100|010|soff:9|00|Rn|Vd"},
-      {"inst": "ldur Sd, [Xn|SP, #soff]"                                 , "op": "10111100|010|soff:9|00|Rn|Vd"},
-      {"inst": "ldur Dd, [Xn|SP, #soff]"                                 , "op": "11111100|010|soff:9|00|Rn|Vd"},
-      {"inst": "ldur Qd, [Xn|SP, #soff]"                                 , "op": "00111100|110|soff:9|00|Rn|Vd"},
+      {"inst": "ldr Sd, [PC, #offS*4]"                                   , "op": "00011100|offS:19|Vd"},
+      {"inst": "ldr Dd, [PC, #offS*4]"                                   , "op": "01011100|offS:19|Vd"},
+      {"inst": "ldr Qd, [PC, #offS*4]"                                   , "op": "10011100|offS:19|Vd"},
+      {"inst": "ldr Bd, [Xn|SP, #offZ]"                                  , "op": "00111101|01|offZ:12|Rn|Vd"},
+      {"inst": "ldr Hd, [Xn|SP, #offZ*2]"                                , "op": "01111101|01|offZ:12|Rn|Vd"},
+      {"inst": "ldr Sd, [Xn|SP, #offZ*4]"                                , "op": "10111101|01|offZ:12|Rn|Vd"},
+      {"inst": "ldr Dd, [Xn|SP, #offZ*8]"                                , "op": "11111101|01|offZ:12|Rn|Vd"},
+      {"inst": "ldr Qd, [Xn|SP, #offZ*16]"                               , "op": "00111101|11|offZ:12|Rn|Vd"},
+      {"inst": "ldr Bd, [Xn|SP, #offS]!"                                 , "op": "00111100|010|offS:9|11|Rn|Vd"},
+      {"inst": "ldr Hd, [Xn|SP, #offS*2]!"                               , "op": "01111100|010|offS:9|11|Rn|Vd"},
+      {"inst": "ldr Sd, [Xn|SP, #offS*4]!"                               , "op": "10111100|010|offS:9|11|Rn|Vd"},
+      {"inst": "ldr Dd, [Xn|SP, #offS*8]!"                               , "op": "11111100|010|offS:9|11|Rn|Vd"},
+      {"inst": "ldr Qd, [Xn|SP, #offS*16]!"                              , "op": "00111100|110|offS:9|11|Rn|Vd"},
+      {"inst": "ldr Bd, [Xn|SP, #offS]@"                                 , "op": "00111100|010|offS:9|01|Rn|Vd"},
+      {"inst": "ldr Hd, [Xn|SP, #offS*2]@"                               , "op": "01111100|010|offS:9|01|Rn|Vd"},
+      {"inst": "ldr Sd, [Xn|SP, #offS*4]@"                               , "op": "10111100|010|offS:9|01|Rn|Vd"},
+      {"inst": "ldr Dd, [Xn|SP, #offS*8]@"                               , "op": "11111100|010|offS:9|01|Rn|Vd"},
+      {"inst": "ldr Qd, [Xn|SP, #offS*16]@"                              , "op": "00111100|110|offS:9|01|Rn|Vd"},
+      {"inst": "ldur Bd, [Xn|SP, #offS]"                                 , "op": "00111100|010|offS:9|00|Rn|Vd"},
+      {"inst": "ldur Hd, [Xn|SP, #offS]"                                 , "op": "01111100|010|offS:9|00|Rn|Vd"},
+      {"inst": "ldur Sd, [Xn|SP, #offS]"                                 , "op": "10111100|010|offS:9|00|Rn|Vd"},
+      {"inst": "ldur Dd, [Xn|SP, #offS]"                                 , "op": "11111100|010|offS:9|00|Rn|Vd"},
+      {"inst": "ldur Qd, [Xn|SP, #offS]"                                 , "op": "00111100|110|offS:9|00|Rn|Vd"},
       {"inst": "mla Vx.t, Vn.t, Vm.t"                                    , "op": "00001110|sz|1|Vm|10010|1|Vn|Vx"                        , "t": "8B 4H 2S"},
       {"inst": "mla Vx.t, Vn.t, Vm.t"                                    , "op": "01001110|sz|1|Vm|10010|1|Vn|Vx"                        , "t": "16B 8H 4S"},
       {"inst": "mla Vx.4H, Vn.4H, Vm.H[#idx]"                            , "op": "00101111|01|idx[1:0]|Vm:4|0000|idx[2]|0|Vn|Vx"},
@@ -1934,18 +1934,18 @@
       {"inst": "sminv Hd, Vn.4H"                                         , "op": "00001110|01|11000|11010|10|Vn|Vd"},
       {"inst": "sminv Hd, Vn.8H"                                         , "op": "01001110|01|11000|11010|10|Vn|Vd"},
       {"inst": "sminv Sd, Vn.4S"                                         , "op": "01001110|10|11000|11010|10|Vn|Vd"},
-      {"inst": "smlal Vd.ta, Vn.tb, Vm.tb"                               , "op": "00001110|sz|1|Vm|10000|0|Vn|Vd"                        , "t": "8H.8B 4S.4H 2D.2S"},
-      {"inst": "smlal2 Vd.ta, Vn.tb, Vm.tb"                              , "op": "01001110|sz|1|Vm|10000|0|Vn|Vd"                        , "t": "8H.16B 4S.8H 2D.4S"},
-      {"inst": "smlal Vd.4S, Vn.4H, Vm.H[#dx]"                           , "op": "00001111|01|idx[1:0]|Vm:4|0010|idx[2]|0|Vn|Vd"},
-      {"inst": "smlal2 Vd.4S, Vn.8H, Vm.H[#dx]"                          , "op": "01001111|01|idx[1:0]|Vm:4|0010|idx[2]|0|Vn|Vd"},
-      {"inst": "smlal Vd.2D, Vn.2S, Vm.S[#dx]"                           , "op": "00001111|10|idx[0]  |Vm  |0010|idx[1]|0|Vn|Vd"},
-      {"inst": "smlal2 Vd.2D, Vn.4S, Vm.S[#dx]"                          , "op": "01001111|10|idx[0]  |Vm  |0010|idx[1]|0|Vn|Vd"},
-      {"inst": "smlsl Vd.ta, Vn.tb, Vm.tb"                               , "op": "00001110|sz|1|Vm|10100|0|Vn|Vd"                        , "t": "8H.8B 4S.4H 2D.2S"},
-      {"inst": "smlsl2 Vd.ta, Vn.tb, Vm.tb"                              , "op": "01001110|sz|1|Vm|10100|0|Vn|Vd"                        , "t": "8H.16B 4S.8H 2D.4S"},
-      {"inst": "smlsl Vd.4S, Vn.4H, Vm.H[#dx]"                           , "op": "00001111|01|idx[1:0]|Vm:4|0110|idx[2]|0|Vn|Vd"},
-      {"inst": "smlsl2 Vd.4S, Vn.8H, Vm.H[#dx]"                          , "op": "01001111|01|idx[1:0]|Vm:4|0110|idx[2]|0|Vn|Vd"},
-      {"inst": "smlsl Vd.2D, Vn.2S, Vm.S[#dx]"                           , "op": "00001111|10|idx[0]  |Vm  |0110|idx[1]|0|Vn|Vd"},
-      {"inst": "smlsl2 Vd.2D, Vn.4S, Vm.S[#dx]"                          , "op": "01001111|10|idx[0]  |Vm  |0110|idx[1]|0|Vn|Vd"},
+      {"inst": "smlal Vx.ta, Vn.tb, Vm.tb"                               , "op": "00001110|sz|1|Vm|10000|0|Vn|Vx"                        , "t": "8H.8B 4S.4H 2D.2S"},
+      {"inst": "smlal2 Vx.ta, Vn.tb, Vm.tb"                              , "op": "01001110|sz|1|Vm|10000|0|Vn|Vx"                        , "t": "8H.16B 4S.8H 2D.4S"},
+      {"inst": "smlal Vx.4S, Vn.4H, Vm.H[#dx]"                           , "op": "00001111|01|idx[1:0]|Vm:4|0010|idx[2]|0|Vn|Vx"},
+      {"inst": "smlal2 Vx.4S, Vn.8H, Vm.H[#dx]"                          , "op": "01001111|01|idx[1:0]|Vm:4|0010|idx[2]|0|Vn|Vx"},
+      {"inst": "smlal Vx.2D, Vn.2S, Vm.S[#dx]"                           , "op": "00001111|10|idx[0]  |Vm  |0010|idx[1]|0|Vn|Vx"},
+      {"inst": "smlal2 Vx.2D, Vn.4S, Vm.S[#dx]"                          , "op": "01001111|10|idx[0]  |Vm  |0010|idx[1]|0|Vn|Vx"},
+      {"inst": "smlsl Vx.ta, Vn.tb, Vm.tb"                               , "op": "00001110|sz|1|Vm|10100|0|Vn|Vx"                        , "t": "8H.8B 4S.4H 2D.2S"},
+      {"inst": "smlsl2 Vx.ta, Vn.tb, Vm.tb"                              , "op": "01001110|sz|1|Vm|10100|0|Vn|Vx"                        , "t": "8H.16B 4S.8H 2D.4S"},
+      {"inst": "smlsl Vx.4S, Vn.4H, Vm.H[#dx]"                           , "op": "00001111|01|idx[1:0]|Vm:4|0110|idx[2]|0|Vn|Vx"},
+      {"inst": "smlsl2 Vx.4S, Vn.8H, Vm.H[#dx]"                          , "op": "01001111|01|idx[1:0]|Vm:4|0110|idx[2]|0|Vn|Vx"},
+      {"inst": "smlsl Vx.2D, Vn.2S, Vm.S[#dx]"                           , "op": "00001111|10|idx[0]  |Vm  |0110|idx[1]|0|Vn|Vx"},
+      {"inst": "smlsl2 Vx.2D, Vn.4S, Vm.S[#dx]"                          , "op": "01001111|10|idx[0]  |Vm  |0110|idx[1]|0|Vn|Vx"},
       {"inst": "smov Wd, Vn.B[#idx]"                                     , "op": "00001110|00|0|idx:4|  1|00101|1|Vn|Rd"},
       {"inst": "smov Wd, Vn.H[#idx]"                                     , "op": "00001110|00|0|idx:3| 10|00101|1|Vn|Rd"},
       {"inst": "smov Xd, Vn.B[#idx]"                                     , "op": "01001110|00|0|idx:4|  1|00101|1|Vn|Rd"},
@@ -2216,37 +2216,37 @@
       {"inst": "st4 4x{Vs.t}+, [Xn|SP, Xm]@"                             , "op": "01001100|100|Rm   |0000|sz|Rn|Vs"                      , "t": "16B 8H 4S 2D"},
       {"inst": "st4 4x{Vs.t}+, [Xn|SP, #off==32]@"                       , "op": "00001100|100|11111|0000|sz|Rn|Vs"                      , "t": "8B 4H 2S"},
       {"inst": "st4 4x{Vs.t}+, [Xn|SP, #off==64]@"                       , "op": "01001100|100|11111|0000|sz|Rn|Vs"                      , "t": "16B 8H 4S 2D"},
-      {"inst": "stnp Sd, Sd2, [Xn|SP, #soff*4]"                          , "op": "00101100|00|soff:7|Vs2|Vn|Vs"},
-      {"inst": "stnp Dd, Dd2, [Xn|SP, #soff*8]"                          , "op": "01101100|00|soff:7|Vs2|Vn|Vs"},
-      {"inst": "stnp Qd, Qd2, [Xn|SP, #soff*16]"                         , "op": "10101100|00|soff:7|Vs2|Vn|Vs"},
-      {"inst": "stp Sd, Sd2, [Xn|SP, #soff*4]{@}{!}"                     , "op": "0010110|!post|W|0|soff:7|Vs2|Vn|Vs"},
-      {"inst": "stp Dd, Dd2, [Xn|SP, #soff*8]{@}{!}"                     , "op": "0110110|!post|W|0|soff:7|Vs2|Vn|Vs"},
-      {"inst": "stp Qd, Qd2, [Xn|SP, #soff*16]{@}{!}"                    , "op": "1010110|!post|W|0|soff:7|Vs2|Vn|Vs"},
+      {"inst": "stnp Sd, Sd2, [Xn|SP, #offS*4]"                          , "op": "00101100|00|offS:7|Vs2|Vn|Vs"},
+      {"inst": "stnp Dd, Dd2, [Xn|SP, #offS*8]"                          , "op": "01101100|00|offS:7|Vs2|Vn|Vs"},
+      {"inst": "stnp Qd, Qd2, [Xn|SP, #offS*16]"                         , "op": "10101100|00|offS:7|Vs2|Vn|Vs"},
+      {"inst": "stp Sd, Sd2, [Xn|SP, #offS*4]{@}{!}"                     , "op": "0010110|!post|W|0|offS:7|Vs2|Vn|Vs"},
+      {"inst": "stp Dd, Dd2, [Xn|SP, #offS*8]{@}{!}"                     , "op": "0110110|!post|W|0|offS:7|Vs2|Vn|Vs"},
+      {"inst": "stp Qd, Qd2, [Xn|SP, #offS*16]{@}{!}"                    , "op": "1010110|!post|W|0|offS:7|Vs2|Vn|Vs"},
       {"inst": "str Bd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]"            , "op": "00111100|001|Rm|option:3|n:1|10|Rn|Vs"},
       {"inst": "str Hd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]"            , "op": "01111100|001|Rm|option:3|n:1|10|Rn|Vs"},
       {"inst": "str Sd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n*2}]"          , "op": "10111100|001|Rm|option:3|n:1|10|Rn|Vs"},
       {"inst": "str Dd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n*3}]"          , "op": "11111100|001|Rm|option:3|n:1|10|Rn|Vs"},
       {"inst": "str Qd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n*4}]"          , "op": "00111100|101|Rm|option:3|n:1|10|Rn|Vs"},
-      {"inst": "str Bd, [Xn|SP, #zoff]"                                  , "op": "00111101|00|zoff:12|Rn|Vs"},
-      {"inst": "str Hd, [Xn|SP, #zoff*2]"                                , "op": "01111101|00|zoff:12|Rn|Vs"},
-      {"inst": "str Sd, [Xn|SP, #zoff*4]"                                , "op": "10111101|00|zoff:12|Rn|Vs"},
-      {"inst": "str Dd, [Xn|SP, #zoff*8]"                                , "op": "11111101|00|zoff:12|Rn|Vs"},
-      {"inst": "str Qd, [Xn|SP, #zoff*16]"                               , "op": "00111101|10|zoff:12|Rn|Vs"},
-      {"inst": "str Bd, [Xn|SP, #soff]!"                                 , "op": "00111100|000|soff:9|11|Rn|Vs"},
-      {"inst": "str Hd, [Xn|SP, #soff*2]!"                               , "op": "01111100|000|soff:9|11|Rn|Vs"},
-      {"inst": "str Sd, [Xn|SP, #soff*4]!"                               , "op": "10111100|000|soff:9|11|Rn|Vs"},
-      {"inst": "str Dd, [Xn|SP, #soff*8]!"                               , "op": "11111100|000|soff:9|11|Rn|Vs"},
-      {"inst": "str Qd, [Xn|SP, #soff*16]!"                              , "op": "00111100|100|soff:9|11|Rn|Vs"},
-      {"inst": "str Bd, [Xn|SP, #soff]@"                                 , "op": "00111100|000|soff:9|01|Rn|Vs"},
-      {"inst": "str Hd, [Xn|SP, #soff*2]@"                               , "op": "01111100|000|soff:9|01|Rn|Vs"},
-      {"inst": "str Sd, [Xn|SP, #soff*4]@"                               , "op": "10111100|000|soff:9|01|Rn|Vs"},
-      {"inst": "str Dd, [Xn|SP, #soff*8]@"                               , "op": "11111100|000|soff:9|01|Rn|Vs"},
-      {"inst": "str Qd, [Xn|SP, #soff*16]@"                              , "op": "00111100|100|soff:9|01|Rn|Vs"},
-      {"inst": "stur Bd, [Xn|SP, #soff]"                                 , "op": "00111100|000|soff:9|00|Rn|Vs"},
-      {"inst": "stur Hd, [Xn|SP, #soff]"                                 , "op": "01111100|000|soff:9|00|Rn|Vs"},
-      {"inst": "stur Sd, [Xn|SP, #soff]"                                 , "op": "10111100|000|soff:9|00|Rn|Vs"},
-      {"inst": "stur Dd, [Xn|SP, #soff]"                                 , "op": "11111100|000|soff:9|00|Rn|Vs"},
-      {"inst": "stur Qd, [Xn|SP, #soff]"                                 , "op": "00111100|100|soff:9|00|Rn|Vs"},
+      {"inst": "str Bd, [Xn|SP, #offZ]"                                  , "op": "00111101|00|offZ:12|Rn|Vs"},
+      {"inst": "str Hd, [Xn|SP, #offZ*2]"                                , "op": "01111101|00|offZ:12|Rn|Vs"},
+      {"inst": "str Sd, [Xn|SP, #offZ*4]"                                , "op": "10111101|00|offZ:12|Rn|Vs"},
+      {"inst": "str Dd, [Xn|SP, #offZ*8]"                                , "op": "11111101|00|offZ:12|Rn|Vs"},
+      {"inst": "str Qd, [Xn|SP, #offZ*16]"                               , "op": "00111101|10|offZ:12|Rn|Vs"},
+      {"inst": "str Bd, [Xn|SP, #offS]!"                                 , "op": "00111100|000|offS:9|11|Rn|Vs"},
+      {"inst": "str Hd, [Xn|SP, #offS*2]!"                               , "op": "01111100|000|offS:9|11|Rn|Vs"},
+      {"inst": "str Sd, [Xn|SP, #offS*4]!"                               , "op": "10111100|000|offS:9|11|Rn|Vs"},
+      {"inst": "str Dd, [Xn|SP, #offS*8]!"                               , "op": "11111100|000|offS:9|11|Rn|Vs"},
+      {"inst": "str Qd, [Xn|SP, #offS*16]!"                              , "op": "00111100|100|offS:9|11|Rn|Vs"},
+      {"inst": "str Bd, [Xn|SP, #offS]@"                                 , "op": "00111100|000|offS:9|01|Rn|Vs"},
+      {"inst": "str Hd, [Xn|SP, #offS*2]@"                               , "op": "01111100|000|offS:9|01|Rn|Vs"},
+      {"inst": "str Sd, [Xn|SP, #offS*4]@"                               , "op": "10111100|000|offS:9|01|Rn|Vs"},
+      {"inst": "str Dd, [Xn|SP, #offS*8]@"                               , "op": "11111100|000|offS:9|01|Rn|Vs"},
+      {"inst": "str Qd, [Xn|SP, #offS*16]@"                              , "op": "00111100|100|offS:9|01|Rn|Vs"},
+      {"inst": "stur Bd, [Xn|SP, #offS]"                                 , "op": "00111100|000|offS:9|00|Rn|Vs"},
+      {"inst": "stur Hd, [Xn|SP, #offS]"                                 , "op": "01111100|000|offS:9|00|Rn|Vs"},
+      {"inst": "stur Sd, [Xn|SP, #offS]"                                 , "op": "10111100|000|offS:9|00|Rn|Vs"},
+      {"inst": "stur Dd, [Xn|SP, #offS]"                                 , "op": "11111100|000|offS:9|00|Rn|Vs"},
+      {"inst": "stur Qd, [Xn|SP, #offS]"                                 , "op": "00111100|100|offS:9|00|Rn|Vs"},
       {"inst": "sub Dd, Dn, Dm"                                          , "op": "01111110|11|1|Vm|10000|1|Vn|Vd"},
       {"inst": "sub Vd.t, Vn.t, Vm.t"                                    , "op": "00101110|sz|1|Vm|10000|1|Vn|Vd"                        , "t": "8B 4H 2S"},
       {"inst": "sub Vd.t, Vn.t, Vm.t"                                    , "op": "01101110|sz|1|Vm|10000|1|Vn|Vd"                        , "t": "16B 8H 4S 2D"},
@@ -2810,17 +2810,17 @@
 
     {"category": "ASIMD", "ext": "ASIMD LRCPC3", "data": [
       {"inst": "ldap1 Vd.D[#idx], [Xn|SP]"                               , "op": "0|idx:1|001101|010|00001|10000|1|Rn|Vd"},
-      {"inst": "ldapur Bd, [Xn|SP, #soff]"                               , "op": "00011101|010|soff:9|10|Rn|Vd"},
-      {"inst": "ldapur Hd, [Xn|SP, #soff]"                               , "op": "01011101|010|soff:9|10|Rn|Vd"},
-      {"inst": "ldapur Sd, [Xn|SP, #soff]"                               , "op": "10011101|010|soff:9|10|Rn|Vd"},
-      {"inst": "ldapur Dd, [Xn|SP, #soff]"                               , "op": "11011101|010|soff:9|10|Rn|Vd"},
-      {"inst": "ldapur Qd, [Xn|SP, #soff]"                               , "op": "00011101|110|soff:9|10|Rn|Vd"},
+      {"inst": "ldapur Bd, [Xn|SP, #offS]"                               , "op": "00011101|010|offS:9|10|Rn|Vd"},
+      {"inst": "ldapur Hd, [Xn|SP, #offS]"                               , "op": "01011101|010|offS:9|10|Rn|Vd"},
+      {"inst": "ldapur Sd, [Xn|SP, #offS]"                               , "op": "10011101|010|offS:9|10|Rn|Vd"},
+      {"inst": "ldapur Dd, [Xn|SP, #offS]"                               , "op": "11011101|010|offS:9|10|Rn|Vd"},
+      {"inst": "ldapur Qd, [Xn|SP, #offS]"                               , "op": "00011101|110|offS:9|10|Rn|Vd"},
       {"inst": "stl1 Vs.D[#idx], [Xn|SP]"                                , "op": "0|idx:1|001101|000|00001|10000|1|Rn|Vs"},
-      {"inst": "stlur Bs, [Xn|SP, #soff]"                                , "op": "00011101|000|soff:9|10|Rn|Vs"},
-      {"inst": "stlur Hs, [Xn|SP, #soff]"                                , "op": "01011101|000|soff:9|10|Rn|Vs"},
-      {"inst": "stlur Ss, [Xn|SP, #soff]"                                , "op": "10011101|000|soff:9|10|Rn|Vs"},
-      {"inst": "stlur Ds, [Xn|SP, #soff]"                                , "op": "11011101|000|soff:9|10|Rn|Vs"},
-      {"inst": "stlur Qs, [Xn|SP, #soff]"                                , "op": "00011101|100|soff:9|10|Rn|Vs"}
+      {"inst": "stlur Bs, [Xn|SP, #offS]"                                , "op": "00011101|000|offS:9|10|Rn|Vs"},
+      {"inst": "stlur Hs, [Xn|SP, #offS]"                                , "op": "01011101|000|offS:9|10|Rn|Vs"},
+      {"inst": "stlur Ss, [Xn|SP, #offS]"                                , "op": "10011101|000|offS:9|10|Rn|Vs"},
+      {"inst": "stlur Ds, [Xn|SP, #offS]"                                , "op": "11011101|000|offS:9|10|Rn|Vs"},
+      {"inst": "stlur Qs, [Xn|SP, #offS]"                                , "op": "00011101|100|offS:9|10|Rn|Vs"}
     ]},
 
     {"category": "ASIMD", "ext": "RDM", "data": [

deps/asmjit/db/isa_x86.json

@@ -341,13 +341,13 @@
       {"inst": "or x:ax, iw/uw"                                             , "op": "66 0D iw"                       , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0", "altForm": true},
       {"inst": "or X:eax, id/ud"                                            , "op": "0D id"                          , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0", "altForm": true},
       {"inst": "or X:rax, id"                                               , "op": "REX.W 0D id"                    , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0", "altForm": true},
-      {"inst": "[lock|xacqrel] or x:r8/m8, ib/ub"                           , "op": "M: 80 /1 ib"                   , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
-      {"inst": "[lock|xacqrel] or x:r16/m16, iw/uw"                         , "op": "M: 66 81 /1 iw"                , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
-      {"inst": "[lock|xacqrel] or X:r32/m32, id/ud"                         , "op": "M: 81 /1 id"                   , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
-      {"inst": "[lock|xacqrel] or X:r64/m64, id"                            , "op": "M: REX.W 81 /1 id"             , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
-      {"inst": "[lock|xacqrel] or x:r16/m16, ib"                            , "op": "M: 66 83 /1 ib"                , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
-      {"inst": "[lock|xacqrel] or X:r32/m32, ib"                            , "op": "M: 83 /1 ib"                   , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
-      {"inst": "[lock|xacqrel] or X:r64/m64, ib"                            , "op": "M: REX.W 83 /1 ib"             , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+      {"inst": "[lock|xacqrel] or x:r8/m8, ib/ub"                           , "op": "M: 80 /1 ib"                    , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+      {"inst": "[lock|xacqrel] or x:r16/m16, iw/uw"                         , "op": "M: 66 81 /1 iw"                 , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+      {"inst": "[lock|xacqrel] or X:r32/m32, id/ud"                         , "op": "M: 81 /1 id"                    , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+      {"inst": "[lock|xacqrel] or X:r64/m64, id"                            , "op": "M: REX.W 81 /1 id"              , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+      {"inst": "[lock|xacqrel] or x:r16/m16, ib"                            , "op": "M: 66 83 /1 ib"                 , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+      {"inst": "[lock|xacqrel] or X:r32/m32, ib"                            , "op": "M: 83 /1 ib"                    , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+      {"inst": "[lock|xacqrel] or X:r64/m64, ib"                            , "op": "M: REX.W 83 /1 ib"              , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
       {"inst": "[lock|xacqrel] or x:~r8/m8, ~r8"                            , "op": "MR: 08 /r"                      , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
       {"inst": "[lock|xacqrel] or x:~r16/m16, ~r16"                         , "op": "MR: 66 09 /r"                   , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
       {"inst": "[lock|xacqrel] or X:~r32/m32, ~r32"                         , "op": "MR: 09 /r"                      , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
@@ -624,200 +624,405 @@
       {"inst": "[rep] outs R:dx, R:m32(ds:zsi)"                             , "op": "6F"}
     ]},
 
-    {"category": "GP GP_EXT", "data": [
-      {"inst": "aadd X:m32, r32"                                            , "op": "MR: 0F 38 FC /r"                , "ext": "RAO_INT"},
-      {"inst": "aadd X:m64, r64"                                            , "op": "MR: REX.W 0F 38 FC /r"          , "ext": "RAO_INT"},
-      {"inst": "aand X:m32, r32"                                            , "op": "MR: 66 0F 38 FC /r"             , "ext": "RAO_INT"},
-      {"inst": "aand X:m64, r64"                                            , "op": "MR: REX.W 66 0F 38 FC /r"       , "ext": "RAO_INT"},
-      {"inst": "adcx X:~r32, ~r32/m32"                                      , "op": "RM: 66 0F 38 F6 /r"             , "ext": "ADX"        , "io": "CF=X"},
-      {"inst": "adcx X:~r64, ~r64/m64"                                      , "op": "RM: REX.W 66 0F 38 F6 /r"       , "ext": "ADX"        , "io": "CF=X"},
-      {"inst": "adox X:~r32, ~r32/m32"                                      , "op": "RM: F3 0F 38 F6 /r"             , "ext": "ADX"        , "io": "OF=X"},
-      {"inst": "adox X:~r64, ~r64/m64"                                      , "op": "RM: REX.W F3 0F 38 F6 /r"       , "ext": "ADX"        , "io": "OF=X"},
-      {"inst": "andn W:r32, r32, r32/m32"                                   , "op": "RVM: VEX.LZ.0F38.W0 F2 /r"      , "ext": "BMI"        , "io": "OF=0 SF=W ZF=W AF=U PF=U CF=0"},
-      {"inst": "andn W:r64, r64, r64/m64"                                   , "op": "RVM: VEX.LZ.0F38.W1 F2 /r"      , "ext": "BMI"        , "io": "OF=0 SF=W ZF=W AF=U PF=U CF=0"},
-      {"inst": "aor X:m32, r32"                                             , "op": "MR: F2 0F 38 FC /r"             , "ext": "RAO_INT"},
-      {"inst": "aor X:m64, r64"                                             , "op": "MR: REX.W F2 0F 38 FC /r"       , "ext": "RAO_INT"},
-      {"inst": "axor X:m32, r32"                                            , "op": "MR: F3 0F 38 FC /r"             , "ext": "RAO_INT"},
-      {"inst": "axor X:m64, r64"                                            , "op": "MR: REX.W F3 0F 38 FC /r"       , "ext": "RAO_INT"},
-      {"inst": "bextr W:r32, r32/m32, r32"                                  , "op": "RMV: VEX.LZ.0F38.W0 F7 /r"      , "ext": "BMI"        , "io": "OF=0 SF=U ZF=W AF=U PF=U CF=0"},
-      {"inst": "bextr W:r64, r64/m64, r64"                                  , "op": "RMV: VEX.LZ.0F38.W1 F7 /r"      , "ext": "BMI"        , "io": "OF=0 SF=U ZF=W AF=U PF=U CF=0"},
-      {"inst": "blsi W:r32, r32/m32"                                        , "op": "VM: VEX.LZ.0F38.W0 F3 /3"       , "ext": "BMI"        , "io": "OF=0 SF=W ZF=W AF=U PF=U CF=W"},
-      {"inst": "blsi W:r64, r64/m64"                                        , "op": "VM: VEX.LZ.0F38.W1 F3 /3"       , "ext": "BMI"        , "io": "OF=0 SF=W ZF=W AF=U PF=U CF=W"},
-      {"inst": "blsmsk W:r32, r32/m32"                                      , "op": "VM: VEX.LZ.0F38.W0 F3 /2"       , "ext": "BMI"        , "io": "OF=0 SF=W ZF=0 AF=U PF=U CF=W"},
-      {"inst": "blsmsk W:r64, r64/m64"                                      , "op": "VM: VEX.LZ.0F38.W1 F3 /2"       , "ext": "BMI"        , "io": "OF=0 SF=W ZF=0 AF=U PF=U CF=W"},
-      {"inst": "blsr W:r32, r32/m32"                                        , "op": "VM: VEX.LZ.0F38.W0 F3 /1"       , "ext": "BMI"        , "io": "OF=0 SF=W ZF=W AF=U PF=U CF=W"},
-      {"inst": "blsr W:r64, r64/m64"                                        , "op": "VM: VEX.LZ.0F38.W1 F3 /1"       , "ext": "BMI"        , "io": "OF=0 SF=W ZF=W AF=U PF=U CF=W"},
-      {"inst": "bzhi W:r32, r32/m32, r32"                                   , "op": "RMV: VEX.LZ.0F38.W0 F5 /r"      , "ext": "BMI2"       , "io": "OF=0 SF=W ZF=W AF=U PF=U CF=W"},
-      {"inst": "bzhi W:r64, r64/m64, r64"                                   , "op": "RMV: VEX.LZ.0F38.W1 F5 /r"      , "ext": "BMI2"       , "io": "OF=0 SF=W ZF=W AF=U PF=U CF=W"},
-      {"inst": "cldemote R:mem"                                             , "op": "0F 1C /0"                       , "ext": "CLDEMOTE"},
-      {"inst": "clflush R:mem"                                              , "op": "0F AE /7"                       , "ext": "CLFLUSH"},
-      {"inst": "clflushopt R:mem"                                           , "op": "66 0F AE /7"                    , "ext": "CLFLUSHOPT"},
-      {"inst": "clwb R:mem"                                                 , "op": "66 0F AE /6"                    , "ext": "CLWB"},
-      {"inst": "clzero R:<m512(ds:zax)>"                                    , "op": "0F 01 FC"                       , "ext": "CLZERO"},
-      {"inst": "cmovo x:r16, r16/m16"                                       , "op": "RM: 66 0F 40 /r"                , "ext": "CMOV"       , "io": "OF=R"},
-      {"inst": "cmovo X:r32, r32/m32"                                       , "op": "RM: 0F 40 /r"                   , "ext": "CMOV"       , "io": "OF=R"},
-      {"inst": "cmovo X:r64, r64/m64"                                       , "op": "RM: REX.W 0F 40 /r"             , "ext": "CMOV"       , "io": "OF=R"},
-      {"inst": "cmovno x:r16, r16/m16"                                      , "op": "RM: 66 0F 41 /r"                , "ext": "CMOV"       , "io": "OF=R"},
-      {"inst": "cmovno X:r32, r32/m32"                                      , "op": "RM: 0F 41 /r"                   , "ext": "CMOV"       , "io": "OF=R"},
-      {"inst": "cmovno X:r64, r64/m64"                                      , "op": "RM: REX.W 0F 41 /r"             , "ext": "CMOV"       , "io": "OF=R"},
-      {"inst": "cmovb|cmovnae|cmovc x:r16, r16/m16"                         , "op": "RM: 66 0F 42 /r"                , "ext": "CMOV"       , "io": "CF=R"},
-      {"inst": "cmovb|cmovnae|cmovc X:r32, r32/m32"                         , "op": "RM: 0F 42 /r"                   , "ext": "CMOV"       , "io": "CF=R"},
-      {"inst": "cmovb|cmovnae|cmovc X:r64, r64/m64"                         , "op": "RM: REX.W 0F 42 /r"             , "ext": "CMOV"       , "io": "CF=R"},
-      {"inst": "cmovae|cmovnb|cmovnc x:r16, r16/m16"                        , "op": "RM: 66 0F 43 /r"                , "ext": "CMOV"       , "io": "CF=R"},
-      {"inst": "cmovae|cmovnb|cmovnc X:r32, r32/m32"                        , "op": "RM: 0F 43 /r"                   , "ext": "CMOV"       , "io": "CF=R"},
-      {"inst": "cmovae|cmovnb|cmovnc X:r64, r64/m64"                        , "op": "RM: REX.W 0F 43 /r"             , "ext": "CMOV"       , "io": "CF=R"},
-      {"inst": "cmove|cmovz x:r16, r16/m16"                                 , "op": "RM: 66 0F 44 /r"                , "ext": "CMOV"       , "io": "ZF=R"},
-      {"inst": "cmove|cmovz X:r32, r32/m32"                                 , "op": "RM: 0F 44 /r"                   , "ext": "CMOV"       , "io": "ZF=R"},
-      {"inst": "cmove|cmovz X:r64, r64/m64"                                 , "op": "RM: REX.W 0F 44 /r"             , "ext": "CMOV"       , "io": "ZF=R"},
-      {"inst": "cmovne|cmovnz x:r16, r16/m16"                               , "op": "RM: 66 0F 45 /r"                , "ext": "CMOV"       , "io": "ZF=R"},
-      {"inst": "cmovne|cmovnz X:r32, r32/m32"                               , "op": "RM: 0F 45 /r"                   , "ext": "CMOV"       , "io": "ZF=R"},
-      {"inst": "cmovne|cmovnz X:r64, r64/m64"                               , "op": "RM: REX.W 0F 45 /r"             , "ext": "CMOV"       , "io": "ZF=R"},
-      {"inst": "cmovbe|cmovna x:r16, r16/m16"                               , "op": "RM: 66 0F 46 /r"                , "ext": "CMOV"       , "io": "CF=R ZF=R"},
-      {"inst": "cmovbe|cmovna X:r32, r32/m32"                               , "op": "RM: 0F 46 /r"                   , "ext": "CMOV"       , "io": "CF=R ZF=R"},
-      {"inst": "cmovbe|cmovna X:r64, r64/m64"                               , "op": "RM: REX.W 0F 46 /r"             , "ext": "CMOV"       , "io": "CF=R ZF=R"},
-      {"inst": "cmova|cmovnbe x:r16, r16/m16"                               , "op": "RM: 66 0F 47 /r"                , "ext": "CMOV"       , "io": "CF=R ZF=R"},
-      {"inst": "cmova|cmovnbe X:r32, r32/m32"                               , "op": "RM: 0F 47 /r"                   , "ext": "CMOV"       , "io": "CF=R ZF=R"},
-      {"inst": "cmova|cmovnbe X:r64, r64/m64"                               , "op": "RM: REX.W 0F 47 /r"             , "ext": "CMOV"       , "io": "CF=R ZF=R"},
-      {"inst": "cmovs x:r16, r16/m16"                                       , "op": "RM: 66 0F 48 /r"                , "ext": "CMOV"       , "io": "SF=R"},
-      {"inst": "cmovs X:r32, r32/m32"                                       , "op": "RM: 0F 48 /r"                   , "ext": "CMOV"       , "io": "SF=R"},
-      {"inst": "cmovs X:r64, r64/m64"                                       , "op": "RM: REX.W 0F 48 /r"             , "ext": "CMOV"       , "io": "SF=R"},
-      {"inst": "cmovns x:r16, r16/m16"                                      , "op": "RM: 66 0F 49 /r"                , "ext": "CMOV"       , "io": "SF=R"},
-      {"inst": "cmovns X:r32, r32/m32"                                      , "op": "RM: 0F 49 /r"                   , "ext": "CMOV"       , "io": "SF=R"},
-      {"inst": "cmovns X:r64, r64/m64"                                      , "op": "RM: REX.W 0F 49 /r"             , "ext": "CMOV"       , "io": "SF=R"},
-      {"inst": "cmovp|cmovpe x:r16, r16/m16"                                , "op": "RM: 66 0F 4A /r"                , "ext": "CMOV"       , "io": "PF=R"},
-      {"inst": "cmovp|cmovpe X:r32, r32/m32"                                , "op": "RM: 0F 4A /r"                   , "ext": "CMOV"       , "io": "PF=R"},
-      {"inst": "cmovp|cmovpe X:r64, r64/m64"                                , "op": "RM: REX.W 0F 4A /r"             , "ext": "CMOV"       , "io": "PF=R"},
-      {"inst": "cmovnp|cmovpo x:r16, r16/m16"                               , "op": "RM: 66 0F 4B /r"                , "ext": "CMOV"       , "io": "PF=R"},
-      {"inst": "cmovnp|cmovpo X:r32, r32/m32"                               , "op": "RM: 0F 4B /r"                   , "ext": "CMOV"       , "io": "PF=R"},
-      {"inst": "cmovnp|cmovpo X:r64, r64/m64"                               , "op": "RM: REX.W 0F 4B /r"             , "ext": "CMOV"       , "io": "PF=R"},
-      {"inst": "cmovl|cmovnge x:r16, r16/m16"                               , "op": "RM: 66 0F 4C /r"                , "ext": "CMOV"       , "io": "SF=R OF=R"},
-      {"inst": "cmovl|cmovnge X:r32, r32/m32"                               , "op": "RM: 0F 4C /r"                   , "ext": "CMOV"       , "io": "SF=R OF=R"},
-      {"inst": "cmovl|cmovnge X:r64, r64/m64"                               , "op": "RM: REX.W 0F 4C /r"             , "ext": "CMOV"       , "io": "SF=R OF=R"},
-      {"inst": "cmovge|cmovnl x:r16, r16/m16"                               , "op": "RM: 66 0F 4D /r"                , "ext": "CMOV"       , "io": "SF=R OF=R"},
-      {"inst": "cmovge|cmovnl X:r32, r32/m32"                               , "op": "RM: 0F 4D /r"                   , "ext": "CMOV"       , "io": "SF=R OF=R"},
-      {"inst": "cmovge|cmovnl X:r64, r64/m64"                               , "op": "RM: REX.W 0F 4D /r"             , "ext": "CMOV"       , "io": "SF=R OF=R"},
-      {"inst": "cmovle|cmovng x:r16, r16/m16"                               , "op": "RM: 66 0F 4E /r"                , "ext": "CMOV"       , "io": "ZF=R SF=R OF=R"},
-      {"inst": "cmovle|cmovng X:r32, r32/m32"                               , "op": "RM: 0F 4E /r"                   , "ext": "CMOV"       , "io": "ZF=R SF=R OF=R"},
-      {"inst": "cmovle|cmovng X:r64, r64/m64"                               , "op": "RM: REX.W 0F 4E /r"             , "ext": "CMOV"       , "io": "ZF=R SF=R OF=R"},
-      {"inst": "cmovg|cmovnle x:r16, r16/m16"                               , "op": "RM: 66 0F 4F /r"                , "ext": "CMOV"       , "io": "ZF=R SF=R OF=R"},
-      {"inst": "cmovg|cmovnle X:r32, r32/m32"                               , "op": "RM: 0F 4F /r"                   , "ext": "CMOV"       , "io": "ZF=R SF=R OF=R"},
-      {"inst": "cmovg|cmovnle X:r64, r64/m64"                               , "op": "RM: REX.W 0F 4F /r"             , "ext": "CMOV"       , "io": "ZF=R SF=R OF=R"},
-      {"inst": "cmpbexadd X:m32, X:r32, R:r32"                              , "op": "MVR: VEX.128.66.0F38.W0 E6 /r"  , "ext": "CMPCCXADD"  , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
-      {"inst": "cmpbexadd X:m64, X:r64, R:r64"                              , "op": "MVR: VEX.128.66.0F38.W1 E6 /r"  , "ext": "CMPCCXADD"  , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
-      {"inst": "cmpbxadd X:m32, X:r32, R:r32"                               , "op": "MVR: VEX.128.66.0F38.W0 E2 /r"  , "ext": "CMPCCXADD"  , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
-      {"inst": "cmpbxadd X:m64, X:r64, R:r64"                               , "op": "MVR: VEX.128.66.0F38.W1 E2 /r"  , "ext": "CMPCCXADD"  , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
-      {"inst": "cmplexadd X:m32, X:r32, R:r32"                              , "op": "MVR: VEX.128.66.0F38.W0 EE /r"  , "ext": "CMPCCXADD"  , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
-      {"inst": "cmplexadd X:m64, X:r64, R:r64"                              , "op": "MVR: VEX.128.66.0F38.W1 EE /r"  , "ext": "CMPCCXADD"  , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
-      {"inst": "cmplxadd X:m32, X:r32, R:r32"                               , "op": "MVR: VEX.128.66.0F38.W0 EC /r"  , "ext": "CMPCCXADD"  , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
-      {"inst": "cmplxadd X:m64, X:r64, R:r64"                               , "op": "MVR: VEX.128.66.0F38.W1 EC /r"  , "ext": "CMPCCXADD"  , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
-      {"inst": "cmpnbexadd X:m32, X:r32, R:r32"                             , "op": "MVR: VEX.128.66.0F38.W0 E7 /r"  , "ext": "CMPCCXADD"  , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
-      {"inst": "cmpnbexadd X:m64, X:r64, R:r64"                             , "op": "MVR: VEX.128.66.0F38.W1 E7 /r"  , "ext": "CMPCCXADD"  , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
-      {"inst": "cmpnbxadd X:m32, X:r32, R:r32"                              , "op": "MVR: VEX.128.66.0F38.W0 E3 /r"  , "ext": "CMPCCXADD"  , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
-      {"inst": "cmpnbxadd X:m64, X:r64, R:r64"                              , "op": "MVR: VEX.128.66.0F38.W1 E3 /r"  , "ext": "CMPCCXADD"  , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
-      {"inst": "cmpnlexadd X:m32, X:r32, R:r32"                             , "op": "MVR: VEX.128.66.0F38.W0 EF /r"  , "ext": "CMPCCXADD"  , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
-      {"inst": "cmpnlexadd X:m64, X:r64, R:r64"                             , "op": "MVR: VEX.128.66.0F38.W1 EF /r"  , "ext": "CMPCCXADD"  , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
-      {"inst": "cmpnlxadd X:m32, X:r32, R:r32"                              , "op": "MVR: VEX.128.66.0F38.W0 ED /r"  , "ext": "CMPCCXADD"  , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
-      {"inst": "cmpnlxadd X:m64, X:r64, R:r64"                              , "op": "MVR: VEX.128.66.0F38.W1 ED /r"  , "ext": "CMPCCXADD"  , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
-      {"inst": "cmpnoxadd X:m32, X:r32, R:r32"                              , "op": "MVR: VEX.128.66.0F38.W0 E1 /r"  , "ext": "CMPCCXADD"  , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
-      {"inst": "cmpnoxadd X:m64, X:r64, R:r64"                              , "op": "MVR: VEX.128.66.0F38.W1 E1 /r"  , "ext": "CMPCCXADD"  , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
-      {"inst": "cmpnpxadd X:m32, X:r32, R:r32"                              , "op": "MVR: VEX.128.66.0F38.W0 EB /r"  , "ext": "CMPCCXADD"  , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
-      {"inst": "cmpnpxadd X:m64, X:r64, R:r64"                              , "op": "MVR: VEX.128.66.0F38.W1 EB /r"  , "ext": "CMPCCXADD"  , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
-      {"inst": "cmpnsxadd X:m32, X:r32, R:r32"                              , "op": "MVR: VEX.128.66.0F38.W0 E9 /r"  , "ext": "CMPCCXADD"  , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
-      {"inst": "cmpnsxadd X:m64, X:r64, R:r64"                              , "op": "MVR: VEX.128.66.0F38.W1 E9 /r"  , "ext": "CMPCCXADD"  , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
-      {"inst": "cmpnzxadd X:m32, X:r32, R:r32"                              , "op": "MVR: VEX.128.66.0F38.W0 E5 /r"  , "ext": "CMPCCXADD"  , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
-      {"inst": "cmpnzxadd X:m64, X:r64, R:r64"                              , "op": "MVR: VEX.128.66.0F38.W1 E5 /r"  , "ext": "CMPCCXADD"  , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
-      {"inst": "cmpoxadd X:m32, X:r32, R:r32"                               , "op": "MVR: VEX.128.66.0F38.W0 E0 /r"  , "ext": "CMPCCXADD"  , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
-      {"inst": "cmpoxadd X:m64, X:r64, R:r64"                               , "op": "MVR: VEX.128.66.0F38.W1 E0 /r"  , "ext": "CMPCCXADD"  , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
-      {"inst": "cmppxadd X:m32, X:r32, R:r32"                               , "op": "MVR: VEX.128.66.0F38.W0 EA /r"  , "ext": "CMPCCXADD"  , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
-      {"inst": "cmppxadd X:m64, X:r64, R:r64"                               , "op": "MVR: VEX.128.66.0F38.W1 EA /r"  , "ext": "CMPCCXADD"  , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
-      {"inst": "cmpsxadd X:m32, X:r32, R:r32"                               , "op": "MVR: VEX.128.66.0F38.W0 E8 /r"  , "ext": "CMPCCXADD"  , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
-      {"inst": "cmpsxadd X:m64, X:r64, R:r64"                               , "op": "MVR: VEX.128.66.0F38.W1 E8 /r"  , "ext": "CMPCCXADD"  , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
-      {"inst": "[lock|xacqrel] cmpxchg x:r8/m8, r8, <al>"                   , "op": "MR: 0F B0 /r"                   , "ext": "I486"       , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
-      {"inst": "[lock|xacqrel] cmpxchg x:r16/m16, r16, <ax>"                , "op": "MR: 66 0F B1 /r"                , "ext": "I486"       , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
-      {"inst": "[lock|xacqrel] cmpxchg X:r32/m32, r32, <eax>"               , "op": "MR: 0F B1 /r"                   , "ext": "I486"       , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
-      {"inst": "[lock|xacqrel] cmpxchg X:r64/m64, r64, <rax>"               , "op": "MR: REX.W 0F B1 /r"             , "ext": "I486"       , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
-      {"inst": "[lock|xacqrel] cmpxchg8b X:m64,X:<edx>,X:<eax>,<ecx>,<ebx>" , "op": "0F C7 /1"                       , "ext": "CMPXCHG8B"  , "io": "ZF=W"},
-      {"inst": "[lock|xacqrel] cmpxchg16b X:m128,X:<rdx>,X:<rax>,<rcx>,<rbx>","op": "REX.W 0F C7 /1"                 , "ext": "CMPXCHG16B" , "io": "ZF=W"},
-      {"inst": "cmpzxadd X:m32, X:r32, R:r32"                               , "op": "VEX.128.66.0F38.W0 E4 /r"       , "ext": "CMPCCXADD"  , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
-      {"inst": "cmpzxadd X:m64, X:r64, R:r64"                               , "op": "VEX.128.66.0F38.W1 E4 /r"       , "ext": "CMPCCXADD"  , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
-      {"inst": "cpuid X:<eax>, W:<ebx>, X:<ecx>, W:<edx>"                   , "op": "0F A2"                          , "ext": "I486"       , "volatile": true},
-      {"inst": "lahf w:<ah>"                                                , "op": "9F"                             , "ext": "LAHFSAHF"   , "io": "SF=R ZF=R AF=R PF=R CF=R"},
-      {"inst": "lfence"                                                     , "op": "0F AE E8"                       , "ext": "SSE2"},
-      {"inst": "lzcnt w:r16, r16/m16"                                       , "op": "RM: 66 F3 0F BD /r"             , "ext": "LZCNT"      , "io": "OF=U SF=U ZF=W AF=U PF=U CF=W"},
-      {"inst": "lzcnt W:r32, r32/m32"                                       , "op": "RM: F3 0F BD /r"                , "ext": "LZCNT"      , "io": "OF=U SF=U ZF=W AF=U PF=U CF=W"},
-      {"inst": "lzcnt W:r64, r64/m64"                                       , "op": "RM: REX.W F3 0F BD /r"          , "ext": "LZCNT"      , "io": "OF=U SF=U ZF=W AF=U PF=U CF=W"},
-      {"inst": "mcommit"                                                    , "op": "F3 0F 01 FA"                    , "ext": "MCOMMIT"    , "io": "OF=0 SF=0 ZF=0 AF=0 PF=0 CF=W"},
-      {"inst": "mfence"                                                     , "op": "0F AE F0"                       , "ext": "SSE2"},
-      {"inst": "movbe w:r16, m16"                                           , "op": "RM: 66 0F 38 F0 /r"             , "ext": "MOVBE"},
-      {"inst": "movbe W:r32, m32"                                           , "op": "RM: 0F 38 F0 /r"                , "ext": "MOVBE"},
-      {"inst": "movbe W:r64, m64"                                           , "op": "RM: REX.W 0F 38 F0 /r"          , "ext": "MOVBE"},
-      {"inst": "movbe W:m16, r16"                                           , "op": "MR: 66 0F 38 F1 /r"             , "ext": "MOVBE"},
-      {"inst": "movbe W:m32, r32"                                           , "op": "MR: 0F 38 F1 /r"                , "ext": "MOVBE"},
-      {"inst": "movbe W:m64, r64"                                           , "op": "MR: REX.W 0F 38 F1 /r"          , "ext": "MOVBE"},
-      {"inst": "movdiri W:m32, r32"                                         , "op": "MR: 0F 38 F9 /r"                , "ext": "MOVDIRI"},
-      {"inst": "movdiri W:m64, r64"                                         , "op": "MR: REX.W 0F 38 F9 /r"          , "ext": "MOVDIRI"},
-      {"inst": "movdir64b W:m512(es:r32), m512"                             , "op": "RM: 66 0F 38 F8 /r"             , "ext": "MOVDIR64B"},
-      {"inst": "movdir64b W:m512(es:r64), m512"                             , "op": "RM: 66 0F 38 F8 /r"             , "ext": "MOVDIR64B"},
-      {"inst": "movnti W:m32, r32"                                          , "op": "MR: 0F C3 /r"                   , "ext": "SSE2"},
-      {"inst": "movnti W:m64, r64"                                          , "op": "MR: REX.W 0F C3 /r"             , "ext": "SSE2"},
-      {"inst": "mulx W:r32, W:r32, ~r32/m32, ~<edx>"                        , "op": "RVM: VEX.LZ.F2.0F38.W0 F6 /r"   , "ext": "BMI2"},
-      {"inst": "mulx W:r64, W:r64, ~r64/m64, ~<rdx>"                        , "op": "RVM: VEX.LZ.F2.0F38.W1 F6 /r"   , "ext": "BMI2"},
-      {"inst": "pdep W:r32, r32, r32/m32"                                   , "op": "RVM: VEX.LZ.F2.0F38.W0 F5 /r"   , "ext": "BMI2"},
-      {"inst": "pdep W:r64, r64, r64/m64"                                   , "op": "RVM: VEX.LZ.F2.0F38.W1 F5 /r"   , "ext": "BMI2"},
-      {"inst": "pext W:r32, r32, r32/m32"                                   , "op": "RVM: VEX.LZ.F3.0F38.W0 F5 /r"   , "ext": "BMI2"},
-      {"inst": "pext W:r64, r64, r64/m64"                                   , "op": "RVM: VEX.LZ.F3.0F38.W1 F5 /r"   , "ext": "BMI2"},
-      {"inst": "popcnt w:r16, r16/m16"                                      , "op": "RM: 66 F3 0F B8 /r"             , "ext": "POPCNT"     , "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=0"},
-      {"inst": "popcnt W:r32, r32/m32"                                      , "op": "RM: F3 0F B8 /r"                , "ext": "POPCNT"     , "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=0"},
-      {"inst": "popcnt W:r64, r64/m64"                                      , "op": "RM: REX.W F3 0F B8 /r"          , "ext": "POPCNT"     , "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=0"},
-      {"inst": "prefetch R:mem"                                             , "op": "0F 0D /0"                       , "ext": "3DNOW"},
-      {"inst": "prefetchit0 R:mem"                                          , "op": "0F 18 /7"                       , "ext": "PREFETCHI"  , "arch": "X64"},
-      {"inst": "prefetchit1 R:mem"                                          , "op": "0F 18 /6"                       , "ext": "PREFETCHI"  , "arch": "X64"},
-      {"inst": "prefetchnta R:mem"                                          , "op": "0F 18 /0"                       , "ext": "SSE"},
-      {"inst": "prefetcht0 R:mem"                                           , "op": "0F 18 /1"                       , "ext": "SSE"},
-      {"inst": "prefetcht1 R:mem"                                           , "op": "0F 18 /2"                       , "ext": "SSE"},
-      {"inst": "prefetcht2 R:mem"                                           , "op": "0F 18 /3"                       , "ext": "SSE"},
-      {"inst": "prefetchw R:mem"                                            , "op": "0F 0D /1"                       , "ext": "PREFETCHW"  , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"},
-      {"inst": "prefetchwt1 R:mem"                                          , "op": "0F 0D /2"                       , "ext": "PREFETCHWT1", "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"},
-      {"inst": "ptwrite R:r32/m32"                                          , "op": "F3 0F AE /4"                    , "ext": "PTWRITE"},
-      {"inst": "ptwrite R:r64/m64"                                          , "op": "REX.W F3 0F AE /4"              , "ext": "PTWRITE"},
-      {"inst": "rdpid W:r32"                                                , "op": "R: F3 0F C7 /7"                 , "ext": "RDPID"      , "arch": "X86"},
-      {"inst": "rdpid W:r64"                                                , "op": "R: F3 0F C7 /7"                 , "ext": "RDPID"      , "arch": "X64"},
-      {"inst": "rdpkru W:<edx>, W:<eax>, R:<ecx>"                           , "op": "0F 01 EE"                       , "ext": "OSPKE"},
-      {"inst": "rdpru W:<edx>, W:<eax>, R:<ecx>"                            , "op": "0F 01 FD"                       , "ext": "RDPRU"},
-      {"inst": "rdrand w:r16"                                               , "op": "66 0F C7 /6"                    , "ext": "RDRAND"     , "io": "OF=0 SF=0 ZF=0 AF=0 PF=0 CF=W"},
-      {"inst": "rdrand W:r32"                                               , "op": "0F C7 /6"                       , "ext": "RDRAND"     , "io": "OF=0 SF=0 ZF=0 AF=0 PF=0 CF=W"},
-      {"inst": "rdrand W:r64"                                               , "op": "REX.W 0F C7 /6"                 , "ext": "RDRAND"     , "io": "OF=0 SF=0 ZF=0 AF=0 PF=0 CF=W"},
-      {"inst": "rdseed w:r16"                                               , "op": "66 0F C7 /7"                    , "ext": "RDSEED"     , "io": "OF=0 SF=0 ZF=0 AF=0 PF=0 CF=W"},
-      {"inst": "rdseed W:r32"                                               , "op": "0F C7 /7"                       , "ext": "RDSEED"     , "io": "OF=0 SF=0 ZF=0 AF=0 PF=0 CF=W"},
-      {"inst": "rdseed W:r64"                                               , "op": "REX.W 0F C7 /7"                 , "ext": "RDSEED"     , "io": "OF=0 SF=0 ZF=0 AF=0 PF=0 CF=W"},
-      {"inst": "rdtsc W:<edx>, W:<eax>"                                     , "op": "0F 31"                          , "ext": "RDTSC"},
-      {"inst": "rdtscp W:<edx>, W:<eax>, W:<ecx>"                           , "op": "0F 01 F9"                       , "ext": "RDTSCP"},
-      {"inst": "rorx W:r32, r32/m32, ib/ub"                                 , "op": "RM: VEX.LZ.F2.0F3A.W0 F0 /r ib" , "ext": "BMI2"},
-      {"inst": "rorx W:r64, r64/m64, ib/ub"                                 , "op": "RM: VEX.LZ.F2.0F3A.W1 F0 /r ib" , "ext": "BMI2"},
-      {"inst": "sahf R:<ah>"                                                , "op": "9E"                             , "ext": "LAHFSAHF"   , "io": "SF=W ZF=W AF=W PF=W CF=W"},
-      {"inst": "sarx W:r32, r32/m32, r32"                                   , "op": "RMV: VEX.LZ.F3.0F38.W0 F7 /r"   , "ext": "BMI2"},
-      {"inst": "sarx W:r64, r64/m64, r64"                                   , "op": "RMV: VEX.LZ.F3.0F38.W1 F7 /r"   , "ext": "BMI2"},
-      {"inst": "serialize"                                                  , "op": "0F 01 E8"                       , "ext": "SERIALIZE"},
-      {"inst": "sfence"                                                     , "op": "0F AE F8"                       , "ext": "SSE"},
-      {"inst": "shlx W:r32, r32/m32, r32"                                   , "op": "RMV: VEX.LZ.66.0F38.W0 F7 /r"   , "ext": "BMI2"},
-      {"inst": "shlx W:r64, r64/m64, r64"                                   , "op": "RMV: VEX.LZ.66.0F38.W1 F7 /r"   , "ext": "BMI2"},
-      {"inst": "shrx W:r32, r32/m32, r32"                                   , "op": "RMV: VEX.LZ.F2.0F38.W0 F7 /r"   , "ext": "BMI2"},
-      {"inst": "shrx W:r64, r64/m64, r64"                                   , "op": "RMV: VEX.LZ.F2.0F38.W1 F7 /r"   , "ext": "BMI2"},
-      {"inst": "tzcnt w:r16, r16/m16"                                       , "op": "RM: 66 F3 0F BC /r"             , "ext": "BMI"        , "io": "OF=U SF=U ZF=W AF=U PF=U CF=W"},
-      {"inst": "tzcnt W:r32, r32/m32"                                       , "op": "RM: F3 0F BC /r"                , "ext": "BMI"        , "io": "OF=U SF=U ZF=W AF=U PF=U CF=W"},
-      {"inst": "tzcnt W:r64, r64/m64"                                       , "op": "RM: REX.W F3 0F BC /r"          , "ext": "BMI"        , "io": "OF=U SF=U ZF=W AF=U PF=U CF=W"},
-      {"inst": "[lock|xacqrel] xadd x:r8/m8, x:r8"                          , "op": "MR: 0F C0 /r"                   , "ext": "I486"       , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
-      {"inst": "[lock|xacqrel] xadd x:r16/m16, x:r16"                       , "op": "MR: 66 0F C1 /r"                , "ext": "I486"       , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
-      {"inst": "[lock|xacqrel] xadd X:r32/m32, X:r32"                       , "op": "MR: 0F C1 /r"                   , "ext": "I486"       , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
-      {"inst": "[lock|xacqrel] xadd X:r64/m64, X:r64"                       , "op": "MR: REX.W 0F C1 /r"             , "ext": "I486"       , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}
+    {"category": "GP GP_EXT", "ext": "I486", "data": [
+      {"inst": "[lock|xacqrel] cmpxchg x:r8/m8, r8, <al>"                   , "op": "MR: 0F B0 /r"                   , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+      {"inst": "[lock|xacqrel] cmpxchg x:r16/m16, r16, <ax>"                , "op": "MR: 66 0F B1 /r"                , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+      {"inst": "[lock|xacqrel] cmpxchg X:r32/m32, r32, <eax>"               , "op": "MR: 0F B1 /r"                   , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+      {"inst": "[lock|xacqrel] cmpxchg X:r64/m64, r64, <rax>"               , "op": "MR: REX.W 0F B1 /r"             , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+      {"inst": "cpuid X:<eax>, W:<ebx>, X:<ecx>, W:<edx>"                   , "op": "0F A2"                          , "volatile": true},
+      {"inst": "[lock|xacqrel] xadd x:r8/m8, x:r8"                          , "op": "MR: 0F C0 /r"                   , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+      {"inst": "[lock|xacqrel] xadd x:r16/m16, x:r16"                       , "op": "MR: 66 0F C1 /r"                , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+      {"inst": "[lock|xacqrel] xadd X:r32/m32, X:r32"                       , "op": "MR: 0F C1 /r"                   , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+      {"inst": "[lock|xacqrel] xadd X:r64/m64, X:r64"                       , "op": "MR: REX.W 0F C1 /r"             , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}
     ]},
 
-    {"category": "GP GP_EXT CRYPTO_HASH", "data": [
-      {"inst": "crc32 X:r32, r8/m8"                                         , "op": "RM: F2 0F 38 F0 /r"             , "ext": "SSE4_2"},
-      {"inst": "crc32 X:r32, r16/m16"                                       , "op": "RM: 66 F2 0F 38 F1 /r"          , "ext": "SSE4_2"},
-      {"inst": "crc32 X:r32, r32/m32"                                       , "op": "RM: F2 0F 38 F1 /r"             , "ext": "SSE4_2"},
-      {"inst": "crc32 X:r64, r8/m8"                                         , "op": "RM: REX.W F2 0F 38 F0 /r"       , "ext": "SSE4_2"},
-      {"inst": "crc32 X:r64, r64/m64"                                       , "op": "RM: REX.W F2 0F 38 F1 /r"       , "ext": "SSE4_2"}
+    {"category": "GP GP_EXT", "ext": "3DNOW", "volatile": true, "data": [
+      {"inst": "prefetch R:mem"                                             , "op": "0F 0D /0"}
+    ]},
+
+    {"category": "GP GP_EXT", "ext": "ADX", "data": [
+      {"inst": "adcx X:~r32, ~r32/m32"                                      , "op": "RM: 66 0F 38 F6 /r"             , "io": "CF=X"},
+      {"inst": "adcx X:~r64, ~r64/m64"                                      , "op": "RM: REX.W 66 0F 38 F6 /r"       , "io": "CF=X"},
+      {"inst": "adox X:~r32, ~r32/m32"                                      , "op": "RM: F3 0F 38 F6 /r"             , "io": "OF=X"},
+      {"inst": "adox X:~r64, ~r64/m64"                                      , "op": "RM: REX.W F3 0F 38 F6 /r"       , "io": "OF=X"}
+    ]},
+
+    {"category": "GP GP_EXT", "ext": "BMI", "data": [
+      {"inst": "andn W:r32, r32, r32/m32"                                   , "op": "RVM: VEX.LZ.0F38.W0 F2 /r"      , "io": "OF=0 SF=W ZF=W AF=U PF=U CF=0"},
+      {"inst": "andn W:r64, r64, r64/m64"                                   , "op": "RVM: VEX.LZ.0F38.W1 F2 /r"      , "io": "OF=0 SF=W ZF=W AF=U PF=U CF=0"},
+      {"inst": "bextr W:r32, r32/m32, r32"                                  , "op": "RMV: VEX.LZ.0F38.W0 F7 /r"      , "io": "OF=0 SF=U ZF=W AF=U PF=U CF=0"},
+      {"inst": "bextr W:r64, r64/m64, r64"                                  , "op": "RMV: VEX.LZ.0F38.W1 F7 /r"      , "io": "OF=0 SF=U ZF=W AF=U PF=U CF=0"},
+      {"inst": "blsi W:r32, r32/m32"                                        , "op": "VM: VEX.LZ.0F38.W0 F3 /3"       , "io": "OF=0 SF=W ZF=W AF=U PF=U CF=W"},
+      {"inst": "blsi W:r64, r64/m64"                                        , "op": "VM: VEX.LZ.0F38.W1 F3 /3"       , "io": "OF=0 SF=W ZF=W AF=U PF=U CF=W"},
+      {"inst": "blsmsk W:r32, r32/m32"                                      , "op": "VM: VEX.LZ.0F38.W0 F3 /2"       , "io": "OF=0 SF=W ZF=0 AF=U PF=U CF=W"},
+      {"inst": "blsmsk W:r64, r64/m64"                                      , "op": "VM: VEX.LZ.0F38.W1 F3 /2"       , "io": "OF=0 SF=W ZF=0 AF=U PF=U CF=W"},
+      {"inst": "blsr W:r32, r32/m32"                                        , "op": "VM: VEX.LZ.0F38.W0 F3 /1"       , "io": "OF=0 SF=W ZF=W AF=U PF=U CF=W"},
+      {"inst": "blsr W:r64, r64/m64"                                        , "op": "VM: VEX.LZ.0F38.W1 F3 /1"       , "io": "OF=0 SF=W ZF=W AF=U PF=U CF=W"},
+      {"inst": "tzcnt w:r16, r16/m16"                                       , "op": "RM: 66 F3 0F BC /r"             , "io": "OF=U SF=U ZF=W AF=U PF=U CF=W"},
+      {"inst": "tzcnt W:r32, r32/m32"                                       , "op": "RM: F3 0F BC /r"                , "io": "OF=U SF=U ZF=W AF=U PF=U CF=W"},
+      {"inst": "tzcnt W:r64, r64/m64"                                       , "op": "RM: REX.W F3 0F BC /r"          , "io": "OF=U SF=U ZF=W AF=U PF=U CF=W"}
+    ]},
+
+    {"category": "GP GP_EXT", "ext": "BMI2", "data": [
+      {"inst": "bzhi W:r32, r32/m32, r32"                                   , "op": "RMV: VEX.LZ.0F38.W0 F5 /r"      , "io": "OF=0 SF=W ZF=W AF=U PF=U CF=W"},
+      {"inst": "bzhi W:r64, r64/m64, r64"                                   , "op": "RMV: VEX.LZ.0F38.W1 F5 /r"      , "io": "OF=0 SF=W ZF=W AF=U PF=U CF=W"},
+      {"inst": "mulx W:r32, W:r32, ~r32/m32, ~<edx>"                        , "op": "RVM: VEX.LZ.F2.0F38.W0 F6 /r"},
+      {"inst": "mulx W:r64, W:r64, ~r64/m64, ~<rdx>"                        , "op": "RVM: VEX.LZ.F2.0F38.W1 F6 /r"},
+      {"inst": "pdep W:r32, r32, r32/m32"                                   , "op": "RVM: VEX.LZ.F2.0F38.W0 F5 /r"},
+      {"inst": "pdep W:r64, r64, r64/m64"                                   , "op": "RVM: VEX.LZ.F2.0F38.W1 F5 /r"},
+      {"inst": "pext W:r32, r32, r32/m32"                                   , "op": "RVM: VEX.LZ.F3.0F38.W0 F5 /r"},
+      {"inst": "pext W:r64, r64, r64/m64"                                   , "op": "RVM: VEX.LZ.F3.0F38.W1 F5 /r"},
+      {"inst": "rorx W:r32, r32/m32, ib/ub"                                 , "op": "RM: VEX.LZ.F2.0F3A.W0 F0 /r ib"},
+      {"inst": "rorx W:r64, r64/m64, ib/ub"                                 , "op": "RM: VEX.LZ.F2.0F3A.W1 F0 /r ib"},
+      {"inst": "sarx W:r32, r32/m32, r32"                                   , "op": "RMV: VEX.LZ.F3.0F38.W0 F7 /r"},
+      {"inst": "sarx W:r64, r64/m64, r64"                                   , "op": "RMV: VEX.LZ.F3.0F38.W1 F7 /r"},
+      {"inst": "shlx W:r32, r32/m32, r32"                                   , "op": "RMV: VEX.LZ.66.0F38.W0 F7 /r"},
+      {"inst": "shlx W:r64, r64/m64, r64"                                   , "op": "RMV: VEX.LZ.66.0F38.W1 F7 /r"},
+      {"inst": "shrx W:r32, r32/m32, r32"                                   , "op": "RMV: VEX.LZ.F2.0F38.W0 F7 /r"},
+      {"inst": "shrx W:r64, r64/m64, r64"                                   , "op": "RMV: VEX.LZ.F2.0F38.W1 F7 /r"}
+    ]},
+
+    {"category": "GP GP_EXT", "ext": "CET_SS", "volatile": true, "data": [
+      {"inst": "incsspd r32"                                                , "op": "F3 0F AE /5"},
+      {"inst": "incsspq r64"                                                , "op": "REX.W F3 0F AE /5"},
+      {"inst": "rdsspd W:r32"                                               , "op": "F3 0F 1E /1"},
+      {"inst": "rdsspq W:r64"                                               , "op": "REX.W F3 0F 1E /1"},
+      {"inst": "rstorssp R:m64"                                             , "op": "F3 0F 01 /5"                    , "io": "OF=0 SF=0 ZF=0 AF=0 PF=0 CF=W"},
+      {"inst": "saveprevssp"                                                , "op": "F3 0F 01 EA"                    , "io": "OF=0 SF=0 ZF=0 AF=0 PF=0 CF=W"}
+    ]},
+
+    {"category": "GP GP_EXT", "ext": "CLDEMOTE", "data": [
+      {"inst": "cldemote R:mem"                                             , "op": "0F 1C /0"}
+    ]},
+
+    {"category": "GP GP_EXT", "ext": "CLFLUSH", "data": [
+      {"inst": "clflush R:mem"                                              , "op": "0F AE /7"}
+    ]},
+
+    {"category": "GP GP_EXT", "ext": "CLFLUSHOPT", "data": [
+      {"inst": "clflushopt R:mem"                                           , "op": "66 0F AE /7"}
+    ]},
+
+    {"category": "GP GP_EXT", "ext": "CLWB", "data": [
+      {"inst": "clwb R:mem"                                                 , "op": "66 0F AE /6"}
+    ]},
+
+    {"category": "GP GP_EXT", "ext": "CLZERO", "data": [
+      {"inst": "clzero R:<m512(ds:zax)>"                                    , "op": "0F 01 FC"}
+    ]},
+
+    {"category": "GP GP_EXT", "ext": "CMOV", "data": [
+      {"inst": "cmovo x:r16, r16/m16"                                       , "op": "RM: 66 0F 40 /r"                , "io": "OF=R"},
+      {"inst": "cmovo X:r32, r32/m32"                                       , "op": "RM: 0F 40 /r"                   , "io": "OF=R"},
+      {"inst": "cmovo X:r64, r64/m64"                                       , "op": "RM: REX.W 0F 40 /r"             , "io": "OF=R"},
+      {"inst": "cmovno x:r16, r16/m16"                                      , "op": "RM: 66 0F 41 /r"                , "io": "OF=R"},
+      {"inst": "cmovno X:r32, r32/m32"                                      , "op": "RM: 0F 41 /r"                   , "io": "OF=R"},
+      {"inst": "cmovno X:r64, r64/m64"                                      , "op": "RM: REX.W 0F 41 /r"             , "io": "OF=R"},
+      {"inst": "cmovb|cmovnae|cmovc x:r16, r16/m16"                         , "op": "RM: 66 0F 42 /r"                , "io": "CF=R"},
+      {"inst": "cmovb|cmovnae|cmovc X:r32, r32/m32"                         , "op": "RM: 0F 42 /r"                   , "io": "CF=R"},
+      {"inst": "cmovb|cmovnae|cmovc X:r64, r64/m64"                         , "op": "RM: REX.W 0F 42 /r"             , "io": "CF=R"},
+      {"inst": "cmovae|cmovnb|cmovnc x:r16, r16/m16"                        , "op": "RM: 66 0F 43 /r"                , "io": "CF=R"},
+      {"inst": "cmovae|cmovnb|cmovnc X:r32, r32/m32"                        , "op": "RM: 0F 43 /r"                   , "io": "CF=R"},
+      {"inst": "cmovae|cmovnb|cmovnc X:r64, r64/m64"                        , "op": "RM: REX.W 0F 43 /r"             , "io": "CF=R"},
+      {"inst": "cmove|cmovz x:r16, r16/m16"                                 , "op": "RM: 66 0F 44 /r"                , "io": "ZF=R"},
+      {"inst": "cmove|cmovz X:r32, r32/m32"                                 , "op": "RM: 0F 44 /r"                   , "io": "ZF=R"},
+      {"inst": "cmove|cmovz X:r64, r64/m64"                                 , "op": "RM: REX.W 0F 44 /r"             , "io": "ZF=R"},
+      {"inst": "cmovne|cmovnz x:r16, r16/m16"                               , "op": "RM: 66 0F 45 /r"                , "io": "ZF=R"},
+      {"inst": "cmovne|cmovnz X:r32, r32/m32"                               , "op": "RM: 0F 45 /r"                   , "io": "ZF=R"},
+      {"inst": "cmovne|cmovnz X:r64, r64/m64"                               , "op": "RM: REX.W 0F 45 /r"             , "io": "ZF=R"},
+      {"inst": "cmovbe|cmovna x:r16, r16/m16"                               , "op": "RM: 66 0F 46 /r"                , "io": "CF=R ZF=R"},
+      {"inst": "cmovbe|cmovna X:r32, r32/m32"                               , "op": "RM: 0F 46 /r"                   , "io": "CF=R ZF=R"},
+      {"inst": "cmovbe|cmovna X:r64, r64/m64"                               , "op": "RM: REX.W 0F 46 /r"             , "io": "CF=R ZF=R"},
+      {"inst": "cmova|cmovnbe x:r16, r16/m16"                               , "op": "RM: 66 0F 47 /r"                , "io": "CF=R ZF=R"},
+      {"inst": "cmova|cmovnbe X:r32, r32/m32"                               , "op": "RM: 0F 47 /r"                   , "io": "CF=R ZF=R"},
+      {"inst": "cmova|cmovnbe X:r64, r64/m64"                               , "op": "RM: REX.W 0F 47 /r"             , "io": "CF=R ZF=R"},
+      {"inst": "cmovs x:r16, r16/m16"                                       , "op": "RM: 66 0F 48 /r"                , "io": "SF=R"},
+      {"inst": "cmovs X:r32, r32/m32"                                       , "op": "RM: 0F 48 /r"                   , "io": "SF=R"},
+      {"inst": "cmovs X:r64, r64/m64"                                       , "op": "RM: REX.W 0F 48 /r"             , "io": "SF=R"},
+      {"inst": "cmovns x:r16, r16/m16"                                      , "op": "RM: 66 0F 49 /r"                , "io": "SF=R"},
+      {"inst": "cmovns X:r32, r32/m32"                                      , "op": "RM: 0F 49 /r"                   , "io": "SF=R"},
+      {"inst": "cmovns X:r64, r64/m64"                                      , "op": "RM: REX.W 0F 49 /r"             , "io": "SF=R"},
+      {"inst": "cmovp|cmovpe x:r16, r16/m16"                                , "op": "RM: 66 0F 4A /r"                , "io": "PF=R"},
+      {"inst": "cmovp|cmovpe X:r32, r32/m32"                                , "op": "RM: 0F 4A /r"                   , "io": "PF=R"},
+      {"inst": "cmovp|cmovpe X:r64, r64/m64"                                , "op": "RM: REX.W 0F 4A /r"             , "io": "PF=R"},
+      {"inst": "cmovnp|cmovpo x:r16, r16/m16"                               , "op": "RM: 66 0F 4B /r"                , "io": "PF=R"},
+      {"inst": "cmovnp|cmovpo X:r32, r32/m32"                               , "op": "RM: 0F 4B /r"                   , "io": "PF=R"},
+      {"inst": "cmovnp|cmovpo X:r64, r64/m64"                               , "op": "RM: REX.W 0F 4B /r"             , "io": "PF=R"},
+      {"inst": "cmovl|cmovnge x:r16, r16/m16"                               , "op": "RM: 66 0F 4C /r"                , "io": "SF=R OF=R"},
+      {"inst": "cmovl|cmovnge X:r32, r32/m32"                               , "op": "RM: 0F 4C /r"                   , "io": "SF=R OF=R"},
+      {"inst": "cmovl|cmovnge X:r64, r64/m64"                               , "op": "RM: REX.W 0F 4C /r"             , "io": "SF=R OF=R"},
+      {"inst": "cmovge|cmovnl x:r16, r16/m16"                               , "op": "RM: 66 0F 4D /r"                , "io": "SF=R OF=R"},
+      {"inst": "cmovge|cmovnl X:r32, r32/m32"                               , "op": "RM: 0F 4D /r"                   , "io": "SF=R OF=R"},
+      {"inst": "cmovge|cmovnl X:r64, r64/m64"                               , "op": "RM: REX.W 0F 4D /r"             , "io": "SF=R OF=R"},
+      {"inst": "cmovle|cmovng x:r16, r16/m16"                               , "op": "RM: 66 0F 4E /r"                , "io": "ZF=R SF=R OF=R"},
+      {"inst": "cmovle|cmovng X:r32, r32/m32"                               , "op": "RM: 0F 4E /r"                   , "io": "ZF=R SF=R OF=R"},
+      {"inst": "cmovle|cmovng X:r64, r64/m64"                               , "op": "RM: REX.W 0F 4E /r"             , "io": "ZF=R SF=R OF=R"},
+      {"inst": "cmovg|cmovnle x:r16, r16/m16"                               , "op": "RM: 66 0F 4F /r"                , "io": "ZF=R SF=R OF=R"},
+      {"inst": "cmovg|cmovnle X:r32, r32/m32"                               , "op": "RM: 0F 4F /r"                   , "io": "ZF=R SF=R OF=R"},
+      {"inst": "cmovg|cmovnle X:r64, r64/m64"                               , "op": "RM: REX.W 0F 4F /r"             , "io": "ZF=R SF=R OF=R"}
+    ]},
+
+    {"category": "GP GP_EXT", "ext": "CMPCCXADD", "data": [
+      {"inst": "cmpbexadd X:m32, X:r32, R:r32"                              , "op": "MVR: VEX.128.66.0F38.W0 E6 /r"  , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
+      {"inst": "cmpbexadd X:m64, X:r64, R:r64"                              , "op": "MVR: VEX.128.66.0F38.W1 E6 /r"  , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
+      {"inst": "cmpbxadd X:m32, X:r32, R:r32"                               , "op": "MVR: VEX.128.66.0F38.W0 E2 /r"  , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
+      {"inst": "cmpbxadd X:m64, X:r64, R:r64"                               , "op": "MVR: VEX.128.66.0F38.W1 E2 /r"  , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
+      {"inst": "cmplexadd X:m32, X:r32, R:r32"                              , "op": "MVR: VEX.128.66.0F38.W0 EE /r"  , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
+      {"inst": "cmplexadd X:m64, X:r64, R:r64"                              , "op": "MVR: VEX.128.66.0F38.W1 EE /r"  , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
+      {"inst": "cmplxadd X:m32, X:r32, R:r32"                               , "op": "MVR: VEX.128.66.0F38.W0 EC /r"  , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
+      {"inst": "cmplxadd X:m64, X:r64, R:r64"                               , "op": "MVR: VEX.128.66.0F38.W1 EC /r"  , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
+      {"inst": "cmpnbexadd X:m32, X:r32, R:r32"                             , "op": "MVR: VEX.128.66.0F38.W0 E7 /r"  , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
+      {"inst": "cmpnbexadd X:m64, X:r64, R:r64"                             , "op": "MVR: VEX.128.66.0F38.W1 E7 /r"  , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
+      {"inst": "cmpnbxadd X:m32, X:r32, R:r32"                              , "op": "MVR: VEX.128.66.0F38.W0 E3 /r"  , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
+      {"inst": "cmpnbxadd X:m64, X:r64, R:r64"                              , "op": "MVR: VEX.128.66.0F38.W1 E3 /r"  , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
+      {"inst": "cmpnlexadd X:m32, X:r32, R:r32"                             , "op": "MVR: VEX.128.66.0F38.W0 EF /r"  , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
+      {"inst": "cmpnlexadd X:m64, X:r64, R:r64"                             , "op": "MVR: VEX.128.66.0F38.W1 EF /r"  , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
+      {"inst": "cmpnlxadd X:m32, X:r32, R:r32"                              , "op": "MVR: VEX.128.66.0F38.W0 ED /r"  , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
+      {"inst": "cmpnlxadd X:m64, X:r64, R:r64"                              , "op": "MVR: VEX.128.66.0F38.W1 ED /r"  , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
+      {"inst": "cmpnoxadd X:m32, X:r32, R:r32"                              , "op": "MVR: VEX.128.66.0F38.W0 E1 /r"  , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
+      {"inst": "cmpnoxadd X:m64, X:r64, R:r64"                              , "op": "MVR: VEX.128.66.0F38.W1 E1 /r"  , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
+      {"inst": "cmpnpxadd X:m32, X:r32, R:r32"                              , "op": "MVR: VEX.128.66.0F38.W0 EB /r"  , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
+      {"inst": "cmpnpxadd X:m64, X:r64, R:r64"                              , "op": "MVR: VEX.128.66.0F38.W1 EB /r"  , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
+      {"inst": "cmpnsxadd X:m32, X:r32, R:r32"                              , "op": "MVR: VEX.128.66.0F38.W0 E9 /r"  , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
+      {"inst": "cmpnsxadd X:m64, X:r64, R:r64"                              , "op": "MVR: VEX.128.66.0F38.W1 E9 /r"  , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
+      {"inst": "cmpnzxadd X:m32, X:r32, R:r32"                              , "op": "MVR: VEX.128.66.0F38.W0 E5 /r"  , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
+      {"inst": "cmpnzxadd X:m64, X:r64, R:r64"                              , "op": "MVR: VEX.128.66.0F38.W1 E5 /r"  , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
+      {"inst": "cmpoxadd X:m32, X:r32, R:r32"                               , "op": "MVR: VEX.128.66.0F38.W0 E0 /r"  , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
+      {"inst": "cmpoxadd X:m64, X:r64, R:r64"                               , "op": "MVR: VEX.128.66.0F38.W1 E0 /r"  , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
+      {"inst": "cmppxadd X:m32, X:r32, R:r32"                               , "op": "MVR: VEX.128.66.0F38.W0 EA /r"  , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
+      {"inst": "cmppxadd X:m64, X:r64, R:r64"                               , "op": "MVR: VEX.128.66.0F38.W1 EA /r"  , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
+      {"inst": "cmpsxadd X:m32, X:r32, R:r32"                               , "op": "MVR: VEX.128.66.0F38.W0 E8 /r"  , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
+      {"inst": "cmpsxadd X:m64, X:r64, R:r64"                               , "op": "MVR: VEX.128.66.0F38.W1 E8 /r"  , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
+      {"inst": "cmpzxadd X:m32, X:r32, R:r32"                               , "op": "VEX.128.66.0F38.W0 E4 /r"       , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
+      {"inst": "cmpzxadd X:m64, X:r64, R:r64"                               , "op": "VEX.128.66.0F38.W1 E4 /r"       , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"}
+    ]},
+
+    {"category": "GP GP_EXT", "ext": "CMPXCHG8B", "data": [
+      {"inst": "[lock|xacqrel] cmpxchg8b X:m64,X:<edx>,X:<eax>,<ecx>,<ebx>" , "op": "0F C7 /1"                       , "io": "ZF=W"}
+    ]},
+
+    {"category": "GP GP_EXT", "ext": "CMPXCHG16B", "data": [
+      {"inst": "[lock|xacqrel] cmpxchg16b X:m128,X:<rdx>,X:<rax>,<rcx>,<rbx>","op": "REX.W 0F C7 /1"                 , "io": "ZF=W"}
+    ]},
+
+    {"category": "GP GP_EXT", "ext": "FSGSBASE", "arch": "X64", "volatile": true, "data": [
+      {"inst": "rdfsbase W:r32"                                             , "op": "F3 0F AE /0"},
+      {"inst": "rdfsbase W:r64"                                             , "op": "REX.W F3 0F AE /0"},
+      {"inst": "rdgsbase W:r32"                                             , "op": "F3 0F AE /1"},
+      {"inst": "rdgsbase W:r64"                                             , "op": "REX.W F3 0F AE /1"},
+      {"inst": "wrfsbase R:r32"                                             , "op": "F3 0F AE /2"},
+      {"inst": "wrfsbase R:r64"                                             , "op": "REX.W F3 0F AE /2"},
+      {"inst": "wrgsbase R:r32"                                             , "op": "F3 0F AE /3"},
+      {"inst": "wrgsbase R:r64"                                             , "op": "REX.W F3 0F AE /3"}
+    ]},
+
+    {"category": "GP GP_EXT", "ext": "FXSR", "volatile": true, "data": [
+      {"inst": "fxrstor R:mem"                                              , "op": "0F AE /1"                       , "io": "C0=W C1=W C2=W C3=W"},
+      {"inst": "fxrstor64 R:mem"                                            , "op": "REX.W 0F AE /1"                 , "io": "C0=W C1=W C2=W C3=W"},
+      {"inst": "fxsave W:mem"                                               , "op": "0F AE /0"                       , "io": "C0=R C1=R C2=R C3=R"},
+      {"inst": "fxsave64 W:mem"                                             , "op": "REX.W 0F AE /0"                 , "io": "C0=R C1=R C2=R C3=R"}
+    ]},
+
+    {"category": "GP GP_EXT", "ext": "LAHFSAHF", "data": [
+      {"inst": "lahf w:<ah>"                                                , "op": "9F"                             , "io": "SF=R ZF=R AF=R PF=R CF=R"},
+      {"inst": "sahf R:<ah>"                                                , "op": "9E"                             , "io": "SF=W ZF=W AF=W PF=W CF=W"}
+    ]},
+
+    {"category": "GP GP_EXT", "ext": "LWP", "volatile": true, "data": [
+      {"inst": "llwpcb R:r32"                                               , "op": "XOP.L0.P0.M09.W0 12 /0"},
+      {"inst": "llwpcb R:r64"                                               , "op": "XOP.L0.P0.M09.W1 12 /0"},
+      {"inst": "lwpins R:r32, R:r32/m32, id/ud"                             , "op": "VM: XOP.L0.P0.M0A.W0 12 /0 id"},
+      {"inst": "lwpins R:r64, R:r32/m32, id/ud"                             , "op": "VM: XOP.L0.P0.M0A.W1 12 /0 id"},
+      {"inst": "lwpval R:r32, R:r32/m32, id/ud"                             , "op": "VM: XOP.L0.P0.M0A.W0 12 /1 id"},
+      {"inst": "lwpval R:r64, R:r32/m32, id/ud"                             , "op": "VM: XOP.L0.P0.M0A.W1 12 /1 id"},
+      {"inst": "slwpcb W:r32"                                               , "op": "XOP.L0.P0.M09.W0 12 /1"},
+      {"inst": "slwpcb W:r64"                                               , "op": "XOP.L0.P0.M09.W1 12 /1"}
+    ]},
+
+    {"category": "GP GP_EXT", "ext": "LZCNT", "data": [
+      {"inst": "lzcnt w:r16, r16/m16"                                       , "op": "RM: 66 F3 0F BD /r"             , "io": "OF=U SF=U ZF=W AF=U PF=U CF=W"},
+      {"inst": "lzcnt W:r32, r32/m32"                                       , "op": "RM: F3 0F BD /r"                , "io": "OF=U SF=U ZF=W AF=U PF=U CF=W"},
+      {"inst": "lzcnt W:r64, r64/m64"                                       , "op": "RM: REX.W F3 0F BD /r"          , "io": "OF=U SF=U ZF=W AF=U PF=U CF=W"}
+    ]},
+
+    {"category": "GP GP_EXT", "ext": "MONITORX", "volatile": true, "data": [
+      {"inst": "monitorx R:<mem(ds:zax)>, R:<ecx>, R:<edx>"                 , "op": "0F 01 FA"},
+      {"inst": "mwaitx R:<eax>, R:<ecx>, R:<ebx>"                           , "op": "0F 01 FB"}
+    ]},
+
+    {"category": "GP GP_EXT", "ext": "MCOMMIT", "data": [
+      {"inst": "mcommit"                                                    , "op": "F3 0F 01 FA"                    , "io": "OF=0 SF=0 ZF=0 AF=0 PF=0 CF=W"}
+    ]},
+
+    {"category": "GP GP_EXT", "ext": "MOVBE", "data": [
+      {"inst": "movbe w:r16, m16"                                           , "op": "RM: 66 0F 38 F0 /r"},
+      {"inst": "movbe W:r32, m32"                                           , "op": "RM: 0F 38 F0 /r"},
+      {"inst": "movbe W:r64, m64"                                           , "op": "RM: REX.W 0F 38 F0 /r"},
+      {"inst": "movbe W:m16, r16"                                           , "op": "MR: 66 0F 38 F1 /r"},
+      {"inst": "movbe W:m32, r32"                                           , "op": "MR: 0F 38 F1 /r"},
+      {"inst": "movbe W:m64, r64"                                           , "op": "MR: REX.W 0F 38 F1 /r"}
+    ]},
+
+    {"category": "GP GP_EXT", "ext": "MOVDIRI", "data": [
+      {"inst": "movdiri W:m32, r32"                                         , "op": "MR: 0F 38 F9 /r"},
+      {"inst": "movdiri W:m64, r64"                                         , "op": "MR: REX.W 0F 38 F9 /r"}
+    ]},
+
+    {"category": "GP GP_EXT", "ext": "MOVDIR64B", "data": [
+      {"inst": "movdir64b W:m512(es:r32), m512"                             , "op": "RM: 66 0F 38 F8 /r"},
+      {"inst": "movdir64b W:m512(es:r64), m512"                             , "op": "RM: 66 0F 38 F8 /r"}
+    ]},
+
+    {"category": "GP GP_EXT", "ext": "PCONFIG", "volatile": true, "data": [
+      {"inst": "pconfig"                                                    , "op": "0F 01 C5"}
+    ]},
+
+    {"category": "GP GP_EXT", "ext": "POPCNT", "data": [
+      {"inst": "popcnt w:r16, r16/m16"                                      , "op": "RM: 66 F3 0F B8 /r"             , "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=0"},
+      {"inst": "popcnt W:r32, r32/m32"                                      , "op": "RM: F3 0F B8 /r"                , "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=0"},
+      {"inst": "popcnt W:r64, r64/m64"                                      , "op": "RM: REX.W F3 0F B8 /r"          , "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=0"}
+    ]},
+
+    {"category": "GP GP_EXT", "ext": "OSPKE", "data": [
+      {"inst": "rdpkru W:<edx>, W:<eax>, R:<ecx>"                           , "op": "0F 01 EE"}
+    ]},
+
+    {"category": "GP GP_EXT", "ext": "PREFETCHI", "arch": "X64", "volatile": true, "data": [
+      {"inst": "prefetchit0 R:mem"                                          , "op": "0F 18 /7"},
+      {"inst": "prefetchit1 R:mem"                                          , "op": "0F 18 /6"}
+    ]},
+
+    {"category": "GP GP_EXT", "ext": "PREFETCHW", "volatile": true, "data": [
+      {"inst": "prefetchw R:mem"                                            , "op": "0F 0D /1"                       , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"}
+    ]},
+
+    {"category": "GP GP_EXT", "ext": "PREFETCHWT1", "volatile": true, "data": [
+      {"inst": "prefetchwt1 R:mem"                                          , "op": "0F 0D /2"                       , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"}
+    ]},
+
+    {"category": "GP GP_EXT", "ext": "PTWRITE", "volatile": true, "data": [
+      {"inst": "ptwrite R:r32/m32"                                          , "op": "F3 0F AE /4"},
+      {"inst": "ptwrite R:r64/m64"                                          , "op": "REX.W F3 0F AE /4"}
+    ]},
+
+    {"category": "GP GP_EXT", "ext": "RAO_INT", "volatile": true, "data": [
+      {"inst": "aadd X:m32, r32"                                            , "op": "MR: 0F 38 FC /r"},
+      {"inst": "aadd X:m64, r64"                                            , "op": "MR: REX.W 0F 38 FC /r"},
+      {"inst": "aand X:m32, r32"                                            , "op": "MR: 66 0F 38 FC /r"},
+      {"inst": "aand X:m64, r64"                                            , "op": "MR: REX.W 66 0F 38 FC /r"},
+      {"inst": "aor X:m32, r32"                                             , "op": "MR: F2 0F 38 FC /r"},
+      {"inst": "aor X:m64, r64"                                             , "op": "MR: REX.W F2 0F 38 FC /r"},
+      {"inst": "axor X:m32, r32"                                            , "op": "MR: F3 0F 38 FC /r"},
+      {"inst": "axor X:m64, r64"                                            , "op": "MR: REX.W F3 0F 38 FC /r"}
+    ]},
+
+    {"category": "GP GP_EXT", "ext": "RDPID", "data": [
+      {"inst": "rdpid W:r32"                                                , "op": "R: F3 0F C7 /7"                 , "arch": "X86"},
+      {"inst": "rdpid W:r64"                                                , "op": "R: F3 0F C7 /7"                 , "arch": "X64"}
+    ]},
+
+    {"category": "GP GP_EXT", "ext": "RDPRU", "data": [
+      {"inst": "rdpru W:<edx>, W:<eax>, R:<ecx>"                            , "op": "0F 01 FD"}
+    ]},
+
+    {"category": "GP GP_EXT", "ext": "RDRAND", "data": [
+      {"inst": "rdrand w:r16"                                               , "op": "66 0F C7 /6"                    , "io": "OF=0 SF=0 ZF=0 AF=0 PF=0 CF=W"},
+      {"inst": "rdrand W:r32"                                               , "op": "0F C7 /6"                       , "io": "OF=0 SF=0 ZF=0 AF=0 PF=0 CF=W"},
+      {"inst": "rdrand W:r64"                                               , "op": "REX.W 0F C7 /6"                 , "io": "OF=0 SF=0 ZF=0 AF=0 PF=0 CF=W"}
+    ]},
+
+    {"category": "GP GP_EXT", "ext": "RDSEED", "data": [
+      {"inst": "rdseed w:r16"                                               , "op": "66 0F C7 /7"                    , "io": "OF=0 SF=0 ZF=0 AF=0 PF=0 CF=W"},
+      {"inst": "rdseed W:r32"                                               , "op": "0F C7 /7"                       , "io": "OF=0 SF=0 ZF=0 AF=0 PF=0 CF=W"},
+      {"inst": "rdseed W:r64"                                               , "op": "REX.W 0F C7 /7"                 , "io": "OF=0 SF=0 ZF=0 AF=0 PF=0 CF=W"}
+    ]},
+
+    {"category": "GP GP_EXT", "ext": "RDTSC", "data": [
+      {"inst": "rdtsc W:<edx>, W:<eax>"                                     , "op": "0F 31"}
+    ]},
+
+    {"category": "GP GP_EXT", "ext": "RDTSCP", "data": [
+      {"inst": "rdtscp W:<edx>, W:<eax>, W:<ecx>"                           , "op": "0F 01 F9"}
+    ]},
+
+    {"category": "GP GP_EXT", "ext": "RTM", "volatile": true, "data": [
+      {"inst": "xabort ib/ub"                                               , "op": "C6 /7 ib"},
+      {"inst": "xbegin rel16"                                               , "op": "66 C7 /7 cw"},
+      {"inst": "xbegin rel32"                                               , "op": "C7 /7 cd"},
+      {"inst": "xend"                                                       , "op": "0F 01 D5"}
+    ]},
+
+    {"category": "GP GP_EXT", "ext": "SERIALIZE", "volatile": true, "data": [
+      {"inst": "serialize"                                                  , "op": "0F 01 E8"}
+    ]},
+
+    {"category": "GP GP_EXT", "ext": "SSE", "volatile": true, "data": [
+      {"inst": "prefetchnta R:mem"                                          , "op": "0F 18 /0"},
+      {"inst": "prefetcht0 R:mem"                                           , "op": "0F 18 /1"},
+      {"inst": "prefetcht1 R:mem"                                           , "op": "0F 18 /2"},
+      {"inst": "prefetcht2 R:mem"                                           , "op": "0F 18 /3"},
+      {"inst": "sfence"                                                     , "op": "0F AE F8"}
+    ]},
+
+    {"category": "GP GP_EXT", "ext": "SSE2", "volatile": true, "data": [
+      {"inst": "lfence"                                                     , "op": "0F AE E8"},
+      {"inst": "mfence"                                                     , "op": "0F AE F0"},
+      {"inst": "movnti W:m32, r32"                                          , "op": "MR: 0F C3 /r"},
+      {"inst": "movnti W:m64, r64"                                          , "op": "MR: REX.W 0F C3 /r"}
+    ]},
+
+    {"category": "GP GP_EXT CRYPTO_HASH", "ext": "SSE4_2", "data": [
+      {"inst": "crc32 X:r32, r8/m8"                                         , "op": "RM: F2 0F 38 F0 /r"},
+      {"inst": "crc32 X:r32, r16/m16"                                       , "op": "RM: 66 F2 0F 38 F1 /r"},
+      {"inst": "crc32 X:r32, r32/m32"                                       , "op": "RM: F2 0F 38 F1 /r"},
+      {"inst": "crc32 X:r64, r8/m8"                                         , "op": "RM: REX.W F2 0F 38 F0 /r"},
+      {"inst": "crc32 X:r64, r64/m64"                                       , "op": "RM: REX.W F2 0F 38 F1 /r"}
+    ]},
+
+    {"category": "GP GP_EXT", "ext": "TSE", "arch": "X64", "volatile": true, "data": [
+      {"inst": "pbndkb W:<rax>, R:<mem(ds:rbx)>, W:<mem(ds:rcx)>"           , "op": "0F 01 C7"                       , "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=0"}
+    ]},
+
+    {"category": "GP GP_EXT", "ext": "TSX", "volatile": true, "data": [
+      {"inst": "xtest"                                                      , "op": "0F 01 D6"                       , "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=0"}
+    ]},
+
+    {"category": "GP GP_EXT", "ext": "TSXLDTRK", "volatile": true, "data": [
+      {"inst": "xresldtrk"                                                  , "op": "F2 0F 01 E9"},
+      {"inst": "xsusldtrk"                                                  , "op": "F2 0F 01 E8"}
+    ]},
+
+    {"category": "GP GP_EXT", "ext": "UINTR", "arch": "X64", "volatile": true, "data": [
+      {"inst": "uiret"                                                      , "op": "F3 0F 01 EC"},
+      {"inst": "clui"                                                       , "op": "F3 0F 01 EE"},
+      {"inst": "stui"                                                       , "op": "F3 0F 01 EF"},
+      {"inst": "testui"                                                     , "op": "F3 0F 01 ED"                    , "io": "OF=0 SF=0 ZF=0 AF=0 PF=0 CF=W"},
+      {"inst": "senduipi R:r64"                                             , "op": "R: F3 0F C7 /6"}
+    ]},
+
+    {"category": "GP GP_EXT", "ext": "WAITPKG", "volatile": true, "data": [
+      {"inst": "tpause R:r32, <edx>, <eax>"                                 , "op": "66 0F AE /6"                    , "io": "OF=0 SF=0 ZF=0 AF=0 PF=0 CF=W"},
+      {"inst": "umonitor R:mem(ds:r32)"                                     , "op": "F3 0F AE /6"                    , "arch": "X86"},
+      {"inst": "umonitor R:mem(ds:r64)"                                     , "op": "F3 0F AE /6"                    , "arch": "X64"},
+      {"inst": "umwait R:r32, <edx>, <eax>"                                 , "op": "F2 0F AE /6"                    , "io": "OF=0 SF=0 ZF=0 AF=0 PF=0 CF=W"}
+    ]},
+
+    {"category": "GP GP_EXT", "ext": "XSAVE", "volatile": true, "data": [
+      {"inst": "xgetbv W:<edx>, W:<eax>, R:<ecx>"                           , "op": "0F 01 D0"                       , "io": "XCR=R"},
+      {"inst": "xrstor R:mem, <edx>, <eax>"                                 , "op": "0F AE /5"                       , "io": "XCR=R"},
+      {"inst": "xrstor64 R:mem, <edx>, <eax>"                               , "op": "REX.W 0F AE /5"                 , "io": "XCR=R"},
+      {"inst": "xsave W:mem, <edx>, <eax>"                                  , "op": "0F AE /4"                       , "io": "XCR=R"},
+      {"inst": "xsave64 W:mem, <edx>, <eax>"                                , "op": "REX.W 0F AE /4"                 , "io": "XCR=R"}
+    ]},
+
+    {"category": "GP GP_EXT", "ext": "XSAVEC", "volatile": true, "data": [
+      {"inst": "xsavec W:mem, <edx>, <eax>"                                 , "op": "0F C7 /4"                       , "io": "XCR=R"},
+      {"inst": "xsavec64 W:mem, <edx>, <eax>"                               , "op": "REX.W 0F C7 /4"                 , "io": "XCR=R"}
+    ]},
+
+    {"category": "GP GP_EXT", "ext": "XSAVEOPT", "volatile": true, "data": [
+      {"inst": "xsaveopt W:mem, <edx>, <eax>"                               , "op": "0F AE /6"                       , "io": "XCR=R"},
+      {"inst": "xsaveopt64 W:mem, <edx>, <eax>"                             , "op": "REX.W 0F AE /6"                 , "io": "XCR=R"}
     ]},
 
     {"category": "GP", "volatile": true, "data": [
@@ -863,21 +1068,35 @@
       {"inst": "xlatb"                                                      , "op": "D7"}
     ]},
 
-    {"category": "GP", "deprecated": true, "data": [
-      {"inst": "aaa x:<ax>"                                                 , "op": "37"                             , "arch": "X86", "io": "OF=U SF=U ZF=U AF=W PF=U CF=W"},
-      {"inst": "aas x:<ax>"                                                 , "op": "3F"                             , "arch": "X86", "io": "OF=U SF=U ZF=U AF=W PF=U CF=W"},
-      {"inst": "aad x:<ax>, ib/ub"                                          , "op": "D5 ib"                          , "arch": "X86", "io": "OF=U SF=W ZF=W AF=U PF=W CF=U"},
-      {"inst": "aam x:<ax>, ib/ub"                                          , "op": "D4 ib"                          , "arch": "X86", "io": "OF=U SF=W ZF=W AF=U PF=W CF=U"},
-      {"inst": "arpl x:r16/m16, R:r16"                                      , "op": "MR: 63 /r"                      , "arch": "X86", "io": "ZF=W"},
-      {"inst": "bound R:r16, R:m32"                                         , "op": "RM: 66 62 /r"                   , "arch": "X86"},
-      {"inst": "bound R:r32, R:m64"                                         , "op": "RM: 62 /r"                      , "arch": "X86"},
-      {"inst": "daa x:<ax>"                                                 , "op": "27"                             , "arch": "X86", "io": "OF=U SF=W ZF=W AF=W PF=W CF=W"},
-      {"inst": "das x:<ax>"                                                 , "op": "2F"                             , "arch": "X86", "io": "OF=U SF=W ZF=W AF=W PF=W CF=W"},
-      {"inst": "into"                                                       , "op": "CE"                             , "arch": "X86", "io": "OF=R"},
-      {"inst": "popa"                                                       , "op": "66 61"                          , "arch": "X86"},
-      {"inst": "popad"                                                      , "op": "61"                             , "arch": "X86"},
-      {"inst": "pusha"                                                      , "op": "66 60"                          , "arch": "X86"},
-      {"inst": "pushad"                                                     , "op": "60"                             , "arch": "X86"}
+    {"category": "GP", "deprecated": true, "arch": "X86", "data": [
+      {"inst": "aaa x:<ax>"                                                 , "op": "37"                             , "io": "OF=U SF=U ZF=U AF=W PF=U CF=W"},
+      {"inst": "aas x:<ax>"                                                 , "op": "3F"                             , "io": "OF=U SF=U ZF=U AF=W PF=U CF=W"},
+      {"inst": "aad x:<ax>, ib/ub"                                          , "op": "D5 ib"                          , "io": "OF=U SF=W ZF=W AF=U PF=W CF=U"},
+      {"inst": "aam x:<ax>, ib/ub"                                          , "op": "D4 ib"                          , "io": "OF=U SF=W ZF=W AF=U PF=W CF=U"},
+      {"inst": "arpl x:r16/m16, R:r16"                                      , "op": "MR: 63 /r"                      , "io": "ZF=W"},
+      {"inst": "bound R:r16, R:m32"                                         , "op": "RM: 66 62 /r"},
+      {"inst": "bound R:r32, R:m64"                                         , "op": "RM: 62 /r"},
+      {"inst": "daa x:<ax>"                                                 , "op": "27"                             , "io": "OF=U SF=W ZF=W AF=W PF=W CF=W"},
+      {"inst": "das x:<ax>"                                                 , "op": "2F"                             , "io": "OF=U SF=W ZF=W AF=W PF=W CF=W"},
+      {"inst": "into"                                                       , "op": "CE"                             , "io": "OF=R"},
+      {"inst": "popa"                                                       , "op": "66 61"},
+      {"inst": "popad"                                                      , "op": "61"},
+      {"inst": "pusha"                                                      , "op": "66 60"},
+      {"inst": "pushad"                                                     , "op": "60"}
+    ]},
+
+    {"category": "GP GP_EXT", "ext": "MPX", "deprecated": true, "data": [
+      {"inst": "bndcl R:bnd, r32/m32"                                       , "op": "RM: F3 0F 1A /r"                , "arch": "X86"},
+      {"inst": "bndcl R:bnd, r64/m64"                                       , "op": "RM: F3 0F 1A /r"                , "arch": "X64"},
+      {"inst": "bndcn R:bnd, r32/m32"                                       , "op": "RM: F2 0F 1B /r"                , "arch": "X86"},
+      {"inst": "bndcn R:bnd, r64/m64"                                       , "op": "RM: F2 0F 1B /r"                , "arch": "X64"},
+      {"inst": "bndcu R:bnd, r32/m32"                                       , "op": "RM: F2 0F 1A /r"                , "arch": "X86"},
+      {"inst": "bndcu R:bnd, r64/m64"                                       , "op": "RM: F2 0F 1A /r"                , "arch": "X64"},
+      {"inst": "bndldx W:bnd, mib"                                          , "op": "RM: 0F 1A /r"},
+      {"inst": "bndmk W:bnd, mem"                                           , "op": "RM: F3 0F 1B /r"},
+      {"inst": "bndmov W:bnd, bnd/mem"                                      , "op": "RM: 66 0F 1A /r"},
+      {"inst": "bndmov W:bnd/mem, bnd"                                      , "op": "MR: 66 0F 1B /r"},
+      {"inst": "bndstx W:mib, bnd"                                          , "op": "MR: 0F 1B /r"}
     ]},
 
     {"category": "GP GP_EXT", "ext": "TBM", "deprecated": true, "data": [
@@ -901,141 +1120,84 @@
       {"inst": "t1mskc W:r64, r64/m64"                                      , "op": "VM: XOP.LZ.M09.W1 01 /7"}
     ]},
 
-    {"category": "GP GP_EXT", "ext": "MPX", "deprecated": true, "data": [
-      {"inst": "bndcl R:bnd, r32/m32"                                       , "op": "RM: F3 0F 1A /r"                , "arch": "X86"},
-      {"inst": "bndcl R:bnd, r64/m64"                                       , "op": "RM: F3 0F 1A /r"                , "arch": "X64"},
-      {"inst": "bndcn R:bnd, r32/m32"                                       , "op": "RM: F2 0F 1B /r"                , "arch": "X86"},
-      {"inst": "bndcn R:bnd, r64/m64"                                       , "op": "RM: F2 0F 1B /r"                , "arch": "X64"},
-      {"inst": "bndcu R:bnd, r32/m32"                                       , "op": "RM: F2 0F 1A /r"                , "arch": "X86"},
-      {"inst": "bndcu R:bnd, r64/m64"                                       , "op": "RM: F2 0F 1A /r"                , "arch": "X64"},
-      {"inst": "bndldx W:bnd, mib"                                          , "op": "RM: 0F 1A /r"},
-      {"inst": "bndmk W:bnd, mem"                                           , "op": "RM: F3 0F 1B /r"},
-      {"inst": "bndmov W:bnd, bnd/mem"                                      , "op": "RM: 66 0F 1A /r"},
-      {"inst": "bndmov W:bnd/mem, bnd"                                      , "op": "MR: 66 0F 1B /r"},
-      {"inst": "bndstx W:mib, bnd"                                          , "op": "MR: 0F 1B /r"}
-    ]},
-
-    {"category": "GP GP_EXT", "volatile": true, "data": [
-      {"inst": "fxrstor R:mem"                                              , "op": "0F AE /1"                       , "ext": "FXSR"    , "io": "C0=W C1=W C2=W C3=W"},
-      {"inst": "fxrstor64 R:mem"                                            , "op": "REX.W 0F AE /1"                 , "ext": "FXSR"    , "io": "C0=W C1=W C2=W C3=W"},
-      {"inst": "fxsave W:mem"                                               , "op": "0F AE /0"                       , "ext": "FXSR"    , "io": "C0=R C1=R C2=R C3=R"},
-      {"inst": "fxsave64 W:mem"                                             , "op": "REX.W 0F AE /0"                 , "ext": "FXSR"    , "io": "C0=R C1=R C2=R C3=R"},
-      {"inst": "xgetbv W:<edx>, W:<eax>, R:<ecx>"                           , "op": "0F 01 D0"                       , "ext": "XSAVE"   , "io": "XCR=R"},
-      {"inst": "xrstor R:mem, <edx>, <eax>"                                 , "op": "0F AE /5"                       , "ext": "XSAVE"   , "io": "XCR=R"},
-      {"inst": "xrstor64 R:mem, <edx>, <eax>"                               , "op": "REX.W 0F AE /5"                 , "ext": "XSAVE"   , "io": "XCR=R"},
-      {"inst": "xsave W:mem, <edx>, <eax>"                                  , "op": "0F AE /4"                       , "ext": "XSAVE"   , "io": "XCR=R"},
-      {"inst": "xsave64 W:mem, <edx>, <eax>"                                , "op": "REX.W 0F AE /4"                 , "ext": "XSAVE"   , "io": "XCR=R"},
-      {"inst": "xsavec W:mem, <edx>, <eax>"                                 , "op": "0F C7 /4"                       , "ext": "XSAVEC"  , "io": "XCR=R"},
-      {"inst": "xsavec64 W:mem, <edx>, <eax>"                               , "op": "REX.W 0F C7 /4"                 , "ext": "XSAVEC"  , "io": "XCR=R"},
-      {"inst": "xsaveopt W:mem, <edx>, <eax>"                               , "op": "0F AE /6"                       , "ext": "XSAVEOPT", "io": "XCR=R"},
-      {"inst": "xsaveopt64 W:mem, <edx>, <eax>"                             , "op": "REX.W 0F AE /6"                 , "ext": "XSAVEOPT", "io": "XCR=R"}
-    ]},
-
-    {"category": "GP GP_EXT", "volatile": true, "data": [
-      {"inst": "incsspd r32"                                                , "op": "F3 0F AE /5"                    , "ext": "CET_SS"},
-      {"inst": "incsspq r64"                                                , "op": "REX.W F3 0F AE /5"              , "ext": "CET_SS"},
-      {"inst": "monitorx R:<mem(ds:zax)>, R:<ecx>, R:<edx>"                 , "op": "0F 01 FA"                       , "ext": "MONITORX"},
-      {"inst": "mwaitx R:<eax>, R:<ecx>, R:<ebx>"                           , "op": "0F 01 FB"                       , "ext": "MONITORX"},
-      {"inst": "rdsspd W:r32"                                               , "op": "F3 0F 1E /1"                    , "ext": "CET_SS"},
-      {"inst": "rdsspq W:r64"                                               , "op": "REX.W F3 0F 1E /1"              , "ext": "CET_SS"},
-      {"inst": "rstorssp R:m64"                                             , "op": "F3 0F 01 /5"                    , "ext": "CET_SS"  , "io": "OF=0 SF=0 ZF=0 AF=0 PF=0 CF=W"},
-      {"inst": "saveprevssp"                                                , "op": "F3 0F 01 EA"                    , "ext": "CET_SS"  , "io": "OF=0 SF=0 ZF=0 AF=0 PF=0 CF=W"},
-      {"inst": "tpause R:r32, <edx>, <eax>"                                 , "op": "66 0F AE /6"                    , "ext": "WAITPKG" , "io": "OF=0 SF=0 ZF=0 AF=0 PF=0 CF=W"},
-      {"inst": "umonitor R:mem(ds:r32)"                                     , "op": "F3 0F AE /6"                    , "ext": "WAITPKG" , "arch": "X86"},
-      {"inst": "umonitor R:mem(ds:r64)"                                     , "op": "F3 0F AE /6"                    , "ext": "WAITPKG" , "arch": "X64"},
-      {"inst": "umwait R:r32, <edx>, <eax>"                                 , "op": "F2 0F AE /6"                    , "ext": "WAITPKG" , "io": "OF=0 SF=0 ZF=0 AF=0 PF=0 CF=W"}
-    ]},
-
-    {"category": "GP GP_EXT", "ext": "LWP", "volatile": true, "data": [
-      {"inst": "llwpcb R:r32"                                               , "op": "XOP.L0.P0.M09.W0 12 /0"},
-      {"inst": "llwpcb R:r64"                                               , "op": "XOP.L0.P0.M09.W1 12 /0"},
-      {"inst": "lwpins R:r32, R:r32/m32, id/ud"                             , "op": "VM: XOP.L0.P0.M0A.W0 12 /0 id"},
-      {"inst": "lwpins R:r64, R:r32/m32, id/ud"                             , "op": "VM: XOP.L0.P0.M0A.W1 12 /0 id"},
-      {"inst": "lwpval R:r32, R:r32/m32, id/ud"                             , "op": "VM: XOP.L0.P0.M0A.W0 12 /1 id"},
-      {"inst": "lwpval R:r64, R:r32/m32, id/ud"                             , "op": "VM: XOP.L0.P0.M0A.W1 12 /1 id"},
-      {"inst": "slwpcb W:r32"                                               , "op": "XOP.L0.P0.M09.W0 12 /1"},
-      {"inst": "slwpcb W:r64"                                               , "op": "XOP.L0.P0.M09.W1 12 /1"}
-    ]},
-
-    {"category": "GP GP_EXT", "ext": "FSGSBASE", "arch": "X64", "volatile": true, "data": [
-      {"inst": "rdfsbase W:r32"                                             , "op": "F3 0F AE /0"},
-      {"inst": "rdfsbase W:r64"                                             , "op": "REX.W F3 0F AE /0"},
-      {"inst": "rdgsbase W:r32"                                             , "op": "F3 0F AE /1"},
-      {"inst": "rdgsbase W:r64"                                             , "op": "REX.W F3 0F AE /1"},
-      {"inst": "wrfsbase R:r32"                                             , "op": "F3 0F AE /2"},
-      {"inst": "wrfsbase R:r64"                                             , "op": "REX.W F3 0F AE /2"},
-      {"inst": "wrgsbase R:r32"                                             , "op": "F3 0F AE /3"},
-      {"inst": "wrgsbase R:r64"                                             , "op": "REX.W F3 0F AE /3"}
-    ]},
-
-    {"category": "GP GP_EXT", "ext": "UINTR", "arch": "X64", "volatile": true, "data": [
-      {"inst": "uiret"                                                      , "op": "F3 0F 01 EC"},
-      {"inst": "clui"                                                       , "op": "F3 0F 01 EE"},
-      {"inst": "stui"                                                       , "op": "F3 0F 01 EF"},
-      {"inst": "testui"                                                     , "op": "F3 0F 01 ED"                    , "io": "OF=0 SF=0 ZF=0 AF=0 PF=0 CF=W"},
-      {"inst": "senduipi R:r64"                                             , "op": "R: F3 0F C7 /6"}
-    ]},
-
-    {"category": "GP GP_EXT", "ext": "PCONFIG", "volatile": true, "data": [
-      {"inst": "pconfig"                                                    , "op": "0F 01 C5"}
-    ]},
-
-    {"category": "GP GP_EXT", "ext": "TSE", "arch": "X64", "volatile": true, "data": [
-      {"inst": "pbndkb"                                                     , "op": "0F 01 C7"}
-    ]},
-
-    {"category": "GP GP_EXT", "volatile": true, "data": [
-      {"inst": "xabort ib/ub"                                               , "op": "C6 /7 ib"                       , "ext": "RTM"},
-      {"inst": "xbegin rel16"                                               , "op": "66 C7 /7 cw"                    , "ext": "RTM"},
-      {"inst": "xbegin rel32"                                               , "op": "C7 /7 cd"                       , "ext": "RTM"},
-      {"inst": "xend"                                                       , "op": "0F 01 D5"                       , "ext": "RTM"},
-      {"inst": "xresldtrk"                                                  , "op": "F2 0F 01 E9"                    , "ext": "TSXLDTRK"},
-      {"inst": "xsusldtrk"                                                  , "op": "F2 0F 01 E8"                    , "ext": "TSXLDTRK"},
-      {"inst": "xtest"                                                      , "op": "0F 01 D6"                       , "ext": "TSX"     , "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=0"}
-    ]},
-
     {"category": "GP", "volatile": true, "privilege": "L0", "data": [
-      {"inst": "clrssbsy R:m64"                                             , "op": "F3 0F AE /6"                    , "ext": "CET_SS"  , "io": "OF=0 SF=0 ZF=0 AF=0 PF=0 CF=W"},
       {"inst": "clts"                                                       , "op": "0F 06"},
-      {"inst": "endbr32"                                                    , "op": "F3 0F 1E FB"                    , "ext": "CET_IBT"},
-      {"inst": "endbr64"                                                    , "op": "F3 0F 1E FA"                    , "ext": "CET_IBT"},
-      {"inst": "getsec <eax>"                                               , "op": "0F 37"                          , "ext": "SMX"},
       {"inst": "hlt"                                                        , "op": "F4"},
-      {"inst": "hreset ib/ub, W:<eax>"                                      , "op": "F3 0F 3A F0 /0 ib"              , "ext": "HRESET"},
-      {"inst": "invd"                                                       , "op": "0F 08"                          , "ext": "I486" },
-      {"inst": "invlpg R:mem"                                               , "op": "0F 01 /7"                       , "ext": "I486"},
-      {"inst": "invpcid R:r32, R:m128"                                      , "op": "RM: 66 0F 38 82 /r"             , "ext": "I486"    , "arch": "X86"},
-      {"inst": "invpcid R:r64, R:m128"                                      , "op": "RM: 66 0F 38 82 /r"             , "ext": "I486"    , "arch": "X64"},
       {"inst": "lgdt R:mem"                                                 , "op": "0F 01 /2"},
       {"inst": "lidt R:mem"                                                 , "op": "0F 01 /3"},
       {"inst": "lldt R:r16/m16"                                             , "op": "0F 00 /2"},
       {"inst": "lmsw R:r16/m16"                                             , "op": "0F 01 /6"},
       {"inst": "ltr R:r16/m16"                                              , "op": "0F 00 /3"},
-      {"inst": "monitor R:<mem(ds:zax)>, R:<ecx>, R:<edx>"                  , "op": "0F 01 C8"                       , "ext": "MONITOR"},
-      {"inst": "mwait R:<eax>, R:<ecx>"                                     , "op": "0F 01 C9"                       , "ext": "MONITOR"},
       {"inst": "rdpmc W:<edx>, W:<eax>, R:<ecx>"                            , "op": "0F 33"},
-      {"inst": "rdmsr W:<edx>, W:<eax>, R:<ecx>"                            , "op": "0F 32"                          , "ext": "MSR"     , "io": "MSR=R"},
-      {"inst": "rdmsrlist R:<mem(ds:rsi)>, W:<mem(ds:rdi)>, X:<rcx>"        , "op": "F2 0F 01 C6"                    , "ext": "MSRLIST" , "arch": "X64", "io": "MSR=R"},
-      {"inst": "setssbsy"                                                   , "op": "F3 0F 01 E8"                    , "ext": "CET_SS"},
       {"inst": "swapgs"                                                     , "op": "0F 01 F8"                       , "arch": "X64"},
       {"inst": "sysexit"                                                    , "op": "0F 35"},
       {"inst": "sysexitq"                                                   , "op": "REX.W 0F 35"},
       {"inst": "sysret"                                                     , "op": "0F 07"                          , "arch": "X64"},
-      {"inst": "sysretq"                                                    , "op": "REX.W 0F 07"                    , "arch": "X64"},
-      {"inst": "wbinvd"                                                     , "op": "0F 09"                          , "ext": "I486"},
-      {"inst": "wbnoinvd"                                                   , "op": "F3 0F 09"                       , "ext": "WBNOINVD"},
-      {"inst": "wrmsrns R:<edx>, R:<eax>, R:<ecx>"                          , "op": "0F 01 C6"                       , "ext": "WRMSRNS" , "io": "MSR=W"},
-      {"inst": "wrmsr R:<edx>, R:<eax>, R:<ecx>"                            , "op": "0F 30"                          , "ext": "MSR"     , "io": "MSR=W"},
-      {"inst": "wrmsrlist R:<mem(ds:rsi)>, R:<mem(ds:rdi)>, X:<rcx>"        , "op": "F3 0F 01 C6"                    , "ext": "MSRLIST" , "arch": "X64", "io": "MSR=W"},
-      {"inst": "wrssd W:r32/m32, r32"                                       , "op": "MR: 0F 38 F6 /r"                , "ext": "CET_SS"},
-      {"inst": "wrssq W:r64/m64, r64"                                       , "op": "MR: REX.W 0F 38 F6 /r"          , "ext": "CET_SS"},
-      {"inst": "xrstors R:mem, <edx>, <eax>"                                , "op": "0F C7 /3"                       , "ext": "XSAVES"  , "io": "XCR=R"},
-      {"inst": "xrstors64 R:mem, <edx>, <eax>"                              , "op": "REX.W 0F C7 /3"                 , "ext": "XSAVES"  , "io": "XCR=R"},
-      {"inst": "wrussd W:r32/m32, r32"                                      , "op": "MR: 66 0F 38 F5 /r"             , "ext": "CET_SS"},
-      {"inst": "wrussq W:r64/m64, r64"                                      , "op": "MR: REX.W 66 0F 38 F5 /r"       , "ext": "CET_SS"},
-      {"inst": "xsaves W:mem, <edx>, <eax>"                                 , "op": "0F C7 /5"                       , "ext": "XSAVES"  , "io": "XCR=R"},
-      {"inst": "xsaves64 W:mem, <edx>, <eax>"                               , "op": "REX.W 0F C7 /5"                 , "ext": "XSAVES"  , "io": "XCR=R"},
-      {"inst": "xsetbv R:<edx>, R:<eax>, R:<ecx>"                           , "op": "0F 01 D1"                       , "ext": "XSAVE"   , "io": "XCR=W"}
+      {"inst": "sysretq"                                                    , "op": "REX.W 0F 07"                    , "arch": "X64"}
+    ]},
+
+    {"category": "GP", "ext": "I486", "volatile": true, "privilege": "L0", "data": [
+      {"inst": "invd"                                                       , "op": "0F 08"},
+      {"inst": "invlpg R:mem"                                               , "op": "0F 01 /7"},
+      {"inst": "invpcid R:r32, R:m128"                                      , "op": "RM: 66 0F 38 82 /r"             , "arch": "X86"},
+      {"inst": "invpcid R:r64, R:m128"                                      , "op": "RM: 66 0F 38 82 /r"             , "arch": "X64"},
+      {"inst": "wbinvd"                                                     , "op": "0F 09"}
+    ]},
+
+    {"category": "GP GP_EXT", "ext": "CET_IBT", "volatile": true, "privilege": "L0", "data": [
+      {"inst": "endbr32"                                                    , "op": "F3 0F 1E FB"},
+      {"inst": "endbr64"                                                    , "op": "F3 0F 1E FA"}
+    ]},
+
+    {"category": "GP GP_EXT", "ext": "CET_SS", "volatile": true, "privilege": "L0", "data": [
+      {"inst": "clrssbsy R:m64"                                             , "op": "F3 0F AE /6"                    , "io": "OF=0 SF=0 ZF=0 AF=0 PF=0 CF=W"},
+      {"inst": "setssbsy"                                                   , "op": "F3 0F 01 E8"},
+      {"inst": "wrssd W:r32/m32, r32"                                       , "op": "MR: 0F 38 F6 /r"},
+      {"inst": "wrssq W:r64/m64, r64"                                       , "op": "MR: REX.W 0F 38 F6 /r"},
+      {"inst": "wrussd W:r32/m32, r32"                                      , "op": "MR: 66 0F 38 F5 /r"},
+      {"inst": "wrussq W:r64/m64, r64"                                      , "op": "MR: REX.W 66 0F 38 F5 /r"}
+    ]},
+
+    {"category": "GP GP_EXT", "ext": "HRESET", "volatile": true, "privilege": "L0", "data": [
+      {"inst": "hreset ib/ub, W:<eax>"                                      , "op": "F3 0F 3A F0 /0 ib"}
+    ]},
+
+    {"category": "GP GP_EXT", "ext": "MONITOR", "volatile": true, "privilege": "L0", "data": [
+      {"inst": "monitor R:<mem(ds:zax)>, R:<ecx>, R:<edx>"                  , "op": "0F 01 C8"},
+      {"inst": "mwait R:<eax>, R:<ecx>"                                     , "op": "0F 01 C9"}
+    ]},
+
+    {"category": "GP GP_EXT", "ext": "MSR", "volatile": true, "privilege": "L0", "data": [
+      {"inst": "rdmsr W:<edx>, W:<eax>, R:<ecx>"                            , "op": "0F 32"                          , "io": "MSR=R"},
+      {"inst": "wrmsr R:<edx>, R:<eax>, R:<ecx>"                            , "op": "0F 30"                          , "io": "MSR=W"}
+    ]},
+
+    {"category": "GP GP_EXT", "ext": "MSRLIST", "arch": "X64", "volatile": true, "privilege": "L0", "data": [
+      {"inst": "rdmsrlist R:<mem(ds:rsi)>, W:<mem(ds:rdi)>, X:<rcx>"        , "op": "F2 0F 01 C6"                    , "io": "MSR=R"},
+      {"inst": "wrmsrlist R:<mem(ds:rsi)>, R:<mem(ds:rdi)>, X:<rcx>"        , "op": "F3 0F 01 C6"                    , "io": "MSR=W"}
+    ]},
+
+    {"category": "GP GP_EXT", "ext": "SMX", "volatile": true, "privilege": "L0", "data": [
+      {"inst": "getsec <eax>"                                               , "op": "0F 37"}
+    ]},
+
+    {"category": "GP GP_EXT", "ext": "WBNOINVD", "volatile": true, "privilege": "L0", "data": [
+      {"inst": "wbnoinvd"                                                   , "op": "F3 0F 09"}
+    ]},
+
+    {"category": "GP GP_EXT", "ext": "WRMSRNS", "volatile": true, "privilege": "L0", "data": [
+      {"inst": "wrmsrns R:<edx>, R:<eax>, R:<ecx>"                          , "op": "0F 01 C6"                       , "io": "MSR=W"}
+    ]},
+
+    {"category": "GP GP_EXT", "ext": "XSAVE", "volatile": true, "privilege": "L0", "data": [
+      {"inst": "xsetbv R:<edx>, R:<eax>, R:<ecx>"                           , "op": "0F 01 D1"                       , "io": "XCR=W"}
+    ]},
+
+    {"category": "GP GP_EXT", "ext": "XSAVES", "volatile": true, "privilege": "L0", "data": [
+      {"inst": "xrstors R:mem, <edx>, <eax>"                                , "op": "0F C7 /3"                       , "io": "XCR=R"},
+      {"inst": "xrstors64 R:mem, <edx>, <eax>"                              , "op": "REX.W 0F C7 /3"                 , "io": "XCR=R"},
+      {"inst": "xsaves W:mem, <edx>, <eax>"                                 , "op": "0F C7 /5"                       , "io": "XCR=R"},
+      {"inst": "xsaves64 W:mem, <edx>, <eax>"                               , "op": "REX.W 0F C7 /5"                 , "io": "XCR=R"}
     ]},
 
     {"category": "VIRTUALIZATION", "volatile": true, "data": [
@@ -1108,14 +1270,6 @@
       {"inst": "fbstp W:m80bcd"                                             , "op": "DF /6"                          , "io": "C0=U C1=W C2=U C3=U", "fpuStack": "pop"},
       {"inst": "fchs"                                                       , "op": "D9 E0"                          , "io": "C0=U C1=0 C2=U C3=U"},
       {"inst": "fclex"                                                      , "op": "9B DB E2"                       , "io": "C0=U C1=U C2=U C3=U"},
-      {"inst": "fcmovb st(i)"                                               , "op": "DA C0+i"                        , "io": "C0=U C1=W C2=U C3=U CF=R"     , "ext": "CMOV"},
-      {"inst": "fcmovbe st(i)"                                              , "op": "DA D0+i"                        , "io": "C0=U C1=W C2=U C3=U CF=R ZF=R", "ext": "CMOV"},
-      {"inst": "fcmove st(i)"                                               , "op": "DA C8+i"                        , "io": "C0=U C1=W C2=U C3=U ZF=R"     , "ext": "CMOV"},
-      {"inst": "fcmovnb st(i)"                                              , "op": "DB C0+i"                        , "io": "C0=U C1=W C2=U C3=U CF=R"     , "ext": "CMOV"},
-      {"inst": "fcmovnbe st(i)"                                             , "op": "DB D0+i"                        , "io": "C0=U C1=W C2=U C3=U CF=R ZF=R", "ext": "CMOV"},
-      {"inst": "fcmovne st(i)"                                              , "op": "DB C8+i"                        , "io": "C0=U C1=W C2=U C3=U ZF=R"     , "ext": "CMOV"},
-      {"inst": "fcmovnu st(i)"                                              , "op": "DB D8+i"                        , "io": "C0=U C1=W C2=U C3=U PF=R"     , "ext": "CMOV"},
-      {"inst": "fcmovu st(i)"                                               , "op": "DA D8+i"                        , "io": "C0=U C1=W C2=U C3=U PF=R"     , "ext": "CMOV"},
       {"inst": "fcom"                                                       , "op": "D8 D1"                          , "io": "C0=W C1=0 C2=W C3=W"},
       {"inst": "fcom R:m32fp"                                               , "op": "D8 /2"                          , "io": "C0=W C1=0 C2=W C3=W"},
       {"inst": "fcom R:m64fp"                                               , "op": "DC /2"                          , "io": "C0=W C1=0 C2=W C3=W"},
@@ -1164,9 +1318,6 @@
       {"inst": "fistp W:m16int"                                             , "op": "DF /3"                          , "io": "C0=U C1=W C2=U C3=U", "fpuStack": "pop"},
       {"inst": "fistp W:m32int"                                             , "op": "DB /3"                          , "io": "C0=U C1=W C2=U C3=U", "fpuStack": "pop"},
       {"inst": "fistp W:m64int"                                             , "op": "DF /7"                          , "io": "C0=U C1=W C2=U C3=U", "fpuStack": "pop"},
-      {"inst": "fisttp W:m16int"                                            , "op": "DF /1"                          , "io": "C0=U C1=0 C2=U C3=U", "fpuStack": "pop", "ext": "SSE3"},
-      {"inst": "fisttp W:m32int"                                            , "op": "DB /1"                          , "io": "C0=U C1=0 C2=U C3=U", "fpuStack": "pop", "ext": "SSE3"},
-      {"inst": "fisttp W:m64int"                                            , "op": "DD /1"                          , "io": "C0=U C1=0 C2=U C3=U", "fpuStack": "pop", "ext": "SSE3"},
       {"inst": "fisub R:m16int"                                             , "op": "DE /4"                          , "io": "C0=U C1=W C2=U C3=U"},
       {"inst": "fisub R:m32int"                                             , "op": "DA /4"                          , "io": "C0=U C1=W C2=U C3=U"},
       {"inst": "fisubr R:m16int"                                            , "op": "DE /5"                          , "io": "C0=U C1=W C2=U C3=U"},
@@ -1249,6 +1400,23 @@
       {"inst": "fyl2xp1"                                                    , "op": "D9 F9"                          , "io": "C0=U C1=W C2=U C3=U", "fpuStack": "pop"}
     ]},
 
+    {"category": "FPU", "ext": "FPU CMOV", "data": [
+      {"inst": "fcmovb st(i)"                                               , "op": "DA C0+i"                        , "io": "C0=U C1=W C2=U C3=U CF=R"     },
+      {"inst": "fcmovbe st(i)"                                              , "op": "DA D0+i"                        , "io": "C0=U C1=W C2=U C3=U CF=R ZF=R"},
+      {"inst": "fcmove st(i)"                                               , "op": "DA C8+i"                        , "io": "C0=U C1=W C2=U C3=U ZF=R"     },
+      {"inst": "fcmovnb st(i)"                                              , "op": "DB C0+i"                        , "io": "C0=U C1=W C2=U C3=U CF=R"     },
+      {"inst": "fcmovnbe st(i)"                                             , "op": "DB D0+i"                        , "io": "C0=U C1=W C2=U C3=U CF=R ZF=R"},
+      {"inst": "fcmovne st(i)"                                              , "op": "DB C8+i"                        , "io": "C0=U C1=W C2=U C3=U ZF=R"     },
+      {"inst": "fcmovnu st(i)"                                              , "op": "DB D8+i"                        , "io": "C0=U C1=W C2=U C3=U PF=R"     },
+      {"inst": "fcmovu st(i)"                                               , "op": "DA D8+i"                        , "io": "C0=U C1=W C2=U C3=U PF=R"     }
+    ]},
+
+    {"category": "FPU", "ext": "FPU SSE3", "data": [
+      {"inst": "fisttp W:m16int"                                            , "op": "DF /1"                          , "io": "C0=U C1=0 C2=U C3=U", "fpuStack": "pop"},
+      {"inst": "fisttp W:m32int"                                            , "op": "DB /1"                          , "io": "C0=U C1=0 C2=U C3=U", "fpuStack": "pop"},
+      {"inst": "fisttp W:m64int"                                            , "op": "DD /1"                          , "io": "C0=U C1=0 C2=U C3=U", "fpuStack": "pop"}
+    ]},
+
     {"category": "MMX STATE", "deprecated": true, "volatile": true, "data": [
       {"inst": "emms"                                                       , "op": "0F 77"                          , "ext": "MMX"},
       {"inst": "femms"                                                      , "op": "0F 0E"                          , "ext": "3DNOW"}
@@ -1649,7 +1817,7 @@
       {"inst": "movntdqa W:xmm, m128"                                       , "op": "RM: 66 0F 38 2A /r"},
       {"inst": "mpsadbw X:xmm, xmm/m128, ib/ub"                             , "op": "RM: 66 0F 3A 42 /r ib"},
       {"inst": "packusdw X:xmm, xmm/m128"                                   , "op": "RM: 66 0F 38 2B /r"},
-      {"inst": "pblendvb X:xmm, xmm/m128, <xmm0>"                           , "op": "RM: 66 0F E0 /r"},
+      {"inst": "pblendvb X:xmm, xmm/m128, <xmm0>"                           , "op": "RM: 66 0F 38 10 /r"},
       {"inst": "pblendw X:xmm, xmm/m128, ib/ub"                             , "op": "RM: 66 0F 3A 0E /r ib"},
       {"inst": "pcmpeqq X:~xmm, ~xmm/m128"                                  , "op": "RM: 66 0F 38 29 /r"},
       {"inst": "pextrb W:r32[7:0]/m8, xmm, ib/ub"                           , "op": "MR: 66 0F 3A 14 /r ib"},
@@ -1707,10 +1875,6 @@
       {"inst": "insertq X:xmm, xmm, ib/ub, ib/ub"                           , "op": "RM: F2 0F 78 /r ib ib"}
     ]},
 
-    {"category": "SSE SIMD", "ext": "PCLMULQDQ", "data": [
-      {"inst": "pclmulqdq X:xmm, xmm/m128, ib/ub"                           , "op": "RM: 66 0F 3A 44 /r ib"}
-    ]},
-
     {"category": "SSE SIMD CRYPTO_HASH", "ext": "AESNI", "data": [
       {"inst": "aesdec X:xmm, xmm/m128"                                     , "op": "RM: 66 0F 38 DE /r"},
       {"inst": "aesdeclast X:xmm, xmm/m128"                                 , "op": "RM: 66 0F 38 DF /r"},
@@ -1720,6 +1884,16 @@
       {"inst": "aeskeygenassist W:xmm, xmm/m128, ib/ub"                     , "op": "RM: 66 0F 3A DF /r ib"}
     ]},
 
+    {"category": "SSE SIMD", "ext": "GFNI", "data": [
+      {"inst": "gf2p8affineinvqb X:xmm, xmm/m128, ib/ub"                    , "op": "RM: 66 0F 3A CF /r ib"},
+      {"inst": "gf2p8affineqb X:xmm, xmm/m128, ib/ub"                       , "op": "RM: 66 0F 3A CE /r ib"},
+      {"inst": "gf2p8mulb X:xmm, xmm/m128"                                  , "op": "RM: 66 0F 38 CF /r"}
+    ]},
+
+    {"category": "SSE SIMD", "ext": "PCLMULQDQ", "data": [
+      {"inst": "pclmulqdq X:xmm, xmm/m128, ib/ub"                           , "op": "RM: 66 0F 3A 44 /r ib"}
+    ]},
+
     {"category": "SSE SIMD CRYPTO_HASH", "ext": "SHA", "data": [
       {"inst": "sha1msg1 xmm, xmm/m128"                                     , "op": "RM: 0F 38 C9 /r"},
       {"inst": "sha1msg2 xmm, xmm/m128"                                     , "op": "RM: 0F 38 CA /r"},
@@ -1730,12 +1904,6 @@
       {"inst": "sha256rnds2 xmm, xmm/m128, <xmm0>"                          , "op": "RM: 0F 38 CB /r"}
     ]},
 
-    {"category": "SSE SIMD", "ext": "GFNI", "data": [
-      {"inst": "gf2p8affineinvqb X:xmm, xmm/m128, ib/ub"                    , "op": "RM: 66 0F 3A CF /r ib"},
-      {"inst": "gf2p8affineqb X:xmm, xmm/m128, ib/ub"                       , "op": "RM: 66 0F 3A CE /r ib"},
-      {"inst": "gf2p8mulb X:xmm, xmm/m128"                                  , "op": "RM: 66 0F 38 CF /r"}
-    ]},
-
     {"category": "AVX STATE", "ext": "AVX", "data": [
       {"inst": "vldmxcsr R:m32"                                             , "op": "VEX.LZ.0F.WIG AE /2", "io": "MXCSR=W"},
       {"inst": "vstmxcsr W:m32"                                             , "op": "VEX.LZ.0F.WIG AE /3", "io": "MXCSR=R"},
@@ -2626,7 +2794,7 @@
     {"category": "AVX SIMD", "ext": "AVX SM3", "data": [
       {"inst": "vsm3msg1 X:xmm, xmm, xmm/m128"                              , "op": "RVM: VEX.128.NP.0F38.W0 DA /r"},
       {"inst": "vsm3msg2 X:xmm, xmm, xmm/m128"                              , "op": "RVM: VEX.128.66.0F38.W0 DA /r"},
-      {"inst": "vsm3rnds2 X:xmm, xmm, xmm/m128, ib/ub"                      , "op": "RVM: VEX.128.66.0F3A.W0 DE /r /ib"}
+      {"inst": "vsm3rnds2 X:xmm, xmm, xmm/m128, ib/ub"                      , "op": "RVM: VEX.128.66.0F3A.W0 DE /r ib"}
     ]},
 
     {"category": "AVX SIMD", "ext": "AVX SM4", "data": [

deps/asmjit/db/x86.js

@@ -1,7 +1,7 @@
 // This file is part of AsmJit project <https://asmjit.com>
 //
 // See asmjit.h or LICENSE.md for license and copyright information
-// SPDX-License-Identifier: Zlib
+// SPDX-License-Identifier: (Zlib or Unlicense)
 
 (function($scope, $as) {
 "use strict";

deps/asmjit/src/asmjit/a64.h

@@ -26,16 +26,16 @@
 //!
 //! ### Register Operands
 //!
-//!   - \ref arm::Reg - Base class for any AArch32/AArch64 register.
-//!     - \ref arm::Gp - General purpose register:
-//!       - \ref arm::GpW - 32-bit register.
-//!       - \ref arm::GpX - 64-bit register.
-//!     - \ref arm::Vec - Vector (SIMD) register:
-//!       - \ref arm::VecB - 8-bit SIMD register.
-//!       - \ref arm::VecH - 16-bit SIMD register.
-//!       - \ref arm::VecS - 32-bit SIMD register.
-//!       - \ref arm::VecD - 64-bit SIMD register.
-//!       - \ref arm::VecV - 128-bit SIMD register.
+//!   - \ref arm::Reg - Base class of all AArch32/AArch64 registers.
+//!     - \ref a64::Gp - General purpose register (AArch64):
+//!       - \ref a64::GpW - 32-bit general purpose register (AArch64).
+//!       - \ref a64::GpX - 64-bit general purpose register (AArch64).
+//!     - \ref a64::Vec - Vector (SIMD) register:
+//!       - \ref a64::VecB - 8-bit SIMD register.
+//!       - \ref a64::VecH - 16-bit SIMD register.
+//!       - \ref a64::VecS - 32-bit SIMD register.
+//!       - \ref a64::VecD - 64-bit SIMD register.
+//!       - \ref a64::VecV - 128-bit SIMD register.
 //!
 //! ### Memory Operands
 //!

deps/asmjit/src/asmjit/arm.h

@@ -18,14 +18,16 @@
 //!
 //! ### Emitters
 //!
-//!   - AArch64
+//!   - AArch32
 //!     - \ref a32::Assembler - AArch32 assembler (must read, provides examples).
-//!     - \ref a64::Assembler - AArch64 assembler (must read, provides examples).
 //!     - \ref a32::Builder - AArch32 builder.
-//!     - \ref a64::Builder - AArch64 builder.
 //!     - \ref a32::Compiler - AArch32 compiler.
-//!     - \ref a64::Compiler - AArch64 compiler.
 //!     - \ref a32::Emitter - AArch32 emitter (abstract).
+//!
+//!   - AArch64
+//!     - \ref a64::Assembler - AArch64 assembler (must read, provides examples).
+//!     - \ref a64::Builder - AArch64 builder.
+//!     - \ref a64::Compiler - AArch64 compiler.
 //!     - \ref a64::Emitter - AArch64 emitter (abstract).
 //!
 //! ### Supported Instructions
@@ -46,16 +48,22 @@
 //!
 //! ### Register Operands
 //!
-//!   - \ref arm::Reg - Base class for any AArch32/AArch64 register.
-//!     - \ref arm::Gp - General purpose register:
-//!       - \ref arm::GpW - 32-bit register.
-//!       - \ref arm::GpX - 64-bit register (AArch64 only).
-//!     - \ref arm::Vec - Vector (SIMD) register:
-//!       - \ref arm::VecB - 8-bit SIMD register (AArch64 only).
-//!       - \ref arm::VecH - 16-bit SIMD register (AArch64 only).
-//!       - \ref arm::VecS - 32-bit SIMD register.
-//!       - \ref arm::VecD - 64-bit SIMD register.
-//!       - \ref arm::VecV - 128-bit SIMD register.
+//!   - \ref arm::Reg - Base class of all AArch32/AArch64 registers.
+//!     - \ref a32::Gp - 32-bit general purpose register used by AArch32:
+//!     - \ref a64::Gp - 32-bit or 64-bit general purpose register used by AArch64:
+//!       - \ref a64::GpW - 32-bit register (AArch64).
+//!       - \ref a64::GpX - 64-bit register (AArch64).
+//!     - \ref arm::BaseVec - Base vector (SIMD) register.
+//!       - \ref a32::Vec - Vector (SIMD) register (AArch32):
+//!         - \ref a32::VecS - 32-bit SIMD register (AArch32).
+//!         - \ref a32::VecD - 64-bit SIMD register (AArch32).
+//!         - \ref a32::VecV - 128-bit SIMD register (AArch32).
+//!       - \ref a64::Vec - Vector (SIMD) register (AArch64):
+//!         - \ref a64::VecB - 8-bit SIMD register (AArch64).
+//!         - \ref a64::VecH - 16-bit SIMD register (AArch64).
+//!         - \ref a64::VecS - 32-bit SIMD register (AArch64).
+//!         - \ref a64::VecD - 64-bit SIMD register (AArch64).
+//!         - \ref a64::VecV - 128-bit SIMD register (AArch64).
 //!
 //! ### Memory Operands
 //!

deps/asmjit/src/asmjit/arm/a64assembler.cpp

@@ -21,12 +21,16 @@
 
 ASMJIT_BEGIN_SUB_NAMESPACE(a64)
 
+// a64::Assembler - Utils
+// ======================
+
+static ASMJIT_FORCE_INLINE constexpr uint32_t diff(RegType a, RegType b) noexcept { return uint32_t(a) - uint32_t(b); }
+static ASMJIT_FORCE_INLINE constexpr uint32_t diff(VecElementType elementType, VecElementType baseType) noexcept { return uint32_t(elementType) - uint32_t(baseType); }
+
 // a64::Assembler - Cond
 // =====================
 
-static inline uint32_t condCodeToOpcodeCond(uint32_t cond) noexcept {
-  return (uint32_t(cond) - 2u) & 0xFu;
-}
+static inline uint32_t condCodeToOpcodeCond(uint32_t cond) noexcept { return (uint32_t(cond) - 2u) & 0xFu; }
 
 // a64::Assembler - Bits
 // =====================
@@ -49,10 +53,6 @@ static constexpr uint32_t kWX = InstDB::kWX;
 static const uint8_t armShiftOpToLdStOptMap[] = { ASMJIT_LOOKUP_TABLE_16(VALUE, 0) };
 #undef VALUE
 
-static inline constexpr uint32_t diff(RegType a, RegType b) noexcept {
-  return uint32_t(a) - uint32_t(b);
-}
-
 // asmjit::a64::Assembler - SizeOp
 // ===============================
 
@@ -118,25 +118,25 @@ struct SizeOpTable {
 };
 
 #define VALUE_BIN(x) { \
-  x == (((uint32_t(RegType::kARM_VecD) - uint32_t(RegType::kARM_VecB)) << 3) | (Vec::kElementTypeNone)) ? SizeOp::k00  : \
-  x == (((uint32_t(RegType::kARM_VecV) - uint32_t(RegType::kARM_VecB)) << 3) | (Vec::kElementTypeNone)) ? SizeOp::k00Q : \
-  x == (((uint32_t(RegType::kARM_VecD) - uint32_t(RegType::kARM_VecB)) << 3) | (Vec::kElementTypeB   )) ? SizeOp::k00  : \
-  x == (((uint32_t(RegType::kARM_VecV) - uint32_t(RegType::kARM_VecB)) << 3) | (Vec::kElementTypeB   )) ? SizeOp::k00Q : SizeOp::kInvalid \
+  x == (((uint32_t(RegType::kARM_VecD) - uint32_t(RegType::kARM_VecB)) << 3) | uint32_t(VecElementType::kNone)) ? SizeOp::k00  : \
+  x == (((uint32_t(RegType::kARM_VecV) - uint32_t(RegType::kARM_VecB)) << 3) | uint32_t(VecElementType::kNone)) ? SizeOp::k00Q : \
+  x == (((uint32_t(RegType::kARM_VecD) - uint32_t(RegType::kARM_VecB)) << 3) | uint32_t(VecElementType::kB   )) ? SizeOp::k00  : \
+  x == (((uint32_t(RegType::kARM_VecV) - uint32_t(RegType::kARM_VecB)) << 3) | uint32_t(VecElementType::kB   )) ? SizeOp::k00Q : SizeOp::kInvalid \
 }
 
 #define VALUE_ANY(x) { \
-  x == (((uint32_t(RegType::kARM_VecB) - uint32_t(RegType::kARM_VecB)) << 3) | (Vec::kElementTypeNone)) ? SizeOp::k00S : \
-  x == (((uint32_t(RegType::kARM_VecH) - uint32_t(RegType::kARM_VecB)) << 3) | (Vec::kElementTypeNone)) ? SizeOp::k01S : \
-  x == (((uint32_t(RegType::kARM_VecS) - uint32_t(RegType::kARM_VecB)) << 3) | (Vec::kElementTypeNone)) ? SizeOp::k10S : \
-  x == (((uint32_t(RegType::kARM_VecD) - uint32_t(RegType::kARM_VecB)) << 3) | (Vec::kElementTypeNone)) ? SizeOp::k11S : \
-  x == (((uint32_t(RegType::kARM_VecD) - uint32_t(RegType::kARM_VecB)) << 3) | (Vec::kElementTypeB   )) ? SizeOp::k00  : \
-  x == (((uint32_t(RegType::kARM_VecV) - uint32_t(RegType::kARM_VecB)) << 3) | (Vec::kElementTypeB   )) ? SizeOp::k00Q : \
-  x == (((uint32_t(RegType::kARM_VecD) - uint32_t(RegType::kARM_VecB)) << 3) | (Vec::kElementTypeH   )) ? SizeOp::k01  : \
-  x == (((uint32_t(RegType::kARM_VecV) - uint32_t(RegType::kARM_VecB)) << 3) | (Vec::kElementTypeH   )) ? SizeOp::k01Q : \
-  x == (((uint32_t(RegType::kARM_VecD) - uint32_t(RegType::kARM_VecB)) << 3) | (Vec::kElementTypeS   )) ? SizeOp::k10  : \
-  x == (((uint32_t(RegType::kARM_VecV) - uint32_t(RegType::kARM_VecB)) << 3) | (Vec::kElementTypeS   )) ? SizeOp::k10Q : \
-  x == (((uint32_t(RegType::kARM_VecD) - uint32_t(RegType::kARM_VecB)) << 3) | (Vec::kElementTypeD   )) ? SizeOp::k11S : \
-  x == (((uint32_t(RegType::kARM_VecV) - uint32_t(RegType::kARM_VecB)) << 3) | (Vec::kElementTypeD   )) ? SizeOp::k11Q : SizeOp::kInvalid \
+  x == (((uint32_t(RegType::kARM_VecB) - uint32_t(RegType::kARM_VecB)) << 3) | uint32_t(VecElementType::kNone)) ? SizeOp::k00S : \
+  x == (((uint32_t(RegType::kARM_VecH) - uint32_t(RegType::kARM_VecB)) << 3) | uint32_t(VecElementType::kNone)) ? SizeOp::k01S : \
+  x == (((uint32_t(RegType::kARM_VecS) - uint32_t(RegType::kARM_VecB)) << 3) | uint32_t(VecElementType::kNone)) ? SizeOp::k10S : \
+  x == (((uint32_t(RegType::kARM_VecD) - uint32_t(RegType::kARM_VecB)) << 3) | uint32_t(VecElementType::kNone)) ? SizeOp::k11S : \
+  x == (((uint32_t(RegType::kARM_VecD) - uint32_t(RegType::kARM_VecB)) << 3) | uint32_t(VecElementType::kB   )) ? SizeOp::k00  : \
+  x == (((uint32_t(RegType::kARM_VecV) - uint32_t(RegType::kARM_VecB)) << 3) | uint32_t(VecElementType::kB   )) ? SizeOp::k00Q : \
+  x == (((uint32_t(RegType::kARM_VecD) - uint32_t(RegType::kARM_VecB)) << 3) | uint32_t(VecElementType::kH   )) ? SizeOp::k01  : \
+  x == (((uint32_t(RegType::kARM_VecV) - uint32_t(RegType::kARM_VecB)) << 3) | uint32_t(VecElementType::kH   )) ? SizeOp::k01Q : \
+  x == (((uint32_t(RegType::kARM_VecD) - uint32_t(RegType::kARM_VecB)) << 3) | uint32_t(VecElementType::kS   )) ? SizeOp::k10  : \
+  x == (((uint32_t(RegType::kARM_VecV) - uint32_t(RegType::kARM_VecB)) << 3) | uint32_t(VecElementType::kS   )) ? SizeOp::k10Q : \
+  x == (((uint32_t(RegType::kARM_VecD) - uint32_t(RegType::kARM_VecB)) << 3) | uint32_t(VecElementType::kD   )) ? SizeOp::k11S : \
+  x == (((uint32_t(RegType::kARM_VecV) - uint32_t(RegType::kARM_VecB)) << 3) | uint32_t(VecElementType::kD   )) ? SizeOp::k11Q : SizeOp::kInvalid \
 }
 
 static const SizeOpTable sizeOpTable[SizeOpTable::kCount] = {
@@ -254,16 +254,16 @@ static const Operand_& significantSimdOp(const Operand_& o0, const Operand_& o1,
   return !(instFlags & InstDB::kInstFlagLong) ? o0 : o1;
 }
 
-static inline SizeOp armElementTypeToSizeOp(uint32_t vecOpType, RegType regType, uint32_t elementType) noexcept {
+static inline SizeOp armElementTypeToSizeOp(uint32_t vecOpType, RegType regType, VecElementType elementType) noexcept {
   // Instruction data or Assembler is wrong if this triggers an assertion failure.
   ASMJIT_ASSERT(vecOpType < InstDB::kVO_Count);
   // ElementType uses 3 bits in the operand signature, it should never overflow.
-  ASMJIT_ASSERT(elementType <= 0x7u);
+  ASMJIT_ASSERT(uint32_t(elementType) <= 0x7u);
 
   const SizeOpMap& map = sizeOpMap[vecOpType];
   const SizeOpTable& table = sizeOpTable[map.tableId];
 
-  size_t index = (Support::min<uint32_t>(diff(regType, RegType::kARM_VecB), diff(RegType::kARM_VecV, RegType::kARM_VecB) + 1) << 3) | elementType;
+  size_t index = (Support::min<uint32_t>(diff(regType, RegType::kARM_VecB), diff(RegType::kARM_VecV, RegType::kARM_VecB) + 1) << 3) | uint32_t(elementType);
   SizeOp op = table.array[index];
   SizeOp modifiedOp { uint8_t(op.value & map.sizeOpMask) };
 
@@ -467,7 +467,7 @@ static inline bool matchSignature(const Operand_& o0, const Operand_& o1, const
 }
 
 static inline bool matchSignature(const Operand_& o0, const Operand_& o1, const Operand_& o2, const Operand_& o3, uint32_t instFlags) noexcept {
-  return matchSignature(o0, o1, instFlags) && o1.signature() == o2.signature() && o2.signature() == o3.signature();;
+  return matchSignature(o0, o1, instFlags) && o1.signature() == o2.signature() && o2.signature() == o3.signature();
 }
 
 // Memory must be either:
@@ -537,7 +537,7 @@ static inline bool pickFpOpcode(const Vec& reg, uint32_t sOp, uint32_t sHf, uint
   else {
     // Vector operation [HSD].
     uint32_t q = diff(reg.type(), RegType::kARM_VecD);
-    uint32_t sz = reg.elementType() - Vec::kElementTypeH;
+    uint32_t sz = diff(reg.elementType(), VecElementType::kH);
 
     if (q > 1u || sz > 2u || !Support::bitTest(szBits[vHf].sizeMask, sz))
       return false;
@@ -716,8 +716,6 @@ static inline bool checkValidRegs(const Operand_& o0, const Operand_& o1, const
 
 Assembler::Assembler(CodeHolder* code) noexcept : BaseAssembler() {
   _archMask = uint64_t(1) << uint32_t(Arch::kAArch64);
-  assignEmitterFuncs(this);
-
   if (code)
     code->attach(this);
 }
@@ -803,7 +801,7 @@ Error Assembler::_emit(InstId instId, const Operand_& o0, const Operand_& o1, co
       Operand_ opArray[Globals::kMaxOpCount];
       EmitterUtils::opArrayFromEmitArgs(opArray, o0, o1, o2, opExt);
 
-      err = _funcs.validate(arch(), BaseInst(instId, options, _extraReg), opArray, Globals::kMaxOpCount, ValidationFlags::kNone);
+      err = _funcs.validate(BaseInst(instId, options, _extraReg), opArray, Globals::kMaxOpCount, ValidationFlags::kNone);
       if (ASMJIT_UNLIKELY(err))
         goto Failed;
     }
@@ -2241,6 +2239,86 @@ Error Assembler::_emit(InstId instId, const Operand_& o0, const Operand_& o1, co
       break;
     }
 
+    // ------------------------------------------------------------------------
+    // [Base - Prefetch]
+    // ------------------------------------------------------------------------
+
+    case InstDB::kEncodingBasePrfm: {
+      const InstDB::EncodingData::BasePrfm& opData = InstDB::EncodingData::basePrfm[encodingIndex];
+
+      if (isign4 == ENC_OPS2(Imm, Mem)) {
+        const Mem& m = o1.as<Mem>();
+        rmRel = &m;
+
+        uint32_t immShift = 3u;
+
+        if (o0.as<Imm>().valueAs<uint64_t>() > 0x1Fu)
+          goto InvalidImmediate;
+
+        if (!armCheckMemBaseIndexRel(m))
+          goto InvalidAddress;
+
+        int64_t offset = m.offset();
+        uint32_t prfop = o0.as<Imm>().valueAs<uint32_t>();
+
+        if (m.hasBaseReg()) {
+          // [Base {Offset | Index}]
+          if (m.hasIndex()) {
+            uint32_t opt = armShiftOpToLdStOptMap[size_t(m.shiftOp())];
+            if (opt == 0xFF)
+              goto InvalidAddress;
+
+            uint32_t shift = m.shift();
+            uint32_t s = shift != 0;
+
+            if (s && shift != immShift)
+              goto InvalidAddressScale;
+
+            opcode.reset(uint32_t(opData.registerOp) << 21);
+            opcode.addImm(opt, 13);
+            opcode.addImm(s, 12);
+            opcode |= B(11);
+            opcode.addImm(prfop, 0);
+            goto EmitOp_MemBaseIndex_Rn5_Rm16;
+          }
+
+          if (!Support::isInt32(offset))
+            goto InvalidDisplacement;
+
+          int32_t offset32 = int32_t(offset);
+
+          if (m.isPreOrPost())
+            goto InvalidAddress;
+
+          uint32_t imm12 = uint32_t(offset32) >> immShift;
+
+          if (Support::isUInt12(imm12) && (imm12 << immShift) == uint32_t(offset32)) {
+            opcode.reset(uint32_t(opData.sOffsetOp) << 22);
+            opcode.addImm(imm12, 10);
+            opcode.addImm(prfop, 0);
+            goto EmitOp_MemBase_Rn5;
+          }
+
+          if (Support::isInt9(offset32)) {
+            opcode.reset(uint32_t(opData.uOffsetOp) << 21);
+            opcode.addImm(uint32_t(offset32) & 0x1FFu, 12);
+            opcode.addImm(prfop, 0);
+            goto EmitOp_MemBase_Rn5;
+          }
+
+          goto InvalidAddress;
+        }
+        else {
+          opcode.reset(uint32_t(opData.literalOp) << 24);
+          opcode.addImm(prfop, 0);
+          offsetFormat.resetToImmValue(OffsetType::kSignedOffset, 4, 5, 19, 2);
+          goto EmitOp_Rel;
+        }
+      }
+
+      break;
+    }
+
     // ------------------------------------------------------------------------
     // [Base - Load / Store]
     // ------------------------------------------------------------------------
@@ -2272,7 +2350,7 @@ Error Assembler::_emit(InstId instId, const Operand_& o0, const Operand_& o1, co
         if (m.hasBaseReg()) {
           // [Base {Offset | Index}]
           if (m.hasIndex()) {
-            uint32_t opt = armShiftOpToLdStOptMap[m.predicate()];
+            uint32_t opt = armShiftOpToLdStOptMap[size_t(m.shiftOp())];
             if (opt == 0xFF)
               goto InvalidAddress;
 
@@ -2690,7 +2768,7 @@ Case_BaseLdurStur:
         //   hD, vS.{4|8}h (16-bit)
         //   sD, vS.4s     (32-bit)
         uint32_t sz = diff(o0.as<Reg>().type(), RegType::kARM_VecH);
-        uint32_t elementSz = o1.as<Vec>().elementType() - Vec::kElementTypeH;
+        uint32_t elementSz = diff(o1.as<Vec>().elementType(), VecElementType::kH);
 
         // Size greater than 1 means 64-bit elements, not supported.
         if ((sz | elementSz) > 1 || sz != elementSz)
@@ -2812,7 +2890,7 @@ Case_BaseLdurStur:
         if (q > 1)
           goto InvalidInstruction;
 
-        uint32_t sz = o0.as<Vec>().elementType() - Vec::kElementTypeB;
+        uint32_t sz = diff(o0.as<Vec>().elementType(), VecElementType::kB);
         if (sz == 0 || sz > 3)
           goto InvalidInstruction;
 
@@ -2904,7 +2982,7 @@ Case_BaseLdurStur:
         if (q > 1)
           goto InvalidInstruction;
 
-        uint32_t sz = o0.as<Vec>().elementType() - Vec::kElementTypeB;
+        uint32_t sz = diff(o0.as<Vec>().elementType(), VecElementType::kB);
         if (sz == 0 || sz > 3)
           goto InvalidInstruction;
 
@@ -3086,11 +3164,11 @@ Case_BaseLdurStur:
         if (uint32_t(opcode.hasQ()) != q)
           goto InvalidInstruction;
 
-        if (rL.isVecS4() && rN.elementType() == Vec::kElementTypeH && !opData.isCvtxn()) {
+        if (rL.isVecS4() && rN.elementType() == VecElementType::kH && !opData.isCvtxn()) {
           goto EmitOp_Rd0_Rn5;
         }
 
-        if (rL.isVecD2() && rN.elementType() == Vec::kElementTypeS) {
+        if (rL.isVecD2() && rN.elementType() == VecElementType::kS) {
           opcode |= B(22);
           goto EmitOp_Rd0_Rn5;
         }
@@ -3201,8 +3279,8 @@ Case_BaseLdurStur:
         }
 
         if (uint32_t(o0.as<Reg>().type()) != uint32_t(o1.as<Reg>().type()) + qIsOptional ||
-            o0.as<Vec>().elementType() != opData.tA ||
-            o1.as<Vec>().elementType() != opData.tB)
+            uint32_t(o0.as<Vec>().elementType()) != opData.tA ||
+            uint32_t(o1.as<Vec>().elementType()) != opData.tB)
           goto InvalidInstruction;
 
         if (!o2.as<Vec>().hasElementIndex()) {
@@ -3214,7 +3292,7 @@ Case_BaseLdurStur:
           goto EmitOp_Rd0_Rn5_Rm16;
         }
         else {
-          if (o2.as<Vec>().elementType() != opData.tElement)
+          if (uint32_t(o2.as<Vec>().elementType()) != opData.tElement)
             goto InvalidInstruction;
 
           if (o2.as<Reg>().id() > 15)
@@ -3364,7 +3442,7 @@ Case_BaseLdurStur:
           }
           else {
             uint32_t q = diff(o0.as<Vec>().type(), RegType::kARM_VecD);
-            uint32_t sz = o0.as<Vec>().elementType() - Vec::kElementTypeH;
+            uint32_t sz = diff(o0.as<Vec>().elementType(), VecElementType::kH);
 
             if (q > 1 || sz > 2)
               goto InvalidInstruction;
@@ -3418,7 +3496,7 @@ Case_BaseLdurStur:
         if (q > 1)
           goto InvalidInstruction;
 
-        uint32_t sz = o0.as<Vec>().elementType() - Vec::kElementTypeH;
+        uint32_t sz = diff(o0.as<Vec>().elementType(), VecElementType::kH);
         if (sz > 2)
           goto InvalidInstruction;
 
@@ -3442,7 +3520,7 @@ Case_BaseLdurStur:
       if (isign4 == ENC_OPS2(Reg, Reg)) {
         // The first destination operand is scalar, which matches element-type of source vectors.
         uint32_t L = (instFlags & InstDB::kInstFlagLong) != 0;
-        if (diff(o0.as<Vec>().type(), RegType::kARM_VecB) != o1.as<Vec>().elementType() - Vec::kElementTypeB + L)
+        if (diff(o0.as<Vec>().type(), RegType::kARM_VecB) != diff(o1.as<Vec>().elementType(), VecElementType::kB) + L)
           goto InvalidInstruction;
 
         SizeOp sizeOp = armElementTypeToSizeOp(opData.vecOpType, o1.as<Reg>().type(), o1.as<Vec>().elementType());
@@ -3542,7 +3620,7 @@ Case_BaseLdurStur:
         if (!sizeOp.isValid())
           goto InvalidInstruction;
 
-        if (!checkSignature(o0, o1) || !o0.as<Reg>().isVecV() || o0.as<Vec>().elementType() != o2.as<Vec>().elementType() + 1)
+        if (!checkSignature(o0, o1) || !o0.as<Reg>().isVecV() || uint32_t(o0.as<Vec>().elementType()) != uint32_t(o2.as<Vec>().elementType()) + 1u)
           goto InvalidInstruction;
 
         opcode.reset(opData.opcode());
@@ -3827,9 +3905,9 @@ Case_BaseLdurStur:
           if (o0.as<Reg>().type() != o1.as<Reg>().type() || o1.as<Reg>().type() != o2.as<Reg>().type())
             goto InvalidInstruction;
 
-          if (o0.as<Vec>().elementType() != opData.tA ||
-              o1.as<Vec>().elementType() != opData.tB ||
-              o2.as<Vec>().elementType() != opData.tB)
+          if (uint32_t(o0.as<Vec>().elementType()) != opData.tA ||
+              uint32_t(o1.as<Vec>().elementType()) != opData.tB ||
+              uint32_t(o2.as<Vec>().elementType()) != opData.tB)
             goto InvalidInstruction;
 
           opcode.reset(uint32_t(opData.vectorOp) << 10);
@@ -3843,9 +3921,9 @@ Case_BaseLdurStur:
           if (o0.as<Reg>().type() != o1.as<Reg>().type() || !o2.as<Reg>().isVecV())
             goto InvalidInstruction;
 
-          if (o0.as<Vec>().elementType() != opData.tA ||
-              o1.as<Vec>().elementType() != opData.tB ||
-              o2.as<Vec>().elementType() != opData.tElement)
+          if (uint32_t(o0.as<Vec>().elementType()) != opData.tA ||
+              uint32_t(o1.as<Vec>().elementType()) != opData.tB ||
+              uint32_t(o2.as<Vec>().elementType()) != opData.tElement)
             goto InvalidInstruction;
 
           uint32_t elementIndex = o2.as<Vec>().elementIndex();
@@ -3871,13 +3949,13 @@ Case_BaseLdurStur:
     case InstDB::kEncodingSimdDup: SimdDup: {
       if (isign4 == ENC_OPS2(Reg, Reg)) {
         // Truth table of valid encodings of `Q:1|ElementType:3`
-        uint32_t kValidEncodings = B(Vec::kElementTypeB + 0) |
-                                   B(Vec::kElementTypeH + 0) |
-                                   B(Vec::kElementTypeS + 0) |
-                                   B(Vec::kElementTypeB + 8) |
-                                   B(Vec::kElementTypeH + 8) |
-                                   B(Vec::kElementTypeS + 8) |
-                                   B(Vec::kElementTypeD + 8) ;
+        uint32_t kValidEncodings = B(uint32_t(VecElementType::kB) + 0) |
+                                   B(uint32_t(VecElementType::kH) + 0) |
+                                   B(uint32_t(VecElementType::kS) + 0) |
+                                   B(uint32_t(VecElementType::kB) + 8) |
+                                   B(uint32_t(VecElementType::kH) + 8) |
+                                   B(uint32_t(VecElementType::kS) + 8) |
+                                   B(uint32_t(VecElementType::kD) + 8) ;
 
         uint32_t q = diff(o0.as<Reg>().type(), RegType::kARM_VecD);
 
@@ -3886,7 +3964,7 @@ Case_BaseLdurStur:
           //
           // NOTE: This is only scalar for `dup d, x` case, otherwise the value
           // would be duplicated across all vector elements (1, 2, 4, 8, or 16).
-          uint32_t elementType = o0.as<Vec>().elementType();
+          uint32_t elementType = uint32_t(o0.as<Vec>().elementType());
           if (q > 1 || !Support::bitTest(kValidEncodings, (q << 3) | elementType))
             goto InvalidInstruction;
 
@@ -3907,7 +3985,7 @@ Case_BaseLdurStur:
           // DUP - Vec (scalar) <- Vec[N].
           uint32_t lsbIndex = diff(o0.as<Reg>().type(), RegType::kARM_VecB);
 
-          if (lsbIndex != o1.as<Vec>().elementType() - Vec::kElementTypeB || lsbIndex > 3)
+          if (lsbIndex != diff(o1.as<Vec>().elementType(), VecElementType::kB) || lsbIndex > 3)
             goto InvalidInstruction;
 
           uint32_t imm5 = ((dstIndex << 1) | 1u) << lsbIndex;
@@ -3920,7 +3998,7 @@ Case_BaseLdurStur:
         }
         else {
           // DUP - Vec (all) <- Vec[N].
-          uint32_t elementType = o0.as<Vec>().elementType();
+          uint32_t elementType = uint32_t(o0.as<Vec>().elementType());
           if (q > 1 || !Support::bitTest(kValidEncodings, (q << 3) | elementType))
             goto InvalidInstruction;
 
@@ -3945,7 +4023,7 @@ Case_BaseLdurStur:
         if (!o0.as<Vec>().hasElementIndex())
           goto InvalidInstruction;
 
-        uint32_t elementType = o0.as<Vec>().elementType();
+        uint32_t elementType = uint32_t(o0.as<Vec>().elementType());
         uint32_t dstIndex = o0.as<Vec>().elementIndex();
         uint32_t lsbIndex = elementType - 1u;
 
@@ -4114,7 +4192,6 @@ Case_BaseLdurStur:
 
             if (inverted) {
               imm8 = ~imm8 & 0xFFu;
-              inverted = 0;
             }
 
             cmode = B(3) | B(2) | B(1);
@@ -4147,7 +4224,6 @@ Case_BaseLdurStur:
           case 3:
             if (inverted) {
               imm8 = ~imm8 & 0xFFu;
-              inverted = 0;
             }
 
             op = 1;
@@ -4435,7 +4511,7 @@ Case_BaseLdurStur:
         if (m.hasBaseReg()) {
           // [Base {Offset | Index}]
           if (m.hasIndex()) {
-            uint32_t opt = armShiftOpToLdStOptMap[m.predicate()];
+            uint32_t opt = armShiftOpToLdStOptMap[size_t(m.shiftOp())];
             if (opt == 0xFFu)
               goto InvalidAddress;
 
@@ -4659,7 +4735,7 @@ Case_SimdLdurStur:
       uint32_t q = 0;
       uint32_t rm = 0;
       uint32_t rn = m.baseId();
-      uint32_t sz = v.elementType() - Vec::kElementTypeB;
+      uint32_t sz = diff(v.elementType(), VecElementType::kB);
       uint32_t opcSsize = sz;
       uint32_t offsetPossibility = 0;
 
@@ -5091,6 +5167,10 @@ Error Assembler::align(AlignMode alignMode, uint32_t alignment) {
 
 Error Assembler::onAttach(CodeHolder* code) noexcept {
   ASMJIT_PROPAGATE(Base::onAttach(code));
+
+  _instructionAlignment = uint8_t(4);
+  assignEmitterFuncs(this);
+
   return kErrorOk;
 }
 

deps/asmjit/src/asmjit/arm/a64assembler.h

@@ -23,7 +23,7 @@ class ASMJIT_VIRTAPI Assembler
 public:
   typedef BaseAssembler Base;
 
-  //! \name Construction / Destruction
+  //! \name Construction & Destruction
   //! \{
 
   ASMJIT_API Assembler(CodeHolder* code = nullptr) noexcept;
@@ -31,17 +31,6 @@ public:
 
   //! \}
 
-  //! \name Accessors
-  //! \{
-
-  //! Gets whether the current ARM mode is THUMB (alternative to 32-bit ARM encoding).
-  ASMJIT_INLINE_NODEBUG bool isInThumbMode() const noexcept { return _environment.isArchThumb(); }
-
-  //! Gets the current code alignment of the current mode (ARM vs THUMB).
-  ASMJIT_INLINE_NODEBUG uint32_t codeAlignment() const noexcept { return isInThumbMode() ? 2 : 4; }
-
-  //! \}
-
   //! \name Emit
   //! \{
 

deps/asmjit/src/asmjit/arm/a64builder.cpp

@@ -17,8 +17,6 @@ ASMJIT_BEGIN_SUB_NAMESPACE(a64)
 
 Builder::Builder(CodeHolder* code) noexcept : BaseBuilder() {
   _archMask = uint64_t(1) << uint32_t(Arch::kAArch64);
-  assignEmitterFuncs(this);
-
   if (code)
     code->attach(this);
 }
@@ -28,13 +26,19 @@ Builder::~Builder() noexcept {}
 // =====================
 
 Error Builder::onAttach(CodeHolder* code) noexcept {
-  return Base::onAttach(code);
+  ASMJIT_PROPAGATE(Base::onAttach(code));
+
+  _instructionAlignment = uint8_t(4);
+  assignEmitterFuncs(this);
+
+  return kErrorOk;
 }
 
 Error Builder::onDetach(CodeHolder* code) noexcept {
   return Base::onDetach(code);
 }
 
+
 // a64::Builder - Finalize
 // =======================
 

deps/asmjit/src/asmjit/arm/a64compiler.cpp

@@ -18,8 +18,6 @@ ASMJIT_BEGIN_SUB_NAMESPACE(a64)
 
 Compiler::Compiler(CodeHolder* code) noexcept : BaseCompiler() {
   _archMask = uint64_t(1) << uint32_t(Arch::kAArch64);
-  assignEmitterFuncs(this);
-
   if (code)
     code->attach(this);
 }
@@ -37,6 +35,9 @@ Error Compiler::onAttach(CodeHolder* code) noexcept {
     return err;
   }
 
+  _instructionAlignment = uint8_t(4);
+  assignEmitterFuncs(this);
+
   return kErrorOk;
 }
 

deps/asmjit/src/asmjit/arm/a64compiler.h

@@ -45,20 +45,27 @@ public:
     return reg;
   }
 
+  template<typename RegT, typename Type>
+  ASMJIT_INLINE_NODEBUG RegT _newRegInternal(const Type& type, const char* s) {
+#ifndef ASMJIT_NO_LOGGING
+    RegT reg(Globals::NoInit);
+    _newReg(&reg, type, s);
+    return reg;
+#else
+    DebugUtils::unused(s);
+    return _newRegInternal<RegT>(type);
+#endif
+  }
+
   template<typename RegT, typename Type, typename... Args>
   ASMJIT_INLINE_NODEBUG RegT _newRegInternal(const Type& type, const char* s, Args&&... args) {
 #ifndef ASMJIT_NO_LOGGING
     RegT reg(Globals::NoInit);
-    if (sizeof...(Args) == 0)
-      _newReg(&reg, type, s);
-    else
-      _newRegFmt(&reg, type, s, std::forward<Args>(args)...);
+    _newRegFmt(&reg, type, s, std::forward<Args>(args)...);
     return reg;
 #else
     DebugUtils::unused(s, std::forward<Args>(args)...);
-    RegT reg(Globals::NoInit);
-    _newReg(&reg, type, nullptr);
-    return reg;
+    return _newRegInternal<RegT>(type);
 #endif
   }
   //! \endcond

deps/asmjit/src/asmjit/arm/a64emithelper.cpp

@@ -169,7 +169,7 @@ Error EmitHelper::emitArgMove(
 
   if (TypeUtils::isInt(dstTypeId)) {
     if (TypeUtils::isInt(srcTypeId)) {
-      uint32_t x = dstSize == 8;
+      uint32_t x = uint32_t(dstSize == 8);
 
       dst.setSignature(OperandSignature{x ? uint32_t(GpX::kSignature) : uint32_t(GpW::kSignature)});
       _emitter->setInlineComment(comment);
@@ -186,7 +186,7 @@ Error EmitHelper::emitArgMove(
           case TypeId::kInt16: instId = Inst::kIdLdrsh; break;
           case TypeId::kUInt16: instId = Inst::kIdLdrh; break;
           case TypeId::kInt32: instId = x ? Inst::kIdLdrsw : Inst::kIdLdr; break;
-          case TypeId::kUInt32: instId = Inst::kIdLdr; x = 0; break;
+          case TypeId::kUInt32: instId = Inst::kIdLdr; break;
           case TypeId::kInt64: instId = Inst::kIdLdr; break;
           case TypeId::kUInt64: instId = Inst::kIdLdr; break;
           default:
@@ -312,6 +312,12 @@ ASMJIT_FAVOR_SIZE Error EmitHelper::emitProlog(const FuncFrame& frame) {
     { Inst::kIdStr_v, Inst::kIdStp_v }
   }};
 
+  // Emit: 'bti' (indirect branch protection).
+  if (frame.hasIndirectBranchProtection()) {
+    // TODO: The instruction is not available at the moment (would be ABI break).
+    // ASMJIT_PROPAGATE(emitter->bti());
+  }
+
   uint32_t adjustInitialOffset = pei.sizeTotal;
 
   for (RegGroup group : Support::EnumValues<RegGroup, RegGroup::kGp, RegGroup::kVec>{}) {
@@ -339,7 +345,7 @@ ASMJIT_FAVOR_SIZE Error EmitHelper::emitProlog(const FuncFrame& frame) {
       else
         ASMJIT_PROPAGATE(emitter->emit(insts.pairInstId, regs[0], regs[1], mem));
 
-      mem.resetToFixedOffset();
+      mem.resetOffsetMode();
 
       if (i == 0 && frame.hasPreservedFP()) {
         ASMJIT_PROPAGATE(emitter->mov(x29, sp));
@@ -421,7 +427,7 @@ ASMJIT_FAVOR_SIZE Error EmitHelper::emitEpilog(const FuncFrame& frame) {
       else
         ASMJIT_PROPAGATE(emitter->emit(insts.pairInstId, regs[0], regs[1], mem));
 
-      mem.resetToFixedOffset();
+      mem.resetOffsetMode();
     }
   }
 

deps/asmjit/src/asmjit/arm/a64emitter.h

@@ -71,7 +71,7 @@ ASMJIT_BEGIN_SUB_NAMESPACE(a64)
 //! ARM emitter.
 //!
 //! NOTE: This class cannot be instantiated, you can only cast to it and use it as emitter that emits to either
-//! \ref Assembler, \ref Builder, or \ref Compiler (use withcaution with \ref Compiler as it expects virtual
+//! \ref Assembler, \ref Builder, or \ref Compiler (use with caution with \ref Compiler as it expects virtual
 //! registers to be used).
 template<typename This>
 struct EmitterExplicitT {
@@ -79,11 +79,22 @@ struct EmitterExplicitT {
 
   // These two are unfortunately reported by the sanitizer. We know what we do, however, the sanitizer doesn't.
   // I have tried to use reinterpret_cast instead, but that would generate bad code when compiled by MSC.
-  ASMJIT_ATTRIBUTE_NO_SANITIZE_UNDEF inline This* _emitter() noexcept { return static_cast<This*>(this); }
-  ASMJIT_ATTRIBUTE_NO_SANITIZE_UNDEF inline const This* _emitter() const noexcept { return static_cast<const This*>(this); }
+  ASMJIT_ATTRIBUTE_NO_SANITIZE_UNDEF ASMJIT_INLINE_NODEBUG This* _emitter() noexcept { return static_cast<This*>(this); }
+  ASMJIT_ATTRIBUTE_NO_SANITIZE_UNDEF ASMJIT_INLINE_NODEBUG const This* _emitter() const noexcept { return static_cast<const This*>(this); }
 
   //! \endcond
 
+
+  //! \name Native Registers
+  //! \{
+
+  //! Returns either 32-bit or 64-bit GP register of the given `id` depending on the emitter's architecture.
+  inline Gp gpz(uint32_t id) const noexcept { return Gp(_emitter()->_gpSignature, id); }
+  //! Clones the given `reg` to either 32-bit or 64-bit GP register depending on the emitter's architecture.
+  inline Gp gpz(const Gp& reg) const noexcept { return Gp(_emitter()->_gpSignature, reg.id()); }
+
+  //! \}
+
   //! \name General Purpose Instructions
   //! \{
 
@@ -514,6 +525,8 @@ struct EmitterExplicitT {
   ASMJIT_INST_2x(ldxrb, Ldxrb, Gp, Mem)
   ASMJIT_INST_2x(ldxrh, Ldxrh, Gp, Mem)
 
+  ASMJIT_INST_2x(prfm, Prfm, Imm, Mem)
+
   ASMJIT_INST_2x(stadd, Stadd, Gp, Mem)
   ASMJIT_INST_2x(staddb, Staddb, Gp, Mem)
   ASMJIT_INST_2x(staddh, Staddh, Gp, Mem)

deps/asmjit/src/asmjit/arm/a64formatter.cpp

@@ -29,12 +29,10 @@ ASMJIT_FAVOR_SIZE Error FormatterInternal::formatInstruction(
   Arch arch,
   const BaseInst& inst, const Operand_* operands, size_t opCount) noexcept {
 
-  DebugUtils::unused(arch);
-
   // Format instruction options and instruction mnemonic.
   InstId instId = inst.realId();
-  if (instId < Inst::_kIdCount)
-    ASMJIT_PROPAGATE(InstInternal::instIdToString(arch, instId, sb));
+  if (instId != Inst::kIdNone && instId < Inst::_kIdCount)
+    ASMJIT_PROPAGATE(InstInternal::instIdToString(instId, sb));
   else
     ASMJIT_PROPAGATE(sb.appendFormat("[InstId=#%u]", unsigned(instId)));
 

deps/asmjit/src/asmjit/arm/a64func.cpp

@@ -41,12 +41,13 @@ static RegType regTypeFromFpOrVecTypeId(TypeId typeId) noexcept {
 
 ASMJIT_FAVOR_SIZE Error initCallConv(CallConv& cc, CallConvId ccId, const Environment& environment) noexcept {
   cc.setArch(environment.arch());
+  cc.setStrategy(environment.isDarwin() ? CallConvStrategy::kAArch64Apple : CallConvStrategy::kDefault);
 
   cc.setSaveRestoreRegSize(RegGroup::kGp, 8);
   cc.setSaveRestoreRegSize(RegGroup::kVec, 8);
   cc.setSaveRestoreAlignment(RegGroup::kGp, 16);
   cc.setSaveRestoreAlignment(RegGroup::kVec, 16);
-  cc.setSaveRestoreAlignment(RegGroup::kExtraVirt2, 1);
+  cc.setSaveRestoreAlignment(RegGroup::kMask, 1);
   cc.setSaveRestoreAlignment(RegGroup::kExtraVirt3, 1);
   cc.setPassedOrder(RegGroup::kGp, 0, 1, 2, 3, 4, 5, 6, 7);
   cc.setPassedOrder(RegGroup::kVec, 0, 1, 2, 3, 4, 5, 6, 7);
@@ -68,7 +69,7 @@ ASMJIT_FAVOR_SIZE Error initCallConv(CallConv& cc, CallConvId ccId, const Enviro
   return kErrorOk;
 }
 
-ASMJIT_FAVOR_SIZE Error initFuncDetail(FuncDetail& func, const FuncSignature& signature, uint32_t registerSize) noexcept {
+ASMJIT_FAVOR_SIZE Error initFuncDetail(FuncDetail& func, const FuncSignature& signature) noexcept {
   DebugUtils::unused(signature);
 
   const CallConv& cc = func.callConv();
@@ -77,6 +78,13 @@ ASMJIT_FAVOR_SIZE Error initFuncDetail(FuncDetail& func, const FuncSignature& si
   uint32_t i;
   uint32_t argCount = func.argCount();
 
+  // Minimum stack size of a single argument passed via stack. The standard AArch64 calling convention
+  // specifies 8 bytes, so each function argument would occupy at least 8 bytes even if it needs less.
+  // However, Apple has decided to not follow this rule and function argument can occupy less, for
+  // example two consecutive 32-bit arguments would occupy 8 bytes total, instead of 16 as specified
+  // by ARM.
+  uint32_t minStackArgSize = cc.strategy() == CallConvStrategy::kAArch64Apple ? 4u : 8u;
+
   if (func.hasRet()) {
     for (uint32_t valueIndex = 0; valueIndex < Globals::kMaxValuePack; valueIndex++) {
       TypeId typeId = func._rets[valueIndex].typeId();
@@ -119,7 +127,8 @@ ASMJIT_FAVOR_SIZE Error initFuncDetail(FuncDetail& func, const FuncSignature& si
   }
 
   switch (cc.strategy()) {
-    case CallConvStrategy::kDefault: {
+    case CallConvStrategy::kDefault:
+    case CallConvStrategy::kAArch64Apple: {
       uint32_t gpzPos = 0;
       uint32_t vecPos = 0;
 
@@ -140,7 +149,9 @@ ASMJIT_FAVOR_SIZE Error initFuncDetail(FuncDetail& func, const FuncSignature& si
             gpzPos++;
           }
           else {
-            uint32_t size = Support::max<uint32_t>(TypeUtils::sizeOf(typeId), registerSize);
+            uint32_t size = Support::max<uint32_t>(TypeUtils::sizeOf(typeId), minStackArgSize);
+            if (size >= 8)
+              stackOffset = Support::alignUp(stackOffset, 8);
             arg.assignStackOffset(int32_t(stackOffset));
             stackOffset += size;
           }
@@ -164,7 +175,9 @@ ASMJIT_FAVOR_SIZE Error initFuncDetail(FuncDetail& func, const FuncSignature& si
             vecPos++;
           }
           else {
-            uint32_t size = TypeUtils::sizeOf(typeId);
+            uint32_t size = Support::max<uint32_t>(TypeUtils::sizeOf(typeId), minStackArgSize);
+            if (size >= 8)
+              stackOffset = Support::alignUp(stackOffset, 8);
             arg.assignStackOffset(int32_t(stackOffset));
             stackOffset += size;
           }
@@ -178,7 +191,7 @@ ASMJIT_FAVOR_SIZE Error initFuncDetail(FuncDetail& func, const FuncSignature& si
       return DebugUtils::errored(kErrorInvalidState);
   }
 
-  func._argStackSize = stackOffset;
+  func._argStackSize = Support::alignUp(stackOffset, 8u);
   return kErrorOk;
 }
 

deps/asmjit/src/asmjit/arm/a64func_p.h

@@ -21,7 +21,7 @@ namespace FuncInternal {
 Error initCallConv(CallConv& cc, CallConvId ccId, const Environment& environment) noexcept;
 
 //! Initialize `FuncDetail` (AArch64 specific).
-Error initFuncDetail(FuncDetail& func, const FuncSignature& signature, uint32_t registerSize) noexcept;
+Error initFuncDetail(FuncDetail& func, const FuncSignature& signature) noexcept;
 
 } // {FuncInternal}
 

deps/asmjit/src/asmjit/arm/a64globals.h

@@ -15,9 +15,6 @@
 
 ASMJIT_BEGIN_SUB_NAMESPACE(a64)
 
-// a64 uses everything from arm namespace and adds into it.
-using namespace arm;
-
 //! \addtogroup asmjit_a64
 //! \{
 
@@ -293,6 +290,7 @@ struct Inst {
     kIdPacdza,                           //!< Instruction 'pacdza'.
     kIdPacdzb,                           //!< Instruction 'pacdzb'.
     kIdPacga,                            //!< Instruction 'pacga'.
+    kIdPrfm,                             //!< Instruction 'prfm'.
     kIdPssbb,                            //!< Instruction 'pssbb'.
     kIdRbit,                             //!< Instruction 'rbit'.
     kIdRet,                              //!< Instruction 'ret'.

deps/asmjit/src/asmjit/arm/a64instapi.cpp

@@ -15,65 +15,22 @@
 
 ASMJIT_BEGIN_SUB_NAMESPACE(a64)
 
+namespace InstInternal {
+
 // a64::InstInternal - Text
 // ========================
 
 #ifndef ASMJIT_NO_TEXT
-Error InstInternal::instIdToString(Arch arch, InstId instId, String& output) noexcept {
+Error instIdToString(InstId instId, String& output) noexcept {
   uint32_t realId = instId & uint32_t(InstIdParts::kRealId);
-  DebugUtils::unused(arch);
-
   if (ASMJIT_UNLIKELY(!Inst::isDefinedId(realId)))
     return DebugUtils::errored(kErrorInvalidInstruction);
 
-
-  char nameData[32];
-  size_t nameSize = Support::decodeInstName(nameData, InstDB::_instNameIndexTable[realId], InstDB::_instNameStringTable);
-
-  return output.append(nameData, nameSize);
+  return InstNameUtils::decode(output, InstDB::_instNameIndexTable[realId], InstDB::_instNameStringTable);
 }
 
-InstId InstInternal::stringToInstId(Arch arch, const char* s, size_t len) noexcept {
-  DebugUtils::unused(arch);
-
-  if (ASMJIT_UNLIKELY(!s))
-    return Inst::kIdNone;
-
-  if (len == SIZE_MAX)
-    len = strlen(s);
-
-  if (ASMJIT_UNLIKELY(len == 0 || len > InstDB::kMaxNameSize))
-    return Inst::kIdNone;
-
-  uint32_t prefix = uint32_t(s[0]) - 'a';
-  if (ASMJIT_UNLIKELY(prefix > 'z' - 'a'))
-    return Inst::kIdNone;
-
-  size_t base = InstDB::instNameIndex[prefix].start;
-  size_t end = InstDB::instNameIndex[prefix].end;
-
-  if (ASMJIT_UNLIKELY(!base))
-    return Inst::kIdNone;
-
-  char nameData[32];
-  for (size_t lim = end - base; lim != 0; lim >>= 1) {
-    size_t instId = base + (lim >> 1);
-    size_t nameSize = Support::decodeInstName(nameData, InstDB::_instNameIndexTable[instId], InstDB::_instNameStringTable);
-
-    int result = Support::compareStringViews(s, len, nameData, nameSize);
-    if (result < 0)
-      continue;
-
-    if (result > 0) {
-      base = instId + 1;
-      lim--;
-      continue;
-    }
-
-    return InstId(instId);
-  }
-
-  return Inst::kIdNone;
+InstId stringToInstId(const char* s, size_t len) noexcept {
+  return InstNameUtils::find(s, len, InstDB::instNameIndex, InstDB::_instNameIndexTable, InstDB::_instNameStringTable);
 }
 #endif // !ASMJIT_NO_TEXT
 
@@ -81,9 +38,9 @@ InstId InstInternal::stringToInstId(Arch arch, const char* s, size_t len) noexce
 // ============================
 
 #ifndef ASMJIT_NO_VALIDATION
-ASMJIT_FAVOR_SIZE Error InstInternal::validate(Arch arch, const BaseInst& inst, const Operand_* operands, size_t opCount, ValidationFlags validationFlags) noexcept {
+ASMJIT_FAVOR_SIZE Error validate(const BaseInst& inst, const Operand_* operands, size_t opCount, ValidationFlags validationFlags) noexcept {
   // TODO:
-  DebugUtils::unused(arch, inst, operands, opCount, validationFlags);
+  DebugUtils::unused(inst, operands, opCount, validationFlags);
   return kErrorOk;
 }
 #endif // !ASMJIT_NO_VALIDATION
@@ -127,13 +84,7 @@ static const InstRWInfoData instRWInfoData[] = {
 
 static const uint8_t elementTypeSize[8] = { 0, 1, 2, 4, 8, 4, 4, 0 };
 
-Error InstInternal::queryRWInfo(Arch arch, const BaseInst& inst, const Operand_* operands, size_t opCount, InstRWInfo* out) noexcept {
-  // Unused in Release configuration as the assert is not compiled in.
-  DebugUtils::unused(arch);
-
-  // Only called when `arch` matches X86 family.
-  ASMJIT_ASSERT(Environment::isFamilyARM(arch));
-
+Error queryRWInfo(const BaseInst& inst, const Operand_* operands, size_t opCount, InstRWInfo* out) noexcept {
   // Get the instruction data.
   uint32_t realId = inst.id() & uint32_t(InstIdParts::kRealId);
 
@@ -223,10 +174,10 @@ Error InstInternal::queryRWInfo(Arch arch, const BaseInst& inst, const Operand_*
       if (srcOp.isReg()) {
         if (srcOp.as<Vec>().hasElementIndex()) {
           // Only part of the vector is accessed if element index [] is used.
-          uint32_t elementType = srcOp.as<Vec>().elementType();
+          VecElementType elementType = srcOp.as<Vec>().elementType();
           uint32_t elementIndex = srcOp.as<Vec>().elementIndex();
 
-          uint32_t elementSize = elementTypeSize[elementType];
+          uint32_t elementSize = elementTypeSize[size_t(elementType)];
           uint64_t accessMask = uint64_t(Support::lsbMask<uint32_t>(elementSize)) << (elementIndex * elementSize);
 
           op._readByteMask &= accessMask;
@@ -243,8 +194,7 @@ Error InstInternal::queryRWInfo(Arch arch, const BaseInst& inst, const Operand_*
         }
 
         if (memOp.hasIndex()) {
-          op.addOpFlags(OpRWFlags::kMemIndexRead);
-          op.addOpFlags(memOp.isPreOrPost() ? OpRWFlags::kMemIndexWrite : OpRWFlags::kNone);
+          op.addOpFlags(memOp.isPreOrPost() ? OpRWFlags::kMemIndexRW : OpRWFlags::kMemIndexRead);
         }
       }
     }
@@ -258,13 +208,15 @@ Error InstInternal::queryRWInfo(Arch arch, const BaseInst& inst, const Operand_*
 // =================================
 
 #ifndef ASMJIT_NO_INTROSPECTION
-Error InstInternal::queryFeatures(Arch arch, const BaseInst& inst, const Operand_* operands, size_t opCount, CpuFeatures* out) noexcept {
+Error queryFeatures(const BaseInst& inst, const Operand_* operands, size_t opCount, CpuFeatures* out) noexcept {
   // TODO: [ARM] QueryFeatures not implemented yet.
-  DebugUtils::unused(arch, inst, operands, opCount, out);
+  DebugUtils::unused(inst, operands, opCount, out);
   return kErrorOk;
 }
 #endif // !ASMJIT_NO_INTROSPECTION
 
+} // {InstInternal}
+
 // a64::InstInternal - Unit
 // ========================
 

deps/asmjit/src/asmjit/arm/a64instapi_p.h

@@ -18,17 +18,17 @@ ASMJIT_BEGIN_SUB_NAMESPACE(a64)
 namespace InstInternal {
 
 #ifndef ASMJIT_NO_TEXT
-Error ASMJIT_CDECL instIdToString(Arch arch, InstId instId, String& output) noexcept;
-InstId ASMJIT_CDECL stringToInstId(Arch arch, const char* s, size_t len) noexcept;
+Error ASMJIT_CDECL instIdToString(InstId instId, String& output) noexcept;
+InstId ASMJIT_CDECL stringToInstId(const char* s, size_t len) noexcept;
 #endif // !ASMJIT_NO_TEXT
 
 #ifndef ASMJIT_NO_VALIDATION
-Error ASMJIT_CDECL validate(Arch arch, const BaseInst& inst, const Operand_* operands, size_t opCount, ValidationFlags validationFlags) noexcept;
+Error ASMJIT_CDECL validate(const BaseInst& inst, const Operand_* operands, size_t opCount, ValidationFlags validationFlags) noexcept;
 #endif // !ASMJIT_NO_VALIDATION
 
 #ifndef ASMJIT_NO_INTROSPECTION
-Error ASMJIT_CDECL queryRWInfo(Arch arch, const BaseInst& inst, const Operand_* operands, size_t opCount, InstRWInfo* out) noexcept;
-Error ASMJIT_CDECL queryFeatures(Arch arch, const BaseInst& inst, const Operand_* operands, size_t opCount, CpuFeatures* out) noexcept;
+Error ASMJIT_CDECL queryRWInfo(const BaseInst& inst, const Operand_* operands, size_t opCount, InstRWInfo* out) noexcept;
+Error ASMJIT_CDECL queryFeatures(const BaseInst& inst, const Operand_* operands, size_t opCount, CpuFeatures* out) noexcept;
 #endif // !ASMJIT_NO_INTROSPECTION
 
 } // {InstInternal}

deps/asmjit/src/asmjit/arm/a64instdb.h

@@ -29,7 +29,7 @@ enum InstFlags : uint32_t {
   //! SIMD element access of half-words can only be used with v0..15.
   kInstFlagVH0_15 = 0x00000010u,
 
-  //! Instruction may consecutive registers if the number of operands is greater than 2.
+  //! Instruction uses consecutive registers if the number of operands is greater than 2.
   kInstFlagConsecutive = 0x00000080u
 };
 

deps/asmjit/src/asmjit/arm/a64instdb_p.h

@@ -7,6 +7,7 @@
 #define ASMJIT_ARM_A64INSTDB_H_P_INCLUDED
 
 #include "../core/codeholder.h"
+#include "../core/instdb_p.h"
 #include "../arm/a64instdb.h"
 #include "../arm/a64operand.h"
 
@@ -58,14 +59,14 @@ enum RWInfoType : uint32_t {
 // a64::InstDB - ElementType
 // =========================
 
-enum ElementType : uint8_t {
-  kET_None = Vec::kElementTypeNone,
-  kET_B    = Vec::kElementTypeB,
-  kET_H    = Vec::kElementTypeH,
-  kET_S    = Vec::kElementTypeS,
-  kET_D    = Vec::kElementTypeD,
-  kET_2H   = Vec::kElementTypeH2,
-  kET_4B   = Vec::kElementTypeB4
+enum InstElementType : uint8_t {
+  kET_None = uint8_t(VecElementType::kNone),
+  kET_B    = uint8_t(VecElementType::kB),
+  kET_H    = uint8_t(VecElementType::kH),
+  kET_S    = uint8_t(VecElementType::kS),
+  kET_D    = uint8_t(VecElementType::kD),
+  kET_2H   = uint8_t(VecElementType::kH2),
+  kET_4B   = uint8_t(VecElementType::kB4)
 };
 
 // a64::InstDB - GpType
@@ -192,6 +193,7 @@ enum EncodingId : uint32_t {
   kEncodingBaseMvnNeg,
   kEncodingBaseOp,
   kEncodingBaseOpImm,
+  kEncodingBasePrfm,
   kEncodingBaseR,
   kEncodingBaseRM_NoImm,
   kEncodingBaseRM_SImm10,
@@ -412,6 +414,13 @@ struct BaseRM_SImm10 {
   uint32_t immShift : 4;
 };
 
+struct BasePrfm {
+  uint32_t registerOp : 11;
+  uint32_t sOffsetOp  : 10;
+  uint32_t uOffsetOp  : 11;
+  uint32_t literalOp;
+};
+
 struct BaseLdSt {
   uint32_t uOffsetOp  : 10;
   uint32_t prePostOp  : 11;
@@ -787,6 +796,7 @@ extern const BaseMovKNZ baseMovKNZ[3];
 extern const BaseMvnNeg baseMvnNeg[3];
 extern const BaseOp baseOp[23];
 extern const BaseOpImm baseOpImm[14];
+extern const BasePrfm basePrfm[1];
 extern const BaseR baseR[10];
 extern const BaseRM_NoImm baseRM_NoImm[21];
 extern const BaseRM_SImm10 baseRM_SImm10[2];
@@ -843,27 +853,13 @@ extern const SimdTblTbx simdTblTbx[2];
 
 } // {EncodingData}
 
-// a64::InstDB - InstNameIndex
-// ===========================
-
-// ${NameLimits:Begin}
-// ------------------- Automatically generated, do not edit -------------------
-enum : uint32_t { kMaxNameSize = 9 };
-// ----------------------------------------------------------------------------
-// ${NameLimits:End}
-
-struct InstNameIndex {
-  uint16_t start;
-  uint16_t end;
-};
-
 // a64::InstDB - Tables
 // ====================
 
 #ifndef ASMJIT_NO_TEXT
-extern const uint32_t _instNameIndexTable[];
+extern const InstNameIndex instNameIndex;
 extern const char _instNameStringTable[];
-extern const InstNameIndex instNameIndex[26];
+extern const uint32_t _instNameIndexTable[];
 #endif // !ASMJIT_NO_TEXT
 
 } // {InstDB}

deps/asmjit/src/asmjit/arm/a64operand.cpp

@@ -56,7 +56,7 @@ UNIT(a64_operand) {
   EXPECT_EQ(vd_1.group(), RegGroup::kVec);
   EXPECT_EQ(vd_1.id(), 15u);
   EXPECT_TRUE(vd_1.isVecD2());
-  EXPECT_EQ(vd_1.elementType(), Vec::kElementTypeD);
+  EXPECT_EQ(vd_1.elementType(), VecElementType::kD);
   EXPECT_TRUE(vd_1.hasElementIndex());
   EXPECT_EQ(vd_1.elementIndex(), 1u);
 
@@ -65,7 +65,7 @@ UNIT(a64_operand) {
   EXPECT_EQ(vs_3.group(), RegGroup::kVec);
   EXPECT_EQ(vs_3.id(), 15u);
   EXPECT_TRUE(vs_3.isVecS4());
-  EXPECT_EQ(vs_3.elementType(), Vec::kElementTypeS);
+  EXPECT_EQ(vs_3.elementType(), VecElementType::kS);
   EXPECT_TRUE(vs_3.hasElementIndex());
   EXPECT_EQ(vs_3.elementIndex(), 3u);
 
@@ -74,7 +74,7 @@ UNIT(a64_operand) {
   EXPECT_EQ(vb_4.group(), RegGroup::kVec);
   EXPECT_EQ(vb_4.id(), 15u);
   EXPECT_TRUE(vb_4.isVecB4x4());
-  EXPECT_EQ(vb_4.elementType(), Vec::kElementTypeB4);
+  EXPECT_EQ(vb_4.elementType(), VecElementType::kB4);
   EXPECT_TRUE(vb_4.hasElementIndex());
   EXPECT_EQ(vb_4.elementIndex(), 3u);
 }

deps/asmjit/src/asmjit/arm/a64operand.h

@@ -13,24 +13,276 @@ ASMJIT_BEGIN_SUB_NAMESPACE(a64)
 //! \addtogroup asmjit_a64
 //! \{
 
-using arm::Reg;
-using arm::Mem;
-using arm::Gp;
-using arm::GpW;
-using arm::GpX;
+class GpW;
+class GpX;
 
-using arm::Vec;
-using arm::VecB;
-using arm::VecH;
-using arm::VecS;
-using arm::VecD;
-using arm::VecV;
+class VecB;
+class VecH;
+class VecS;
+class VecD;
+class VecV;
+
+//! General purpose register (AArch64).
+class Gp : public Reg {
+public:
+  ASMJIT_DEFINE_ABSTRACT_REG(Gp, Reg)
+
+  //! Special register id.
+  enum Id : uint32_t {
+    //! Register that depends on OS, could be used as TLS offset.
+    kIdOs = 18,
+    //! Frame pointer register id.
+    kIdFp = 29,
+    //! Link register id.
+    kIdLr = 30,
+    //! Stack register id.
+    kIdSp = 31,
+    //! Zero register id.
+    //!
+    //! Although zero register has the same id as stack register it has a special treatment, because we need to be
+    //! able to distinguish between these two at API level. Some instructions were designed to be used with SP and
+    //! some other with ZR - so we need a way to distinguish these two to make sure we emit the right thing.
+    //!
+    //! The number 63 is not random, when you perform `id & 31` you would always get 31 for both SP and ZR inputs,
+    //! which is the identifier used by AArch64 ISA to encode either SP or ZR depending on the instruction.
+    kIdZr = 63
+  };
+
+  //! Test whether this register is ZR register.
+  ASMJIT_INLINE_NODEBUG constexpr bool isZR() const noexcept { return id() == kIdZr; }
+  //! Test whether this register is SP register.
+  ASMJIT_INLINE_NODEBUG constexpr bool isSP() const noexcept { return id() == kIdSp; }
+
+  //! Cast this register to a 32-bit W register (returns a new operand).
+  ASMJIT_INLINE_NODEBUG GpW w() const noexcept;
+  //! \overload
+  ASMJIT_INLINE_NODEBUG GpW r32() const noexcept;
+  //! Cast this register to a 64-bit X register (returns a new operand).
+  ASMJIT_INLINE_NODEBUG GpX x() const noexcept;
+  //! \overload
+  ASMJIT_INLINE_NODEBUG GpX r64() const noexcept;
+};
+
+//! 32-bit general purpose W register (AArch64).
+class GpW : public Gp { ASMJIT_DEFINE_FINAL_REG(GpW, Gp, RegTraits<RegType::kARM_GpW>); };
+//! 64-bit general purpose X register (AArch64).
+class GpX : public Gp { ASMJIT_DEFINE_FINAL_REG(GpX, Gp, RegTraits<RegType::kARM_GpX>); };
+
+#ifndef _DOXYGEN
+ASMJIT_INLINE_NODEBUG GpW Gp::w() const noexcept { return GpW(id()); }
+ASMJIT_INLINE_NODEBUG GpX Gp::x() const noexcept { return GpX(id()); }
+ASMJIT_INLINE_NODEBUG GpW Gp::r32() const noexcept { return GpW(id()); }
+ASMJIT_INLINE_NODEBUG GpX Gp::r64() const noexcept { return GpX(id()); }
+#endif
+
+//! Vector element type (AArch64).
+enum class VecElementType : uint32_t {
+  //! No element type specified.
+  kNone = 0,
+  //! Byte elements (B8 or B16).
+  kB,
+  //! Halfword elements (H4 or H8).
+  kH,
+  //! Singleword elements (S2 or S4).
+  kS,
+  //! Doubleword elements (D2).
+  kD,
+  //! Byte elements grouped by 4 bytes (B4).
+  //!
+  //! \note This element-type is only used by few instructions.
+  kB4,
+  //! Halfword elements grouped by 2 halfwords (H2).
+  //!
+  //! \note This element-type is only used by few instructions.
+  kH2,
+
+  //! Maximum value of \ref VecElementType
+  kMaxValue = kH2
+};
+
+//! Vector register (AArch64).
+class Vec : public BaseVec {
+public:
+  ASMJIT_DEFINE_ABSTRACT_REG(Vec, BaseVec)
+
+  //! \cond
+  //! Shortcuts.
+  enum SignatureReg : uint32_t {
+    kSignatureElementB = uint32_t(VecElementType::kB) << kSignatureRegElementTypeShift,
+    kSignatureElementH = uint32_t(VecElementType::kH) << kSignatureRegElementTypeShift,
+    kSignatureElementS = uint32_t(VecElementType::kS) << kSignatureRegElementTypeShift,
+    kSignatureElementD = uint32_t(VecElementType::kD) << kSignatureRegElementTypeShift,
+    kSignatureElementB4 = uint32_t(VecElementType::kB4) << kSignatureRegElementTypeShift,
+    kSignatureElementH2 = uint32_t(VecElementType::kH2) << kSignatureRegElementTypeShift
+  };
+  //! \endcond
+
+  //! Returns whether the register has element type or element index (or both).
+  ASMJIT_INLINE_NODEBUG constexpr bool hasElementTypeOrIndex() const noexcept { return _signature.hasField<kSignatureRegElementTypeMask | kSignatureRegElementFlagMask>(); }
+
+  //! Returns whether the vector register has associated a vector element type.
+  ASMJIT_INLINE_NODEBUG constexpr bool hasElementType() const noexcept { return _signature.hasField<kSignatureRegElementTypeMask>(); }
+  //! Returns vector element type of the register.
+  ASMJIT_INLINE_NODEBUG constexpr VecElementType elementType() const noexcept { return VecElementType(_signature.getField<kSignatureRegElementTypeMask>()); }
+  //! Sets vector element type of the register to `elementType`.
+  ASMJIT_INLINE_NODEBUG void setElementType(VecElementType elementType) noexcept { _signature.setField<kSignatureRegElementTypeMask>(uint32_t(elementType)); }
+  //! Resets vector element type to none.
+  ASMJIT_INLINE_NODEBUG void resetElementType() noexcept { _signature.setField<kSignatureRegElementTypeMask>(0); }
+
+  ASMJIT_INLINE_NODEBUG constexpr bool isVecB8() const noexcept { return _signature.subset(kBaseSignatureMask | kSignatureRegElementTypeMask) == (RegTraits<RegType::kARM_VecD>::kSignature | kSignatureElementB); }
+  ASMJIT_INLINE_NODEBUG constexpr bool isVecH4() const noexcept { return _signature.subset(kBaseSignatureMask | kSignatureRegElementTypeMask) == (RegTraits<RegType::kARM_VecD>::kSignature | kSignatureElementH); }
+  ASMJIT_INLINE_NODEBUG constexpr bool isVecS2() const noexcept { return _signature.subset(kBaseSignatureMask | kSignatureRegElementTypeMask) == (RegTraits<RegType::kARM_VecD>::kSignature | kSignatureElementS); }
+  ASMJIT_INLINE_NODEBUG constexpr bool isVecD1() const noexcept { return _signature.subset(kBaseSignatureMask | kSignatureRegElementTypeMask) == (RegTraits<RegType::kARM_VecD>::kSignature); }
+
+  ASMJIT_INLINE_NODEBUG constexpr bool isVecB16() const noexcept { return _signature.subset(kBaseSignatureMask | kSignatureRegElementTypeMask) == (RegTraits<RegType::kARM_VecV>::kSignature | kSignatureElementB); }
+  ASMJIT_INLINE_NODEBUG constexpr bool isVecH8() const noexcept { return _signature.subset(kBaseSignatureMask | kSignatureRegElementTypeMask) == (RegTraits<RegType::kARM_VecV>::kSignature | kSignatureElementH); }
+  ASMJIT_INLINE_NODEBUG constexpr bool isVecS4() const noexcept { return _signature.subset(kBaseSignatureMask | kSignatureRegElementTypeMask) == (RegTraits<RegType::kARM_VecV>::kSignature | kSignatureElementS); }
+  ASMJIT_INLINE_NODEBUG constexpr bool isVecD2() const noexcept { return _signature.subset(kBaseSignatureMask | kSignatureRegElementTypeMask) == (RegTraits<RegType::kARM_VecV>::kSignature | kSignatureElementD); }
+  ASMJIT_INLINE_NODEBUG constexpr bool isVecB4x4() const noexcept { return _signature.subset(kBaseSignatureMask | kSignatureRegElementTypeMask) == (RegTraits<RegType::kARM_VecV>::kSignature | kSignatureElementB4); }
+  ASMJIT_INLINE_NODEBUG constexpr bool isVecH2x4() const noexcept { return _signature.subset(kBaseSignatureMask | kSignatureRegElementTypeMask) == (RegTraits<RegType::kARM_VecV>::kSignature | kSignatureElementH2); }
+
+  //! Creates a cloned register with element access.
+  ASMJIT_INLINE_NODEBUG Vec at(uint32_t elementIndex) const noexcept {
+    return Vec((signature() & ~kSignatureRegElementIndexMask) | (elementIndex << kSignatureRegElementIndexShift) | kSignatureRegElementFlagMask, id());
+  }
+
+  //! Cast this register to an 8-bit B register (AArch64 only).
+  ASMJIT_INLINE_NODEBUG VecB b() const noexcept;
+  //! Cast this register to a 16-bit H register (AArch64 only).
+  ASMJIT_INLINE_NODEBUG VecH h() const noexcept;
+  //! Cast this register to a 32-bit S register.
+  ASMJIT_INLINE_NODEBUG VecS s() const noexcept;
+  //! Cast this register to a 64-bit D register.
+  ASMJIT_INLINE_NODEBUG VecD d() const noexcept;
+  //! Cast this register to a 128-bit Q register.
+  ASMJIT_INLINE_NODEBUG VecV q() const noexcept;
+  //! Cast this register to a 128-bit V register.
+  ASMJIT_INLINE_NODEBUG VecV v() const noexcept;
+
+  //! Casts this register to b (clone).
+  ASMJIT_INLINE_NODEBUG Vec v8() const noexcept;
+  //! Casts this register to h (clone).
+  ASMJIT_INLINE_NODEBUG Vec v16() const noexcept;
+  //! Casts this register to s (clone).
+  ASMJIT_INLINE_NODEBUG Vec v32() const noexcept;
+  //! Casts this register to d (clone).
+  ASMJIT_INLINE_NODEBUG Vec v64() const noexcept;
+  //! Casts this register to q (clone).
+  ASMJIT_INLINE_NODEBUG Vec v128() const noexcept;
+
+  //! Cast this register to a 128-bit V.B[elementIndex] register.
+  ASMJIT_INLINE_NODEBUG VecV b(uint32_t elementIndex) const noexcept;
+  //! Cast this register to a 128-bit V.H[elementIndex] register.
+  ASMJIT_INLINE_NODEBUG VecV h(uint32_t elementIndex) const noexcept;
+  //! Cast this register to a 128-bit V.S[elementIndex] register.
+  ASMJIT_INLINE_NODEBUG VecV s(uint32_t elementIndex) const noexcept;
+  //! Cast this register to a 128-bit V.D[elementIndex] register.
+  ASMJIT_INLINE_NODEBUG VecV d(uint32_t elementIndex) const noexcept;
+  //! Cast this register to a 128-bit V.H2[elementIndex] register.
+  ASMJIT_INLINE_NODEBUG VecV h2(uint32_t elementIndex) const noexcept;
+  //! Cast this register to a 128-bit V.B4[elementIndex] register.
+  ASMJIT_INLINE_NODEBUG VecV b4(uint32_t elementIndex) const noexcept;
+
+  //! Cast this register to V.8B.
+  ASMJIT_INLINE_NODEBUG VecD b8() const noexcept;
+  //! Cast this register to V.16B.
+  ASMJIT_INLINE_NODEBUG VecV b16() const noexcept;
+  //! Cast this register to V.2H.
+  ASMJIT_INLINE_NODEBUG VecS h2() const noexcept;
+  //! Cast this register to V.4H.
+  ASMJIT_INLINE_NODEBUG VecD h4() const noexcept;
+  //! Cast this register to V.8H.
+  ASMJIT_INLINE_NODEBUG VecV h8() const noexcept;
+  //! Cast this register to V.2S.
+  ASMJIT_INLINE_NODEBUG VecD s2() const noexcept;
+  //! Cast this register to V.4S.
+  ASMJIT_INLINE_NODEBUG VecV s4() const noexcept;
+  //! Cast this register to V.2D.
+  ASMJIT_INLINE_NODEBUG VecV d2() const noexcept;
+
+  static ASMJIT_INLINE_NODEBUG constexpr OperandSignature _makeElementAccessSignature(VecElementType elementType, uint32_t elementIndex) noexcept {
+    return OperandSignature{
+      uint32_t(RegTraits<RegType::kARM_VecV>::kSignature)       |
+      uint32_t(kSignatureRegElementFlagMask)                    |
+      (uint32_t(elementType) << kSignatureRegElementTypeShift)  |
+      (uint32_t(elementIndex << kSignatureRegElementIndexShift))};
+  }
+};
+
+//! 8-bit view (S) of VFP/SIMD register.
+class VecB : public Vec {
+public:
+  ASMJIT_DEFINE_FINAL_REG(VecB, Vec, RegTraits<RegType::kARM_VecB>)
+};
+
+//! 16-bit view (S) of VFP/SIMD register.
+class VecH : public Vec {
+public:
+  ASMJIT_DEFINE_FINAL_REG(VecH, Vec, RegTraits<RegType::kARM_VecH>)
+};
+
+//! 32-bit view (S) of VFP/SIMD register.
+class VecS : public Vec {
+public:
+  ASMJIT_DEFINE_FINAL_REG(VecS, Vec, RegTraits<RegType::kARM_VecS>)
+};
+
+//! 64-bit view (D) of VFP/SIMD register.
+class VecD : public Vec {
+public:
+  ASMJIT_DEFINE_FINAL_REG(VecD, Vec, RegTraits<RegType::kARM_VecD>)
+};
+
+//! 128-bit vector register (Q or V).
+class VecV : public Vec {
+public:
+  ASMJIT_DEFINE_FINAL_REG(VecV, Vec, RegTraits<RegType::kARM_VecV>)
+};
+
+ASMJIT_INLINE_NODEBUG VecB Vec::b() const noexcept { return VecB(id()); }
+ASMJIT_INLINE_NODEBUG VecH Vec::h() const noexcept { return VecH(id()); }
+ASMJIT_INLINE_NODEBUG VecS Vec::s() const noexcept { return VecS(id()); }
+ASMJIT_INLINE_NODEBUG VecD Vec::d() const noexcept { return VecD(id()); }
+ASMJIT_INLINE_NODEBUG VecV Vec::q() const noexcept { return VecV(id()); }
+ASMJIT_INLINE_NODEBUG VecV Vec::v() const noexcept { return VecV(id()); }
+
+ASMJIT_INLINE_NODEBUG Vec Vec::v8() const noexcept { return VecB(id()); }
+ASMJIT_INLINE_NODEBUG Vec Vec::v16() const noexcept { return VecH(id()); }
+ASMJIT_INLINE_NODEBUG Vec Vec::v32() const noexcept { return VecS(id()); }
+ASMJIT_INLINE_NODEBUG Vec Vec::v64() const noexcept { return VecD(id()); }
+ASMJIT_INLINE_NODEBUG Vec Vec::v128() const noexcept { return VecV(id()); }
+
+ASMJIT_INLINE_NODEBUG VecV Vec::b(uint32_t elementIndex) const noexcept { return VecV(_makeElementAccessSignature(VecElementType::kB, elementIndex), id()); }
+ASMJIT_INLINE_NODEBUG VecV Vec::h(uint32_t elementIndex) const noexcept { return VecV(_makeElementAccessSignature(VecElementType::kH, elementIndex), id()); }
+ASMJIT_INLINE_NODEBUG VecV Vec::s(uint32_t elementIndex) const noexcept { return VecV(_makeElementAccessSignature(VecElementType::kS, elementIndex), id()); }
+ASMJIT_INLINE_NODEBUG VecV Vec::d(uint32_t elementIndex) const noexcept { return VecV(_makeElementAccessSignature(VecElementType::kD, elementIndex), id()); }
+ASMJIT_INLINE_NODEBUG VecV Vec::h2(uint32_t elementIndex) const noexcept { return VecV(_makeElementAccessSignature(VecElementType::kH2, elementIndex), id()); }
+ASMJIT_INLINE_NODEBUG VecV Vec::b4(uint32_t elementIndex) const noexcept { return VecV(_makeElementAccessSignature(VecElementType::kB4, elementIndex), id()); }
+
+ASMJIT_INLINE_NODEBUG VecD Vec::b8() const noexcept { return VecD(OperandSignature{VecD::kSignature | kSignatureElementB}, id()); }
+ASMJIT_INLINE_NODEBUG VecS Vec::h2() const noexcept { return VecS(OperandSignature{VecS::kSignature | kSignatureElementH}, id()); }
+ASMJIT_INLINE_NODEBUG VecD Vec::h4() const noexcept { return VecD(OperandSignature{VecD::kSignature | kSignatureElementH}, id()); }
+ASMJIT_INLINE_NODEBUG VecD Vec::s2() const noexcept { return VecD(OperandSignature{VecD::kSignature | kSignatureElementS}, id()); }
+ASMJIT_INLINE_NODEBUG VecV Vec::b16() const noexcept { return VecV(OperandSignature{VecV::kSignature | kSignatureElementB}, id()); }
+ASMJIT_INLINE_NODEBUG VecV Vec::h8() const noexcept { return VecV(OperandSignature{VecV::kSignature | kSignatureElementH}, id()); }
+ASMJIT_INLINE_NODEBUG VecV Vec::s4() const noexcept { return VecV(OperandSignature{VecV::kSignature | kSignatureElementS}, id()); }
+ASMJIT_INLINE_NODEBUG VecV Vec::d2() const noexcept { return VecV(OperandSignature{VecV::kSignature | kSignatureElementD}, id()); }
 
 #ifndef _DOXYGEN
 namespace regs {
 #endif
 
-using namespace ::asmjit::arm::regs;
+//! Creates a 32-bit W register operand.
+static ASMJIT_INLINE_NODEBUG constexpr GpW w(uint32_t id) noexcept { return GpW(id); }
+//! Creates a 64-bit X register operand.
+static ASMJIT_INLINE_NODEBUG constexpr GpX x(uint32_t id) noexcept { return GpX(id); }
+
+//! Creates a 32-bit S register operand.
+static ASMJIT_INLINE_NODEBUG constexpr VecS s(uint32_t id) noexcept { return VecS(id); }
+//! Creates a 64-bit D register operand.
+static ASMJIT_INLINE_NODEBUG constexpr VecD d(uint32_t id) noexcept { return VecD(id); }
+//! Creates a 1282-bit V register operand.
+static ASMJIT_INLINE_NODEBUG constexpr VecV v(uint32_t id) noexcept { return VecV(id); }
 
 static constexpr GpW w0 = GpW(0);
 static constexpr GpW w1 = GpW(1);
@@ -305,8 +557,94 @@ static constexpr VecV v31 = VecV(31);
 using namespace regs;
 #endif
 
+//! \name Shift Operation Construction
+//! \{
+
+//! Constructs a `UXTB #value` extend and shift (unsigned byte extend) (AArch64).
+static ASMJIT_INLINE_NODEBUG constexpr Shift uxtb(uint32_t value) noexcept { return Shift(ShiftOp::kUXTB, value); }
+//! Constructs a `UXTH #value` extend and shift (unsigned hword extend) (AArch64).
+static ASMJIT_INLINE_NODEBUG constexpr Shift uxth(uint32_t value) noexcept { return Shift(ShiftOp::kUXTH, value); }
+//! Constructs a `UXTW #value` extend and shift (unsigned word extend) (AArch64).
+static ASMJIT_INLINE_NODEBUG constexpr Shift uxtw(uint32_t value) noexcept { return Shift(ShiftOp::kUXTW, value); }
+//! Constructs a `UXTX #value` extend and shift (unsigned dword extend) (AArch64).
+static ASMJIT_INLINE_NODEBUG constexpr Shift uxtx(uint32_t value) noexcept { return Shift(ShiftOp::kUXTX, value); }
+
+//! Constructs a `SXTB #value` extend and shift (signed byte extend) (AArch64).
+static ASMJIT_INLINE_NODEBUG constexpr Shift sxtb(uint32_t value) noexcept { return Shift(ShiftOp::kSXTB, value); }
+//! Constructs a `SXTH #value` extend and shift (signed hword extend) (AArch64).
+static ASMJIT_INLINE_NODEBUG constexpr Shift sxth(uint32_t value) noexcept { return Shift(ShiftOp::kSXTH, value); }
+//! Constructs a `SXTW #value` extend and shift (signed word extend) (AArch64).
+static ASMJIT_INLINE_NODEBUG constexpr Shift sxtw(uint32_t value) noexcept { return Shift(ShiftOp::kSXTW, value); }
+//! Constructs a `SXTX #value` extend and shift (signed dword extend) (AArch64).
+static ASMJIT_INLINE_NODEBUG constexpr Shift sxtx(uint32_t value) noexcept { return Shift(ShiftOp::kSXTX, value); }
+
+//! \}
+
+//! \name Memory Operand Construction
+//! \{
+
+//! Creates `[base, offset]` memory operand (offset mode) (AArch64).
+static ASMJIT_INLINE_NODEBUG constexpr Mem ptr(const Gp& base, int32_t offset = 0) noexcept {
+  return Mem(base, offset);
+}
+
+//! Creates `[base, offset]!` memory operand (pre-index mode) (AArch64).
+static ASMJIT_INLINE_NODEBUG constexpr Mem ptr_pre(const Gp& base, int32_t offset = 0) noexcept {
+  return Mem(base, offset, OperandSignature::fromValue<Mem::kSignatureMemOffsetModeMask>(OffsetMode::kPreIndex));
+}
+
+//! Creates `[base], offset` memory operand (post-index mode) (AArch64).
+static ASMJIT_INLINE_NODEBUG constexpr Mem ptr_post(const Gp& base, int32_t offset = 0) noexcept {
+  return Mem(base, offset, OperandSignature::fromValue<Mem::kSignatureMemOffsetModeMask>(OffsetMode::kPostIndex));
+}
+
+//! Creates `[base, index]` memory operand (AArch64).
+static ASMJIT_INLINE_NODEBUG constexpr Mem ptr(const Gp& base, const Gp& index) noexcept {
+  return Mem(base, index);
+}
+
+//! Creates `[base, index]!` memory operand (pre-index mode) (AArch64).
+static ASMJIT_INLINE_NODEBUG constexpr Mem ptr_pre(const Gp& base, const Gp& index) noexcept {
+  return Mem(base, index, OperandSignature::fromValue<Mem::kSignatureMemOffsetModeMask>(OffsetMode::kPreIndex));
+}
+
+//! Creates `[base], index` memory operand (post-index mode) (AArch64).
+static ASMJIT_INLINE_NODEBUG constexpr Mem ptr_post(const Gp& base, const Gp& index) noexcept {
+  return Mem(base, index, OperandSignature::fromValue<Mem::kSignatureMemOffsetModeMask>(OffsetMode::kPostIndex));
+}
+
+//! Creates `[base, index, SHIFT_OP #shift]` memory operand (AArch64).
+static ASMJIT_INLINE_NODEBUG constexpr Mem ptr(const Gp& base, const Gp& index, const Shift& shift) noexcept {
+  return Mem(base, index, shift);
+}
+
+//! Creates `[base, offset]` memory operand (AArch64).
+static ASMJIT_INLINE_NODEBUG constexpr Mem ptr(const Label& base, int32_t offset = 0) noexcept {
+  return Mem(base, offset);
+}
+
+// TODO: [ARM] PC + offset address.
+#if 0
+//! Creates `[PC + offset]` (relative) memory operand.
+static ASMJIT_INLINE_NODEBUG constexpr Mem ptr(const PC& pc, int32_t offset = 0) noexcept {
+  return Mem(pc, offset);
+}
+#endif
+
+//! \}
+
 //! \}
 
 ASMJIT_END_SUB_NAMESPACE
 
+//! \cond INTERNAL
+ASMJIT_BEGIN_NAMESPACE
+ASMJIT_DEFINE_TYPE_ID(a64::GpW, TypeId::kInt32);
+ASMJIT_DEFINE_TYPE_ID(a64::GpX, TypeId::kInt64);
+ASMJIT_DEFINE_TYPE_ID(a64::VecS, TypeId::kFloat32x1);
+ASMJIT_DEFINE_TYPE_ID(a64::VecD, TypeId::kFloat64x1);
+ASMJIT_DEFINE_TYPE_ID(a64::VecV, TypeId::kInt32x4);
+ASMJIT_END_NAMESPACE
+//! \endcond
+
 #endif // ASMJIT_ARM_A64OPERAND_H_INCLUDED

deps/asmjit/src/asmjit/arm/a64rapass.cpp

@@ -131,7 +131,7 @@ Error RACFGBuilder::onInst(InstNode* inst, InstControlFlow& controlType, RAInstB
     InstId instId = inst->id();
     uint32_t opCount = inst->opCount();
     const Operand* opArray = inst->operands();
-    ASMJIT_PROPAGATE(InstInternal::queryRWInfo(_arch, inst->baseInst(), opArray, opCount, &rwInfo));
+    ASMJIT_PROPAGATE(InstInternal::queryRWInfo(inst->baseInst(), opArray, opCount, &rwInfo));
 
     const InstDB::InstInfo& instInfo = InstDB::infoById(instId);
     uint32_t singleRegOps = 0;
@@ -230,7 +230,7 @@ Error RACFGBuilder::onInst(InstNode* inst, InstControlFlow& controlType, RAInstB
             if (reg.as<Vec>().hasElementIndex()) {
               // Only the first 0..15 registers can be used if the register uses
               // element accessor that accesses half-words (h[0..7] elements).
-              if (instInfo.hasFlag(InstDB::kInstFlagVH0_15) && reg.as<Vec>().elementType() == Vec::kElementTypeH) {
+              if (instInfo.hasFlag(InstDB::kInstFlagVH0_15) && reg.as<Vec>().elementType() == VecElementType::kH) {
                 if (Support::test(flags, RATiedFlags::kUse))
                   useId &= 0x0000FFFFu;
                 else
@@ -595,14 +595,14 @@ void ARMRAPass::onInit() noexcept {
   _archTraits = &ArchTraits::byArch(arch);
   _physRegCount.set(RegGroup::kGp, 32);
   _physRegCount.set(RegGroup::kVec, 32);
-  _physRegCount.set(RegGroup::kExtraVirt2, 0);
+  _physRegCount.set(RegGroup::kMask, 0);
   _physRegCount.set(RegGroup::kExtraVirt3, 0);
   _buildPhysIndex();
 
   _availableRegCount = _physRegCount;
   _availableRegs[RegGroup::kGp] = Support::lsbMask<uint32_t>(_physRegCount.get(RegGroup::kGp));
   _availableRegs[RegGroup::kVec] = Support::lsbMask<uint32_t>(_physRegCount.get(RegGroup::kVec));
-  _availableRegs[RegGroup::kExtraVirt3] = Support::lsbMask<uint32_t>(_physRegCount.get(RegGroup::kExtraVirt2));
+  _availableRegs[RegGroup::kMask] = Support::lsbMask<uint32_t>(_physRegCount.get(RegGroup::kMask));
   _availableRegs[RegGroup::kExtraVirt3] = Support::lsbMask<uint32_t>(_physRegCount.get(RegGroup::kExtraVirt3));
 
   _scratchRegIndexes[0] = uint8_t(27);
@@ -612,7 +612,9 @@ void ARMRAPass::onInit() noexcept {
   // make unavailable all registers that are special and cannot be used in general.
   bool hasFP = _func->frame().hasPreservedFP();
 
-  if (hasFP)
+  // Apple ABI requires that the frame-pointer register is not changed by leaf functions and properly updated
+  // by non-leaf functions. So, let's make this register unavailable as it's just not safe to update it.
+  if (hasFP || cc()->environment().isDarwin())
     makeUnavailable(RegGroup::kGp, Gp::kIdFp);
 
   makeUnavailable(RegGroup::kGp, Gp::kIdSp);

deps/asmjit/src/asmjit/arm/armformatter.cpp

@@ -9,7 +9,7 @@
 #include "../core/misc_p.h"
 #include "../core/support.h"
 #include "../arm/armformatter_p.h"
-#include "../arm/armoperand.h"
+#include "../arm/a64operand.h"
 #include "../arm/a64instapi_p.h"
 #include "../arm/a64instdb_p.h"
 
@@ -31,26 +31,45 @@ Error FormatterInternal::formatFeature(String& sb, uint32_t featureId) noexcept
     "ARMv8a\0"
     "THUMB\0"
     "THUMBv2\0"
+    "ABLE\0"
+    "ADERR\0"
     "AES\0"
     "AFP\0"
+    "AIE\0"
+    "AMU1\0"
+    "AMU1_1\0"
+    "ANERR\0"
     "ASIMD\0"
     "BF16\0"
+    "BRBE\0"
     "BTI\0"
+    "BWE\0"
     "CCIDX\0"
     "CHK\0"
     "CLRBHB\0"
+    "CMOW\0"
+    "CONSTPACFIELD\0"
+    "CPA\0"
+    "CPA2\0"
     "CPUID\0"
     "CRC32\0"
     "CSSC\0"
+    "CSV2\0"
+    "CSV2_3\0"
+    "CSV3\0"
     "D128\0"
     "DGH\0"
     "DIT\0"
     "DOTPROD\0"
     "DPB\0"
     "DPB2\0"
+    "EBEP\0"
     "EBF16\0"
+    "ECBHB\0"
     "ECV\0"
+    "EDHSR\0"
     "EDSP\0"
+    "FAMINMAX\0"
     "FCMA\0"
     "FGT\0"
     "FGT2\0"
@@ -61,13 +80,25 @@ Error FormatterInternal::formatFeature(String& sb, uint32_t featureId) noexcept
     "FP\0"
     "FP16\0"
     "FP16CONV\0"
+    "FP8\0"
+    "FP8DOT2\0"
+    "FP8DOT4\0"
+    "FP8FMA\0"
+    "FPMR\0"
     "FRINTTS\0"
     "GCS\0"
+    "HACDBS\0"
+    "HAFDBS\0"
+    "HAFT\0"
+    "HDBSS\0"
     "HBC\0"
     "HCX\0"
+    "HPDS\0"
+    "HPDS2\0"
     "I8MM\0"
     "IDIVA\0"
     "IDIVT\0"
+    "ITE\0"
     "JSCVT\0"
     "LOR\0"
     "LRCPC\0"
@@ -79,12 +110,24 @@ Error FormatterInternal::formatFeature(String& sb, uint32_t featureId) noexcept
     "LSE\0"
     "LSE128\0"
     "LSE2\0"
+    "LUT\0"
+    "LVA\0"
+    "LVA3\0"
+    "MEC\0"
     "MOPS\0"
     "MPAM\0"
     "MTE\0"
     "MTE2\0"
     "MTE3\0"
     "MTE4\0"
+    "MTE_ASYM_FAULT\0"
+    "MTE_ASYNC\0"
+    "MTE_CANONICAL_TAGS\0"
+    "MTE_NO_ADDRESS_TAGS\0"
+    "MTE_PERM_S1\0"
+    "MTE_STORE_ONLY\0"
+    "MTE_TAGGED_FAR\0"
+    "MTPMU\0"
     "NMI\0"
     "NV\0"
     "NV2\0"
@@ -92,19 +135,28 @@ Error FormatterInternal::formatFeature(String& sb, uint32_t featureId) noexcept
     "PAN2\0"
     "PAN3\0"
     "PAUTH\0"
+    "PFAR\0"
     "PMU\0"
     "PMULL\0"
     "PRFMSLC\0"
     "RAS\0"
     "RAS1_1\0"
     "RAS2\0"
+    "RASSA2\0"
     "RDM\0"
     "RME\0"
     "RNG\0"
     "RNG_TRAP\0"
     "RPRES\0"
     "RPRFM\0"
+    "S1PIE\0"
+    "S1POE\0"
+    "S2PIE\0"
+    "S2POE\0"
     "SB\0"
+    "SCTLR2\0"
+    "SEBEP\0"
+    "SEL2\0"
     "SHA1\0"
     "SHA256\0"
     "SHA3\0"
@@ -121,14 +173,32 @@ Error FormatterInternal::formatFeature(String& sb, uint32_t featureId) noexcept
     "SME_F16F32\0"
     "SME_F32F32\0"
     "SME_F64F64\0"
+    "SME_F8F16\0"
+    "SME_F8F32\0"
     "SME_FA64\0"
     "SME_I16I32\0"
     "SME_I16I64\0"
     "SME_I8I32\0"
+    "SME_LUTv2\0"
+    "SPE\0"
+    "SPE1_1\0"
+    "SPE1_2\0"
+    "SPE1_3\0"
+    "SPE1_4\0"
+    "SPE_ALTCLK\0"
+    "SPE_CRR\0"
+    "SPE_EFT\0"
+    "SPE_FDS\0"
+    "SPE_FPF\0"
+    "SPE_SME\0"
     "SPECRES\0"
     "SPECRES2\0"
+    "SPMU\0"
     "SSBS\0"
     "SSBS2\0"
+    "SSVE_FP8DOT2\0"
+    "SSVE_FP8DOT4\0"
+    "SSVE_FP8FMA\0"
     "SVE\0"
     "SVE2\0"
     "SVE2_1\0"
@@ -146,25 +216,35 @@ Error FormatterInternal::formatFeature(String& sb, uint32_t featureId) noexcept
     "SYSINSTR128\0"
     "SYSREG128\0"
     "THE\0"
+    "TLBIOS\0"
+    "TLBIRANGE\0"
+    "TLBIW\0"
     "TME\0"
     "TRF\0"
     "UAO\0"
     "VFP_D32\0"
     "VHE\0"
+    "VMID16\0"
     "WFXT\0"
+    "XNX\0"
     "XS\0"
     "<Unknown>\0";
 
   static const uint16_t sFeatureIndex[] = {
-    0, 5, 11, 17, 24, 30, 38, 42, 46, 52, 57, 61, 67, 71, 78, 84, 90, 95, 100,
-    104, 108, 116, 120, 125, 131, 135, 140, 145, 149, 154, 158, 164, 171, 176,
-    179, 184, 193, 201, 205, 209, 213, 218, 224, 230, 236, 240, 246, 253, 260,
-    265, 278, 285, 289, 296, 301, 306, 311, 315, 320, 325, 330, 334, 337, 341,
-    345, 350, 355, 361, 365, 371, 379, 383, 390, 395, 399, 403, 407, 416, 422,
-    428, 431, 436, 443, 448, 455, 459, 463, 467, 472, 479, 490, 501, 513, 524,
-    535, 546, 557, 566, 577, 588, 598, 606, 615, 620, 626, 630, 635, 642, 650,
-    661, 670, 682, 692, 702, 712, 721, 734, 743, 751, 763, 773, 777, 781, 785,
-    789, 797, 801, 806, 809
+    0, 5, 11, 17, 24, 30, 38, 43, 49, 53, 57, 61, 66, 73, 79, 85, 90, 95, 99,
+    103, 109, 113, 120, 125, 139, 143, 148, 154, 160, 165, 170, 177, 182, 187,
+    191, 195, 203, 207, 212, 217, 223, 229, 233, 239, 244, 253, 258, 262, 267,
+    271, 277, 284, 289, 292, 297, 306, 310, 318, 326, 333, 338, 346, 350, 357,
+    364, 369, 375, 379, 383, 388, 394, 399, 405, 411, 415, 421, 425, 431, 438,
+    445, 450, 463, 470, 474, 481, 486, 490, 494, 499, 503, 508, 513, 517, 522,
+    527, 532, 547, 557, 576, 596, 608, 623, 638, 644, 648, 651, 655, 659, 664,
+    669, 675, 680, 684, 690, 698, 702, 709, 714, 721, 725, 729, 733, 742, 748,
+    754, 760, 766, 772, 778, 781, 788, 794, 799, 804, 811, 816, 823, 827, 831,
+    835, 840, 847, 858, 869, 881, 892, 903, 914, 925, 935, 945, 954, 965, 976,
+    986, 996, 1000, 1007, 1014, 1021, 1028, 1039, 1047, 1055, 1063, 1071, 1079,
+    1087, 1096, 1101, 1106, 1112, 1125, 1138, 1150, 1154, 1159, 1166, 1174, 1185,
+    1194, 1206, 1216, 1226, 1236, 1245, 1258, 1267, 1275, 1287, 1297, 1301, 1308,
+    1318, 1324, 1328, 1332, 1336, 1344, 1348, 1355, 1360, 1364, 1367
   };
   // @EnumStringEnd@
 
@@ -178,14 +258,14 @@ ASMJIT_FAVOR_SIZE Error FormatterInternal::formatCondCode(String& sb, CondCode c
   static const char condCodeData[] =
     "al\0" "na\0"
     "eq\0" "ne\0"
-    "cs\0" "cc\0" "mi\0" "pl\0" "vs\0" "vc\0"
+    "hs\0" "lo\0" "mi\0" "pl\0" "vs\0" "vc\0"
     "hi\0" "ls\0" "ge\0" "lt\0" "gt\0" "le\0"
     "<Unknown>";
   return sb.append(condCodeData + Support::min<uint32_t>(uint32_t(cc), 16u) * 3);
 }
 
 ASMJIT_FAVOR_SIZE Error FormatterInternal::formatShiftOp(String& sb, ShiftOp shiftOp) noexcept {
-  const char* str = "<Unknown>";
+  const char* str = nullptr;
   switch (shiftOp) {
     case ShiftOp::kLSL: str = "lsl"; break;
     case ShiftOp::kLSR: str = "lsr"; break;
@@ -201,6 +281,7 @@ ASMJIT_FAVOR_SIZE Error FormatterInternal::formatShiftOp(String& sb, ShiftOp shi
     case ShiftOp::kSXTH: str = "sxth"; break;
     case ShiftOp::kSXTW: str = "sxtw"; break;
     case ShiftOp::kSXTX: str = "sxtx"; break;
+    default: str = "<Unknown>"; break;
   }
   return sb.append(str);
 }
@@ -208,6 +289,25 @@ ASMJIT_FAVOR_SIZE Error FormatterInternal::formatShiftOp(String& sb, ShiftOp shi
 // arm::FormatterInternal - Format Register
 // ========================================
 
+struct FormatElementData {
+  char letter;
+  uint8_t elementCount;
+  uint8_t onlyIndex;
+  uint8_t reserved;
+};
+
+static constexpr FormatElementData formatElementDataTable[9] = {
+  { '?' , 0 , 0, 0 }, // None
+  { 'b' , 16, 0, 0 }, // bX or b[index]
+  { 'h' , 8 , 0, 0 }, // hX or h[index]
+  { 's' , 4 , 0, 0 }, // sX or s[index]
+  { 'd' , 2 , 0, 0 }, // dX or d[index]
+  { 'b' , 4 , 1, 0 }, // ?? or b4[index]
+  { 'h' , 2 , 1, 0 }, // ?? or h2[index]
+  { '?' , 0 , 0, 0 }, // invalid (possibly stored in Operand)
+  { '?' , 0 , 0, 0 }  // invalid (never stored in Operand, bug...)
+};
+
 ASMJIT_FAVOR_SIZE Error FormatterInternal::formatRegister(
   String& sb,
   FormatFlags flags,
@@ -264,31 +364,22 @@ ASMJIT_FAVOR_SIZE Error FormatterInternal::formatRegister(
         if (Environment::is64Bit(arch)) {
           letter = 'w';
 
-          if (rId == Gp::kIdZr)
+          if (rId == a64::Gp::kIdZr)
             return sb.append("wzr", 3);
 
-          if (rId == Gp::kIdSp)
+          if (rId == a64::Gp::kIdSp)
             return sb.append("wsp", 3);
         }
         else {
           letter = 'r';
-
-          if (rId == 13)
-            return sb.append("sp", 2);
-
-          if (rId == 14)
-            return sb.append("lr", 2);
-
-          if (rId == 15)
-            return sb.append("pc", 2);
         }
         break;
 
       case RegType::kARM_GpX:
         if (Environment::is64Bit(arch)) {
-          if (rId == Gp::kIdZr)
+          if (rId == a64::Gp::kIdZr)
             return sb.append("xzr", 3);
-          if (rId == Gp::kIdSp)
+          if (rId == a64::Gp::kIdSp)
             return sb.append("sp", 2);
 
           letter = 'x';
@@ -299,7 +390,7 @@ ASMJIT_FAVOR_SIZE Error FormatterInternal::formatRegister(
         ASMJIT_FALLTHROUGH;
 
       default:
-        ASMJIT_PROPAGATE(sb.appendFormat("<Reg-%u>?$u", uint32_t(regType), rId));
+        ASMJIT_PROPAGATE(sb.appendFormat("<Reg-%u>?%u", uint32_t(regType), rId));
         break;
     }
 
@@ -307,54 +398,69 @@ ASMJIT_FAVOR_SIZE Error FormatterInternal::formatRegister(
       ASMJIT_PROPAGATE(sb.appendFormat("%c%u", letter, rId));
   }
 
+  constexpr uint32_t kElementTypeCount = uint32_t(a64::VecElementType::kMaxValue) + 1;
   if (elementType) {
-    char elementLetter = '\0';
-    uint32_t elementCount = 0;
+    elementType = Support::min(elementType, kElementTypeCount);
 
-    switch (elementType) {
-      case Vec::kElementTypeB:
-        elementLetter = 'b';
-        elementCount = 16;
-        break;
+    FormatElementData elementData = formatElementDataTable[elementType];
+    uint32_t elementCount = elementData.elementCount;
 
-      case Vec::kElementTypeH:
-        elementLetter = 'h';
-        elementCount = 8;
-        break;
-
-      case Vec::kElementTypeS:
-        elementLetter = 's';
-        elementCount = 4;
-        break;
-
-      case Vec::kElementTypeD:
-        elementLetter = 'd';
-        elementCount = 2;
-        break;
-
-      default:
-        return sb.append(".<Unknown>");
+    if (regType == RegType::kARM_VecD) {
+      elementCount /= 2u;
     }
 
-    if (elementLetter) {
-      if (elementIndex == 0xFFFFFFFFu) {
-        if (regType == RegType::kARM_VecD)
-          elementCount /= 2u;
-        ASMJIT_PROPAGATE(sb.appendFormat(".%u%c", elementCount, elementLetter));
-      }
-      else {
-        ASMJIT_PROPAGATE(sb.appendFormat(".%c[%u]", elementLetter, elementIndex));
-      }
+    ASMJIT_PROPAGATE(sb.append('.'));
+    if (elementCount) {
+      ASMJIT_PROPAGATE(sb.appendUInt(elementCount));
     }
+    ASMJIT_PROPAGATE(sb.append(elementData.letter));
   }
-  else if (elementIndex != 0xFFFFFFFFu) {
-    // This should only be used by AArch32 - AArch64 requires an additional elementType in index[].
+
+  if (elementIndex != 0xFFFFFFFFu) {
     ASMJIT_PROPAGATE(sb.appendFormat("[%u]", elementIndex));
   }
 
   return kErrorOk;
 }
 
+ASMJIT_FAVOR_SIZE Error FormatterInternal::formatRegisterList(
+  String& sb,
+  FormatFlags flags,
+  const BaseEmitter* emitter,
+  Arch arch,
+  RegType regType,
+  uint32_t rMask) noexcept {
+
+  bool first = true;
+
+  ASMJIT_PROPAGATE(sb.append('{'));
+  while (rMask != 0u) {
+    uint32_t start = Support::ctz(rMask);
+    uint32_t count = 0u;
+
+    uint32_t mask = 1u << start;
+    do {
+      rMask &= ~mask;
+      mask <<= 1u;
+      count++;
+    } while (rMask & mask);
+
+    if (!first)
+      ASMJIT_PROPAGATE(sb.append(", "));
+
+    ASMJIT_PROPAGATE(formatRegister(sb, flags, emitter, arch, regType, start, 0, 0xFFFFFFFFu));
+    if (count >= 2u) {
+      ASMJIT_PROPAGATE(sb.append('-'));
+      ASMJIT_PROPAGATE(formatRegister(sb, flags, emitter, arch, regType, start + count - 1, 0, 0xFFFFFFFFu));
+    }
+
+    first = false;
+  }
+  ASMJIT_PROPAGATE(sb.append('}'));
+
+  return kErrorOk;
+}
+
 // a64::FormatterInternal - Format Operand
 // =======================================
 
@@ -368,10 +474,10 @@ ASMJIT_FAVOR_SIZE Error FormatterInternal::formatOperand(
   if (op.isReg()) {
     const BaseReg& reg = op.as<BaseReg>();
 
-    uint32_t elementType = op.as<Vec>().elementType();
-    uint32_t elementIndex = op.as<Vec>().elementIndex();
+    uint32_t elementType = op._signature.getField<BaseVec::kSignatureRegElementTypeMask>();
+    uint32_t elementIndex = op.as<BaseVec>().elementIndex();
 
-    if (!op.as<Vec>().hasElementIndex())
+    if (!op.as<BaseVec>().hasElementIndex())
       elementIndex = 0xFFFFFFFFu;
 
     return formatRegister(sb, flags, emitter, arch, reg.type(), reg.id(), elementType, elementIndex);
@@ -433,7 +539,7 @@ ASMJIT_FAVOR_SIZE Error FormatterInternal::formatOperand(
     if (m.hasShift()) {
       ASMJIT_PROPAGATE(sb.append(' '));
       if (!m.isPreOrPost())
-        ASMJIT_PROPAGATE(formatShiftOp(sb, (ShiftOp)m.predicate()));
+        ASMJIT_PROPAGATE(formatShiftOp(sb, m.shiftOp()));
       ASMJIT_PROPAGATE(sb.appendFormat(" %u", m.shift()));
     }
 
@@ -449,6 +555,12 @@ ASMJIT_FAVOR_SIZE Error FormatterInternal::formatOperand(
   if (op.isImm()) {
     const Imm& i = op.as<Imm>();
     int64_t val = i.value();
+    uint32_t predicate = i.predicate();
+
+    if (predicate) {
+      ASMJIT_PROPAGATE(formatShiftOp(sb, ShiftOp(predicate)));
+      ASMJIT_PROPAGATE(sb.append(' '));
+    }
 
     if (Support::test(flags, FormatFlags::kHexImms) && uint64_t(val) > 9) {
       ASMJIT_PROPAGATE(sb.append("0x"));
@@ -463,6 +575,11 @@ ASMJIT_FAVOR_SIZE Error FormatterInternal::formatOperand(
     return Formatter::formatLabel(sb, flags, emitter, op.id());
   }
 
+  if (op.isRegList()) {
+    const BaseRegList& regList = op.as<BaseRegList>();
+    return formatRegisterList(sb, flags, emitter, arch, regList.type(), regList.list());
+  }
+
   return sb.append("<None>");
 }
 

deps/asmjit/src/asmjit/arm/armformatter_p.h

@@ -43,6 +43,14 @@ Error ASMJIT_CDECL formatRegister(
   uint32_t elementType = 0,
   uint32_t elementIndex = 0xFFFFFFFF) noexcept;
 
+Error ASMJIT_CDECL formatRegisterList(
+  String& sb,
+  FormatFlags flags,
+  const BaseEmitter* emitter,
+  Arch arch,
+  RegType regType,
+  uint32_t rMask) noexcept;
+
 Error ASMJIT_CDECL formatOperand(
   String& sb,
   FormatFlags flags,

deps/asmjit/src/asmjit/arm/armglobals.h

@@ -14,8 +14,4 @@
 //!
 //! API shared between AArch32 & AArch64 backends.
 
-ASMJIT_BEGIN_SUB_NAMESPACE(arm)
-
-ASMJIT_END_SUB_NAMESPACE
-
 #endif // ASMJIT_ARM_ARMGLOBALS_H_INCLUDED

deps/asmjit/src/asmjit/arm/armoperand.h

@@ -19,18 +19,7 @@ ASMJIT_BEGIN_SUB_NAMESPACE(arm)
 class Reg;
 class Mem;
 
-class Gp;
-class GpW;
-class GpX;
-
-class Vec;
-class VecB;
-class VecH;
-class VecS;
-class VecD;
-class VecV;
-
-//! Register traits (ARM/AArch64).
+//! Register traits (AArch32/AArch64).
 //!
 //! Register traits contains information about a particular register type. It's used by asmjit to setup register
 //! information on-the-fly and to populate tables that contain register information (this way it's possible to
@@ -39,27 +28,31 @@ template<RegType kRegType>
 struct RegTraits : public BaseRegTraits {};
 
 //! \cond
-// <--------------------+-----+-------------------------+------------------------+---+---+------------------+
-//                      | Reg |        Reg-Type         |        Reg-Group       |Sz |Cnt|      TypeId      |
-// <--------------------+-----+-------------------------+------------------------+---+---+------------------+
-ASMJIT_DEFINE_REG_TRAITS(GpW  , RegType::kARM_GpW       , RegGroup::kGp          , 4 , 32, TypeId::kInt32   );
-ASMJIT_DEFINE_REG_TRAITS(GpX  , RegType::kARM_GpX       , RegGroup::kGp          , 8 , 32, TypeId::kInt64   );
-ASMJIT_DEFINE_REG_TRAITS(VecB , RegType::kARM_VecB      , RegGroup::kVec         , 1 , 32, TypeId::kVoid    );
-ASMJIT_DEFINE_REG_TRAITS(VecH , RegType::kARM_VecH      , RegGroup::kVec         , 2 , 32, TypeId::kVoid    );
-ASMJIT_DEFINE_REG_TRAITS(VecS , RegType::kARM_VecS      , RegGroup::kVec         , 4 , 32, TypeId::kInt32x1 );
-ASMJIT_DEFINE_REG_TRAITS(VecD , RegType::kARM_VecD      , RegGroup::kVec         , 8 , 32, TypeId::kInt32x2 );
-ASMJIT_DEFINE_REG_TRAITS(VecV , RegType::kARM_VecV      , RegGroup::kVec         , 16, 32, TypeId::kInt32x4 );
+// <--------------------+------------------------+------------------------+---+------------------+
+//                      |       Reg-Type         |        Reg-Group       |Sz |      TypeId      |
+// <--------------------+------------------------+------------------------+---+------------------+
+ASMJIT_DEFINE_REG_TRAITS(RegType::kARM_GpW       , RegGroup::kGp          , 4 , TypeId::kInt32   ); // AArch32 & AArch64
+ASMJIT_DEFINE_REG_TRAITS(RegType::kARM_GpX       , RegGroup::kGp          , 8 , TypeId::kInt64   ); //           AArch64
+ASMJIT_DEFINE_REG_TRAITS(RegType::kARM_VecB      , RegGroup::kVec         , 1 , TypeId::kVoid    ); //           AArch64
+ASMJIT_DEFINE_REG_TRAITS(RegType::kARM_VecH      , RegGroup::kVec         , 2 , TypeId::kVoid    ); //           AArch64
+ASMJIT_DEFINE_REG_TRAITS(RegType::kARM_VecS      , RegGroup::kVec         , 4 , TypeId::kInt32x1 ); // AArch32 & AArch64
+ASMJIT_DEFINE_REG_TRAITS(RegType::kARM_VecD      , RegGroup::kVec         , 8 , TypeId::kInt32x2 ); // AArch32 & AArch64
+ASMJIT_DEFINE_REG_TRAITS(RegType::kARM_VecQ      , RegGroup::kVec         , 16, TypeId::kInt32x4 ); // AArch32 & AArch64
+ASMJIT_DEFINE_REG_TRAITS(RegType::kARM_PC        , RegGroup::kPC          , 8 , TypeId::kInt64   ); //           AArch64
 //! \endcond
 
-//! Register (ARM).
+//! Register operand that can represent AArch32 and AArch64 registers.
 class Reg : public BaseReg {
 public:
   ASMJIT_DEFINE_ABSTRACT_REG(Reg, BaseReg)
 
-  //! Gets whether the register is a `R|W` register (32-bit).
+  //! Gets whether the register is either `R` or `W` register (32-bit).
+  ASMJIT_INLINE_NODEBUG constexpr bool isGpR() const noexcept { return baseSignature() == RegTraits<RegType::kARM_GpW>::kSignature; }
+  //! Gets whether the register is either `R` or `W` register (32-bit).
   ASMJIT_INLINE_NODEBUG constexpr bool isGpW() const noexcept { return baseSignature() == RegTraits<RegType::kARM_GpW>::kSignature; }
   //! Gets whether the register is an `X` register (64-bit).
   ASMJIT_INLINE_NODEBUG constexpr bool isGpX() const noexcept { return baseSignature() == RegTraits<RegType::kARM_GpX>::kSignature; }
+
   //! Gets whether the register is a VEC-B register (8-bit).
   ASMJIT_INLINE_NODEBUG constexpr bool isVecB() const noexcept { return baseSignature() == RegTraits<RegType::kARM_VecB>::kSignature; }
   //! Gets whether the register is a VEC-H register (16-bit).
@@ -70,13 +63,22 @@ public:
   ASMJIT_INLINE_NODEBUG constexpr bool isVecD() const noexcept { return baseSignature() == RegTraits<RegType::kARM_VecD>::kSignature; }
   //! Gets whether the register is a VEC-Q register (128-bit).
   ASMJIT_INLINE_NODEBUG constexpr bool isVecQ() const noexcept { return baseSignature() == RegTraits<RegType::kARM_VecV>::kSignature; }
-
   //! Gets whether the register is either VEC-D (64-bit) or VEC-Q (128-bit).
   ASMJIT_INLINE_NODEBUG constexpr bool isVecDOrQ() const noexcept { return uint32_t(type()) - uint32_t(RegType::kARM_VecD) <= 1u; }
-
   //! Gets whether the register is a VEC-V register (128-bit).
   ASMJIT_INLINE_NODEBUG constexpr bool isVecV() const noexcept { return baseSignature() == RegTraits<RegType::kARM_VecV>::kSignature; }
 
+  //! Gets whether the register is an 8-bit vector register or view, alias if \ref isVecB().
+  ASMJIT_INLINE_NODEBUG constexpr bool isVec8() const noexcept { return baseSignature() == RegTraits<RegType::kARM_VecB>::kSignature; }
+  //! Gets whether the register is a 16-bit vector register or view, alias if \ref isVecH().
+  ASMJIT_INLINE_NODEBUG constexpr bool isVec16() const noexcept { return baseSignature() == RegTraits<RegType::kARM_VecH>::kSignature; }
+  //! Gets whether the register is a 32-bit vector register or view, alias if \ref isVecS().
+  ASMJIT_INLINE_NODEBUG constexpr bool isVec32() const noexcept { return baseSignature() == RegTraits<RegType::kARM_VecS>::kSignature; }
+  //! Gets whether the register is a 64-bit vector register or view, alias if \ref isVecD().
+  ASMJIT_INLINE_NODEBUG constexpr bool isVec64() const noexcept { return baseSignature() == RegTraits<RegType::kARM_VecD>::kSignature; }
+  //! Gets whether the register is a 128-bit vector register or view, alias if \ref isVecQ().
+  ASMJIT_INLINE_NODEBUG constexpr bool isVec128() const noexcept { return baseSignature() == RegTraits<RegType::kARM_VecV>::kSignature; }
+
   template<RegType kRegType>
   ASMJIT_INLINE_NODEBUG void setRegT(uint32_t id) noexcept {
     setSignature(RegTraits<kRegType>::kSignature);
@@ -99,7 +101,7 @@ public:
   static ASMJIT_INLINE_NODEBUG TypeId typeIdOfT() noexcept { return RegTraits<kRegType>::kTypeId; }
 
   template<RegType kRegType>
-  static ASMJIT_INLINE_NODEBUG OperandSignature signatureOfT() noexcept { return RegTraits<kRegType>::kSignature; }
+  static ASMJIT_INLINE_NODEBUG OperandSignature signatureOfT() noexcept { return OperandSignature{RegTraits<kRegType>::kSignature}; }
 
   static ASMJIT_INLINE_NODEBUG bool isGpW(const Operand_& op) noexcept { return op.as<Reg>().isGpW(); }
   static ASMJIT_INLINE_NODEBUG bool isGpX(const Operand_& op) noexcept { return op.as<Reg>().isGpX(); }
@@ -120,47 +122,12 @@ public:
   static ASMJIT_INLINE_NODEBUG bool isVecV(const Operand_& op, uint32_t id) noexcept { return bool(unsigned(isVecV(op)) & unsigned(op.id() == id)); }
 };
 
-//! General purpose register (ARM).
-class Gp : public Reg {
+//! Vector register base - a common base for both AArch32 & AArch64 vector register.
+class BaseVec : public Reg {
 public:
-  ASMJIT_DEFINE_ABSTRACT_REG(Gp, Reg)
+  ASMJIT_DEFINE_ABSTRACT_REG(BaseVec, Reg)
 
-  //! Special register id.
-  enum Id : uint32_t {
-    //! Register that depends on OS, could be used as TLS offset.
-    kIdOs = 18,
-    //! Frame pointer.
-    kIdFp = 29,
-    //! Link register.
-    kIdLr = 30,
-    //! Stack register id.
-    kIdSp = 31,
-    //! Zero register id.
-    //!
-    //! Although zero register has the same id as stack register it has a special treatment, because we need to be
-    //! able to distinguish between these two at API level. Some intructions were designed to be used with SP and
-    //! some other with ZR - so we need a way to distinguish these two to make sure we emit the right thing.
-    //!
-    //! The number 63 is not random, when you perform `id & 31` you would always get 31 for both SP and ZR inputs,
-    //! which is the identifier used by AArch64 ISA to encode either SP or ZR depending on the instruction.
-    kIdZr = 63
-  };
-
-  ASMJIT_INLINE_NODEBUG constexpr bool isZR() const noexcept { return id() == kIdZr; }
-  ASMJIT_INLINE_NODEBUG constexpr bool isSP() const noexcept { return id() == kIdSp; }
-
-  //! Cast this register to a 32-bit R|W.
-  ASMJIT_INLINE_NODEBUG GpW w() const noexcept;
-  //! Cast this register to a 64-bit X.
-  ASMJIT_INLINE_NODEBUG GpX x() const noexcept;
-};
-
-//! Vector register (ARM).
-class Vec : public Reg {
-public:
-  ASMJIT_DEFINE_ABSTRACT_REG(Vec, Reg)
-
-  //! Additional signature bits used by arm::Vec.
+  //! Additional signature bits used by a vector register.
   enum AdditionalBits : uint32_t {
     // Register element type (3 bits).
     // |........|........|.XXX....|........|
@@ -178,57 +145,8 @@ public:
     kSignatureRegElementIndexMask = 0x0F << kSignatureRegElementIndexShift
   };
 
-  //! Element type (AArch64 only).
-  enum ElementType : uint32_t {
-    //! No element type specified.
-    kElementTypeNone = 0,
-    //! Byte elements (B8 or B16).
-    kElementTypeB,
-    //! Halfword elements (H4 or H8).
-    kElementTypeH,
-    //! Singleword elements (S2 or S4).
-    kElementTypeS,
-    //! Doubleword elements (D2).
-    kElementTypeD,
-    //! Byte elements grouped by 4 bytes (B4).
-    //!
-    //! \note This element-type is only used by few instructions.
-    kElementTypeB4,
-    //! Halfword elements grouped by 2 halfwords (H2).
-    //!
-    //! \note This element-type is only used by few instructions.
-    kElementTypeH2,
-
-    //! Count of element types.
-    kElementTypeCount
-  };
-
-  //! \cond
-  //! Shortcuts.
-  enum SignatureReg : uint32_t {
-    kSignatureElementB  = kElementTypeB  << kSignatureRegElementTypeShift,
-    kSignatureElementH  = kElementTypeH  << kSignatureRegElementTypeShift,
-    kSignatureElementS  = kElementTypeS  << kSignatureRegElementTypeShift,
-    kSignatureElementD  = kElementTypeD  << kSignatureRegElementTypeShift,
-    kSignatureElementB4 = kElementTypeB4 << kSignatureRegElementTypeShift,
-    kSignatureElementH2 = kElementTypeH2 << kSignatureRegElementTypeShift
-  };
-  //! \endcond
-
-  //! Returns whether the register has associated an element type.
-  ASMJIT_INLINE_NODEBUG constexpr bool hasElementType() const noexcept { return _signature.hasField<kSignatureRegElementTypeMask>(); }
   //! Returns whether the register has element index (it's an element index access).
   ASMJIT_INLINE_NODEBUG constexpr bool hasElementIndex() const noexcept { return _signature.hasField<kSignatureRegElementFlagMask>(); }
-  //! Returns whether the reggister has element type or element index (or both).
-  ASMJIT_INLINE_NODEBUG constexpr bool hasElementTypeOrIndex() const noexcept { return _signature.hasField<kSignatureRegElementTypeMask | kSignatureRegElementFlagMask>(); }
-
-  //! Returns element type of the register.
-  ASMJIT_INLINE_NODEBUG constexpr uint32_t elementType() const noexcept { return _signature.getField<kSignatureRegElementTypeMask>(); }
-  //! Sets element type of the register to `elementType`.
-  ASMJIT_INLINE_NODEBUG void setElementType(uint32_t elementType) noexcept { _signature.setField<kSignatureRegElementTypeMask>(elementType); }
-  //! Resets element type to none.
-  ASMJIT_INLINE_NODEBUG void resetElementType() noexcept { _signature.setField<kSignatureRegElementTypeMask>(0); }
-
   //! Returns element index of the register.
   ASMJIT_INLINE_NODEBUG constexpr uint32_t elementIndex() const noexcept { return _signature.getField<kSignatureRegElementIndexMask>(); }
   //! Sets element index of the register to `elementType`.
@@ -240,140 +158,8 @@ public:
   ASMJIT_INLINE_NODEBUG void resetElementIndex() noexcept {
     _signature &= ~(kSignatureRegElementFlagMask | kSignatureRegElementIndexMask);
   }
-
-  ASMJIT_INLINE_NODEBUG constexpr bool isVecB8() const noexcept { return _signature.subset(kBaseSignatureMask | kSignatureRegElementTypeMask) == (RegTraits<RegType::kARM_VecD>::kSignature | kSignatureElementB); }
-  ASMJIT_INLINE_NODEBUG constexpr bool isVecH4() const noexcept { return _signature.subset(kBaseSignatureMask | kSignatureRegElementTypeMask) == (RegTraits<RegType::kARM_VecD>::kSignature | kSignatureElementH); }
-  ASMJIT_INLINE_NODEBUG constexpr bool isVecS2() const noexcept { return _signature.subset(kBaseSignatureMask | kSignatureRegElementTypeMask) == (RegTraits<RegType::kARM_VecD>::kSignature | kSignatureElementS); }
-  ASMJIT_INLINE_NODEBUG constexpr bool isVecD1() const noexcept { return _signature.subset(kBaseSignatureMask | kSignatureRegElementTypeMask) == (RegTraits<RegType::kARM_VecD>::kSignature); }
-
-  ASMJIT_INLINE_NODEBUG constexpr bool isVecB16() const noexcept { return _signature.subset(kBaseSignatureMask | kSignatureRegElementTypeMask) == (RegTraits<RegType::kARM_VecV>::kSignature | kSignatureElementB); }
-  ASMJIT_INLINE_NODEBUG constexpr bool isVecH8() const noexcept { return _signature.subset(kBaseSignatureMask | kSignatureRegElementTypeMask) == (RegTraits<RegType::kARM_VecV>::kSignature | kSignatureElementH); }
-  ASMJIT_INLINE_NODEBUG constexpr bool isVecS4() const noexcept { return _signature.subset(kBaseSignatureMask | kSignatureRegElementTypeMask) == (RegTraits<RegType::kARM_VecV>::kSignature | kSignatureElementS); }
-  ASMJIT_INLINE_NODEBUG constexpr bool isVecD2() const noexcept { return _signature.subset(kBaseSignatureMask | kSignatureRegElementTypeMask) == (RegTraits<RegType::kARM_VecV>::kSignature | kSignatureElementD); }
-  ASMJIT_INLINE_NODEBUG constexpr bool isVecB4x4() const noexcept { return _signature.subset(kBaseSignatureMask | kSignatureRegElementTypeMask) == (RegTraits<RegType::kARM_VecV>::kSignature | kSignatureElementB4); }
-  ASMJIT_INLINE_NODEBUG constexpr bool isVecH2x4() const noexcept { return _signature.subset(kBaseSignatureMask | kSignatureRegElementTypeMask) == (RegTraits<RegType::kARM_VecV>::kSignature | kSignatureElementH2); }
-
-  //! Creates a cloned register with element access.
-  ASMJIT_INLINE_NODEBUG Vec at(uint32_t elementIndex) const noexcept {
-    return Vec((signature() & ~kSignatureRegElementIndexMask) | (elementIndex << kSignatureRegElementIndexShift) | kSignatureRegElementFlagMask, id());
-  }
-
-  //! Cast this register to an 8-bit B register (AArch64 only).
-  ASMJIT_INLINE_NODEBUG VecB b() const noexcept;
-  //! Cast this register to a 16-bit H register (AArch64 only).
-  ASMJIT_INLINE_NODEBUG VecH h() const noexcept;
-  //! Cast this register to a 32-bit S register.
-  ASMJIT_INLINE_NODEBUG VecS s() const noexcept;
-  //! Cast this register to a 64-bit D register.
-  ASMJIT_INLINE_NODEBUG VecD d() const noexcept;
-  //! Cast this register to a 128-bit Q register.
-  ASMJIT_INLINE_NODEBUG VecV q() const noexcept;
-  //! Cast this register to a 128-bit V register.
-  ASMJIT_INLINE_NODEBUG VecV v() const noexcept;
-
-  //! Cast this register to a 128-bit V.B[elementIndex] register.
-  ASMJIT_INLINE_NODEBUG VecV b(uint32_t elementIndex) const noexcept;
-  //! Cast this register to a 128-bit V.H[elementIndex] register.
-  ASMJIT_INLINE_NODEBUG VecV h(uint32_t elementIndex) const noexcept;
-  //! Cast this register to a 128-bit V.S[elementIndex] register.
-  ASMJIT_INLINE_NODEBUG VecV s(uint32_t elementIndex) const noexcept;
-  //! Cast this register to a 128-bit V.D[elementIndex] register.
-  ASMJIT_INLINE_NODEBUG VecV d(uint32_t elementIndex) const noexcept;
-  //! Cast this register to a 128-bit V.H2[elementIndex] register.
-  ASMJIT_INLINE_NODEBUG VecV h2(uint32_t elementIndex) const noexcept;
-  //! Cast this register to a 128-bit V.B4[elementIndex] register.
-  ASMJIT_INLINE_NODEBUG VecV b4(uint32_t elementIndex) const noexcept;
-
-  //! Cast this register to V.8B.
-  ASMJIT_INLINE_NODEBUG VecD b8() const noexcept;
-  //! Cast this register to V.16B.
-  ASMJIT_INLINE_NODEBUG VecV b16() const noexcept;
-  //! Cast this register to V.2H.
-  ASMJIT_INLINE_NODEBUG VecS h2() const noexcept;
-  //! Cast this register to V.4H.
-  ASMJIT_INLINE_NODEBUG VecD h4() const noexcept;
-  //! Cast this register to V.8H.
-  ASMJIT_INLINE_NODEBUG VecV h8() const noexcept;
-  //! Cast this register to V.2S.
-  ASMJIT_INLINE_NODEBUG VecD s2() const noexcept;
-  //! Cast this register to V.4S.
-  ASMJIT_INLINE_NODEBUG VecV s4() const noexcept;
-  //! Cast this register to V.2D.
-  ASMJIT_INLINE_NODEBUG VecV d2() const noexcept;
-
-  static ASMJIT_INLINE_NODEBUG constexpr OperandSignature _makeElementAccessSignature(uint32_t elementType, uint32_t elementIndex) noexcept {
-    return OperandSignature{
-      uint32_t(RegTraits<RegType::kARM_VecV>::kSignature)      |
-      uint32_t(kSignatureRegElementFlagMask)                   |
-      uint32_t(elementType << kSignatureRegElementTypeShift)   |
-      uint32_t(elementIndex << kSignatureRegElementIndexShift)};
-  }
 };
 
-//! 32-bit GPW (AArch64) and/or GPR (ARM/AArch32) register.
-class GpW : public Gp { ASMJIT_DEFINE_FINAL_REG(GpW, Gp, RegTraits<RegType::kARM_GpW>) };
-//! 64-bit GPX (AArch64) register.
-class GpX : public Gp { ASMJIT_DEFINE_FINAL_REG(GpX, Gp, RegTraits<RegType::kARM_GpX>) };
-
-//! 8-bit view (S) of VFP/SIMD register.
-class VecB : public Vec { ASMJIT_DEFINE_FINAL_REG(VecB, Vec, RegTraits<RegType::kARM_VecB>) };
-//! 16-bit view (S) of VFP/SIMD register.
-class VecH : public Vec { ASMJIT_DEFINE_FINAL_REG(VecH, Vec, RegTraits<RegType::kARM_VecH>) };
-//! 32-bit view (S) of VFP/SIMD register.
-class VecS : public Vec { ASMJIT_DEFINE_FINAL_REG(VecS, Vec, RegTraits<RegType::kARM_VecS>) };
-//! 64-bit view (D) of VFP/SIMD register.
-class VecD : public Vec { ASMJIT_DEFINE_FINAL_REG(VecD, Vec, RegTraits<RegType::kARM_VecD>) };
-//! 128-bit vector register (Q or V).
-class VecV : public Vec { ASMJIT_DEFINE_FINAL_REG(VecV, Vec, RegTraits<RegType::kARM_VecV>) };
-
-ASMJIT_INLINE_NODEBUG GpW Gp::w() const noexcept { return GpW(id()); }
-ASMJIT_INLINE_NODEBUG GpX Gp::x() const noexcept { return GpX(id()); }
-
-ASMJIT_INLINE_NODEBUG VecB Vec::b() const noexcept { return VecB(id()); }
-ASMJIT_INLINE_NODEBUG VecH Vec::h() const noexcept { return VecH(id()); }
-ASMJIT_INLINE_NODEBUG VecS Vec::s() const noexcept { return VecS(id()); }
-ASMJIT_INLINE_NODEBUG VecD Vec::d() const noexcept { return VecD(id()); }
-ASMJIT_INLINE_NODEBUG VecV Vec::q() const noexcept { return VecV(id()); }
-ASMJIT_INLINE_NODEBUG VecV Vec::v() const noexcept { return VecV(id()); }
-
-ASMJIT_INLINE_NODEBUG VecV Vec::b(uint32_t elementIndex) const noexcept { return VecV(_makeElementAccessSignature(kElementTypeB, elementIndex), id()); }
-ASMJIT_INLINE_NODEBUG VecV Vec::h(uint32_t elementIndex) const noexcept { return VecV(_makeElementAccessSignature(kElementTypeH, elementIndex), id()); }
-ASMJIT_INLINE_NODEBUG VecV Vec::s(uint32_t elementIndex) const noexcept { return VecV(_makeElementAccessSignature(kElementTypeS, elementIndex), id()); }
-ASMJIT_INLINE_NODEBUG VecV Vec::d(uint32_t elementIndex) const noexcept { return VecV(_makeElementAccessSignature(kElementTypeD, elementIndex), id()); }
-ASMJIT_INLINE_NODEBUG VecV Vec::h2(uint32_t elementIndex) const noexcept { return VecV(_makeElementAccessSignature(kElementTypeH2, elementIndex), id()); }
-ASMJIT_INLINE_NODEBUG VecV Vec::b4(uint32_t elementIndex) const noexcept { return VecV(_makeElementAccessSignature(kElementTypeB4, elementIndex), id()); }
-
-ASMJIT_INLINE_NODEBUG VecD Vec::b8() const noexcept { return VecD(OperandSignature{VecD::kSignature | kSignatureElementB}, id()); }
-ASMJIT_INLINE_NODEBUG VecS Vec::h2() const noexcept { return VecS(OperandSignature{VecS::kSignature | kSignatureElementH}, id()); }
-ASMJIT_INLINE_NODEBUG VecD Vec::h4() const noexcept { return VecD(OperandSignature{VecD::kSignature | kSignatureElementH}, id()); }
-ASMJIT_INLINE_NODEBUG VecD Vec::s2() const noexcept { return VecD(OperandSignature{VecD::kSignature | kSignatureElementS}, id()); }
-ASMJIT_INLINE_NODEBUG VecV Vec::b16() const noexcept { return VecV(OperandSignature{VecV::kSignature | kSignatureElementB}, id()); }
-ASMJIT_INLINE_NODEBUG VecV Vec::h8() const noexcept { return VecV(OperandSignature{VecV::kSignature | kSignatureElementH}, id()); }
-ASMJIT_INLINE_NODEBUG VecV Vec::s4() const noexcept { return VecV(OperandSignature{VecV::kSignature | kSignatureElementS}, id()); }
-ASMJIT_INLINE_NODEBUG VecV Vec::d2() const noexcept { return VecV(OperandSignature{VecV::kSignature | kSignatureElementD}, id()); }
-
-#ifndef _DOXYGEN
-namespace regs {
-#endif
-
-//! Creates a 32-bit W register operand (ARM/AArch64).
-static ASMJIT_INLINE_NODEBUG constexpr GpW w(uint32_t id) noexcept { return GpW(id); }
-//! Creates a 64-bit X register operand (AArch64).
-static ASMJIT_INLINE_NODEBUG constexpr GpX x(uint32_t id) noexcept { return GpX(id); }
-//! Creates a 32-bit S register operand (ARM/AArch64).
-static ASMJIT_INLINE_NODEBUG constexpr VecS s(uint32_t id) noexcept { return VecS(id); }
-//! Creates a 64-bit D register operand (ARM/AArch64).
-static ASMJIT_INLINE_NODEBUG constexpr VecD d(uint32_t id) noexcept { return VecD(id); }
-//! Creates a 1282-bit V register operand (ARM/AArch64).
-static ASMJIT_INLINE_NODEBUG constexpr VecV v(uint32_t id) noexcept { return VecV(id); }
-
-#ifndef _DOXYGEN
-} // {regs}
-
-// Make `arm::regs` accessible through `arm` namespace as well.
-using namespace regs;
-#endif
-
 //! Memory operand (ARM).
 class Mem : public BaseMem {
 public:
@@ -385,23 +171,18 @@ public:
     kSignatureMemShiftValueShift = 14,
     kSignatureMemShiftValueMask = 0x1Fu << kSignatureMemShiftValueShift,
 
-    // Shift operation type (4 bits).
+    // Index shift operation (4 bits).
     // |........|XXXX....|........|........|
-    kSignatureMemPredicateShift = 20,
-    kSignatureMemPredicateMask = 0x0Fu << kSignatureMemPredicateShift
+    kSignatureMemShiftOpShift = 20,
+    kSignatureMemShiftOpMask = 0x0Fu << kSignatureMemShiftOpShift,
+
+    // Offset mode type (2 bits).
+    // |......XX|........|........|........|
+    kSignatureMemOffsetModeShift = 24,
+    kSignatureMemOffsetModeMask = 0x03u << kSignatureMemOffsetModeShift
   };
   //! \endcond
 
-  //! Memory offset mode.
-  //!
-  //! Additional constants that can be used with the `predicate`.
-  enum OffsetMode : uint32_t {
-    //! Pre-index "[BASE, #Offset {, <shift>}]!" with write-back.
-    kOffsetPreIndex = 0xE,
-    //! Post-index "[BASE], #Offset {, <shift>}" with write-back.
-    kOffsetPostIndex = 0xF
-  };
-
   //! \name Construction & Destruction
   //! \{
 
@@ -438,11 +219,11 @@ public:
     : BaseMem(Signature::fromOpType(OperandType::kMem) |
               Signature::fromMemBaseType(base.type()) |
               Signature::fromMemIndexType(index.type()) |
-              Signature::fromValue<kSignatureMemPredicateMask>(uint32_t(shift.op())) |
+              Signature::fromValue<kSignatureMemShiftOpMask>(uint32_t(shift.op())) |
               Signature::fromValue<kSignatureMemShiftValueMask>(shift.value()) |
               signature, base.id(), index.id(), 0) {}
 
-  ASMJIT_INLINE_NODEBUG constexpr Mem(uint64_t base, Signature signature = Signature{0}) noexcept
+  ASMJIT_INLINE_NODEBUG constexpr explicit Mem(uint64_t base, Signature signature = Signature{0}) noexcept
     : BaseMem(Signature::fromOpType(OperandType::kMem) |
               signature, uint32_t(base >> 32), 0, int32_t(uint32_t(base & 0xFFFFFFFFu))) {}
 
@@ -471,14 +252,14 @@ public:
   //! Clones the memory operand and makes it pre-index.
   ASMJIT_INLINE_NODEBUG Mem pre() const noexcept {
     Mem result(*this);
-    result.setPredicate(kOffsetPreIndex);
+    result.setOffsetMode(OffsetMode::kPreIndex);
     return result;
   }
 
   //! Clones the memory operand, applies a given offset `off` and makes it pre-index.
   ASMJIT_INLINE_NODEBUG Mem pre(int64_t off) const noexcept {
     Mem result(*this);
-    result.setPredicate(kOffsetPreIndex);
+    result.setOffsetMode(OffsetMode::kPreIndex);
     result.addOffset(off);
     return result;
   }
@@ -486,14 +267,14 @@ public:
   //! Clones the memory operand and makes it post-index.
   ASMJIT_INLINE_NODEBUG Mem post() const noexcept {
     Mem result(*this);
-    result.setPredicate(kOffsetPostIndex);
+    result.setOffsetMode(OffsetMode::kPostIndex);
     return result;
   }
 
   //! Clones the memory operand, applies a given offset `off` and makes it post-index.
   ASMJIT_INLINE_NODEBUG Mem post(int64_t off) const noexcept {
     Mem result(*this);
-    result.setPredicate(kOffsetPostIndex);
+    result.setOffsetMode(OffsetMode::kPostIndex);
     result.addOffset(off);
     return result;
   }
@@ -520,88 +301,85 @@ public:
     setShift(shift);
   }
 
+  ASMJIT_INLINE_NODEBUG void setIndex(const BaseReg& index, Shift shift) noexcept {
+    setIndex(index);
+    setShift(shift);
+  }
+
   //! \}
 
   //! \name ARM Specific Features
   //! \{
 
+  //! Gets offset mode.
+  ASMJIT_INLINE_NODEBUG constexpr OffsetMode offsetMode() const noexcept { return OffsetMode(_signature.getField<kSignatureMemOffsetModeMask>()); }
+  //! Sets offset mode to `mode`.
+  ASMJIT_INLINE_NODEBUG void setOffsetMode(OffsetMode mode) noexcept { _signature.setField<kSignatureMemOffsetModeMask>(uint32_t(mode)); }
+  //! Resets offset mode to default (fixed offset, without write-back).
+  ASMJIT_INLINE_NODEBUG void resetOffsetMode() noexcept { _signature.setField<kSignatureMemOffsetModeMask>(uint32_t(OffsetMode::kFixed)); }
+
+  //! Tests whether the current memory offset mode is fixed (see \ref OffsetMode::kFixed).
+  ASMJIT_INLINE_NODEBUG constexpr bool isFixedOffset() const noexcept { return offsetMode() == OffsetMode::kFixed; }
+  //! Tests whether the current memory offset mode is either pre-index or post-index (write-back is used).
+  ASMJIT_INLINE_NODEBUG constexpr bool isPreOrPost() const noexcept { return offsetMode() != OffsetMode::kFixed; }
+  //! Tests whether the current memory offset mode is pre-index (write-back is used).
+  ASMJIT_INLINE_NODEBUG constexpr bool isPreIndex() const noexcept { return offsetMode() == OffsetMode::kPreIndex; }
+  //! Tests whether the current memory offset mode is post-index (write-back is used).
+  ASMJIT_INLINE_NODEBUG constexpr bool isPostIndex() const noexcept { return offsetMode() == OffsetMode::kPostIndex; }
+
+  //! Sets offset mode of this memory operand to pre-index (write-back is used).
+  ASMJIT_INLINE_NODEBUG void makePreIndex() noexcept { setOffsetMode(OffsetMode::kPreIndex); }
+  //! Sets offset mode of this memory operand to post-index (write-back is used).
+  ASMJIT_INLINE_NODEBUG void makePostIndex() noexcept { setOffsetMode(OffsetMode::kPostIndex); }
+
+  //! Gets shift operation that is used by index register.
+  ASMJIT_INLINE_NODEBUG constexpr ShiftOp shiftOp() const noexcept { return ShiftOp(_signature.getField<kSignatureMemShiftOpMask>()); }
+  //! Sets shift operation that is used by index register.
+  ASMJIT_INLINE_NODEBUG void setShiftOp(ShiftOp sop) noexcept { _signature.setField<kSignatureMemShiftOpMask>(uint32_t(sop)); }
+  //! Resets shift operation that is used by index register to LSL (default value).
+  ASMJIT_INLINE_NODEBUG void resetShiftOp() noexcept { _signature.setField<kSignatureMemShiftOpMask>(uint32_t(ShiftOp::kLSL)); }
+
   //! Gets whether the memory operand has shift (aka scale) constant.
   ASMJIT_INLINE_NODEBUG constexpr bool hasShift() const noexcept { return _signature.hasField<kSignatureMemShiftValueMask>(); }
   //! Gets the memory operand's shift (aka scale) constant.
   ASMJIT_INLINE_NODEBUG constexpr uint32_t shift() const noexcept { return _signature.getField<kSignatureMemShiftValueMask>(); }
   //! Sets the memory operand's shift (aka scale) constant.
   ASMJIT_INLINE_NODEBUG void setShift(uint32_t shift) noexcept { _signature.setField<kSignatureMemShiftValueMask>(shift); }
+
+  //! Sets the memory operand's shift and shift operation.
+  ASMJIT_INLINE_NODEBUG void setShift(Shift shift) noexcept {
+    _signature.setField<kSignatureMemShiftOpMask>(uint32_t(shift.op()));
+    _signature.setField<kSignatureMemShiftValueMask>(shift.value());
+  }
+
   //! Resets the memory operand's shift (aka scale) constant to zero.
   ASMJIT_INLINE_NODEBUG void resetShift() noexcept { _signature.setField<kSignatureMemShiftValueMask>(0); }
 
-  //! Gets memory predicate (shift mode or offset mode), see \ref ShiftOp and \ref OffsetMode.
-  ASMJIT_INLINE_NODEBUG constexpr uint32_t predicate() const noexcept { return _signature.getField<kSignatureMemPredicateMask>(); }
-  //! Sets memory predicate to `predicate`, see `Mem::ShiftOp`.
-  ASMJIT_INLINE_NODEBUG void setPredicate(uint32_t predicate) noexcept { _signature.setField<kSignatureMemPredicateMask>(predicate); }
-  //! Resets shift mode to LSL (default).
-  ASMJIT_INLINE_NODEBUG void resetPredicate() noexcept { _signature.setField<kSignatureMemPredicateMask>(0); }
-
-  ASMJIT_INLINE_NODEBUG constexpr bool isFixedOffset() const noexcept { return predicate() < kOffsetPreIndex; }
-  ASMJIT_INLINE_NODEBUG constexpr bool isPreOrPost() const noexcept { return predicate() >= kOffsetPreIndex; }
-  ASMJIT_INLINE_NODEBUG constexpr bool isPreIndex() const noexcept { return predicate() == kOffsetPreIndex; }
-  ASMJIT_INLINE_NODEBUG constexpr bool isPostIndex() const noexcept { return predicate() == kOffsetPostIndex; }
-
-  ASMJIT_INLINE_NODEBUG void resetToFixedOffset() noexcept { resetPredicate(); }
-  ASMJIT_INLINE_NODEBUG void makePreIndex() noexcept { setPredicate(kOffsetPreIndex); }
-  ASMJIT_INLINE_NODEBUG void makePostIndex() noexcept { setPredicate(kOffsetPostIndex); }
-
   //! \}
 };
 
-//! Creates `[base, offset]` memory operand (offset mode).
-static ASMJIT_INLINE_NODEBUG constexpr Mem ptr(const Gp& base, int32_t offset = 0) noexcept {
-  return Mem(base, offset);
-}
+//! \name Shift Operation Construction
+//! \{
 
-//! Creates `[base, offset]!` memory operand (pre-index mode).
-static ASMJIT_INLINE_NODEBUG constexpr Mem ptr_pre(const Gp& base, int32_t offset = 0) noexcept {
-  return Mem(base, offset, OperandSignature::fromValue<Mem::kSignatureMemPredicateMask>(Mem::kOffsetPreIndex));
-}
+//! Constructs a `LSL #value` shift (logical shift left).
+static ASMJIT_INLINE_NODEBUG constexpr Shift lsl(uint32_t value) noexcept { return Shift(ShiftOp::kLSL, value); }
+//! Constructs a `LSR #value` shift (logical shift right).
+static ASMJIT_INLINE_NODEBUG constexpr Shift lsr(uint32_t value) noexcept { return Shift(ShiftOp::kLSR, value); }
+//! Constructs a `ASR #value` shift (arithmetic shift right).
+static ASMJIT_INLINE_NODEBUG constexpr Shift asr(uint32_t value) noexcept { return Shift(ShiftOp::kASR, value); }
+//! Constructs a `ROR #value` shift (rotate right).
+static ASMJIT_INLINE_NODEBUG constexpr Shift ror(uint32_t value) noexcept { return Shift(ShiftOp::kROR, value); }
+//! Constructs a `RRX` shift (rotate with carry by 1).
+static ASMJIT_INLINE_NODEBUG constexpr Shift rrx() noexcept { return Shift(ShiftOp::kRRX, 0); }
+//! Constructs a `MSL #value` shift (logical shift left filling ones).
+static ASMJIT_INLINE_NODEBUG constexpr Shift msl(uint32_t value) noexcept { return Shift(ShiftOp::kMSL, value); }
 
-//! Creates `[base], offset` memory operand (post-index mode).
-static ASMJIT_INLINE_NODEBUG constexpr Mem ptr_post(const Gp& base, int32_t offset = 0) noexcept {
-  return Mem(base, offset, OperandSignature::fromValue<Mem::kSignatureMemPredicateMask>(Mem::kOffsetPostIndex));
-}
+//! \}
 
-//! Creates `[base, index]` memory operand.
-static ASMJIT_INLINE_NODEBUG constexpr Mem ptr(const Gp& base, const Gp& index) noexcept {
-  return Mem(base, index);
-}
+//! \name Memory Operand Construction
+//! \{
 
-//! Creates `[base, index]!` memory operand (pre-index mode).
-static ASMJIT_INLINE_NODEBUG constexpr Mem ptr_pre(const Gp& base, const Gp& index) noexcept {
-  return Mem(base, index, OperandSignature::fromValue<Mem::kSignatureMemPredicateMask>(Mem::kOffsetPreIndex));
-}
-
-//! Creates `[base], index` memory operand (post-index mode).
-static ASMJIT_INLINE_NODEBUG constexpr Mem ptr_post(const Gp& base, const Gp& index) noexcept {
-  return Mem(base, index, OperandSignature::fromValue<Mem::kSignatureMemPredicateMask>(Mem::kOffsetPostIndex));
-}
-
-//! Creates `[base, index, SHIFT_OP #shift]` memory operand.
-static ASMJIT_INLINE_NODEBUG constexpr Mem ptr(const Gp& base, const Gp& index, const Shift& shift) noexcept {
-  return Mem(base, index, shift);
-}
-
-//! Creates `[base, offset]` memory operand.
-static ASMJIT_INLINE_NODEBUG constexpr Mem ptr(const Label& base, int32_t offset = 0) noexcept {
-  return Mem(base, offset);
-}
-
-// TODO: [ARM] PC + offset address.
-#if 0
-//! Creates `[PC + offset]` (relative) memory operand.
-static ASMJIT_INLINE_NODEBUG constexpr Mem ptr(const PC& pc, int32_t offset = 0) noexcept {
-  return Mem(pc, offset);
-}
-#endif
-
-//! Creates `[base]` absolute memory operand.
+//! Creates `[base]` absolute memory operand (AArch32 or AArch64).
 //!
 //! \note The concept of absolute memory operands doesn't exist on ARM, the ISA only provides PC relative addressing.
 //! Absolute memory operands can only be used if it's known that the PC relative offset is encodable and that it
@@ -611,16 +389,8 @@ static ASMJIT_INLINE_NODEBUG constexpr Mem ptr(uint64_t base) noexcept { return
 
 //! \}
 
+//! \}
+
 ASMJIT_END_SUB_NAMESPACE
 
-//! \cond INTERNAL
-ASMJIT_BEGIN_NAMESPACE
-ASMJIT_DEFINE_TYPE_ID(arm::GpW, TypeId::kInt32);
-ASMJIT_DEFINE_TYPE_ID(arm::GpX, TypeId::kInt64);
-ASMJIT_DEFINE_TYPE_ID(arm::VecS, TypeId::kFloat32x1);
-ASMJIT_DEFINE_TYPE_ID(arm::VecD, TypeId::kFloat64x1);
-ASMJIT_DEFINE_TYPE_ID(arm::VecV, TypeId::kInt32x4);
-ASMJIT_END_NAMESPACE
-//! \endcond
-
 #endif // ASMJIT_ARM_ARMOPERAND_H_INCLUDED

deps/asmjit/src/asmjit/arm/armutils.h

@@ -6,6 +6,7 @@
 #ifndef ASMJIT_ARM_ARMUTILS_H_INCLUDED
 #define ASMJIT_ARM_ARMUTILS_H_INCLUDED
 
+#include "../core/support.h"
 #include "../arm/armglobals.h"
 
 ASMJIT_BEGIN_SUB_NAMESPACE(arm)
@@ -16,6 +17,38 @@ ASMJIT_BEGIN_SUB_NAMESPACE(arm)
 //! Public utilities and helpers for targeting AArch32 and AArch64 architectures.
 namespace Utils {
 
+//! Encodes a 12-bit immediate part of opcode that ise used by a standard 32-bit ARM encoding.
+ASMJIT_MAYBE_UNUSED
+static inline bool encodeAArch32Imm(uint64_t imm, uint32_t* encodedImmOut) noexcept {
+  if (imm & 0xFFFFFFFF00000000u)
+    return false;
+
+  uint32_t v = uint32_t(imm);
+  uint32_t r = 0;
+
+  if (v <= 0xFFu) {
+    *encodedImmOut = v;
+    return true;
+  }
+
+  // Rotate if there are bits on both ends (LSB and MSB)
+  // (otherwise we would not be able to calculate the rotation with ctz).
+  if (v & 0xFF0000FFu) {
+    v = Support::ror(v, 16);
+    r = 16u;
+  }
+
+  uint32_t n = Support::ctz(v) & ~0x1u;
+  r = (r - n) & 0x1Eu;
+  v = Support::ror(v, n);
+
+  if (v > 0xFFu)
+    return false;
+
+  *encodedImmOut = v | (r << 7);
+  return true;
+}
+
 //! Decomposed fields of a logical immediate value.
 struct LogicalImm {
   uint32_t n;
@@ -94,6 +127,13 @@ static ASMJIT_INLINE_NODEBUG bool isLogicalImm(uint64_t imm, uint32_t width) noe
   return encodeLogicalImm(imm, width, &dummy);
 }
 
+//! Returns true if the given `imm` value is encodable as an immediate with `add` and `sub` instructions on AArch64.
+//! These two instructions can encode 12-bit immediate value optionally shifted left by 12 bits.
+ASMJIT_MAYBE_UNUSED
+static ASMJIT_INLINE_NODEBUG bool isAddSubImm(uint64_t imm) noexcept {
+  return imm <= 0xFFFu || (imm & ~uint64_t(0xFFFu << 12)) == 0;
+}
+
 //! Returns true if the given `imm` value is a byte mask. Byte mask has each byte part of the value set to either
 //! 0x00 or 0xFF. Some ARM instructions accept immediates that form a byte-mask and this function can be used to
 //! verify that the immediate is encodable before using the value.

deps/asmjit/src/asmjit/asmjit.h

@@ -3,7 +3,7 @@
 // SPDX-License-Identifier: Zlib
 // Official GitHub Repository: https://github.com/asmjit/asmjit
 //
-// Copyright (c) 2008-2021 The AsmJit Authors
+// Copyright (c) 2008-2024 The AsmJit Authors
 //
 // This software is provided 'as-is', without any express or implied
 // warranty. In no event will the authors be held liable for any damages

deps/asmjit/src/asmjit/core.h

@@ -179,38 +179,47 @@ namespace asmjit {
 //! AsmJit currently supports only X86/X64 backend, but the plan is to add more backends in the future. By default
 //! AsmJit builds only the host backend, which is auto-detected at compile-time, but this can be overridden.
 //!
-//!   - \ref ASMJIT_NO_X86 - Disable X86/X64 backends.
-//!   - \ref ASMJIT_NO_FOREIGN - Disables the support for foreign architectures.
+//!   - \ref ASMJIT_NO_X86 - Disables both X86 and X86_64 backends.
+//!   - \ref ASMJIT_NO_AARCH64 - Disables AArch64 backend.
+//!   - \ref ASMJIT_NO_FOREIGN - Disables the support for foreign architecture backends, only keeps a native backend.
+//!
+//! ### AsmJit Compilation Options
+//!
+//!   - \ref ASMJIT_NO_DEPRECATED - Disables deprecated API at compile time so it won't be available and the
+//!     compilation will fail if there is attempt to use such API. This includes deprecated classes, namespaces,
+//!     enumerations, and functions.
+//!
+//!   - \ref ASMJIT_NO_SHM_OPEN - Disables functionality that uses `shm_open()`.
+//!
+//!   - \ref ASMJIT_NO_ABI_NAMESPACE - Disables inline ABI namespace within `asmjit` namespace. This is only provided
+//!     for users that control all the dependencies (even transitive ones) and that make sure that no two AsmJit
+//!     versions are used at the same time. This option can be debugging a little simpler as there would not be ABI
+//!     tag after `asmjit::` namespace. Otherwise asmjit would look like `asmjit::_abi_1_13::`, for example.
 //!
 //! ### Features Selection
 //!
 //! AsmJit builds by defaults all supported features, which includes all emitters, logging, instruction validation and
 //! introspection, and JIT memory allocation. Features can be disabled at compile time by using `ASMJIT_NO_...`
 //! definitions.
-//!
-//!   - \ref ASMJIT_NO_DEPRECATED - Disables deprecated API at compile time so it won't be available and the
-//!     compilation will fail if there is attempt to use such API. This includes deprecated classes, namespaces,
-//!     enumerations, and functions.
-//!
-//!   - \ref ASMJIT_NO_BUILDER - Disables \ref asmjit_builder functionality completely. This implies \ref
-//!     ASMJIT_NO_COMPILER as \ref asmjit_compiler cannot be used without \ref asmjit_builder.
-//!
-//!   - \ref ASMJIT_NO_COMPILER - Disables \ref asmjit_compiler functionality completely.
-//!
 //!   - \ref ASMJIT_NO_JIT - Disables JIT memory management and \ref JitRuntime.
 //!
-//!   - \ref ASMJIT_NO_LOGGING - Disables \ref Logger and \ref Formatter.
-//!
 //!   - \ref ASMJIT_NO_TEXT - Disables everything that contains string representation of AsmJit constants, should
 //!     be used together with \ref ASMJIT_NO_LOGGING as logging doesn't make sense without the ability to query
 //!     instruction names, register names, etc...
 //!
+//!   - \ref ASMJIT_NO_LOGGING - Disables \ref Logger and \ref Formatter.
+//!
 //!   - \ref ASMJIT_NO_VALIDATION - Disables validation API.
 //!
 //!   - \ref ASMJIT_NO_INTROSPECTION - Disables instruction introspection API, must be used together with \ref
 //!     ASMJIT_NO_COMPILER as \ref asmjit_compiler requires introspection for its liveness analysis and register
 //!     allocation.
 //!
+//!   - \ref ASMJIT_NO_BUILDER - Disables \ref asmjit_builder functionality completely. This implies \ref
+//!     ASMJIT_NO_COMPILER as \ref asmjit_compiler cannot be used without \ref asmjit_builder.
+//!
+//!   - \ref ASMJIT_NO_COMPILER - Disables \ref asmjit_compiler functionality completely.
+//!
 //! \note It's not recommended to disable features if you plan to build AsmJit as a shared library that will be
 //! used by multiple projects that you don't control how AsmJit was built (for example AsmJit in a Linux distribution).
 //! The possibility to disable certain features exists mainly for customized AsmJit builds.
@@ -231,7 +240,7 @@ namespace asmjit {
 //!
 //! Useful tips before you start:
 //!
-//!   - Visit our [Public Gitter Channel](https://gitter.im/asmjit/asmjit) if you need a quick help.
+//!   - Visit our [Public Gitter Chat](https://app.gitter.im/#/room/#asmjit:gitter.im) if you need a quick help.
 //!
 //!   - Build AsmJit with `ASMJIT_NO_DEPRECATED` macro defined to make sure that you are not using deprecated
 //!     functionality at all. Deprecated functions are decorated with `ASMJIT_DEPRECATED()` macro, but sometimes
@@ -239,6 +248,47 @@ namespace asmjit {
 //!     because some compilers would warn about that. If your project compiles fine with `ASMJIT_NO_DEPRECATED`
 //!     it's not using anything, which was deprecated.
 //!
+//! ### Changes committed at 2024-01-01
+//!
+//! Core changes:
+//!
+//!   - Renamed equality functions `eq()` to `equals()` - Only related to `String`, `ZoneVector`, and `CpuFeatures`.
+//!     Old function names were deprecated.
+//!
+//!   - Removed `CallConvId::kNone` in favor of `CallConvId::kCDecl`, which is now the default calling convention.
+//!
+//!   - Deprecated `CallConvId::kHost` in favor of `CallConvId::kCDecl` - host calling convention is now not part
+//!     of CallConvId, it can be calculated from CallConvId and Environment instead.
+//!
+//! ### Changes committed at 2023-12-27
+//!
+//! Core changes:
+//!
+//!   - Renamed `a64::Vec::ElementType` to `a64::VecElementType` and made it a typed enum. This enum was used mostly
+//!     internally, but there is a public API using it, so it's a breaking change.
+//!
+//!   - Refactored `FuncSignature`, `FuncSignatureT`, and `FuncSignatureBuilder`. There is only `FuncSignature` now,
+//!     which acts as a function signature holder and builder. Replace `FuncSignatureBuilder` with `FuncSignature`
+//!     and use `FuncSignature::build<args>` instead of `FuncSignatureT<args>`. The old API has been deprecated.
+//!
+//!   - The maximum number of function arguments was raised from 16 to 32.
+//!
+//! ### Changes committed at 2023-12-26
+//!
+//! Core changes:
+//!
+//!   - Reworked InstNode and InstExNode to be friendlier to static analysis and to not cause undefined behavior.
+//!     InstNode has no operands visually embedded within the struct so there is no _opArray (which was internal).
+//!     This means that sizeof(InstNode) changed, but since it's allocated by AsmJit this should be fine. Moreover,
+//!     there is no longer InstExNode as that was more a hack, instead there is now InstNodeWithOperands, which is
+//!     a template and specifies the number of operands embedded (InstNode accesses these). All nodes that inherited
+//!     InstExNode now just inherit InstNodeWithOperands<InstNode::kBaseOpCapacity>, which would provide the same
+//!     number of nodes as InstNode.
+//!
+//!   - Moved GP and Vec registers from asmjit::arm namespace to asmjit::a64 namespace. At this time there was
+//!     no prior deprecation as having arm::Vec would collide with a64::Vec as arm namespace is used within a64
+//!     namespace. Just change `arm::Gp` to `a64::Gp` and `arm::Vec` to `a64::Vec`.
+//!
 //! ### Changes committed at 2023-09-10
 //!
 //! Core changes:
@@ -419,7 +469,7 @@ namespace asmjit {
 //! // Calling a function (Compiler) changed - use invoke() instead of call().
 //! void functionInvocation(x86::Compiler& cc) {
 //!   InvokeNode* invokeNode;
-//!   cc.invoke(&invokeNode, targetOperand, FuncSignatureT<...>(...));
+//!   cc.invoke(&invokeNode, targetOperand, FuncSignature::build<...>(...));
 //! }
 //! ```
 
@@ -916,12 +966,15 @@ namespace asmjit {
 //! with assembler requires the knowledge of the following:
 //!
 //!   - \ref BaseAssembler and architecture-specific assemblers:
-//!     - \ref x86::Assembler - Assembler specific to X86 architecture
+//!     - \ref x86::Assembler - Assembler implementation targeting X86 and X86_64 architectures.
+//!     - \ref a64::Assembler - Assembler implementation targeting AArch64 architecture.
 //!   - \ref Operand and its variations:
 //!     - \ref BaseReg - Base class for a register operand, inherited by:
-//!        - \ref x86::Reg - Register operand specific to X86 architecture.
+//!        - \ref x86::Reg - Register operand specific to X86 and X86_64 architectures.
+//!        - \ref arm::Reg - Register operand specific to AArch64 architecture.
 //!     - \ref BaseMem - Base class for a memory operand, inherited by:
 //!        - \ref x86::Mem - Memory operand specific to X86 architecture.
+//!        - \ref arm::Mem - Memory operand specific to AArch64 architecture.
 //!     - \ref Imm - Immediate (value) operand.
 //!     - \ref Label - Label operand.
 //!
@@ -1029,7 +1082,7 @@ namespace asmjit {
 //!
 //!   // Type-unsafe, but possible.
 //!   a.emit(x86::Inst::kIdMov, dst, m);
-//!   // Also possible, `emit()` is typeless and can be used with raw Operand.
+//!   // Also possible, `emit()` is type-less and can be used with raw Operand.
 //!   a.emit(x86::Inst::kIdMov, dst, op);
 //! }
 //! ```
@@ -1100,10 +1153,10 @@ namespace asmjit {
 //!
 //! void testX86Mem() {
 //!   // The same as: dword ptr [rax + rbx].
-//!   x86::Mem a = x86::dword_ptr(rax, rbx);
+//!   x86::Mem a = x86::dword_ptr(x86::rax, x86::rbx);
 //!
 //!   // The same as: qword ptr [rdx + rsi << 0 + 1].
-//!   x86::Mem b = x86::qword_ptr(rdx, rsi, 0, 1);
+//!   x86::Mem b = x86::qword_ptr(x86::rdx, x86::rsi, 0, 1);
 //! }
 //! ```
 //!
@@ -1116,18 +1169,18 @@ namespace asmjit {
 //!
 //! void testX86Mem() {
 //!   // The same as: dword ptr [rax + 12].
-//!   x86::Mem mem = x86::dword_ptr(rax, 12);
+//!   x86::Mem mem = x86::dword_ptr(x86::rax, 12);
 //!
 //!   mem.hasBase();                    // true.
 //!   mem.hasIndex();                   // false.
 //!   mem.size();                       // 4.
 //!   mem.offset();                     // 12.
 //!
-//!   mem.setSize(0);                   // Sets the size to 0 (makes it sizeless).
+//!   mem.setSize(0);                   // Sets the size to 0 (makes it size-less).
 //!   mem.addOffset(-1);                // Adds -1 to the offset and makes it 11.
 //!   mem.setOffset(0);                 // Sets the offset to 0.
-//!   mem.setBase(rcx);                 // Changes BASE to RCX.
-//!   mem.setIndex(rax);                // Changes INDEX to RAX.
+//!   mem.setBase(x86::rcx);            // Changes BASE to RCX.
+//!   mem.setIndex(x86::rax);           // Changes INDEX to RAX.
 //!   mem.hasIndex();                   // true.
 //! }
 //! // ...
@@ -1219,7 +1272,8 @@ namespace asmjit {
 //!
 //! ### Builder Examples
 //!
-//!   - \ref x86::Builder provides many X86/X64 examples.
+//!   - \ref x86::Builder - Builder implementation targeting X86 and X86_64 architectures.
+//!   - \ref a64::Builder - Builder implementation targeting AArch64 architecture.
 
 
 //! \defgroup asmjit_compiler Compiler
@@ -1256,7 +1310,8 @@ namespace asmjit {
 //!
 //! ### Compiler Examples
 //!
-//!   - \ref x86::Compiler provides many X86/X64 examples.
+//!   - \ref x86::Compiler - Compiler implementation targeting X86 and X86_64 architectures.
+//!   - \ref a64::Compiler - Compiler implementation targeting AArch64 architecture.
 //!
 //! ### Compiler Tips
 //!
@@ -1428,7 +1483,7 @@ namespace asmjit {
 //! The first example illustrates how to format operands:
 //!
 //! ```
-//! #include <asmjit/core.h>
+//! #include <asmjit/x86.h>
 //! #include <stdio.h>
 //!
 //! using namespace asmjit;
@@ -1453,17 +1508,17 @@ namespace asmjit {
 //!   // compatible with what AsmJit normally does.
 //!   Arch arch = Arch::kX64;
 //!
-//!   log(arch, rax);                    // Prints 'rax'.
-//!   log(arch, ptr(rax, rbx, 2));       // Prints '[rax + rbx * 4]`.
-//!   log(arch, dword_ptr(rax, rbx, 2)); // Prints 'dword [rax + rbx * 4]`.
-//!   log(arch, imm(42));                // Prints '42'.
+//!   logOperand(arch, rax);                    // Prints 'rax'.
+//!   logOperand(arch, ptr(rax, rbx, 2));       // Prints '[rax + rbx * 4]`.
+//!   logOperand(arch, dword_ptr(rax, rbx, 2)); // Prints 'dword [rax + rbx * 4]`.
+//!   logOperand(arch, imm(42));                // Prints '42'.
 //! }
 //! ```
 //!
 //! Next example illustrates how to format whole instructions:
 //!
 //! ```
-//! #include <asmjit/core.h>
+//! #include <asmjit/x86.h>
 //! #include <stdio.h>
 //! #include <utility>
 //!
@@ -1478,7 +1533,7 @@ namespace asmjit {
 //!   FormatFlags formatFlags = FormatFlags::kNone;
 //!
 //!   // The formatter expects operands in an array.
-//!   Operand_ operands { std::forward<Args>(args)... };
+//!   Operand_ operands[] { std::forward<Args>(args)... };
 //!
 //!   StringTmp<128> sb;
 //!   Formatter::formatInstruction(
@@ -1500,13 +1555,13 @@ namespace asmjit {
 //!   // Prints 'vaddpd zmm0, zmm1, [rax] {1to8}'.
 //!   logInstruction(arch,
 //!                  BaseInst(Inst::kIdVaddpd),
-//!                  zmm0, zmm1, ptr(rax)._1toN());
+//!                  zmm0, zmm1, ptr(rax)._1to8());
 //!
 //!   // BaseInst abstracts instruction id, instruction options, and extraReg.
 //!   // Prints 'lock add [rax], rcx'.
 //!   logInstruction(arch,
 //!                  BaseInst(Inst::kIdAdd, InstOptions::kX86_Lock),
-//!                  x86::ptr(rax), rcx);
+//!                  ptr(rax), rcx);
 //!
 //!   // Similarly an extra register (like AVX-512 selector) can be used.
 //!   // Prints 'vaddpd zmm0 {k2} {z}, zmm1, [rax]'.
@@ -1624,7 +1679,7 @@ namespace asmjit {
 //!
 //! Each instruction can be then queried for the following information:
 //!
-//!   - \ref InstRWInfo - Read/write information of instruction and its oprands (includes \ref OpRWInfo).
+//!   - \ref InstRWInfo - Read/write information of instruction and its operands (includes \ref OpRWInfo).
 //!
 //!   - \ref CpuFeatures - CPU features required to execute the instruction.
 //!

deps/asmjit/src/asmjit/core/api-config.h

@@ -16,7 +16,7 @@
 #define ASMJIT_LIBRARY_MAKE_VERSION(major, minor, patch) ((major << 16) | (minor << 8) | (patch))
 
 //! AsmJit library version, see \ref ASMJIT_LIBRARY_MAKE_VERSION for a version format reference.
-#define ASMJIT_LIBRARY_VERSION ASMJIT_LIBRARY_MAKE_VERSION(1, 11, 0)
+#define ASMJIT_LIBRARY_VERSION ASMJIT_LIBRARY_MAKE_VERSION(1, 13, 0)
 
 //! \def ASMJIT_ABI_NAMESPACE
 //!
@@ -27,7 +27,7 @@
 //! AsmJit default, which makes it possible to use multiple AsmJit libraries within a single project, totally
 //! controlled by users. This is useful especially in cases in which some of such library comes from third party.
 #if !defined(ASMJIT_ABI_NAMESPACE)
-  #define ASMJIT_ABI_NAMESPACE _abi_1_11
+  #define ASMJIT_ABI_NAMESPACE _abi_1_13
 #endif // !ASMJIT_ABI_NAMESPACE
 
 //! \}
@@ -42,7 +42,7 @@
 #include <stdlib.h>
 #include <string.h>
 
-#include <iterator>
+#include <initializer_list>
 #include <limits>
 #include <type_traits>
 #include <utility>
@@ -112,7 +112,7 @@ namespace asmjit {
 #define ASMJIT_NO_INTROSPECTION
 
 // Avoid doxygen preprocessor using feature-selection definitions.
-#undef ASMJIT_BUILD_EMBNED
+#undef ASMJIT_BUILD_EMBED
 #undef ASMJIT_BUILD_STATIC
 #undef ASMJIT_BUILD_DEBUG
 #undef ASMJIT_BUILD_RELEASE
@@ -163,6 +163,41 @@ namespace asmjit {
 // Target Architecture Detection
 // =============================
 
+//! \addtogroup asmjit_core
+//! \{
+
+//! \def ASMJIT_ARCH_X86
+//!
+//! Defined to either 0, 32, or 64 depending on whether the target CPU is X86 (32) or X86_64 (64).
+
+//! \def ASMJIT_ARCH_ARM
+//!
+//! Defined to either 0, 32, or 64 depending on whether the target CPU is ARM (32) or AArch64 (64).
+
+//! \def ASMJIT_ARCH_MIPS
+//!
+//! Defined to either 0, 32, or 64 depending on whether the target CPU is MIPS (32) or MISP64 (64).
+
+//! \def ASMJIT_ARCH_RISCV
+//!
+//! Defined to either 0, 32, or 64 depending on whether the target CPU is RV32 (32) or RV64 (64).
+
+//! \def ASMJIT_ARCH_BITS
+//!
+//! Defined to either 32 or 64 depending on the target.
+
+//! \def ASMJIT_ARCH_LE
+//!
+//! Defined to 1 if the target architecture is little endian.
+
+//! \def ASMJIT_ARCH_BE
+//!
+//! Defined to 1 if the target architecture is big endian.
+
+//! \}
+
+//! \cond NONE
+
 #if defined(_M_X64) || defined(__x86_64__)
   #define ASMJIT_ARCH_X86 64
 #elif defined(_M_IX86) || defined(__X86__) || defined(__i386__)
@@ -187,10 +222,17 @@ namespace asmjit {
   #define ASMJIT_ARCH_MIPS 0
 #endif
 
-#define ASMJIT_ARCH_BITS (ASMJIT_ARCH_X86 | ASMJIT_ARCH_ARM | ASMJIT_ARCH_MIPS)
+// NOTE `__riscv` is the correct macro in this case as specified by "RISC-V Toolchain Conventions".
+#if (defined(__riscv) || defined(__riscv__)) && defined(__riscv_xlen)
+  #define ASMJIT_ARCH_RISCV __riscv_xlen
+#else
+  #define ASMJIT_ARCH_RISCV 0
+#endif
+
+#define ASMJIT_ARCH_BITS (ASMJIT_ARCH_X86 | ASMJIT_ARCH_ARM | ASMJIT_ARCH_MIPS | ASMJIT_ARCH_RISCV)
 #if ASMJIT_ARCH_BITS == 0
   #undef ASMJIT_ARCH_BITS
-  #if defined (__LP64__) || defined(_LP64)
+  #if defined(__LP64__) || defined(_LP64)
     #define ASMJIT_ARCH_BITS 64
   #else
     #define ASMJIT_ARCH_BITS 32
@@ -212,62 +254,88 @@ namespace asmjit {
     #define ASMJIT_NO_X86
   #endif
 
-  #if !ASMJIT_ARCH_ARM && !defined(ASMJIT_NO_AARCH64)
+  #if ASMJIT_ARCH_ARM != 64 && !defined(ASMJIT_NO_AARCH64)
     #define ASMJIT_NO_AARCH64
   #endif
 #endif
 
+//! \endcond
 
 // C++ Compiler and Features Detection
 // ===================================
 
-#define ASMJIT_CXX_GNU 0
-#define ASMJIT_CXX_MAKE_VER(MAJOR, MINOR) ((MAJOR) * 1000 + (MINOR))
-
-// Intel Compiler [pretends to be GNU or MSC, so it must be checked first]:
-//   - https://software.intel.com/en-us/articles/c0x-features-supported-by-intel-c-compiler
-//   - https://software.intel.com/en-us/articles/c14-features-supported-by-intel-c-compiler
-//   - https://software.intel.com/en-us/articles/c17-features-supported-by-intel-c-compiler
-#if defined(__INTEL_COMPILER)
-
-// MSC Compiler:
-//   - https://msdn.microsoft.com/en-us/library/hh567368.aspx
-//
-// Version List:
-//   - 16.00.0 == VS2010
-//   - 17.00.0 == VS2012
-//   - 18.00.0 == VS2013
-//   - 19.00.0 == VS2015
-//   - 19.10.0 == VS2017
-#elif defined(_MSC_VER) && defined(_MSC_FULL_VER)
-
-// Clang Compiler [Pretends to be GNU, so it must be checked before]:
-//   - https://clang.llvm.org/cxx_status.html
-#elif defined(__clang_major__) && defined(__clang_minor__) && defined(__clang_patchlevel__)
-
-// GNU Compiler:
-//   - https://gcc.gnu.org/projects/cxx-status.html
-#elif defined(__GNUC__) && defined(__GNUC_MINOR__) && defined(__GNUC_PATCHLEVEL__)
-
-  #undef ASMJIT_CXX_GNU
-  #define ASMJIT_CXX_GNU ASMJIT_CXX_MAKE_VER(__GNUC__, __GNUC_MINOR__)
-
-#endif
-
-// Compiler features detection macros.
-#if defined(__clang__) && defined(__has_attribute)
+#if defined(__GNUC__) && defined(__has_attribute)
   #define ASMJIT_CXX_HAS_ATTRIBUTE(NAME, CHECK) (__has_attribute(NAME))
 #else
   #define ASMJIT_CXX_HAS_ATTRIBUTE(NAME, CHECK) (!(!(CHECK)))
-#endif
+#endif // !ASMJIT_CXX_HAS_ATTRIBUTE
 
 // API Decorators & C++ Extensions
 // ===============================
 
+//! \addtogroup asmjit_core
+//! \{
+
 //! \def ASMJIT_API
 //!
 //! A decorator that is used to decorate API that AsmJit exports when built as a shared library.
 
+//! \def ASMJIT_VIRTAPI
+//!
+//! This is basically a workaround. When using MSVC and marking class as DLL export everything gets exported, which
+//! is unwanted in most projects. MSVC automatically exports typeinfo and vtable if at least one symbol of the class
+//! is exported. However, GCC has some strange behavior that even if one or more symbol is exported it doesn't export
+//! typeinfo unless the class itself is decorated with "visibility(default)" (i.e. ASMJIT_API).
+
+//! \def ASMJIT_FORCE_INLINE
+//!
+//! Decorator to force inlining of functions, uses either `__attribute__((__always_inline__))` or __forceinline,
+//! depending on C++ compiler.
+
+//! \def ASMJIT_INLINE_NODEBUG
+//!
+//! Like \ref ASMJIT_FORCE_INLINE, but uses additionally `__nodebug__` or `__artificial__` attribute to make the
+//! debugging of some AsmJit functions easier, especially getters and one-line abstractions where usually you don't
+//! want to step in.
+
+//! \def ASMJIT_NOINLINE
+//!
+//! Decorator to avoid inlining of functions, uses either `__attribute__((__noinline__))` or `__declspec(noinline)`
+//! depending on C++ compiler.
+
+//! \def ASMJIT_NORETURN
+//!
+//! Decorator that marks functions that should never return. Typically used to implement assertion handlers that
+//! terminate, so the function never returns.
+
+//! \def ASMJIT_CDECL
+//!
+//! CDECL function attribute - either `__attribute__((__cdecl__))` or `__cdecl`.
+
+//! \def ASMJIT_STDCALL
+//!
+//! STDCALL function attribute - either `__attribute__((__stdcall__))` or `__stdcall`.
+//!
+//! \note This expands to nothing on non-x86 targets as STDCALL is X86 specific.
+
+//! \def ASMJIT_FASTCALL
+//!
+//! FASTCALL function attribute - either `__attribute__((__fastcall__))` or `__fastcall`.
+//!
+//! \note Expands to nothing on non-x86 targets as FASTCALL is X86 specific.
+
+//! \def ASMJIT_REGPARM(N)
+//!
+//! Expands to `__attribute__((__regparm__(N)))` when compiled by GCC or clang, nothing otherwise.
+
+//! \def ASMJIT_VECTORCALL
+//!
+//! VECTORCALL function attribute - either `__attribute__((__vectorcall__))` or `__vectorcall`.
+//!
+//! \note Expands to nothing on non-x86 targets as VECTORCALL is X86 specific.
+
+//! \}
+
 // API (Export / Import).
 #if !defined(ASMJIT_STATIC)
   #if defined(_WIN32) && (defined(_MSC_VER) || defined(__MINGW32__))
@@ -295,13 +363,7 @@ namespace asmjit {
   #define ASMJIT_VARAPI extern ASMJIT_API
 #endif
 
-//! \def ASMJIT_VIRTAPI
-//!
-//! This is basically a workaround. When using MSVC and marking class as DLL export everything gets exported, which
-//! is unwanted in most projects. MSVC automatically exports typeinfo and vtable if at least one symbol of the class
-//! is exported. However, GCC has some strange behavior that even if one or more symbol is exported it doesn't export
-//! typeinfo unless the class itself is decorated with "visibility(default)" (i.e. ASMJIT_API).
-#if !defined(_WIN32) && defined(__GNUC__)
+#if defined(__GNUC__) && !defined(_WIN32)
   #define ASMJIT_VIRTAPI ASMJIT_API
 #else
   #define ASMJIT_VIRTAPI
@@ -458,17 +520,10 @@ namespace asmjit {
 //! Marks function, class, struct, enum, or anything else as deprecated.
 #if defined(__GNUC__)
   #define ASMJIT_DEPRECATED(MESSAGE) __attribute__((__deprecated__(MESSAGE)))
-  #if defined(__clang__)
-    #define ASMJIT_DEPRECATED_STRUCT(MESSAGE) __attribute__((__deprecated__(MESSAGE)))
-  #else
-    #define ASMJIT_DEPRECATED_STRUCT(MESSAGE) /* not usable if a deprecated function uses it */
-  #endif
 #elif defined(_MSC_VER)
   #define ASMJIT_DEPRECATED(MESSAGE) __declspec(deprecated(MESSAGE))
-  #define ASMJIT_DEPRECATED_STRUCT(MESSAGE) /* not usable if a deprecated function uses it */
 #else
   #define ASMJIT_DEPRECATED(MESSAGE)
-  #define ASMJIT_DEPRECATED_STRUCT(MESSAGE)
 #endif
 
 // Utilities.
@@ -477,66 +532,60 @@ namespace asmjit {
 
 #if ASMJIT_CXX_HAS_ATTRIBUTE(no_sanitize, 0)
   #define ASMJIT_ATTRIBUTE_NO_SANITIZE_UNDEF __attribute__((__no_sanitize__("undefined")))
-#elif ASMJIT_CXX_GNU >= ASMJIT_CXX_MAKE_VER(4, 9)
+#elif defined(__GNUC__) && __GNUC__ >= 5
   #define ASMJIT_ATTRIBUTE_NO_SANITIZE_UNDEF __attribute__((__no_sanitize_undefined__))
 #else
   #define ASMJIT_ATTRIBUTE_NO_SANITIZE_UNDEF
 #endif
 
-// Begin-Namespace & End-Namespace Macros
+// Diagnostic Macros
 // ======================================
 
-#if defined _DOXYGEN
-  #define ASMJIT_BEGIN_NAMESPACE namespace asmjit {
-  #define ASMJIT_END_NAMESPACE }
-#elif defined(__clang__)
-  #define ASMJIT_BEGIN_NAMESPACE                                              \
-    namespace asmjit { inline namespace ASMJIT_ABI_NAMESPACE {                \
-      _Pragma("clang diagnostic push")                                        \
-      _Pragma("clang diagnostic ignored \"-Wconstant-logical-operand\"")      \
-      _Pragma("clang diagnostic ignored \"-Wunnamed-type-template-args\"")
-  #define ASMJIT_END_NAMESPACE                                                \
-      _Pragma("clang diagnostic pop")                                         \
-    }}
-#elif defined(__GNUC__) && __GNUC__ == 4
-  #define ASMJIT_BEGIN_NAMESPACE                                              \
-    namespace asmjit { inline namespace ASMJIT_ABI_NAMESPACE {                \
+#if !defined(__clang__) && !defined(__INTEL_COMPILER) && !defined(_DOXYGEN)
+  #if defined(__GNUC__) && __GNUC__ == 4
+    // There is a bug in GCC 4.X that has been fixed in GCC 5+, so just silence the warning.
+    #define ASMJIT_BEGIN_DIAGNOSTIC_SCOPE                                     \
       _Pragma("GCC diagnostic push")                                          \
       _Pragma("GCC diagnostic ignored \"-Wmissing-field-initializers\"")
-  #define ASMJIT_END_NAMESPACE                                                \
-      _Pragma("GCC diagnostic pop")                                           \
-    }}
-#elif defined(__GNUC__) && __GNUC__ >= 8
-  #define ASMJIT_BEGIN_NAMESPACE                                              \
-    namespace asmjit { inline namespace ASMJIT_ABI_NAMESPACE {                \
-      _Pragma("GCC diagnostic push")                                          \
-      _Pragma("GCC diagnostic ignored \"-Wclass-memaccess\"")
-  #define ASMJIT_END_NAMESPACE                                                \
-      _Pragma("GCC diagnostic pop")                                           \
-    }}
-#elif defined(_MSC_VER) && !defined(__INTEL_COMPILER)
-  #define ASMJIT_BEGIN_NAMESPACE                                              \
-    namespace asmjit { inline namespace ASMJIT_ABI_NAMESPACE {                \
+    #define ASMJIT_END_DIAGNOSTIC_SCOPE                                       \
+      _Pragma("GCC diagnostic pop")
+  #elif defined(_MSC_VER)
+    #define ASMJIT_BEGIN_DIAGNOSTIC_SCOPE                                     \
       __pragma(warning(push))                                                 \
       __pragma(warning(disable: 4127))  /* conditional expression is const */ \
       __pragma(warning(disable: 4201))  /* nameless struct/union */
+    #define ASMJIT_END_DIAGNOSTIC_SCOPE                                       \
+      __pragma(warning(pop))
+  #endif
+#endif
+
+#if !defined(ASMJIT_BEGIN_DIAGNOSTIC_SCOPE) && !defined(ASMJIT_END_DIAGNOSTIC_SCOPE)
+  #define ASMJIT_BEGIN_DIAGNOSTIC_SCOPE
+  #define ASMJIT_END_DIAGNOSTIC_SCOPE
+#endif
+
+// Begin-Namespace & End-Namespace Macros
+// ======================================
+
+#if !defined(ASMJIT_NO_ABI_NAMESPACE) && !defined(_DOXYGEN)
+  #define ASMJIT_BEGIN_NAMESPACE                                              \
+    ASMJIT_BEGIN_DIAGNOSTIC_SCOPE                                             \
+    namespace asmjit {                                                        \
+    inline namespace ASMJIT_ABI_NAMESPACE {
   #define ASMJIT_END_NAMESPACE                                                \
-      __pragma(warning(pop))                                                  \
-    }}
+    }}                                                                        \
+    ASMJIT_END_DIAGNOSTIC_SCOPE
+#else
+  #define ASMJIT_BEGIN_NAMESPACE                                              \
+    ASMJIT_BEGIN_DIAGNOSTIC_SCOPE                                             \
+    namespace asmjit {
+  #define ASMJIT_END_NAMESPACE                                                \
+    }                                                                         \
+    ASMJIT_END_DIAGNOSTIC_SCOPE
 #endif
 
-#if !defined(ASMJIT_BEGIN_NAMESPACE) && !defined(ASMJIT_END_NAMESPACE)
-  #define ASMJIT_BEGIN_NAMESPACE namespace asmjit { inline namespace ASMJIT_ABI_NAMESPACE {
-  #define ASMJIT_END_NAMESPACE }}
-#endif
-
-#define ASMJIT_BEGIN_SUB_NAMESPACE(NAMESPACE)                                 \
-  ASMJIT_BEGIN_NAMESPACE                                                      \
-  namespace NAMESPACE {
-
-#define ASMJIT_END_SUB_NAMESPACE                                              \
-  }                                                                           \
-  ASMJIT_END_NAMESPACE
+#define ASMJIT_BEGIN_SUB_NAMESPACE(NAMESPACE) ASMJIT_BEGIN_NAMESPACE namespace NAMESPACE {
+#define ASMJIT_END_SUB_NAMESPACE } ASMJIT_END_NAMESPACE
 
 // C++ Utilities
 // =============
@@ -612,10 +661,4 @@ namespace asmjit {
     }
 #endif
 
-// Cleanup Api-Config Specific Macros
-// ==================================
-
-#undef ASMJIT_CXX_GNU
-#undef ASMJIT_CXX_MAKE_VER
-
 #endif // ASMJIT_CORE_API_CONFIG_H_INCLUDED

deps/asmjit/src/asmjit/core/archcommons.h

@@ -29,8 +29,8 @@ enum class CondCode : uint8_t {
   kNE             = 0x03u,      //!<        Z==0         (any_sign !=)
   kCS             = 0x04u,      //!< C==1                (unsigned >=)
   kHS             = 0x04u,      //!< C==1                (unsigned >=)
-  kCC             = 0x05u,      //!< C==0                (unsigned < )
   kLO             = 0x05u,      //!< C==0                (unsigned < )
+  kCC             = 0x05u,      //!< C==0                (unsigned < )
   kMI             = 0x06u,      //!<               N==1  (is negative)
   kPL             = 0x07u,      //!<               N==0  (is positive or zero)
   kVS             = 0x08u,      //!<               V==1  (is overflow)
@@ -42,21 +42,24 @@ enum class CondCode : uint8_t {
   kGT             = 0x0Eu,      //!<        Z==0 & N==V  (signed   > )
   kLE             = 0x0Fu,      //!<        Z==1 | N!=V  (signed   <=)
 
-  kSign           = kMI,        //!< Sign.
-  kNotSign        = kPL,        //!< Not sign.
-
-  kOverflow       = kVS,        //!< Signed overflow.
-  kNotOverflow    = kVC,        //!< Not signed overflow.
+  kZero           = kEQ,        //!< Zero flag (alias to equal).
+  kNotZero        = kNE,        //!< Not zero (alias to Not Equal).
 
   kEqual          = kEQ,        //!< Equal     `a == b`.
   kNotEqual       = kNE,        //!< Not Equal `a != b`.
 
-  kZero           = kEQ,        //!< Zero (alias to equal).
-  kNotZero        = kNE,        //!< Not Zero (alias to Not Equal).
+  kCarry          = kCS,        //!< Carry flag.
+  kNotCarry       = kCC,        //!< Not carry.
+
+  kSign           = kMI,        //!< Sign flag.
+  kNotSign        = kPL,        //!< Not sign.
 
   kNegative       = kMI,        //!< Negative.
   kPositive       = kPL,        //!< Positive or zero.
 
+  kOverflow       = kVS,        //!< Signed overflow.
+  kNotOverflow    = kVC,        //!< Not signed overflow.
+
   kSignedLT       = kLT,        //!< Signed    `a <  b`.
   kSignedLE       = kLE,        //!< Signed    `a <= b`.
   kSignedGT       = kGT,        //!< Signed    `a >  b`.
@@ -67,49 +70,51 @@ enum class CondCode : uint8_t {
   kUnsignedGT     = kHI,        //!< Unsigned  `a >  b`.
   kUnsignedGE     = kHS,        //!< Unsigned  `a >= b`.
 
+  kBTZero         = kZero,      //!< Tested bit is zero.
+  kBTNotZero      = kNotZero,   //!< Tested bit is not zero.
+
   kAlways         = kAL,        //!< No condition code (always).
 
   kMaxValue       = 0x0Fu       //!< Maximum value of `CondCode`.
 };
 
+
+//! \cond
+static constexpr CondCode _reverseCondTable[] = {
+  CondCode::kAL, // AL <- AL
+  CondCode::kNA, // NA <- NA
+  CondCode::kEQ, // EQ <- EQ
+  CondCode::kNE, // NE <- NE
+  CondCode::kLS, // LS <- CS
+  CondCode::kHI, // HI <- LO
+  CondCode::kMI, // MI <- MI
+  CondCode::kPL, // PL <- PL
+  CondCode::kVS, // VS <- VS
+  CondCode::kVC, // VC <- VC
+  CondCode::kLO, // LO <- HI
+  CondCode::kCS, // CS <- LS
+  CondCode::kLE, // LE <- GE
+  CondCode::kGT, // GT <- LT
+  CondCode::kLT, // LT <- GT
+  CondCode::kGE  // GE <- LE
+};
+//! \endcond
+
+//! Reverses a condition code (reverses the corresponding operands of a comparison).
+static ASMJIT_INLINE_NODEBUG constexpr CondCode reverseCond(CondCode cond) noexcept { return _reverseCondTable[uint8_t(cond)]; }
 //! Negates a condition code.
 static ASMJIT_INLINE_NODEBUG constexpr CondCode negateCond(CondCode cond) noexcept { return CondCode(uint8_t(cond) ^ uint8_t(1)); }
 
-//! Data type that can be encoded with the instruction (AArch32 only).
-enum class DataType : uint32_t {
-  //! No data type specified (default for all general purpose instructions).
-  kNone = 0,
-  //! 8-bit signed integer, specified as `.s8` in assembly.
-  kS8 = 1,
-  //! 16-bit signed integer, specified as `.s16` in assembly.
-  kS16 = 2,
-  //! 32-bit signed integer, specified as `.s32` in assembly.
-  kS32 = 3,
-  //! 64-bit signed integer, specified as `.s64` in assembly.
-  kS64 = 4,
-  //! 8-bit unsigned integer, specified as `.u8` in assembly.
-  kU8 = 5,
-  //! 16-bit unsigned integer, specified as `.u16` in assembly.
-  kU16 = 6,
-  //! 32-bit unsigned integer, specified as `.u32` in assembly.
-  kU32 = 7,
-  //! 64-bit unsigned integer, specified as `.u64` in assembly.
-  kU64 = 8,
-  //! 16-bit floating point (half precision), specified as `.f16` in assembly.
-  kF16 = 10,
-  //! 32-bit floating point (single precision), specified as `.f32` in assembly.
-  kF32 = 11,
-  //! 64-bit floating point (double precision), specified as `.f64` in assembly.
-  kF64 = 12,
-  //! 8-bit polynomial.
-  kP8 = 13,
-  //! 16-bit BF16 floating point.
-  kBF16 = 14,
-  //! 64-bit polynomial.
-  kP64 = 15,
-
-  //! Maximum value of `DataType`.
-  kMaxValue = 15
+//! Memory offset mode.
+//!
+//! Describes either fixed, pre-index, or post-index offset modes.
+enum class OffsetMode : uint32_t {
+  //! Fixed offset mode (either no index at all or a regular index without a write-back).
+  kFixed = 0u,
+  //! Pre-index "[BASE, #Offset {, <shift>}]!" with write-back.
+  kPreIndex = 1u,
+  //! Post-index "[BASE], #Offset {, <shift>}" with write-back.
+  kPostIndex = 2u
 };
 
 //! Shift operation predicate (ARM) describes either SHIFT or EXTEND operation.
@@ -187,45 +192,70 @@ public:
   //! Sets shift operation to `op`.
   ASMJIT_INLINE_NODEBUG void setOp(ShiftOp op) noexcept { _op = op; }
 
-  //! Returns the shift smount.
+  //! Returns the shift amount.
   ASMJIT_INLINE_NODEBUG constexpr uint32_t value() const noexcept { return _value; }
   //! Sets shift amount to `value`.
   ASMJIT_INLINE_NODEBUG void setValue(uint32_t value) noexcept { _value = value; }
 };
 
-//! Constructs a `LSL #value` shift (logical shift left).
-static ASMJIT_INLINE_NODEBUG constexpr Shift lsl(uint32_t value) noexcept { return Shift(ShiftOp::kLSL, value); }
-//! Constructs a `LSR #value` shift (logical shift right).
-static ASMJIT_INLINE_NODEBUG constexpr Shift lsr(uint32_t value) noexcept { return Shift(ShiftOp::kLSR, value); }
-//! Constructs a `ASR #value` shift (arithmetic shift right).
-static ASMJIT_INLINE_NODEBUG constexpr Shift asr(uint32_t value) noexcept { return Shift(ShiftOp::kASR, value); }
-//! Constructs a `ROR #value` shift (rotate right).
-static ASMJIT_INLINE_NODEBUG constexpr Shift ror(uint32_t value) noexcept { return Shift(ShiftOp::kROR, value); }
-//! Constructs a `RRX` shift (rotate with carry by 1).
-static ASMJIT_INLINE_NODEBUG constexpr Shift rrx() noexcept { return Shift(ShiftOp::kRRX, 0); }
-//! Constructs a `MSL #value` shift (logical shift left filling ones).
-static ASMJIT_INLINE_NODEBUG constexpr Shift msl(uint32_t value) noexcept { return Shift(ShiftOp::kMSL, value); }
-
-//! Constructs a `UXTB #value` extend and shift (unsigned byte extend).
-static ASMJIT_INLINE_NODEBUG constexpr Shift uxtb(uint32_t value) noexcept { return Shift(ShiftOp::kUXTB, value); }
-//! Constructs a `UXTH #value` extend and shift (unsigned hword extend).
-static ASMJIT_INLINE_NODEBUG constexpr Shift uxth(uint32_t value) noexcept { return Shift(ShiftOp::kUXTH, value); }
-//! Constructs a `UXTW #value` extend and shift (unsigned word extend).
-static ASMJIT_INLINE_NODEBUG constexpr Shift uxtw(uint32_t value) noexcept { return Shift(ShiftOp::kUXTW, value); }
-//! Constructs a `UXTX #value` extend and shift (unsigned dword extend).
-static ASMJIT_INLINE_NODEBUG constexpr Shift uxtx(uint32_t value) noexcept { return Shift(ShiftOp::kUXTX, value); }
-
-//! Constructs a `SXTB #value` extend and shift (signed byte extend).
-static ASMJIT_INLINE_NODEBUG constexpr Shift sxtb(uint32_t value) noexcept { return Shift(ShiftOp::kSXTB, value); }
-//! Constructs a `SXTH #value` extend and shift (signed hword extend).
-static ASMJIT_INLINE_NODEBUG constexpr Shift sxth(uint32_t value) noexcept { return Shift(ShiftOp::kSXTH, value); }
-//! Constructs a `SXTW #value` extend and shift (signed word extend).
-static ASMJIT_INLINE_NODEBUG constexpr Shift sxtw(uint32_t value) noexcept { return Shift(ShiftOp::kSXTW, value); }
-//! Constructs a `SXTX #value` extend and shift (signed dword extend).
-static ASMJIT_INLINE_NODEBUG constexpr Shift sxtx(uint32_t value) noexcept { return Shift(ShiftOp::kSXTX, value); }
-
 //! \}
 
 ASMJIT_END_SUB_NAMESPACE
 
+ASMJIT_BEGIN_SUB_NAMESPACE(a32)
+
+using namespace arm;
+
+//! Data type that can be encoded with AArch32 instruction identifier.
+//!
+//! \note Data types are frequently used with AArch32 SIMD instructions. For example `VMAX` instruction can
+//! use almost all datatypes in a form `VMAX.F32`, `VMAX.S16`, `VMAX.U32`, etc... Emitter automatically adds
+//! the required data type at emit level.
+enum class DataType : uint32_t {
+  //! No data type specified (default for all general purpose instructions).
+  kNone = 0,
+  //! 8-bit signed integer, specified as `.s8` in assembly.
+  kS8 = 1,
+  //! 16-bit signed integer, specified as `.s16` in assembly.
+  kS16 = 2,
+  //! 32-bit signed integer, specified as `.s32` in assembly.
+  kS32 = 3,
+  //! 64-bit signed integer, specified as `.s64` in assembly.
+  kS64 = 4,
+  //! 8-bit unsigned integer, specified as `.u8` in assembly.
+  kU8 = 5,
+  //! 16-bit unsigned integer, specified as `.u16` in assembly.
+  kU16 = 6,
+  //! 32-bit unsigned integer, specified as `.u32` in assembly.
+  kU32 = 7,
+  //! 64-bit unsigned integer, specified as `.u64` in assembly.
+  kU64 = 8,
+  //! 16-bit floating point (half precision), specified as `.f16` in assembly.
+  kF16 = 10,
+  //! 32-bit floating point (single precision), specified as `.f32` in assembly.
+  kF32 = 11,
+  //! 64-bit floating point (double precision), specified as `.f64` in assembly.
+  kF64 = 12,
+  //! 8-bit polynomial.
+  kP8 = 13,
+  //! 16-bit BF16 floating point.
+  kBF16 = 14,
+  //! 64-bit polynomial.
+  kP64 = 15,
+
+  //! Maximum value of `DataType`.
+  kMaxValue = 15
+};
+
+static ASMJIT_INLINE_NODEBUG uint32_t dataTypeSize(DataType dt) noexcept {
+  static constexpr uint8_t table[] = { 0, 1, 2, 4, 8, 1, 2, 4, 8, 2, 4, 8, 1, 2, 8 };
+  return table[size_t(dt)];
+}
+
+ASMJIT_END_SUB_NAMESPACE
+
+ASMJIT_BEGIN_SUB_NAMESPACE(a64)
+using namespace arm;
+ASMJIT_END_SUB_NAMESPACE
+
 #endif // ASMJIT_CORE_ARCHCOMMONS_H_INCLUDED

deps/asmjit/src/asmjit/core/archtraits.h

@@ -74,6 +74,9 @@ enum class Arch : uint8_t {
     ASMJIT_ARCH_X86 == 32 ? kX86 :
     ASMJIT_ARCH_X86 == 64 ? kX64 :
 
+    ASMJIT_ARCH_RISCV == 32 ? kRISCV32 :
+    ASMJIT_ARCH_RISCV == 64 ? kRISCV64 :
+
     ASMJIT_ARCH_ARM == 32 && ASMJIT_ARCH_LE ? kARM :
     ASMJIT_ARCH_ARM == 32 && ASMJIT_ARCH_BE ? kARM_BE :
     ASMJIT_ARCH_ARM == 64 && ASMJIT_ARCH_LE ? kAArch64 :

deps/asmjit/src/asmjit/core/assembler.h

@@ -25,6 +25,7 @@ ASMJIT_BEGIN_NAMESPACE
 //! Check out architecture specific assemblers for more details and examples:
 //!
 //!   - \ref x86::Assembler - X86/X64 assembler implementation.
+//!   - \ref a64::Assembler - AArch64 assembler implementation.
 class ASMJIT_VIRTAPI BaseAssembler : public BaseEmitter {
 public:
   ASMJIT_NONCOPYABLE(BaseAssembler)

deps/asmjit/src/asmjit/core/builder.cpp

@@ -590,7 +590,7 @@ Error BaseBuilder::_emit(InstId instId, const Operand_& o0, const Operand_& o1,
       EmitterUtils::opArrayFromEmitArgs(opArray, o0, o1, o2, opExt);
 
       ValidationFlags validationFlags = isCompiler() ? ValidationFlags::kEnableVirtRegs : ValidationFlags::kNone;
-      Error err = _funcs.validate(arch(), BaseInst(instId, options, _extraReg), opArray, opCount, validationFlags);
+      Error err = _funcs.validate(BaseInst(instId, options, _extraReg), opArray, opCount, validationFlags);
 
       if (ASMJIT_UNLIKELY(err)) {
 #ifndef ASMJIT_NO_LOGGING

deps/asmjit/src/asmjit/core/builder.h

@@ -48,7 +48,7 @@ enum class NodeType : uint8_t {
 
   // [BaseBuilder]
 
-  //! Node is \ref InstNode or \ref InstExNode.
+  //! Node is \ref InstNode.
   kInst = 1,
   //! Node is \ref SectionNode.
   kSection = 2,
@@ -181,6 +181,7 @@ public:
 //! Check out architecture specific builders for more details and examples:
 //!
 //!   - \ref x86::Builder - X86/X64 builder implementation.
+//!   - \ref a64::Builder - AArch64 builder implementation.
 class ASMJIT_VIRTAPI BaseBuilder : public BaseEmitter {
 public:
   ASMJIT_NONCOPYABLE(BaseBuilder)
@@ -546,7 +547,7 @@ public:
     uint8_t _reserved1;
   };
 
-  //! Data that can have different meaning dependning on \ref NodeType.
+  //! Data that can have different meaning depending on \ref NodeType.
   union {
     //! Data useful by any node type.
     AnyData _any;
@@ -694,8 +695,9 @@ public:
 
   //! Returns user data casted to `T*`.
   //!
-  //! User data is decicated to be used only by AsmJit users and not touched by the library. The data has a pointer
-  //! size so you can either store a pointer or `intptr_t` value through `setUserDataAsIntPtr()`.
+  //! User data is dedicated to be used only by AsmJit users and not touched by the library. The data is of a pointer
+  //! size so you can either store a pointer or `int64_t` value through `setUserDataAsPtr()`, `setUserDataAsInt64()`
+  //! and `setUserDataAsUInt64()`.
   template<typename T>
   ASMJIT_INLINE_NODEBUG T* userDataAsPtr() const noexcept { return static_cast<T*>(_userDataPtr); }
   //! Returns user data casted to `int64_t`.
@@ -747,12 +749,15 @@ public:
   //! \name Constants
   //! \{
 
-  enum : uint32_t {
-    //! Count of embedded operands per `InstNode` that are always allocated as a part of the instruction. Minimum
-    //! embedded operands is 4, but in 32-bit more pointers are smaller and we can embed 5. The rest (up to 6 operands)
-    //! is always stored in `InstExNode`.
-    kBaseOpCapacity = uint32_t((128 - sizeof(BaseNode) - sizeof(BaseInst)) / sizeof(Operand_))
-  };
+  //! The number of embedded operands for a default \ref InstNode instance that are always allocated as a part of
+  //! the instruction itself. Minimum embedded operands is 4, but in 32-bit more pointers are smaller and we can
+  //! embed 5. The rest (up to 6 operands) is considered extended.
+  //!
+  //! The number of operands InstNode holds is decided when \ref InstNode is created.
+  static constexpr uint32_t kBaseOpCapacity = uint32_t((128 - sizeof(BaseNode) - sizeof(BaseInst)) / sizeof(Operand_));
+
+  //! Count of maximum number of operands \ref InstNode can hold.
+  static constexpr uint32_t kFullOpCapacity = Globals::kMaxOpCount;
 
   //! \}
 
@@ -761,8 +766,6 @@ public:
 
   //! Base instruction data.
   BaseInst _baseInst;
-  //! First 4 or 5 operands (indexed from 0).
-  Operand_ _opArray[kBaseOpCapacity];
 
   //! \}
 
@@ -811,11 +814,17 @@ public:
   //! \name Instruction Options
   //! \{
 
+  //! Returns instruction options, see \ref InstOptions for more details.
   ASMJIT_INLINE_NODEBUG InstOptions options() const noexcept { return _baseInst.options(); }
+  //! Tests whether instruction has the given \option` set/enabled.
   ASMJIT_INLINE_NODEBUG bool hasOption(InstOptions option) const noexcept { return _baseInst.hasOption(option); }
+  //! Sets instruction `options` to the provided value, resetting all others.
   ASMJIT_INLINE_NODEBUG void setOptions(InstOptions options) noexcept { _baseInst.setOptions(options); }
+  //! Adds instruction `options` to the instruction.
   ASMJIT_INLINE_NODEBUG void addOptions(InstOptions options) noexcept { _baseInst.addOptions(options); }
+  //! Clears instruction `options` of the instruction (disables the given options).
   ASMJIT_INLINE_NODEBUG void clearOptions(InstOptions options) noexcept { _baseInst.clearOptions(options); }
+  //! Resets instruction options to none - disabling all instruction options.
   ASMJIT_INLINE_NODEBUG void resetOptions() noexcept { _baseInst.resetOptions(); }
 
   //! \}
@@ -850,38 +859,52 @@ public:
   ASMJIT_INLINE_NODEBUG void setOpCount(uint32_t opCount) noexcept { _inst._opCount = uint8_t(opCount); }
 
   //! Returns operands array.
-  ASMJIT_INLINE_NODEBUG Operand* operands() noexcept { return (Operand*)_opArray; }
+  ASMJIT_INLINE_NODEBUG Operand* operands() noexcept {
+    return reinterpret_cast<Operand*>(reinterpret_cast<uint8_t*>(this) + sizeof(InstNode));
+  }
+
   //! Returns operands array (const).
-  ASMJIT_INLINE_NODEBUG const Operand* operands() const noexcept { return (const Operand*)_opArray; }
+  ASMJIT_INLINE_NODEBUG const Operand* operands() const noexcept {
+    return reinterpret_cast<const Operand*>(reinterpret_cast<const uint8_t*>(this) + sizeof(InstNode));
+  }
 
   //! Returns operand at the given `index`.
   inline Operand& op(uint32_t index) noexcept {
     ASMJIT_ASSERT(index < opCapacity());
-    return _opArray[index].as<Operand>();
+
+    Operand* ops = operands();
+    return ops[index].as<Operand>();
   }
 
   //! Returns operand at the given `index` (const).
   inline const Operand& op(uint32_t index) const noexcept {
     ASMJIT_ASSERT(index < opCapacity());
-    return _opArray[index].as<Operand>();
+
+    const Operand* ops = operands();
+    return ops[index].as<Operand>();
   }
 
   //! Sets operand at the given `index` to `op`.
   inline void setOp(uint32_t index, const Operand_& op) noexcept {
     ASMJIT_ASSERT(index < opCapacity());
-    _opArray[index].copyFrom(op);
+
+    Operand* ops = operands();
+    ops[index].copyFrom(op);
   }
 
   //! Resets operand at the given `index` to none.
   inline void resetOp(uint32_t index) noexcept {
     ASMJIT_ASSERT(index < opCapacity());
-    _opArray[index].reset();
+
+    Operand* ops = operands();
+    ops[index].reset();
   }
 
   //! Resets operands at `[start, end)` range.
   inline void resetOpRange(uint32_t start, uint32_t end) noexcept {
+    Operand* ops = operands();
     for (uint32_t i = start; i < end; i++)
-      _opArray[i].reset();
+      ops[i].reset();
   }
 
   //! \}
@@ -889,33 +912,47 @@ public:
   //! \name Utilities
   //! \{
 
+  //! Tests whether the given operand type `opType` is used by the instruction.
   inline bool hasOpType(OperandType opType) const noexcept {
+    const Operand* ops = operands();
     for (uint32_t i = 0, count = opCount(); i < count; i++)
-      if (_opArray[i].opType() == opType)
+      if (ops[i].opType() == opType)
         return true;
     return false;
   }
 
+  //! Tests whether the instruction uses at least one register operand.
   inline bool hasRegOp() const noexcept { return hasOpType(OperandType::kReg); }
+  //! Tests whether the instruction uses at least one memory operand.
   inline bool hasMemOp() const noexcept { return hasOpType(OperandType::kMem); }
+  //! Tests whether the instruction uses at least one immediate operand.
   inline bool hasImmOp() const noexcept { return hasOpType(OperandType::kImm); }
+  //! Tests whether the instruction uses at least one label operand.
   inline bool hasLabelOp() const noexcept { return hasOpType(OperandType::kLabel); }
 
+  //! Returns the index of the given operand type `opType`.
+  //!
+  //! \note If the operand type wa found, the value returned represents its index in \ref operands()
+  //! array, otherwise \ref Globals::kNotFound is returned to signalize that the operand was not found.
   inline uint32_t indexOfOpType(OperandType opType) const noexcept {
     uint32_t i = 0;
     uint32_t count = opCount();
+    const Operand* ops = operands();
 
     while (i < count) {
-      if (_opArray[i].opType() == opType)
-        break;
+      if (ops[i].opType() == opType)
+        return i;
       i++;
     }
 
-    return i;
+    return Globals::kNotFound;
   }
 
+  //! A shortcut that calls `indexOfOpType(OperandType::kMem)`.
   inline uint32_t indexOfMemOp() const noexcept { return indexOfOpType(OperandType::kMem); }
+  //! A shortcut that calls `indexOfOpType(OperandType::kImm)`.
   inline uint32_t indexOfImmOp() const noexcept { return indexOfOpType(OperandType::kImm); }
+  //! A shortcut that calls `indexOfOpType(OperandType::kLabel)`.
   inline uint32_t indexOfLabelOp() const noexcept { return indexOfOpType(OperandType::kLabel); }
 
   //! \}
@@ -924,20 +961,40 @@ public:
   //! \{
 
   //! \cond INTERNAL
+
+  //! Returns uint32_t[] view that represents BaseInst::RegOnly and instruction operands.
   ASMJIT_INLINE_NODEBUG uint32_t* _getRewriteArray() noexcept { return &_baseInst._extraReg._id; }
+  //! \overload
   ASMJIT_INLINE_NODEBUG const uint32_t* _getRewriteArray() const noexcept { return &_baseInst._extraReg._id; }
 
+  //! Maximum value of rewrite id - 6 operands each having 4 slots is 24, one RegOnly having 2 slots => 26.
+  static constexpr uint32_t kMaxRewriteId = 26 - 1;
+
+  //! Returns a rewrite index of the given pointer to `id`.
+  //!
+  //! This function returns a value that can be then passed to `\ref rewriteIdAtIndex() function. It can address
+  //! any id from any operand that is used by the instruction in addition to \ref BaseInst::regOnly field, which
+  //! can also be used by the register allocator.
   inline uint32_t getRewriteIndex(const uint32_t* id) const noexcept {
     const uint32_t* array = _getRewriteArray();
     ASMJIT_ASSERT(array <= id);
 
     size_t index = (size_t)(id - array);
-    ASMJIT_ASSERT(index < 32);
+    ASMJIT_ASSERT(index <= kMaxRewriteId);
 
     return uint32_t(index);
   }
 
+  //! Rewrites the given `index` to the provided identifier `id`.
+  //!
+  //! \note This is an internal function that is used by a \ref BaseCompiler implementation to rewrite virtual
+  //! registers to physical registers. The rewriter in this case sees all operands as array of uint32 values
+  //! and the given `index` describes a position in this array. For example a single \ref Operand would be
+  //! decomposed to 4 uint32_t values, where the first at index 0 would be operand signature, next would be
+  //! base id, etc... This is a comfortable way of patching operands without having to check for their types.
   inline void rewriteIdAtIndex(uint32_t index, uint32_t id) noexcept {
+    ASMJIT_ASSERT(index <= kMaxRewriteId);
+
     uint32_t* array = _getRewriteArray();
     array[index] = id;
   }
@@ -949,43 +1006,40 @@ public:
   //! \{
 
   //! \cond INTERNAL
-  static ASMJIT_INLINE_NODEBUG uint32_t capacityOfOpCount(uint32_t opCount) noexcept {
-    return opCount <= kBaseOpCapacity ? kBaseOpCapacity : Globals::kMaxOpCount;
+
+  //! Returns the capacity required for the given operands count `opCount`.
+  //!
+  //! There are only two capacities used - \ref kBaseOpCapacity and \ref kFullOpCapacity, so this function
+  //! is used to decide between these two. The general rule is that instructions that can be represented with
+  //! \ref kBaseOpCapacity would use this value, and all others would take \ref kFullOpCapacity.
+  static ASMJIT_INLINE_NODEBUG constexpr uint32_t capacityOfOpCount(uint32_t opCount) noexcept {
+    return opCount <= kBaseOpCapacity ? kBaseOpCapacity : kFullOpCapacity;
   }
 
-  static ASMJIT_INLINE_NODEBUG size_t nodeSizeOfOpCapacity(uint32_t opCapacity) noexcept {
-    size_t base = sizeof(InstNode) - kBaseOpCapacity * sizeof(Operand);
-    return base + opCapacity * sizeof(Operand);
+  //! Calculates the size of \ref InstNode required to hold at most `opCapacity` operands.
+  //!
+  //! This function is used internally to allocate \ref InstNode.
+  static ASMJIT_INLINE_NODEBUG constexpr size_t nodeSizeOfOpCapacity(uint32_t opCapacity) noexcept {
+    return sizeof(InstNode) + opCapacity * sizeof(Operand);
   }
   //! \endcond
 
   //! \}
 };
 
-//! Instruction node with maximum number of operands.
+//! Instruction node with embedded operands following \ref InstNode layout.
 //!
-//! This node is created automatically by Builder/Compiler in case that the required number of operands exceeds
-//! the default capacity of `InstNode`.
-class InstExNode : public InstNode {
+//! \note This is used to make tools such as static analysis and compilers happy about the layout. There were two
+//! instruction nodes in the past, having the second extend the operand array of the first, but that has caused
+//! undefined behavior and made recent tools unhappy about that.
+template<uint32_t kN>
+class InstNodeWithOperands : public InstNode {
 public:
-  ASMJIT_NONCOPYABLE(InstExNode)
+  Operand_ _operands[kN];
 
-  //! \name Members
-  //! \{
-
-  //! Continued `_opArray[]` to hold up to `kMaxOpCount` operands.
-  Operand_ _opArrayEx[Globals::kMaxOpCount - kBaseOpCapacity];
-
-  //! \}
-
-  //! \name Construction & Destruction
-  //! \{
-
-  //! Creates a new `InstExNode` instance.
-  ASMJIT_INLINE_NODEBUG InstExNode(BaseBuilder* cb, InstId instId, InstOptions options, uint32_t opCapacity = Globals::kMaxOpCount) noexcept
-    : InstNode(cb, instId, options, opCapacity) {}
-
-  //! \}
+  //! Creates a new `InstNodeWithOperands` instance.
+  ASMJIT_INLINE_NODEBUG InstNodeWithOperands(BaseBuilder* cb, InstId instId, InstOptions options, uint32_t opCount) noexcept
+    : InstNode(cb, instId, options, opCount, kN) {}
 };
 
 //! Section node.
@@ -1012,9 +1066,9 @@ public:
   //! \{
 
   //! Creates a new `SectionNode` instance.
-  ASMJIT_INLINE_NODEBUG SectionNode(BaseBuilder* cb, uint32_t secionId = 0) noexcept
+  ASMJIT_INLINE_NODEBUG SectionNode(BaseBuilder* cb, uint32_t sectionId = 0) noexcept
     : BaseNode(cb, NodeType::kSection, NodeFlags::kHasNoEffect),
-      _id(secionId),
+      _id(sectionId),
       _nextSection(nullptr) {}
 
   //! \}

deps/asmjit/src/asmjit/core/builder_p.h

@@ -13,6 +13,7 @@
 
 ASMJIT_BEGIN_NAMESPACE
 
+//! \cond INTERNAL
 //! \addtogroup asmjit_builder
 //! \{
 
@@ -28,6 +29,7 @@ static inline void BaseBuilder_assignInstState(BaseBuilder* self, InstNode* node
 }
 
 //! \}
+//! \endcond
 
 ASMJIT_END_NAMESPACE
 

deps/asmjit/src/asmjit/core/codeholder.cpp

@@ -132,8 +132,8 @@ CodeHolder::~CodeHolder() noexcept {
   CodeHolder_resetInternal(this, ResetPolicy::kHard);
 }
 
-// CodeHolder - Init & Reset
-// =========================
+// CodeHolder - Initialization & Reset
+// ===================================
 
 inline void CodeHolder_setSectionDefaultName(
   Section* section,
@@ -908,7 +908,7 @@ size_t CodeHolder::codeSize() const noexcept {
     }
   }
 
-  if ((sizeof(uint64_t) > sizeof(size_t) && offset > SIZE_MAX) || of)
+  if ((sizeof(uint64_t) > sizeof(size_t) && offset > uint64_t(SIZE_MAX)) || of)
     return SIZE_MAX;
 
   return size_t(offset);