{ "registers": { "r": {"kind": "gp" , "any": "r", "names": ["r0-31"]}, "b": {"kind": "vec", "any": "b", "names": ["b0-31"]}, "h": {"kind": "vec", "any": "h", "names": ["h0-31"]}, "s": {"kind": "vec", "any": "s", "names": ["s0-31"]}, "d": {"kind": "vec", "any": "d", "names": ["d0-31"]}, "v": {"kind": "vec", "any": "v", "names": ["v0-31"]} }, "instructions": [ {"category": "GP", "data": [ {"inst": "adc Wd, Wn, Wm" , "op": "00011010|000|Rm|000000|Rn|Rd" , "io": "C=R"}, {"inst": "adc Xd, Xn, Xm" , "op": "10011010|000|Rm|000000|Rn|Rd" , "io": "C=R"}, {"inst": "adcs Wd, Wn, Wm" , "op": "00111010|000|Rm|000000|Rn|Rd" , "io": "N=W Z=W C=X V=W"}, {"inst": "adcs Xd, Xn, Xm" , "op": "10111010|000|Rm|000000|Rn|Rd" , "io": "N=W Z=W C=X V=W"}, {"inst": "add Wd, Wn, Wm, {lsl|lsr|asr #n}" , "op": "00001011|sop:2|0|Rm|n:6|Rn|Rd"}, {"inst": "add Xd, Xn, Xm, {lsl|lsr|asr #n}" , "op": "10001011|sop:2|0|Rm|n:6|Rn|Rd"}, {"inst": "add Wd|WSP, Wn|WSP, Wm, {extend #n}" , "op": "00001011|001|Rm|option:3|n:3|Rn|Rd"}, {"inst": "add Xd|SP, Xn|SP, Rm, {extend #n}" , "op": "10001011|001|Rm|option:3|n:3|Rn|Rd"}, {"inst": "add Wd|WSP, Wn|WSP, #immZ, {lsl #n=0|12}" , "op": "00010001|0|n:1|immZ:12|Rn|Rd"}, {"inst": "add Xd|SP, Xn|SP, #immZ, {lsl #n=0|12}" , "op": "10010001|0|n:1|immZ:12|Rn|Rd"}, {"inst": "adds Wd, Wn, Wm, {lsl|lsr|asr #n}" , "op": "00101011|sop:2|0|Rm|n:6|Rn|Rd" , "io": "N=W Z=W C=W V=W"}, {"inst": "adds Xd, Xn, Xm, {lsl|lsr|asr #n}" , "op": "10101011|sop:2|0|Rm|n:6|Rn|Rd" , "io": "N=W Z=W C=W V=W"}, {"inst": "adds Wd, Wn|WSP, Wm, {extend #n}" , "op": "00101011|001|Rm|option:3|n:3|Rn|Rd" , "io": "N=W Z=W C=W V=W"}, {"inst": "adds Xd, Xn|SP, Rm, {extend #n}" , "op": "10101011|001|Rm|option:3|n:3|Rn|Rd" , "io": "N=W Z=W C=W V=W"}, {"inst": "adds Wd|WSP, Wn|WSP, #immZ, {lsl #n=0|12}" , "op": "00110001|0|n:1|immZ:12|Rn|Rd" , "io": "N=W Z=W C=W V=W"}, {"inst": "adds Xd|SP, Xn|SP, #immZ, {lsl #n=0|12}" , "op": "10110001|0|n:1|immZ:12|Rn|Rd" , "io": "N=W Z=W C=W V=W"}, {"inst": "adr Xd, #relS" , "op": "0|relS[1:0]|10000|relS[20:2]|Rd"}, {"inst": "adrp Xd, #relS" , "op": "1|relS[1:0]|10000|relS[20:2]|Rd"}, {"inst": "and Wd|WSP, Wn, Wm, {sop #n}" , "op": "00001010|sop|0|Rm|n:6|Rn|Rd" , "imm": "ShiftImm(n, x)"}, {"inst": "and Xd|SP, Xn, Xm, {sop #n}" , "op": "10001010|sop|0|Rm|n:6|Rn|Rd" , "imm": "ShiftImm(n, x)"}, {"inst": "and Wd|WSP, Wn, #imm" , "op": "00010010|0|imm:13|Rn|Rd" , "imm": "LogicalImm(imm, 0)"}, {"inst": "and Xd|SP, Xn, #imm" , "op": "10010010|0|imm:13|Rn|Rd" , "imm": "LogicalImm(imm, 1)"}, {"inst": "ands Wd|WSP, Wn, Wm, {sop #n}" , "op": "01101010|sop|0|Rm|n:6|Rn|Rd" , "io": "N=W Z=W C=W V=W", "imm": "ShiftImm(n, x)"}, {"inst": "ands Xd|SP, Xn, Xm, {sop #n}" , "op": "11101010|sop|0|Rm|n:6|Rn|Rd" , "io": "N=W Z=W C=W V=W", "imm": "ShiftImm(n, x)"}, {"inst": "ands Wd|WSP, Wn, #imm" , "op": "01110010|0|imm:13|Rn|Rd" , "io": "N=W Z=W C=W V=W", "imm": "LogicalImm(imm, 0)"}, {"inst": "ands Xd|SP, Xn, #imm" , "op": "11110010|0|imm:13|Rn|Rd" , "io": "N=W Z=W C=W V=W", "imm": "LogicalImm(imm, 1)"}, {"inst": "asr|asrv Wd, Wn, Wm" , "op": "00011010|110|Rm|001010|Rn|Rd"}, {"inst": "asr|asrv Xd, Xn, Xm" , "op": "10011010|110|Rm|001010|Rn|Rd"}, {"inst": "asr Wd, Wn, #n" , "op": "00010011|00|immr:6|011111|Rn|Rd"}, {"inst": "asr Xd, Xn, #n" , "op": "10010011|01|immr:6|111111|Rn|Rd"}, {"inst": "at #at_op, Xt" , "op": "11010101|00001|op1:3|0111|CRm|op2:3|Rt" , "imm": "ImmAt(at_op)"}, {"inst": "b #relS*4" , "op": "000101|relS:26" , "control": "jump"}, {"inst": "b. #relS*4" , "op": "01010100|relS:19|0|cond" , "control": "branch", "io": "N=R Z=R C=R V=R"}, {"inst": "bfc Wd, #lsb, #width" , "op": "00110011|00|immr:6|imms:6|11111|Rd"}, {"inst": "bfc Xd, #lsb, #width" , "op": "10110011|01|immr:6|imms:6|11111|Rd"}, {"inst": "bfi Wd, Wn, #lsb, #width" , "op": "00110011|00|immr:6|imms:6|Rn|Rd"}, {"inst": "bfi Xd, Xn, #lsb, #width" , "op": "10110011|01|immr:6|imms:6|Rn|Rd"}, {"inst": "bfm Wd, Wn, #immr, #imms" , "op": "00110011|00|immr:6|imms:6|Rn|Rd" , "imm": "ImmBFM(immr, imms)"}, {"inst": "bfm Xd, Xn, #immr, #imms" , "op": "10110011|01|immr:6|imms:6|Rn|Rd" , "imm": "ImmBFM(immr, imms)"}, {"inst": "bfxil Wd, Wn, #lsb, #width" , "op": "00110011|00|immr:6|imms:6|Rn|Rd"}, {"inst": "bfxil Xd, Xn, #lsb, #width" , "op": "10110011|01|immr:6|imms:6|Rn|Rd"}, {"inst": "bic Wd, Wn, Wm, {sop #n}" , "op": "00001010|sop:2|1|Rm|n:6|Rn|Rd"}, {"inst": "bic Xd, Xn, Xm, {sop #n}" , "op": "10001010|sop:2|1|Rm|n:6|Rn|Rd"}, {"inst": "bics Wd, Wn, Wm, {sop #n}" , "op": "01101010|sop:2|1|Rm|n:6|Rn|Rd" , "io": "N=W Z=W C=W V=W"}, {"inst": "bics Xd, Xn, Xm, {sop #n}" , "op": "11101010|sop:2|1|Rm|n:6|Rn|Rd" , "io": "N=W Z=W C=W V=W"}, {"inst": "bl #relS*4" , "op": "100101|relS:26" , "control": "call"}, {"inst": "blr Xn" , "op": "11010110|001|11111000000|Rn|00000" , "control": "call"}, {"inst": "br Xn" , "op": "11010110|000|11111000000|Rn|00000" , "control": "jump"}, {"inst": "brk #imm" , "op": "11010100|001|imm:16|00000"}, {"inst": "cbnz Wn, #relS*4" , "op": "00110101|relS:19|Rn" , "control": "branch"}, {"inst": "cbnz Xn, #relS*4" , "op": "10110101|relS:19|Rn" , "control": "branch"}, {"inst": "cbz Wn, #relS*4" , "op": "00110101|relS:19|Rn" , "control": "branch"}, {"inst": "cbz Xn, #relS*4" , "op": "10110101|relS:19|Rn" , "control": "branch"}, {"inst": "ccmn Wn, Wm, #nzcv, #cond" , "op": "00111010|010|Rm|cond|00|Rn|0|nzcv" , "io": "N=W Z=W C=W V=W"}, {"inst": "ccmn Xn, Xm, #nzcv, #cond" , "op": "10111010|010|Rm|cond|00|Rn|0|nzcv" , "io": "N=W Z=W C=W V=W"}, {"inst": "ccmn Wn, #imm, #nzcv, #cond" , "op": "00111010|010|imm:5|cond|10|Rn|0|nzcv" , "io": "N=W Z=W C=W V=W"}, {"inst": "ccmn Xn, #imm, #nzcv, #cond" , "op": "10111010|010|imm:5|cond|10|Rn|0|nzcv" , "io": "N=W Z=W C=W V=W"}, {"inst": "ccmp Wn, Wm, #nzcv, #cond" , "op": "01111010|010|Rm|cond|00|Rn|0|nzcv" , "io": "N=W Z=W C=W V=W"}, {"inst": "ccmp Xn, Xm, #nzcv, #cond" , "op": "11111010|010|Rm|cond|00|Rn|0|nzcv" , "io": "N=W Z=W C=W V=W"}, {"inst": "ccmp Wn, #imm, #nzcv, #cond" , "op": "01111010|010|imm:5|cond|10|Rn|0|nzcv" , "io": "N=W Z=W C=W V=W"}, {"inst": "ccmp Xn, #imm, #nzcv, #cond" , "op": "11111010|010|imm:5|cond|10|Rn|0|nzcv" , "io": "N=W Z=W C=W V=W"}, {"inst": "cinc Wd, Wn, #cond" , "op": "00011010|100|Rn|cond|01|Rn|Rd" , "io": "N=R Z=R C=R V=R"}, {"inst": "cinc Xd, Xn, #cond" , "op": "10011010|100|Rn|cond|01|Rn|Rd" , "io": "N=R Z=R C=R V=R"}, {"inst": "cinv Wd, Wn, #cond" , "op": "01011010|100|Rn|cond|00|Rn|Rd" , "io": "N=R Z=R C=R V=R"}, {"inst": "cinv Xd, Xn, #cond" , "op": "11011010|100|Rn|cond|00|Rn|Rd" , "io": "N=R Z=R C=R V=R"}, {"inst": "clrex {#imm=15}" , "op": "11010101|000|00011|0011|CRm|010|11111" , "CRm": "imm"}, {"inst": "cls Wd, Wn" , "op": "01011010|110|00000000101|Rn|Rd"}, {"inst": "cls Xd, Xn" , "op": "11011010|110|00000000101|Rn|Rd"}, {"inst": "clz Wd, Wn" , "op": "01011010|110|00000000100|Rn|Rd"}, {"inst": "clz Xd, Xn" , "op": "11011010|110|00000000100|Rn|Rd"}, {"inst": "cmn Wn|WSP, #imm, {lsl #n=0|12}" , "op": "00110001|0|n:1|imm:12|Rn|11111" , "io": "N=W Z=W C=W V=W"}, {"inst": "cmn Xn|SP, #imm, {lsl #n=0|12}" , "op": "10110001|0|n:1|imm:12|Rn|11111" , "io": "N=W Z=W C=W V=W"}, {"inst": "cmn Wn|WSP, Wm, {extend #n}" , "op": "00101011|001|Rm|option:3|n:3|Rn|11111" , "io": "N=W Z=W C=W V=W"}, {"inst": "cmn Xn|SP, Rm, {extend #n}" , "op": "10101011|001|Rm|option:3|n:3|Rn|11111" , "io": "N=W Z=W C=W V=W"}, {"inst": "cmn Wn, Wm, {lsl|lsr|asr #n}" , "op": "00101011|sop:2|0|Rm|n:6|Rn|11111" , "io": "N=W Z=W C=W V=W"}, {"inst": "cmn Xn, Xm, {lsl|lsr|asr #n}" , "op": "10101011|sop:2|0|Rm|n:6|Rn|11111" , "io": "N=W Z=W C=W V=W"}, {"inst": "cmp Wn, Wm, {lsl|lsr|asr #n}" , "op": "01101011|sop:2|0|Rm|n:6|Rn|11111" , "io": "N=W Z=W C=W V=W"}, {"inst": "cmp Xn, Xm, {lsl|lsr|asr #n}" , "op": "11101011|sop:2|0|Rm|n:6|Rn|11111" , "io": "N=W Z=W C=W V=W"}, {"inst": "cmp Wn|WSP, Wm, {extend #n}" , "op": "01101011|001|Rm|option:3|n:3|Rn|11111" , "io": "N=W Z=W C=W V=W"}, {"inst": "cmp Xn|SP, Rm, {extend #n}" , "op": "11101011|001|Rm|option:3|n:3|Rn|11111" , "io": "N=W Z=W C=W V=W"}, {"inst": "cmp Wn|WSP, #imm, {lsl #n=0|12}" , "op": "01110001|0|n:1|imm:12|Rn|11111" , "io": "N=W Z=W C=W V=W"}, {"inst": "cmp Xn|SP, #imm, {lsl #n=0|12}" , "op": "11110001|0|n:1|imm:12|Rn|11111" , "io": "N=W Z=W C=W V=W"}, {"inst": "cneg Wd, Wn, #cond" , "op": "01011010|100|Rn|cond|01|Rn|Rd" , "io": "N=R Z=R C=R V=R"}, {"inst": "cneg Xd, Xn, #cond" , "op": "11011010|100|Rn|cond|01|Rn|Rd" , "io": "N=R Z=R C=R V=R"}, {"inst": "csdb" , "op": "11010101|00|000|011|0010|0010|100|11111"}, {"inst": "csel Wd, Wn, Wm, #cond" , "op": "00011010|100|Rm|cond|00|Rn|Rd" , "io": "N=R Z=R C=R V=R"}, {"inst": "csel Xd, Xn, Xm, #cond" , "op": "10011010|100|Rm|cond|00|Rn|Rd" , "io": "N=R Z=R C=R V=R"}, {"inst": "cset Wd, #cond" , "op": "00011010|100|11111|cond|01|11111|Rd" , "io": "N=R Z=R C=R V=R"}, {"inst": "cset Xd, #cond" , "op": "10011010|100|11111|cond|01|11111|Rd" , "io": "N=R Z=R C=R V=R"}, {"inst": "csetm Wd, #cond" , "op": "01011010|100|11111|cond|00|11111|Rd" , "io": "N=R Z=R C=R V=R"}, {"inst": "csetm Xd, #cond" , "op": "11011010|100|11111|cond|00|11111|Rd" , "io": "N=R Z=R C=R V=R"}, {"inst": "csinc Wd, Wn, Wm, #cond" , "op": "00011010|100|Rm|cond|01|Rn|Rd" , "io": "N=R Z=R C=R V=R"}, {"inst": "csinc Xd, Xn, Xm, #cond" , "op": "10011010|100|Rm|cond|01|Rn|Rd" , "io": "N=R Z=R C=R V=R"}, {"inst": "csinv Wd, Wn, Wm, #cond" , "op": "01011010|100|Rm|cond|00|Rn|Rd" , "io": "N=R Z=R C=R V=R"}, {"inst": "csinv Xd, Xn, Xm, #cond" , "op": "11011010|100|Rm|cond|00|Rn|Rd" , "io": "N=R Z=R C=R V=R"}, {"inst": "csneg Wd, Wn, Wm, #cond" , "op": "01011010|100|Rm|cond|01|Rn|Rd" , "io": "N=R Z=R C=R V=R"}, {"inst": "csneg Xd, Xn, Xm, #cond" , "op": "11011010|100|Rm|cond|01|Rn|Rd" , "io": "N=R Z=R C=R V=R"}, {"inst": "dc #dc_op, Xt" , "op": "11010101|000|01|op1:3|0111|CRm|op2:3|Rt" , "imm": "ImmDC(dc_op)"}, {"inst": "dcps1 {#imm}" , "op": "11010100|101|imm:16|00001"}, {"inst": "dcps2 {#imm}" , "op": "11010100|101|imm:16|00010"}, {"inst": "dcps3 {#imm}" , "op": "11010100|101|imm:16|00011"}, {"inst": "dmb #barrier_op" , "op": "11010101|000|00|011|0011|CRm|101|11111" , "imm": "ImmDataBarrier(barrier_op)"}, {"inst": "drps" , "op": "11010110|101|11111|00000|01111|1|00000"}, {"inst": "dsb #barrier_op" , "op": "11010101|000|00|011|0011|CRm|101|11111" , "imm": "ImmDataBarrier(barrier_op)", "ext": "XS"}, {"inst": "eon Wd, Wn, Wm, {sop #n}" , "op": "01001010|sop:2|1|Rm|n:6|Rn|Rd"}, {"inst": "eon Xd, Xn, Xm, {sop #n}" , "op": "11001010|sop:2|1|Rm|n:6|Rn|Rd"}, {"inst": "eor Wd, Wn, Wm, {sop #n}" , "op": "01001010|sop:2|0|Rm|n:6|Rn|Rd"}, {"inst": "eor Xd, Xn, Xm, {sop #n}" , "op": "11001010|sop:2|0|Rm|n:6|Rn|Rd"}, {"inst": "eor Wd|WSP, Wn, #imm" , "op": "01010010|0|imm:13|Rn|Rd" , "imm": "LogicalImm(imm, 0)"}, {"inst": "eor Xd|SP, Xn, #imm" , "op": "11010010|0|imm:13|Rn|Rd" , "imm": "LogicalImm(imm, 1)"}, {"inst": "eret" , "op": "11010110|100|11111|0000|00|11111|00000"}, {"inst": "extr Wd, Wn, Wm, #imm" , "op": "00010011|100|Rm|0|imm:5|Rn|Rd"}, {"inst": "extr Xd, Xn, Xm, #imm" , "op": "10010011|110|Rm|imm:6|Rn|Rd"}, {"inst": "hint #imm" , "op": "11010101|000|00|011|0010|imm:7|11111"}, {"inst": "hlt #imm" , "op": "11010100|010|imm:16|00000"}, {"inst": "hvc #imm" , "op": "11010100|000|imm:16|00010"}, {"inst": "ic #ic_op" , "op": "11010101|000|01|op1:3|0111|CRm|op2:3|11111" , "imm": "ImmIC(ic_op)"}, {"inst": "ic #ic_op, Xt" , "op": "11010101|000|01|op1:3|0111|CRm|op2:3|Rt" , "imm": "ImmIC(ic_op)"}, {"inst": "isb {#isb_op=15}" , "op": "11010101|000|00|011|0011|CRm|110|11111" , "imm": "ImmISB(isb_op)"}, {"inst": "ldar Wd, [Xn|SP]" , "op": "10001000|110|11111|1|11111|Rn|Rd"}, {"inst": "ldar Xd, [Xn|SP]" , "op": "11001000|110|11111|1|11111|Rn|Rd"}, {"inst": "ldarb Wd, [Xn|SP]" , "op": "00001000|110|11111|1|11111|Rn|Rd"}, {"inst": "ldarh Wd, [Xn|SP]" , "op": "01001000|110|11111|1|11111|Rn|Rd"}, {"inst": "ldaxp Wd, Wd2, [Xn|SP]" , "op": "10001000|011|11111|1|Rd2|Rn|Rd"}, {"inst": "ldaxp Xd, Xd2, [Xn|SP]" , "op": "11001000|011|11111|1|Rd2|Rn|Rd"}, {"inst": "ldaxr Wd, [Xn|SP]" , "op": "10001000|010|11111|1|11111|Rn|Rd"}, {"inst": "ldaxr Xd, [Xn|SP]" , "op": "11001000|010|11111|1|11111|Rn|Rd"}, {"inst": "ldaxrb Wd, [Xn|SP]" , "op": "00001000|010|11111|1|11111|Rn|Rd"}, {"inst": "ldaxrh Xd, [Xn|SP]" , "op": "01001000|010|11111|1|11111|Rn|Rd"}, {"inst": "ldnp Wd, Wd2, [Xn|SP, #soff*4]" , "op": "00101000|01|soff:7|Rd2|Rn|Rd"}, {"inst": "ldnp Xd, Xd2, [Xn|SP, #soff*8]" , "op": "10101000|01|soff:7|Rd2|Rn|Rd"}, {"inst": "ldp Wd, Wd2, [Xn|SP, #soff*4]{@}{!}" , "op": "0010100|!post|W|1|soff:7|Rd2|Rn|Rd"}, {"inst": "ldp Xd, Xd2, [Xn|SP, #soff*8]{@}{!}" , "op": "1010100|!post|W|1|soff:7|Rd2|Rn|Rd"}, {"inst": "ldpsw Xd, Xd2, [Xn|SP, #soff*4]{@}{!}" , "op": "0110100|!post|W|1|soff:7|Rd2|Rn|Rd"}, {"inst": "ldr Wd, [Xn|SP, #zoff*4]" , "op": "10111001|01|zoff:12|Rn|Rd"}, {"inst": "ldr Xd, [Xn|SP, #zoff*8]" , "op": "11111001|01|zoff:12|Rn|Rd"}, {"inst": "ldr Wd, [Xn|SP, #soff*4]@" , "op": "10111000|010|soff:9|01|Rn|Rd"}, {"inst": "ldr Xd, [Xn|SP, #soff*8]@" , "op": "11111000|010|soff:9|01|Rn|Rd"}, {"inst": "ldr Wd, [Xn|SP, #soff*4]!" , "op": "10111000|010|soff:9|11|Rn|Rd"}, {"inst": "ldr Xd, [Xn|SP, #soff*8]!" , "op": "11111000|010|soff:9|11|Rn|Rd"}, {"inst": "ldr Wd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "10111000|011|Rm|option:3|s:1|10|Rn|Rd" , "imm": "ImmLDR(iop, n)"}, {"inst": "ldr Xd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "11111000|011|Rm|option:3|s:1|10|Rn|Rd" , "imm": "ImmLDR(iop, n)"}, {"inst": "ldr Wd, [PC, #soff*4]" , "op": "00011000|soff:19|Rd"}, {"inst": "ldr Xd, [PC, #soff*4]" , "op": "01011000|soff:19|Rd"}, {"inst": "ldrb Wd, [Xn|SP, #zoff]" , "op": "00111001|01|zoff:12|Rn|Rd"}, {"inst": "ldrb Wd, [Xn|SP, #soff]@" , "op": "00111000|010|soff:9|01|Rn|Rd"}, {"inst": "ldrb Wd, [Xn|SP, #soff]!" , "op": "00111000|010|soff:9|11|Rn|Rd"}, {"inst": "ldrb Wd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "00111000|011|Rm|option:3|s:1|10|Rn|Rd" , "imm": "ImmLDRB(iop, n)"}, {"inst": "ldrh Wd, [Xn|SP, #zoff*2]" , "op": "01111001|01|zoff:12|Rn|Rd"}, {"inst": "ldrh Wd, [Xn|SP, #soff*2]@" , "op": "01111000|010|soff:9|01|Rn|Rd"}, {"inst": "ldrh Wd, [Xn|SP, #soff*2]!" , "op": "01111000|010|soff:9|11|Rn|Rd"}, {"inst": "ldrh Wd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "01111000|011|Rm|option:3|s:1|10|Rn|Rd" , "imm": "ImmLDRH(iop, n)"}, {"inst": "ldrsb Wd, [Xn|SP, #zoff]" , "op": "00111001|11|zoff:12|Rn|Rd"}, {"inst": "ldrsb Xd, [Xn|SP, #zoff]" , "op": "00111001|10|zoff:12|Rn|Rd"}, {"inst": "ldrsb Wd, [Xn|SP, #soff]@" , "op": "00111000|110|soff:9|01|Rn|Rd"}, {"inst": "ldrsb Xd, [Xn|SP, #soff]@" , "op": "00111000|100|soff:9|01|Rn|Rd"}, {"inst": "ldrsb Wd, [Xn|SP, #soff]!" , "op": "00111000|110|soff:9|11|Rn|Rd"}, {"inst": "ldrsb Xd, [Xn|SP, #soff]!" , "op": "00111000|100|soff:9|11|Rn|Rd"}, {"inst": "ldrsb Wd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "00111000|111|Rm|option:3|s:1|10|Rn|Rd" , "imm": "ImmLDRB(iop, n)"}, {"inst": "ldrsb Xd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "00111000|101|Rm|option:3|s:1|10|Rn|Rd" , "imm": "ImmLDRB(iop, n)"}, {"inst": "ldrsh Wd, [Xn|SP, #zoff*2]" , "op": "01111001|11|zoff:12|Rn|Rd"}, {"inst": "ldrsh Xd, [Xn|SP, #zoff*2]" , "op": "01111001|10|zoff:12|Rn|Rd"}, {"inst": "ldrsh Wd, [Xn|SP, #soff*2]@" , "op": "01111000|110|soff:9|01|Rn|Rd"}, {"inst": "ldrsh Xd, [Xn|SP, #soff*2]@" , "op": "01111000|100|soff:9|01|Rn|Rd"}, {"inst": "ldrsh Wd, [Xn|SP, #soff*2]!" , "op": "01111000|110|soff:9|11|Rn|Rd"}, {"inst": "ldrsh Xd, [Xn|SP, #soff*2]!" , "op": "01111000|100|soff:9|11|Rn|Rd"}, {"inst": "ldrsh Wd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "01111000|111|Rm|option:3|s:1|10|Rn|Rd" , "imm": "ImmLDRH(iop, n)"}, {"inst": "ldrsh Xd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "01111000|101|Rm|option:3|s:1|10|Rn|Rd" , "imm": "ImmLDRH(iop, n)"}, {"inst": "ldrsw Xd, [Xn|SP, #zoff*4]" , "op": "10111001|10|zoff:12|Rn|Rd"}, {"inst": "ldrsw Xd, [Xn|SP, #soff*4]@" , "op": "10111000|100|soff:9|01|Rn|Rd"}, {"inst": "ldrsw Xd, [Xn|SP, #soff*4]!" , "op": "10111000|100|soff:9|11|Rn|Rd"}, {"inst": "ldrsw Xd, [PC, #soff*4]" , "op": "10011000|soff:19|Rd"}, {"inst": "ldrsw Xd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "10111000|101|Rm|option:3|s:1|10|Rn|Rd" , "imm": "ImmLDRW(iop, n)"}, {"inst": "ldtr Wd, [Xn|SP, #soff]" , "op": "10111000|010|soff:9|10|Rn|Rd"}, {"inst": "ldtr Xd, [Xn|SP, #soff]" , "op": "11111000|010|soff:9|10|Rn|Rd"}, {"inst": "ldtrb Wd, [Xn|SP, #soff]" , "op": "00111000|010|soff:9|10|Rn|Rd"}, {"inst": "ldtrh Wd, [Xn|SP, #soff]" , "op": "01111000|010|soff:9|10|Rn|Rd"}, {"inst": "ldtrsb Wd, [Xn|SP, #soff]" , "op": "00111000|100|soff:9|10|Rn|Rd"}, {"inst": "ldtrsb Xd, [Xn|SP, #soff]" , "op": "00111000|110|soff:9|10|Rn|Rd"}, {"inst": "ldtrsh Wd, [Xn|SP, #soff]" , "op": "01111000|100|soff:9|10|Rn|Rd"}, {"inst": "ldtrsh Xd, [Xn|SP, #soff]" , "op": "01111000|110|soff:9|10|Rn|Rd"}, {"inst": "ldtrsw Xd, [Xn|SP, #soff]" , "op": "10111000|100|soff:9|10|Rn|Rd"}, {"inst": "ldur Wd, [Xn|SP, #soff]" , "op": "10111000|010|soff:9|00|Rn|Rd"}, {"inst": "ldur Xd, [Xn|SP, #soff]" , "op": "11111000|010|soff:9|00|Rn|Rd"}, {"inst": "ldurb Wd, [Xn|SP, #soff]" , "op": "00111000|010|soff:9|00|Rn|Rd"}, {"inst": "ldurh Wd, [Xn|SP, #soff]" , "op": "01111000|010|soff:9|00|Rn|Rd"}, {"inst": "ldursb Wd, [Xn|SP, #soff]" , "op": "00111000|100|soff:9|00|Rn|Rd"}, {"inst": "ldursb Xd, [Xn|SP, #soff]" , "op": "00111000|110|soff:9|00|Rn|Rd"}, {"inst": "ldursh Wd, [Xn|SP, #soff]" , "op": "01111000|100|soff:9|00|Rn|Rd"}, {"inst": "ldursh Xd, [Xn|SP, #soff]" , "op": "01111000|110|soff:9|00|Rn|Rd"}, {"inst": "ldursw Xd, [Xn|SP, #soff]" , "op": "10111000|100|soff:9|00|Rn|Rd"}, {"inst": "ldxp Wd, Wd2, [Xn|SP, #soff*4]" , "op": "10001000|011|11111|0|Rd2|Rn|Rd"}, {"inst": "ldxp Xd, Xd2, [Xn|SP, #soff*8]" , "op": "11001000|011|11111|0|Rd2|Rn|Rd"}, {"inst": "ldxr Wd, [Xn|SP]" , "op": "10001000|010|11111|0|11111|Rn|Rd"}, {"inst": "ldxr Xd, [Xn|SP]" , "op": "11001000|010|11111|0|11111|Rn|Rd"}, {"inst": "ldxrb Wd, [Xn|SP]" , "op": "00001000|010|11111|0|11111|Rn|Rd"}, {"inst": "ldxrh Wd, [Xn|SP]" , "op": "01001000|010|11111|0|11111|Rn|Rd"}, {"inst": "lsl|lslv Wd, Wn, Wm" , "op": "00011010|110|Rm|001000|Rn|Rd"}, {"inst": "lsl|lslv Xd, Xn, Xm" , "op": "10011010|110|Rm|001000|Rn|Rd"}, {"inst": "lsl Wd, Wn, #n" , "op": "01010011|00|immr:6|imms:6|Rn|Rd"}, {"inst": "lsl Xd, Xn, #n" , "op": "11010011|01|immr:6|imms:6|Rn|Rd"}, {"inst": "lsr|lsrv Wd, Wn, Wm" , "op": "00011010|110|Rm|001001|Rn|Rd"}, {"inst": "lsr|lsrv Xd, Xn, Xm" , "op": "10011010|110|Rm|001001|Rn|Rd"}, {"inst": "lsr Wd, Wn, #n" , "op": "01010011|00|immr:6|011111|Rn|Rd"}, {"inst": "lsr Xd, Xn, #n" , "op": "11010011|01|immr:6|111111|Rn|Rd"}, {"inst": "madd Wd, Wn, Wm, Wa" , "op": "00011011|000|Rm|0|Ra|Rn|Rd"}, {"inst": "madd Xd, Xn, Xm, Xa" , "op": "10011011|000|Rm|0|Ra|Rn|Rd"}, {"inst": "mneg Wd, Wn, Wm" , "op": "00011011|000|Rm|1|11111|Rn|Rd"}, {"inst": "mneg Xd, Xn, Xm" , "op": "10011011|000|Rm|1|11111|Rn|Rd"}, {"inst": "mov Wd, Wm" , "op": "00101010|000|Rm|0|00000|11111|Rd"}, {"inst": "mov Xd, Xm" , "op": "10101010|000|Rm|0|00000|11111|Rd"}, {"inst": "mov Wd|WSP, Wn|WSP" , "op": "00010001|000|00000|0|00000|Rn|Rd"}, {"inst": "mov Xd|SP, Xn|SP" , "op": "10010001|000|00000|0|00000|Rn|Rd"}, {"inst": "mov Wd, #imm" , "op": "01010010|1|hw:2|imm:16|Rd" , "imm": "ImmWide(imm, 0, 0)"}, {"inst": "mov Xd, #imm" , "op": "11010010|1|hw:2|imm:16|Rd" , "imm": "ImmWide(imm, 0, 1)"}, {"inst": "mov Wd, #imm" , "op": "00010010|1|hw:2|imm:16|Rd" , "imm": "ImmWideInv(imm, 0, 0)"}, {"inst": "mov Xd, #imm" , "op": "10010010|1|hw:2|imm:16|Rd" , "imm": "ImmWideInv(imm, 0, 1)"}, {"inst": "mov Wd|WSP, #log_imm" , "op": "00110010|00|immr:6|imms:6|11111|Rd" , "imm": "ImmLogical(log_imm, 0)"}, {"inst": "mov Xd|SP, #log_imm" , "op": "10110010|01|immr:6|imms:6|11111|Rd" , "imm": "ImmLogical(log_imm, 1)"}, {"inst": "movk Wd, #imm, {lsl #n}" , "op": "01110010|1|hw:2|imm:16|Rd" , "imm": "ImmWide(imm, n, 0)"}, {"inst": "movk Xd, #imm, {lsl #n}" , "op": "11110010|1|hw:2|imm:16|Rd" , "imm": "ImmWide(imm, n, 1)"}, {"inst": "movn Wd, #imm, {lsl #n}" , "op": "00010010|1|hw:2|imm:16|Rd" , "imm": "ImmWideInv(imm, n, 0)"}, {"inst": "movn Xd, #imm, {lsl #n}" , "op": "10010010|1|hw:2|imm:16|Rd" , "imm": "ImmWideInv(imm, n, 1)"}, {"inst": "movz Wd, #imm, {lsl #n}" , "op": "01010010|1|hw:2|imm:16|Rd" , "imm": "ImmWide(imm, n, 0)"}, {"inst": "movz Xd, #imm, {lsl #n}" , "op": "11010010|1|hw:2|imm:16|Rd" , "imm": "ImmWide(imm, n, 1)"}, {"inst": "mrs Xd, #sysreg" , "op": "11010101|001|1|sysreg:15|Rd"}, {"inst": "msr #sysreg, Xs" , "op": "11010101|000|1|sysreg:15|Rs"}, {"inst": "msr #pstatefield, #imm" , "op": "11010101|000|00|op1:3|0100|imm:4|op2:3|11111" , "imm": "ImmMSR(pstatefield)"}, {"inst": "msub Wd, Wn, Wm, Wa" , "op": "00011011|000|Rm|1|Ra|Rn|Rd"}, {"inst": "msub Xd, Xn, Xm, Xa" , "op": "10011011|000|Rm|1|Ra|Rn|Rd"}, {"inst": "mul Wd, Wn, Wm" , "op": "00011011|000|Rm|0|11111|Rn|Rd"}, {"inst": "mul Xd, Xn, Xm" , "op": "10011011|000|Rm|0|11111|Rn|Rd"}, {"inst": "mvn Wd, Wn, {sop #n}" , "op": "X0101010|sop|1|Rn|n:6|Rn|Rd"}, {"inst": "mvn Xd, Xn, {sop #n}" , "op": "X0101010|sop|1|Rn|n:6|Rn|Rd"}, {"inst": "neg Wd, Wm, {lsl|lsr|asr #n}" , "op": "01001011|sop:2|0|Rm|n:6|11111|Rd"}, {"inst": "neg Xd, Xm, {lsl|lsr|asr #n}" , "op": "11001011|sop:2|0|Rm|n:6|11111|Rd"}, {"inst": "negs Wd, Wm, {lsl|lsr|asr #n}" , "op": "01101011|sop:2|0|Rm|n:6|11111|Rd" , "io": "N=W Z=W C=W V=W"}, {"inst": "negs Xd, Xm, {lsl|lsr|asr #n}" , "op": "11101011|sop:2|0|Rm|n:6|11111|Rd" , "io": "N=W Z=W C=W V=W"}, {"inst": "ngc Wd, Wm" , "op": "01011010|000|Rm|0|00000|11111|Rd" , "io": "C=R"}, {"inst": "ngc Xd, Xm" , "op": "11011010|000|Rm|0|00000|11111|Rd" , "io": "C=R"}, {"inst": "ngcs Wd, Wm" , "op": "01111010|000|Rm|0|00000|11111|Rd" , "io": "N=W Z=W C=X V=W"}, {"inst": "ngcs Xd, Xm" , "op": "11111010|000|Rm|0|00000|11111|Rd" , "io": "N=W Z=W C=X V=W"}, {"inst": "nop" , "op": "11010101|00|000011|0010|0000|000|11111"}, {"inst": "orn Wd, Wn, Wm, {sop #n}" , "op": "00101010|sop:2|1|Rm|n:6|Rn|Rd"}, {"inst": "orn Xd, Xn, Xm, {sop #n}" , "op": "10101010|sop:2|1|Rm|n:6|Rn|Rd"}, {"inst": "orr Wd, Wn, Wm, {sop #n}" , "op": "00101010|sop:2|0|Rm|n:6|Rn|Rd"}, {"inst": "orr Xd, Xn, Xm, {sop #n}" , "op": "10101010|sop:2|0|Rm|n:6|Rn|Rd"}, {"inst": "orr Wd|WSP, Wn, #log_imm" , "op": "00110010|0|imm:13|Rn|Rd" , "imm": "ImmLogical(log_imm, 0)"}, {"inst": "orr Xd|SP, Xn, #log_imm" , "op": "10110010|0|imm:13|Rn|Rd" , "imm": "ImmLogical(log_imm, 1)"}, {"inst": "prfm #prf_op, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n*8}]" , "op": "11111000|101|Rm|option:3|n:1|10|Rn|prf_op:5" , "imm": "ImmPRF(prf_op)"}, {"inst": "prfm #prf_op, [Xn|SP, #zoff]" , "op": "11111001|10|zoff:12|Rn|prf_op:5" , "imm": "ImmPRF(prf_op)"}, {"inst": "prfm #prf_op, [PC, #soff*4]" , "op": "11011000|soff:19|prf_op:5" , "imm": "ImmPRF(prf_op)"}, {"inst": "prfum #prf_op, [Xn|SP, #soff]" , "op": "11111000|100|soff:9|00|Rn|prf_op:5" , "imm": "ImmPRF(prf_op)"}, {"inst": "pssbb" , "op": "11010101|000|00011|0011|0100|100|11111"}, {"inst": "rbit Wd, Wn" , "op": "01011010|110|00000|0|00000|Rn|Rd"}, {"inst": "rbit Xd, Xn" , "op": "11011010|110|00000|0|00000|Rn|Rd"}, {"inst": "ret Xn" , "op": "11010100|010|11111|0|00000|Rn|00000" , "control": "return"}, {"inst": "rev Wd, Wn" , "op": "01011010|110|00000|0|00010|Rn|Rd"}, {"inst": "rev|rev64 Xd, Xn" , "op": "11011010|110|00000|0|00011|Rn|Rd"}, {"inst": "rev16 Wd, Wn" , "op": "01011010|110|00000|0|00001|Rn|Rd"}, {"inst": "rev16 Xd, Xn" , "op": "11011010|110|00000|0|00001|Rn|Rd"}, {"inst": "rev32 Xd, Xn" , "op": "11011010|110|00000|0|00010|Rn|Rd"}, {"inst": "ror|rorv Wd, Wn, Wm" , "op": "00011010|110|Rm|0|01011|Rn|Rd"}, {"inst": "ror|rorv Xd, Xn, Xm" , "op": "10011010|110|Rm|0|01011|Rn|Rd"}, {"inst": "ror Wd, Wn, #n" , "op": "00010011|100|Rn|n:6|Rn|Rd"}, {"inst": "ror Xd, Xn, #n" , "op": "10010011|111|Rn|n:6|Rn|Rd"}, {"inst": "sbc Wd, Wn, Wm" , "op": "01011010|000|Rm|0|00000|Rn|Rd" , "io": "C=R"}, {"inst": "sbc Xd, Xn, Xm" , "op": "11011010|000|Rm|0|00000|Rn|Rd" , "io": "C=R"}, {"inst": "sbcs Wd, Wn, Wm" , "op": "01111010|000|Rm|0|00000|Rn|Rd" , "io": "N=W Z=W C=X V=W"}, {"inst": "sbcs Xd, Xn, Xm" , "op": "11111010|000|Rm|0|00000|Rn|Rd" , "io": "N=W Z=W C=X V=W"}, {"inst": "sbfiz Wd, Wn, #lsb, #width" , "op": "00010011|00|immr:6|imms:6|Rn|Rd" , "imm": "ImmBFIZ(lsb, width, 0)"}, {"inst": "sbfiz Xd, Xn, #lsb, #width" , "op": "10010011|01|immr:6|imms:6|Rn|Rd" , "imm": "ImmBFIZ(lsb, width, 1)"}, {"inst": "sbfm Wd, Wn, #immr, #imms" , "op": "00010011|00|immr:6|imms:6|Rn|Rd" , "imm": "ImmBFM(immr, imms, 0)"}, {"inst": "sbfm Xd, Xn, #immr, #imms" , "op": "10010011|01|immr:6|imms:6|Rn|Rd" , "imm": "ImmBFM(immr, imms, 1)"}, {"inst": "sbfx Wd, Wn, #lsb, #width" , "op": "00010011|00|immr:6|imms:6|Rn|Rd" , "imm": "ImmBFX(lsb, width, 0)"}, {"inst": "sbfx Xd, Xn, #lsb, #width" , "op": "10010011|01|immr:6|imms:6|Rn|Rd" , "imm": "ImmBFX(lsb, width, 1)"}, {"inst": "sdiv Wd, Wn, Wm" , "op": "00011010|110|Rm|0|00011|Rn|Rd"}, {"inst": "sdiv Xd, Xn, Xm" , "op": "10011010|110|Rm|0|00011|Rn|Rd"}, {"inst": "sev" , "op": "11010101|000|00011|0010|0000|100|11111"}, {"inst": "sevl" , "op": "11010101|000|00011|0010|0000|101|11111"}, {"inst": "smaddl Xd, Wn, Wm, Xa" , "op": "10011011|001|Rm|0|Ra|Rn|Rd"}, {"inst": "smc #zimm" , "op": "11010100|000|zimm:16|00011"}, {"inst": "smnegl Xd, Wn, Wm" , "op": "10011011|001|Rm|1|11111|Rn|Rd"}, {"inst": "smsubl Xd, Wn, Wm, Xa" , "op": "10011011|001|Rm|1|Ra|Rn|Rd"}, {"inst": "smulh Xd, Xn, Xm" , "op": "10011011|010|Rm|0|11111|Rn|Rd"}, {"inst": "smull Xd, Wn, Wm" , "op": "10011011|001|Rm|0|11111|Rn|Rd"}, {"inst": "ssbb" , "op": "11010101|000|00011|0011|0000|100|11111"}, {"inst": "stlr Ws, [Xn|SP]" , "op": "10001000|100|11111|1|11111|Rn|Rs"}, {"inst": "stlr Xs, [Xn|SP]" , "op": "11001000|100|11111|1|11111|Rn|Rs"}, {"inst": "stlrb Ws, [Xn|SP]" , "op": "00001000|100|11111|1|11111|Rn|Rs"}, {"inst": "stlrh Ws, [Xn|SP]" , "op": "01001000|100|11111|1|11111|Rn|Rs"}, {"inst": "stlxp Wd, Ws, Ws2, [Xn|SP]" , "op": "10001000|001|Rd|1|Rs2|Rn|Rs"}, {"inst": "stlxp Wd, Xs, Xs2, [Xn|SP]" , "op": "11001000|001|Rd|1|Rs2|Rn|Rs"}, {"inst": "stlxr Wd, Ws, [Xn|SP]" , "op": "10001000|000|Rd|1|11111|Rn|Rs"}, {"inst": "stlxr Wd, Xs, [Xn|SP]" , "op": "11001000|000|Rd|1|11111|Rn|Rs"}, {"inst": "stlxrb Wd, Ws, [Xn|SP]" , "op": "00001000|000|Rd|1|11111|Rn|Rs"}, {"inst": "stlxrh Wd, Xs, [Xn|SP]" , "op": "01001000|000|Rd|1|11111|Rn|Rs"}, {"inst": "stnp Ws, Ws2, [Xn|SP, #simm*4]" , "op": "00101000|00|simm:7|Rs2|Rn|Rs"}, {"inst": "stnp Xs, Xs2, [Xn|SP, #simm*8]" , "op": "10101000|00|simm:7|Rs2|Rn|Rs"}, {"inst": "stp Ws, Ws2, [Xn|SP, #simm*4]{@}{!}" , "op": "0010100|!post|W|0|simm:7|Rs2|Rn|Rs"}, {"inst": "stp Xs, Xs2, [Xn|SP, #simm*8]{@}{!}" , "op": "1010100|!post|W|0|simm:7|Rs2|Rn|Rs"}, {"inst": "str Ws, [Xn|SP, #zoff*4]" , "op": "10111001|00|zoff:12|Rn|Rs"}, {"inst": "str Xs, [Xn|SP, #zoff*8]" , "op": "11111001|00|zoff:12|Rn|Rs"}, {"inst": "str Ws, [Xn|SP, #soff*4]@" , "op": "10111000|000|soff:9|01|Rn|Rs"}, {"inst": "str Xs, [Xn|SP, #soff*8]@" , "op": "11111000|000|soff:9|01|Rn|Rs"}, {"inst": "str Ws, [Xn|SP, #soff*4]!" , "op": "10111000|000|soff:9|11|Rn|Rs"}, {"inst": "str Xs, [Xn|SP, #soff*8]!" , "op": "11111000|000|soff:9|11|Rn|Rs"}, {"inst": "str Ws, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "10111000|001|Rm|option:3|s:1|10|Rn|Rs" , "imm": "ImmLDR_STR(iop, n)"}, {"inst": "str Xs, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "11111000|001|Rm|option:3|s:1|10|Rn|Rs" , "imm": "ImmLDR_STR(iop, n)"}, {"inst": "strb Ws, [Xn|SP, #zoff]" , "op": "00111001|00|zoff:12|Rn|Rs"}, {"inst": "strb Ws, [Xn|SP, #soff]@" , "op": "00111000|000|soff:9|01|Rn|Rs"}, {"inst": "strb Ws, [Xn|SP, #soff]!" , "op": "00111000|000|soff:9|11|Rn|Rs"}, {"inst": "strb Ws, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "00111000|001|Rm|option:3|s:1|10|Rn|Rs" , "imm": "ImmLDRB_STRB(iop, n)"}, {"inst": "strh Ws, [Xn|SP, #zoff*2]" , "op": "01111001|00|zoff:12|Rn|Rs"}, {"inst": "strh Ws, [Xn|SP, #soff*2]@" , "op": "01111000|000|soff:9|01|Rn|Rs"}, {"inst": "strh Ws, [Xn|SP, #soff*2]!" , "op": "01111000|000|soff:9|11|Rn|Rs"}, {"inst": "strh Ws, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "01111000|001|Rm|option:3|s:1|10|Rn|Rs" , "imm": "ImmLDRH_STRH(iop, n)"}, {"inst": "sttr Ws, [Xn|SP, #soff]" , "op": "10111000|000|soff:9|10|Rn|Rs"}, {"inst": "sttr Xs, [Xn|SP, #soff]" , "op": "11111000|000|soff:9|10|Rn|Rs"}, {"inst": "sttrb Ws, [Xn|SP, #soff]" , "op": "00111000|000|soff:9|10|Rn|Rs"}, {"inst": "sttrh Ws, [Xn|SP, #soff]" , "op": "01111000|000|soff:9|10|Rn|Rs"}, {"inst": "stur Ws, [Xn|SP, #soff]" , "op": "10111000|000|soff:9|00|Rn|Rs"}, {"inst": "stur Xs, [Xn|SP, #soff]" , "op": "11111000|000|soff:9|00|Rn|Rs"}, {"inst": "sturb Ws, [Xn|SP, #soff]" , "op": "00111000|000|soff:9|00|Rn|Rs"}, {"inst": "sturh Ws, [Xn|SP, #soff]" , "op": "01111000|000|soff:9|00|Rn|Rs"}, {"inst": "stxp Wd, Ws, Ws2, [Xn|SP]" , "op": "10001000|001|Rd|0|Rs2|Rn|Rs"}, {"inst": "stxp Wd, Xs, Xs2, [Xn|SP]" , "op": "11001000|001|Rd|0|Rs2|Rn|Rs"}, {"inst": "stxr Wd, Ws, [Xn|SP]" , "op": "10001000|000|Rd|0|11111|Rn|Rs"}, {"inst": "stxr Wd, Xs, [Xn|SP]" , "op": "11001000|000|Rd|0|11111|Rn|Rs"}, {"inst": "stxrb Wd, Ws, [Xn|SP]" , "op": "00001000|000|Rd|0|11111|Rn|Rs"}, {"inst": "stxrh Wd, Xs, [Xn|SP]" , "op": "01001000|000|Rd|0|11111|Rn|Rs"}, {"inst": "sub Wd, Wn, Wm, {lsl|lsr|asr #n}" , "op": "01001011|sop:2|0|Rm|n:6|Rn|Rd"}, {"inst": "sub Xd, Xn, Xm, {lsl|lsr|asr #n}" , "op": "11001011|sop:2|0|Rm|n:6|Rn|Rd"}, {"inst": "sub Wd|WSP, Wn|WSP, Wm, {extend #n}" , "op": "01001011|00|1|Rm|option:3|n:3|Rn|Rd"}, {"inst": "sub Xd|SP, Xn|SP, Rm, {extend #n}" , "op": "11001011|00|1|Rm|option:3|n:3|Rn|Rd"}, {"inst": "sub Wd|WSP, Wn|WSP, #immZ, {lsl #n=0|12}" , "op": "01010001|0|n:1|immZ:12|Rn|Rd"}, {"inst": "sub Xd|SP, Xn|SP, #immZ, {lsl #n=0|12}" , "op": "11010001|0|n:1|immZ:12|Rn|Rd"}, {"inst": "subs Wd, Wn, Wm, {lsl|lsr|asr #n}" , "op": "01101011|sop:2|0|Rm|n:6|Rn|Rd" , "io": "N=W Z=W C=W V=W"}, {"inst": "subs Xd, Xn, Xm, {lsl|lsr|asr #n}" , "op": "11101011|sop:2|0|Rm|n:6|Rn|Rd" , "io": "N=W Z=W C=W V=W"}, {"inst": "subs Wd, Wn|WSP, Wm, {extend #n}" , "op": "01101011|00|1|Rm|option:3|n:3|Rn|Rd" , "io": "N=W Z=W C=W V=W"}, {"inst": "subs Xd, Xn|SP, Rm, {extend #n}" , "op": "11101011|00|1|Rm|option:3|n:3|Rn|Rd" , "io": "N=W Z=W C=W V=W"}, {"inst": "subs Wd|WSP, Wn|WSP, #immZ, {lsl #n=0|12}" , "op": "01110001|0|n:1|immZ:12|Rn|Rd" , "io": "N=W Z=W C=W V=W"}, {"inst": "subs Xd|SP, Xn|SP, #immZ, {lsl #n=0|12}" , "op": "11110001|0|n:1|immZ:12|Rn|Rd" , "io": "N=W Z=W C=W V=W"}, {"inst": "svc #zimm" , "op": "11010100|000|zimm:16|00001"}, {"inst": "sxtb Wd, Wn" , "op": "00010011|000|00000|0|00111|Rn|Rd"}, {"inst": "sxtb Xd, Wn" , "op": "10010011|010|00000|0|00111|Rn|Rd"}, {"inst": "sxth Wd, Wn" , "op": "00010011|000|00000|0|01111|Rn|Rd"}, {"inst": "sxth Xd, Wn" , "op": "10010011|010|00000|0|01111|Rn|Rd"}, {"inst": "sxtw Xd, Wn" , "op": "10010011|010|00000|0|11111|Rn|Rd"}, {"inst": "sys #op1, #Cn, #Cm, #op2" , "op": "11010101|000|01|op1:3|CRn|CRm|op2:3|11111"}, {"inst": "sys #op1, #Cn, #Cm, #op2, Xt" , "op": "11010101|000|01|op1:3|CRn|CRm|op2:3|Rt"}, {"inst": "sysl Xd, #op1, #Cn, #Cm, #op2" , "op": "11010101|001|01|op1:3|CRn|CRm|op2:3|Rd"}, {"inst": "tbnz Wt, #imm, #relS*4" , "op": "00110111|imm:5|relS:14|Rt"}, {"inst": "tbnz Xt, #imm, #relS*4" , "op": "imm:1|0110111|imm:5|relS:14|Rt"}, {"inst": "tbz Wt, #imm, #relS*4" , "op": "00110110|imm:5|relS:14|Rt"}, {"inst": "tbz Xt, #imm, #relS*4" , "op": "imm:1|0110110|imm:5|relS:14|Rt"}, {"inst": "tlbi #tlbi_op" , "op": "11010101|00|001|op1:3|1000|CRm|op2:3|11111" , "imm": "ImmTLBI(tlbi_op)"}, {"inst": "tlbi #tlbi_op, Xt" , "op": "11010101|00|001|op1:3|1000|CRm|op2:3|Rt" , "imm": "ImmTLBI(tlbi_op)"}, {"inst": "tst Wn, Wm, {sop #n}" , "op": "01101010|sop:2|0|Rm|n:6|Rn|11111" , "io": "N=W Z=W C=W V=W"}, {"inst": "tst Xn, Xm, {sop #n}" , "op": "11101010|sop:2|0|Rm|n:6|Rn|11111" , "io": "N=W Z=W C=W V=W"}, {"inst": "tst Wn, #imm" , "op": "01110010|0|imm:13|Rn|11111" , "io": "N=W Z=W C=W V=W", "imm": "LogicalImm(imm, 0)"}, {"inst": "tst Xn, #imm" , "op": "11110010|0|imm:13|Rn|11111" , "io": "N=W Z=W C=W V=W", "imm": "LogicalImm(imm, 1)"}, {"inst": "ubfiz Wd, Wn, #lsb, #width" , "op": "01010011|00|immr:6|imms:6|Rn|Rd" , "imm": "ImmBFIZ(lsb, width, 0)"}, {"inst": "ubfiz Xd, Xn, #lsb, #width" , "op": "11010011|01|immr:6|imms:6|Rn|Rd" , "imm": "ImmBFIZ(lsb, width, 1)"}, {"inst": "ubfm Wd, Wn, #immr, #imms" , "op": "01010011|00|immr:6|imms:6|Rn|Rd" , "imm": "ImmBFM(immr, imms, 0)"}, {"inst": "ubfm Xd, Xn, #immr, #imms" , "op": "11010011|01|immr:6|imms:6|Rn|Rd" , "imm": "ImmBFM(immr, imms, 1)"}, {"inst": "ubfx Wd, Wn, #lsb, #width" , "op": "01010011|00|immr:6|imms:6|Rn|Rd" , "imm": "ImmBFX(lsb, width, 0)"}, {"inst": "ubfx Xd, Xn, #lsb, #width" , "op": "11010011|01|immr:6|imms:6|Rn|Rd" , "imm": "ImmBFX(lsb, width, 1)"}, {"inst": "udf #imm" , "op": "00000000|000|00000|imm:16"}, {"inst": "udiv Wd, Wn, Wm" , "op": "00011010|110|Rm|0|00010|Rn|Rd"}, {"inst": "udiv Xd, Xn, Xm" , "op": "10011010|110|Rm|0|00010|Rn|Rd"}, {"inst": "umaddl Xd, Wn, Wm, Xa" , "op": "10011011|101|Rm|0|Ra|Rn|Rd"}, {"inst": "umnegl Xd, Wn, Wm" , "op": "10011011|101|Rm|1|11111|Rn|Rd"}, {"inst": "umsubl Xd, Wn, Wm, Xa" , "op": "10011011|101|Rm|1|Ra|Rn|Rd"}, {"inst": "umulh Xd, Xn, Xm" , "op": "10011011|110|Rm|0|11111|Rn|Rd"}, {"inst": "umull Xd, Wn, Wm" , "op": "10011011|101|Rm|0|11111|Rn|Rd"}, {"inst": "uxtb Wd, Wn" , "op": "01010011|000|00000|0|00111|Rn|Rd"}, {"inst": "uxth Wd, Wn" , "op": "01010011|000|00000|0|01111|Rn|Rd"}, {"inst": "wfe" , "op": "11010101|000|00011|0010|0000|010|11111"}, {"inst": "wfi" , "op": "11010101|000|00011|0010|0000|011|11111"}, {"inst": "yield" , "op": "11010101|000|00011|0010|0000|001|11111"} ]}, {"category": "GP GP_EXT", "ext": "BRBE", "data": [ {"inst": "brb #brb_op" , "op": "11010101|000|01001|0111|0010|op2:3|11111" , "imm": "ImmBRB(beb_op)"}, {"inst": "brb #brb_op, Xt" , "op": "11010101|000|01001|0111|0010|op2:3|Rt" , "imm": "ImmBRB(beb_op)"} ]}, {"category": "GP GP_EXT", "ext": "BTI", "data": [ {"inst": "bti {#targets}" , "op": "11010101|000|00011|0010|0100|op2:3|11111" , "imm": "ImmBTI(targets)"} ]}, {"category": "GP GP_EXT", "ext": "CHK", "data": [ {"inst": "chkfeat" , "op": "11010101|000|00011|0010|0101|000|11111"} ]}, {"category": "GP GP_EXT", "ext": "CLRBHB", "data": [ {"inst": "clrbhb" , "op": "11010101|000|00011|0010|0010|110|11111"} ]}, {"category": "GP GP_EXT CRYPTO_HASH", "ext": "CRC32", "data": [ {"inst": "crc32b Wd, Wn, Wm" , "op": "00011010|110|Rm|0|10000|Rn|Rd"}, {"inst": "crc32h Wd, Wn, Wm" , "op": "00011010|110|Rm|0|10001|Rn|Rd"}, {"inst": "crc32w Wd, Wn, Wm" , "op": "00011010|110|Rm|0|10010|Rn|Rd"}, {"inst": "crc32x Xd, Xn, Xm" , "op": "10011010|110|Rm|0|10011|Rn|Rd"}, {"inst": "crc32cb Wd, Wn, Wm" , "op": "00011010|110|Rm|0|10100|Rn|Rd"}, {"inst": "crc32ch Wd, Wn, Wm" , "op": "00011010|110|Rm|0|10101|Rn|Rd"}, {"inst": "crc32cw Wd, Wn, Wm" , "op": "00011010|110|Rm|0|10110|Rn|Rd"}, {"inst": "crc32cx Xd, Xn, Xm" , "op": "10011010|110|Rm|0|10111|Rn|Rd"} ]}, {"category": "GP GP_EXT", "ext": "CSSC", "data": [ {"inst": "abs Wd, Wn" , "op": "01011010|110|00000|0|01000|Rn|Rd"}, {"inst": "abs Xd, Xn" , "op": "11011010|110|00000|0|01000|Rn|Rd"}, {"inst": "cnt Wd, Wn" , "op": "01011010|110|00000|0|00111|Rn|Rd"}, {"inst": "cnt Xd, Xn" , "op": "11011010|110|00000|0|00111|Rn|Rd"}, {"inst": "ctz Wd, Wn" , "op": "01011010|110|00000|0|00110|Rn|Rd"}, {"inst": "ctz Xd, Xn" , "op": "11011010|110|00000|0|00110|Rn|Rd"}, {"inst": "smax Wd, Wn, Wm" , "op": "00011010|110|Rm|0|11000|Rn|Rd"}, {"inst": "smax Xd, Xn, Xm" , "op": "10011010|110|Rm|0|11000|Rn|Rd"}, {"inst": "smax Wd, Wn, #simm" , "op": "00010001|110|000|simm:8|Rn|Rd"}, {"inst": "smax Xd, Xn, #simm" , "op": "10010001|110|000|simm:8|Rn|Rd"}, {"inst": "smin Wd, Wn, Wm" , "op": "00011010|110|Rm|0|11010|Rn|Rd"}, {"inst": "smin Xd, Xn, Xm" , "op": "10011010|110|Rm|0|11010|Rn|Rd"}, {"inst": "smin Wd, Wn, #simm" , "op": "00010001|110|010|simm:8|Rn|Rd"}, {"inst": "smin Xd, Xn, #simm" , "op": "10010001|110|010|simm:8|Rn|Rd"}, {"inst": "umax Wd, Wn, Wm" , "op": "00011010|110|Rm|0|11001|Rn|Rd"}, {"inst": "umax Xd, Xn, Xm" , "op": "10011010|110|Rm|0|11001|Rn|Rd"}, {"inst": "umax Wd, Wn, #simm" , "op": "00010001|110|001|simm:8|Rn|Rd"}, {"inst": "umax Xd, Xn, #simm" , "op": "10010001|110|001|simm:8|Rn|Rd"}, {"inst": "umin Wd, Wn, Wm" , "op": "00011010|110|Rm|0|11011|Rn|Rd"}, {"inst": "umin Xd, Xn, Xm" , "op": "10011010|110|Rm|0|11011|Rn|Rd"}, {"inst": "umin Wd, Wn, #simm" , "op": "00010001|110|011|simm:8|Rn|Rd"}, {"inst": "umin Xd, Xn, #simm" , "op": "10010001|110|011|simm:8|Rn|Rd"} ]}, {"category": "GP GP_EXT", "ext": "D128", "data": [ {"inst": "tlbip #tlbip_op, 2x{Xt}+" , "op": "11010101|010|01|op1:3|CRn|CRm|op2:3|Rt" , "imm": "ImmTLBIP(tlbip_op)"} ]}, {"category": "GP GP_EXT", "ext": "DGH", "data": [ {"inst": "dgh" , "op": "11010101|000|00|011|0010|0000|110|11111"} ]}, {"category": "GP GP_EXT", "ext": "FLAGM", "data": [ {"inst": "cfinv" , "op": "11010101|000|00000|0100|0000|000|11111" , "io": "C=X"}, {"inst": "rmif Xn, #shift, #mask" , "op": "10111010|000|shift:6|00001|Rn|0|mask:4" , "io": "N=W Z=W C=W V=W"}, {"inst": "setf16 Wn" , "op": "00111010|000|00000|0|10010|Rn|01101" , "io": "N=W Z=W V=W"}, {"inst": "setf8 Wn" , "op": "00111010|000|00000|0|00010|Rn|01101" , "io": "N=W Z=W V=W"} ]}, {"category": "GP GP_EXT", "ext": "FLAGM2", "data": [ {"inst": "axflag" , "op": "11010101|000|00000|0100|0000|010|11111" , "io": "N=X Z=X C=X V=X"}, {"inst": "xaflag" , "op": "11010101|000|00000|0100|0000|001|11111" , "io": "N=X Z=X C=X V=X"} ]}, {"category": "GP GP_EXT", "ext": "GCS", "data": [ {"inst": "gcsb #dsync" , "op": "11010101|000|00011|0010|0010|011|11111"}, {"inst": "gcspopcx" , "op": "11010101|000|01000|0111|0111|101|11111"}, {"inst": "gcspopcx Xt" , "op": "11010101|000|01000|0111|0111|101|Rt"}, {"inst": "gcspopm Xt" , "op": "11010101|001|01011|0111|0111|001|Rt"}, {"inst": "gcspopx" , "op": "11010101|000|01000|0111|0111|110|11111"}, {"inst": "gcspopx Xt" , "op": "11010101|000|01000|0111|0111|110|Rt"}, {"inst": "gcspushm Xt" , "op": "11010101|000|01011|0111|0111|000|Rt"}, {"inst": "gcspushx" , "op": "11010101|000|01000|0111|0111|100|11111"}, {"inst": "gcspushx Xt" , "op": "11010101|000|01000|0111|0111|100|Rt"}, {"inst": "gcsss1 Xt" , "op": "11010101|000|01011|0111|0111|010|Rt"}, {"inst": "gcsss2 Xt" , "op": "11010101|001|01011|0111|0111|011|Rt"}, {"inst": "gcsstr Xs, [Xn|SP]" , "op": "11011001|000|11111|0|00011|Rn|Rs"}, {"inst": "gcssttr Xs, [Xn|SP]" , "op": "11011001|000|11111|0|00111|Rn|Rs"} ]}, {"category": "GP GP_EXT", "ext": "HBC", "data": [ {"inst": "bc. #relS*4" , "op": "01010100|relS:19|1|cond" , "control": "branch", "io": "N=R Z=R C=R V=R"} ]}, {"category": "GP GP_EXT", "ext": "ITE", "data": [ {"inst": "trcit Xt" , "op": "11010101|000|01011|0111|0010|111|Rt"} ]}, {"category": "GP GP_EXT", "ext": "LOR", "data": [ {"inst": "ldlar Wd, [Xn|SP]" , "op": "10001000|110|11111|0|11111|Rn|Rd"}, {"inst": "ldlar Xd, [Xn|SP]" , "op": "11001000|110|11111|0|11111|Rn|Rd"}, {"inst": "ldlarb Wd, [Xn|SP]" , "op": "00001000|110|11111|0|11111|Rn|Rd"}, {"inst": "ldlarh Wd, [Xn|SP]" , "op": "01001000|110|11111|0|11111|Rn|Rd"}, {"inst": "stllr Ws, [Xn|SP]" , "op": "10001000|100|11111|0|11111|Rn|Rs"}, {"inst": "stllr Xs, [Xn|SP]" , "op": "11001000|100|11111|0|11111|Rn|Rs"}, {"inst": "stllrb Ws, [Xn|SP]" , "op": "00001000|100|11111|0|11111|Rn|Rs"}, {"inst": "stllrh Ws, [Xn|SP]" , "op": "01001000|100|11111|0|11111|Rn|Rs"} ]}, {"category": "GP GP_EXT", "ext": "LRCPC", "data": [ {"inst": "ldapr Wd, [Xn|SP]" , "op": "10111000|101|11111|1|10000|Rn|Rd"}, {"inst": "ldapr Xd, [Xn|SP]" , "op": "11111000|101|11111|1|10000|Rn|Rd"}, {"inst": "ldaprb Wd, [Xn|SP]" , "op": "00111000|101|11111|1|10000|Rn|Rd"}, {"inst": "ldaprh Wd, [Xn|SP]" , "op": "01111000|101|11111|1|10000|Rn|Rd"} ]}, {"category": "GP GP_EXT", "ext": "LRCPC2", "data": [ {"inst": "ldapur Wd, [Xn|SP, #soff]" , "op": "10011001|010|soff:9|00|Rn|Rd"}, {"inst": "ldapur Xd, [Xn|SP, #soff]" , "op": "11011001|010|soff:9|00|Rn|Rd"}, {"inst": "ldapurb Wd, [Xn|SP, #soff]" , "op": "00011001|010|soff:9|00|Rn|Rd"}, {"inst": "ldapurh Wd, [Xn|SP, #soff]" , "op": "01011001|010|soff:9|00|Rn|Rd"}, {"inst": "ldapursb Wd, [Xn|SP, #soff]" , "op": "00011001|110|soff:9|00|Rn|Rd"}, {"inst": "ldapursb Xd, [Xn|SP, #soff]" , "op": "00011001|100|soff:9|00|Rn|Rd"}, {"inst": "ldapursh Wd, [Xn|SP, #soff]" , "op": "01011001|110|soff:9|00|Rn|Rd"}, {"inst": "ldapursh Xd, [Xn|SP, #soff]" , "op": "01011001|100|soff:9|00|Rn|Rd"}, {"inst": "ldapursw Xd, [Xn|SP, #soff]" , "op": "10011001|100|soff:9|00|Rn|Rd"}, {"inst": "stlur Ws, [Xn|SP, #soff]" , "op": "10011001|000|soff:9|00|Rn|Rs"}, {"inst": "stlur Xs, [Xn|SP, #soff]" , "op": "11011001|000|soff:9|00|Rn|Rs"}, {"inst": "stlurb Ws, [Xn|SP, #soff]" , "op": "00011001|000|soff:9|00|Rn|Rs"}, {"inst": "stlurh Ws, [Xn|SP, #soff]" , "op": "01011001|000|soff:9|00|Rn|Rs"} ]}, {"category": "GP GP_EXT", "ext": "LRCPC3", "data": [ {"inst": "ldiapp Wd, Wd2, [Xn|SP]" , "op": "10011001|010|Rd2|0|00110|Rn|Rd"}, {"inst": "ldiapp Wd, Wd2, [Xn|SP, #8]@" , "op": "10011001|010|Rd2|0|00010|Rn|Rd"}, {"inst": "ldiapp Xd, Xd2, [Xn|SP]" , "op": "11011001|010|Rd2|0|00110|Rn|Rd"}, {"inst": "ldiapp Xd, Xd2, [Xn|SP, #16]@" , "op": "11011001|010|Rd2|0|00010|Rn|Rd"}, {"inst": "stilp Ws, Ws2, [Xn|SP]" , "op": "10011001|000|Rs2|0|00110|Rn|Rs"}, {"inst": "stilp Ws, Ws2, [Xn|SP, #8]@" , "op": "10011001|000|Rs2|0|00010|Rn|Rs"}, {"inst": "stilp Xs, Xs2, [Xn|SP]" , "op": "11011001|000|Rs2|0|00110|Rn|Rs"}, {"inst": "stilp Xs, Xs2, [Xn|SP, #16]@" , "op": "11011001|000|Rs2|0|00010|Rn|Rs"} ]}, {"category": "GP GP_EXT", "ext": "LS64", "data": [ {"inst": "ld64b 8x{Xd}+, [Xn|SP]" , "op": "11111000|001|11111|1|10100|Rn|Rd"}, {"inst": "st64b 8x{Xs}+, [Xn|SP]" , "op": "11111000|001|11111|1|00100|Rn|Rs"} ]}, {"category": "GP GP_EXT", "ext": "LS64_ACCDATA", "data": [ {"inst": "st64bv0 Rd, 8x{Xs}+, [Xn|SP]" , "op": "11111000|001|Rd|1|01000|Rn|Rs"} ]}, {"category": "GP GP_EXT", "ext": "LS64_V", "data": [ {"inst": "st64bv Rd, 8x{Xs}+, [Xn|SP]" , "op": "11111000|001|Rd|1|01100|Rn|Rs"} ]}, {"category": "GP GP_EXT", "ext": "LSE", "data": [ {"inst": "cas Ws, Wd, [Xn|SP]" , "op": "10001000|001|Rs|0|11111|Rn|Rd"}, {"inst": "casa Ws, Wd, [Xn|SP]" , "op": "10001000|011|Rs|0|11111|Rn|Rd"}, {"inst": "casal Ws, Wd, [Xn|SP]" , "op": "10001000|011|Rs|1|11111|Rn|Rd"}, {"inst": "casl Ws, Wd, [Xn|SP]" , "op": "10001000|001|Rs|1|11111|Rn|Rd"}, {"inst": "cas Xs, Xd, [Xn|SP]" , "op": "11001000|001|Rs|0|11111|Rn|Rd"}, {"inst": "casa Xs, Xd, [Xn|SP]" , "op": "11001000|011|Rs|0|11111|Rn|Rd"}, {"inst": "casal Xs, Xd, [Xn|SP]" , "op": "11001000|011|Rs|1|11111|Rn|Rd"}, {"inst": "casl Xs, Xd, [Xn|SP]" , "op": "11001000|001|Rs|1|11111|Rn|Rd"}, {"inst": "casab Ws, Wd, [Xn|SP]" , "op": "00001000|111|Rs|0|11111|Rn|Rd"}, {"inst": "casalb Ws, Wd, [Xn|SP]" , "op": "00001000|111|Rs|1|11111|Rn|Rd"}, {"inst": "casb Ws, Wd, [Xn|SP]" , "op": "00001000|101|Rs|0|11111|Rn|Rd"}, {"inst": "caslb Ws, Wd, [Xn|SP]" , "op": "00001000|101|Rs|1|11111|Rn|Rd"}, {"inst": "casah Ws, Wd, [Xn|SP]" , "op": "01001000|111|Rs|0|11111|Rn|Rd"}, {"inst": "casalh Ws, Wd, [Xn|SP]" , "op": "01001000|111|Rs|1|11111|Rn|Rd"}, {"inst": "cash Ws, Wd, [Xn|SP]" , "op": "01001000|101|Rs|0|11111|Rn|Rd"}, {"inst": "caslh Ws, Wd, [Xn|SP]" , "op": "01001000|101|Rs|1|11111|Rn|Rd"}, {"inst": "casp 2x{Ws}+, 2x{Wd}+, [Xn|SP]" , "op": "00001000|001|Rs|0|11111|Rn|Rd"}, {"inst": "caspa 2x{Ws}+, 2x{Wd}+, [Xn|SP]" , "op": "00001000|011|Rs|0|11111|Rn|Rd"}, {"inst": "caspal 2x{Ws}+, 2x{Wd}+, [Xn|SP]" , "op": "00001000|011|Rs|1|11111|Rn|Rd"}, {"inst": "caspl 2x{Ws}+, 2x{Wd}+, [Xn|SP]" , "op": "00001000|001|Rs|1|11111|Rn|Rd"}, {"inst": "casp 2x{Xs}+, 2x{Xd}+, [Xn|SP]" , "op": "01001000|001|Rs|0|11111|Rn|Rd"}, {"inst": "caspa 2x{Xs}+, 2x{Xd}+, [Xn|SP]" , "op": "01001000|011|Rs|0|11111|Rn|Rd"}, {"inst": "caspal 2x{Xs}+, 2x{Xd}+, [Xn|SP]" , "op": "01001000|011|Rs|1|11111|Rn|Rd"}, {"inst": "caspl 2x{Xs}+, 2x{Xd}+, [Xn|SP]" , "op": "01001000|001|Rs|1|11111|Rn|Rd"}, {"inst": "ldadd Ws, Wd, [Xn|SP]" , "op": "10111000|001|Rs|0|00000|Rn|Rd"}, {"inst": "ldadda Ws, Wd, [Xn|SP]" , "op": "10111000|101|Rs|0|00000|Rn|Rd"}, {"inst": "ldaddal Ws, Wd, [Xn|SP]" , "op": "10111000|111|Rs|0|00000|Rn|Rd"}, {"inst": "ldaddl Ws, Wd, [Xn|SP]" , "op": "10111000|011|Rs|0|00000|Rn|Rd"}, {"inst": "ldadd Xs, Xd, [Xn|SP]" , "op": "11111000|001|Rs|0|00000|Rn|Rd"}, {"inst": "ldadda Xs, Xd, [Xn|SP]" , "op": "11111000|101|Rs|0|00000|Rn|Rd"}, {"inst": "ldaddal Xs, Xd, [Xn|SP]" , "op": "11111000|111|Rs|0|00000|Rn|Rd"}, {"inst": "ldaddl Xs, Xd, [Xn|SP]" , "op": "11111000|011|Rs|0|00000|Rn|Rd"}, {"inst": "ldaddb Ws, Wd, [Xn|SP]" , "op": "00111000|001|Rs|0|00000|Rn|Rd"}, {"inst": "ldaddab Ws, Wd, [Xn|SP]" , "op": "00111000|101|Rs|0|00000|Rn|Rd"}, {"inst": "ldaddalb Ws, Wd, [Xn|SP]" , "op": "00111000|111|Rs|0|00000|Rn|Rd"}, {"inst": "ldaddlb Ws, Wd, [Xn|SP]" , "op": "00111000|011|Rs|0|00000|Rn|Rd"}, {"inst": "ldaddh Ws, Wd, [Xn|SP]" , "op": "01111000|001|Rs|0|00000|Rn|Rd"}, {"inst": "ldaddah Ws, Wd, [Xn|SP]" , "op": "01111000|101|Rs|0|00000|Rn|Rd"}, {"inst": "ldaddalh Ws, Wd, [Xn|SP]" , "op": "01111000|111|Rs|0|00000|Rn|Rd"}, {"inst": "ldaddlh Ws, Wd, [Xn|SP]" , "op": "01111000|011|Rs|0|00000|Rn|Rd"}, {"inst": "ldclr Ws, Wd, [Xn|SP]" , "op": "10111000|001|Rs|0|00100|Rn|Rd"}, {"inst": "ldclra Ws, Wd, [Xn|SP]" , "op": "10111000|101|Rs|0|00100|Rn|Rd"}, {"inst": "ldclral Ws, Wd, [Xn|SP]" , "op": "10111000|111|Rs|0|00100|Rn|Rd"}, {"inst": "ldclrl Ws, Wd, [Xn|SP]" , "op": "10111000|011|Rs|0|00100|Rn|Rd"}, {"inst": "ldclr Xs, Xd, [Xn|SP]" , "op": "11111000|001|Rs|0|00100|Rn|Rd"}, {"inst": "ldclra Xs, Xd, [Xn|SP]" , "op": "11111000|101|Rs|0|00100|Rn|Rd"}, {"inst": "ldclral Xs, Xd, [Xn|SP]" , "op": "11111000|111|Rs|0|00100|Rn|Rd"}, {"inst": "ldclrl Xs, Xd, [Xn|SP]" , "op": "11111000|011|Rs|0|00100|Rn|Rd"}, {"inst": "ldclrb Ws, Wd, [Xn|SP]" , "op": "00111000|001|Rs|0|00100|Rn|Rd"}, {"inst": "ldclrab Ws, Wd, [Xn|SP]" , "op": "00111000|101|Rs|0|00100|Rn|Rd"}, {"inst": "ldclralb Ws, Wd, [Xn|SP]" , "op": "00111000|111|Rs|0|00100|Rn|Rd"}, {"inst": "ldclrlb Ws, Wd, [Xn|SP]" , "op": "00111000|011|Rs|0|00100|Rn|Rd"}, {"inst": "ldclrh Ws, Wd, [Xn|SP]" , "op": "01111000|001|Rs|0|00100|Rn|Rd"}, {"inst": "ldclrah Ws, Wd, [Xn|SP]" , "op": "01111000|101|Rs|0|00100|Rn|Rd"}, {"inst": "ldclralh Ws, Wd, [Xn|SP]" , "op": "01111000|111|Rs|0|00100|Rn|Rd"}, {"inst": "ldclrlh Ws, Wd, [Xn|SP]" , "op": "01111000|011|Rs|0|00100|Rn|Rd"}, {"inst": "ldeor Ws, Wd, [Xn|SP]" , "op": "10111000|001|Rs|0|01000|Rn|Rd"}, {"inst": "ldeora Ws, Wd, [Xn|SP]" , "op": "10111000|101|Rs|0|01000|Rn|Rd"}, {"inst": "ldeoral Ws, Wd, [Xn|SP]" , "op": "10111000|111|Rs|0|01000|Rn|Rd"}, {"inst": "ldeorl Ws, Wd, [Xn|SP]" , "op": "10111000|011|Rs|0|01000|Rn|Rd"}, {"inst": "ldeor Xs, Xd, [Xn|SP]" , "op": "11111000|001|Rs|0|01000|Rn|Rd"}, {"inst": "ldeora Xs, Xd, [Xn|SP]" , "op": "11111000|101|Rs|0|01000|Rn|Rd"}, {"inst": "ldeoral Xs, Xd, [Xn|SP]" , "op": "11111000|111|Rs|0|01000|Rn|Rd"}, {"inst": "ldeorl Xs, Xd, [Xn|SP]" , "op": "11111000|011|Rs|0|01000|Rn|Rd"}, {"inst": "ldeorb Ws, Wd, [Xn|SP]" , "op": "00111000|001|Rs|0|01000|Rn|Rd"}, {"inst": "ldeorab Ws, Wd, [Xn|SP]" , "op": "00111000|101|Rs|0|01000|Rn|Rd"}, {"inst": "ldeoralb Ws, Wd, [Xn|SP]" , "op": "00111000|111|Rs|0|01000|Rn|Rd"}, {"inst": "ldeorlb Ws, Wd, [Xn|SP]" , "op": "00111000|011|Rs|0|01000|Rn|Rd"}, {"inst": "ldeorh Ws, Wd, [Xn|SP]" , "op": "01111000|001|Rs|0|01000|Rn|Rd"}, {"inst": "ldeorah Ws, Wd, [Xn|SP]" , "op": "01111000|101|Rs|0|01000|Rn|Rd"}, {"inst": "ldeoralh Ws, Wd, [Xn|SP]" , "op": "01111000|111|Rs|0|01000|Rn|Rd"}, {"inst": "ldeorlh Ws, Wd, [Xn|SP]" , "op": "01111000|011|Rs|0|01000|Rn|Rd"}, {"inst": "ldset Ws, Wd, [Xn|SP]" , "op": "10111000|001|Rs|0|01100|Rn|Rd"}, {"inst": "ldseta Ws, Wd, [Xn|SP]" , "op": "10111000|101|Rs|0|01100|Rn|Rd"}, {"inst": "ldsetal Ws, Wd, [Xn|SP]" , "op": "10111000|111|Rs|0|01100|Rn|Rd"}, {"inst": "ldsetl Ws, Wd, [Xn|SP]" , "op": "10111000|011|Rs|0|01100|Rn|Rd"}, {"inst": "ldset Xs, Wd, [Xn|SP]" , "op": "11111000|001|Rs|0|01100|Rn|Rd"}, {"inst": "ldseta Xs, Wd, [Xn|SP]" , "op": "11111000|101|Rs|0|01100|Rn|Rd"}, {"inst": "ldsetal Xs, Wd, [Xn|SP]" , "op": "11111000|111|Rs|0|01100|Rn|Rd"}, {"inst": "ldsetl Xs, Wd, [Xn|SP]" , "op": "11111000|011|Rs|0|01100|Rn|Rd"}, {"inst": "ldsetb Ws, Wd, [Xn|SP]" , "op": "00111000|001|Rs|0|01100|Rn|Rd"}, {"inst": "ldsetab Ws, Wd, [Xn|SP]" , "op": "00111000|101|Rs|0|01100|Rn|Rd"}, {"inst": "ldsetalb Ws, Wd, [Xn|SP]" , "op": "00111000|111|Rs|0|01100|Rn|Rd"}, {"inst": "ldsetlb Ws, Wd, [Xn|SP]" , "op": "00111000|011|Rs|0|01100|Rn|Rd"}, {"inst": "ldseth Ws, Wd, [Xn|SP]" , "op": "01111000|001|Rs|0|01100|Rn|Rd"}, {"inst": "ldsetah Ws, Wd, [Xn|SP]" , "op": "01111000|101|Rs|0|01100|Rn|Rd"}, {"inst": "ldsetalh Ws, Wd, [Xn|SP]" , "op": "01111000|111|Rs|0|01100|Rn|Rd"}, {"inst": "ldsetlh Ws, Wd, [Xn|SP]" , "op": "01111000|011|Rs|0|01100|Rn|Rd"}, {"inst": "ldsmax Ws, Wd, [Xn|SP]" , "op": "10111000|001|Rs|0|10000|Rn|Rd"}, {"inst": "ldsmaxa Ws, Wd, [Xn|SP]" , "op": "10111000|101|Rs|0|10000|Rn|Rd"}, {"inst": "ldsmaxal Ws, Wd, [Xn|SP]" , "op": "10111000|111|Rs|0|10000|Rn|Rd"}, {"inst": "ldsmaxl Ws, Wd, [Xn|SP]" , "op": "10111000|011|Rs|0|10000|Rn|Rd"}, {"inst": "ldsmax Xs, Xd, [Xn|SP]" , "op": "11111000|001|Rs|0|10000|Rn|Rd"}, {"inst": "ldsmaxa Xs, Xd, [Xn|SP]" , "op": "11111000|101|Rs|0|10000|Rn|Rd"}, {"inst": "ldsmaxal Xs, Xd, [Xn|SP]" , "op": "11111000|111|Rs|0|10000|Rn|Rd"}, {"inst": "ldsmaxl Xs, Xd, [Xn|SP]" , "op": "11111000|011|Rs|0|10000|Rn|Rd"}, {"inst": "ldsmaxb Ws, Wd, [Xn|SP]" , "op": "00111000|001|Rs|0|10000|Rn|Rd"}, {"inst": "ldsmaxab Ws, Wd, [Xn|SP]" , "op": "00111000|101|Rs|0|10000|Rn|Rd"}, {"inst": "ldsmaxalb Ws, Wd, [Xn|SP]" , "op": "00111000|111|Rs|0|10000|Rn|Rd"}, {"inst": "ldsmaxlb Ws, Wd, [Xn|SP]" , "op": "00111000|011|Rs|0|10000|Rn|Rd"}, {"inst": "ldsmaxh Ws, Wd, [Xn|SP]" , "op": "01111000|001|Rs|0|10000|Rn|Rd"}, {"inst": "ldsmaxah Ws, Wd, [Xn|SP]" , "op": "01111000|101|Rs|0|10000|Rn|Rd"}, {"inst": "ldsmaxalh Ws, Wd, [Xn|SP]" , "op": "01111000|111|Rs|0|10000|Rn|Rd"}, {"inst": "ldsmaxlh Ws, Wd, [Xn|SP]" , "op": "01111000|011|Rs|0|10000|Rn|Rd"}, {"inst": "ldsmin Ws, Wd, [Xn|SP]" , "op": "10111000|001|Rs|0|10100|Rn|Rd"}, {"inst": "ldsmina Ws, Wd, [Xn|SP]" , "op": "10111000|101|Rs|0|10100|Rn|Rd"}, {"inst": "ldsminal Ws, Wd, [Xn|SP]" , "op": "10111000|111|Rs|0|10100|Rn|Rd"}, {"inst": "ldsminl Ws, Wd, [Xn|SP]" , "op": "10111000|011|Rs|0|10100|Rn|Rd"}, {"inst": "ldsmin Xs, Xd, [Xn|SP]" , "op": "11111000|001|Rs|0|10100|Rn|Rd"}, {"inst": "ldsmina Xs, Xd, [Xn|SP]" , "op": "11111000|101|Rs|0|10100|Rn|Rd"}, {"inst": "ldsminal Xs, Xd, [Xn|SP]" , "op": "11111000|111|Rs|0|10100|Rn|Rd"}, {"inst": "ldsminl Xs, Xd, [Xn|SP]" , "op": "11111000|011|Rs|0|10100|Rn|Rd"}, {"inst": "ldsminb Ws, Wd, [Xn|SP]" , "op": "00111000|001|Rs|0|10100|Rn|Rd"}, {"inst": "ldsminab Ws, Wd, [Xn|SP]" , "op": "00111000|101|Rs|0|10100|Rn|Rd"}, {"inst": "ldsminalb Ws, Wd, [Xn|SP]" , "op": "00111000|111|Rs|0|10100|Rn|Rd"}, {"inst": "ldsminlb Ws, Wd, [Xn|SP]" , "op": "00111000|011|Rs|0|10100|Rn|Rd"}, {"inst": "ldsminh Ws, Wd, [Xn|SP]" , "op": "01111000|001|Rs|0|10100|Rn|Rd"}, {"inst": "ldsminah Ws, Wd, [Xn|SP]" , "op": "01111000|101|Rs|0|10100|Rn|Rd"}, {"inst": "ldsminalh Ws, Wd, [Xn|SP]" , "op": "01111000|111|Rs|0|10100|Rn|Rd"}, {"inst": "ldsminlh Ws, Wd, [Xn|SP]" , "op": "01111000|011|Rs|0|10100|Rn|Rd"}, {"inst": "ldumax Ws, Wd, [Xn|SP]" , "op": "10111000|001|Rs|0|11000|Rn|Rd"}, {"inst": "ldumaxa Ws, Wd, [Xn|SP]" , "op": "10111000|101|Rs|0|11000|Rn|Rd"}, {"inst": "ldumaxal Ws, Wd, [Xn|SP]" , "op": "10111000|111|Rs|0|11000|Rn|Rd"}, {"inst": "ldumaxl Ws, Wd, [Xn|SP]" , "op": "10111000|011|Rs|0|11000|Rn|Rd"}, {"inst": "ldumax Xs, Xd, [Xn|SP]" , "op": "11111000|001|Rs|0|11000|Rn|Rd"}, {"inst": "ldumaxa Xs, Xd, [Xn|SP]" , "op": "11111000|101|Rs|0|11000|Rn|Rd"}, {"inst": "ldumaxal Xs, Xd, [Xn|SP]" , "op": "11111000|111|Rs|0|11000|Rn|Rd"}, {"inst": "ldumaxl Xs, Xd, [Xn|SP]" , "op": "11111000|011|Rs|0|11000|Rn|Rd"}, {"inst": "ldumaxb Ws, Wd, [Xn|SP]" , "op": "00111000|001|Rs|0|11000|Rn|Rd"}, {"inst": "ldumaxab Ws, Wd, [Xn|SP]" , "op": "00111000|101|Rs|0|11000|Rn|Rd"}, {"inst": "ldumaxalb Ws, Wd, [Xn|SP]" , "op": "00111000|111|Rs|0|11000|Rn|Rd"}, {"inst": "ldumaxlb Ws, Wd, [Xn|SP]" , "op": "00111000|011|Rs|0|11000|Rn|Rd"}, {"inst": "ldumaxh Ws, Wd, [Xn|SP]" , "op": "01111000|001|Rs|0|11000|Rn|Rd"}, {"inst": "ldumaxah Ws, Wd, [Xn|SP]" , "op": "01111000|101|Rs|0|11000|Rn|Rd"}, {"inst": "ldumaxalh Ws, Wd, [Xn|SP]" , "op": "01111000|111|Rs|0|11000|Rn|Rd"}, {"inst": "ldumaxlh Ws, Wd, [Xn|SP]" , "op": "01111000|011|Rs|0|11000|Rn|Rd"}, {"inst": "ldumin Ws, Wd, [Xn|SP]" , "op": "10111000|001|Rs|0|11100|Rn|Rd"}, {"inst": "ldumina Ws, Wd, [Xn|SP]" , "op": "10111000|101|Rs|0|11100|Rn|Rd"}, {"inst": "lduminal Ws, Wd, [Xn|SP]" , "op": "10111000|111|Rs|0|11100|Rn|Rd"}, {"inst": "lduminl Ws, Wd, [Xn|SP]" , "op": "10111000|011|Rs|0|11100|Rn|Rd"}, {"inst": "ldumin Xs, Xd, [Xn|SP]" , "op": "11111000|001|Rs|0|11100|Rn|Rd"}, {"inst": "ldumina Xs, Xd, [Xn|SP]" , "op": "11111000|101|Rs|0|11100|Rn|Rd"}, {"inst": "lduminal Xs, Xd, [Xn|SP]" , "op": "11111000|111|Rs|0|11100|Rn|Rd"}, {"inst": "lduminl Xs, Xd, [Xn|SP]" , "op": "11111000|011|Rs|0|11100|Rn|Rd"}, {"inst": "lduminb Ws, Wd, [Xn|SP]" , "op": "00111000|001|Rs|0|11100|Rn|Rd"}, {"inst": "lduminab Ws, Wd, [Xn|SP]" , "op": "00111000|101|Rs|0|11100|Rn|Rd"}, {"inst": "lduminalb Ws, Wd, [Xn|SP]" , "op": "00111000|111|Rs|0|11100|Rn|Rd"}, {"inst": "lduminlb Ws, Wd, [Xn|SP]" , "op": "00111000|011|Rs|0|11100|Rn|Rd"}, {"inst": "lduminh Ws, Wd, [Xn|SP]" , "op": "01111000|001|Rs|0|11100|Rn|Rd"}, {"inst": "lduminah Ws, Wd, [Xn|SP]" , "op": "01111000|101|Rs|0|11100|Rn|Rd"}, {"inst": "lduminalh Ws, Wd, [Xn|SP]" , "op": "01111000|111|Rs|0|11100|Rn|Rd"}, {"inst": "lduminlh Ws, Wd, [Xn|SP]" , "op": "01111000|011|Rs|0|11100|Rn|Rd"}, {"inst": "stadd Ws, [Xn|SP]" , "op": "10111000|001|Rs|0|00000|Rn|11111"}, {"inst": "stadda Ws, [Xn|SP]" , "op": "10111000|101|Rs|0|00000|Rn|11111"}, {"inst": "staddal Ws, [Xn|SP]" , "op": "10111000|111|Rs|0|00000|Rn|11111"}, {"inst": "staddl Ws, [Xn|SP]" , "op": "10111000|011|Rs|0|00000|Rn|11111"}, {"inst": "stadd Xs, [Xn|SP]" , "op": "11111000|001|Rs|0|00000|Rn|11111"}, {"inst": "stadda Xs, [Xn|SP]" , "op": "11111000|101|Rs|0|00000|Rn|11111"}, {"inst": "staddal Xs, [Xn|SP]" , "op": "11111000|111|Rs|0|00000|Rn|11111"}, {"inst": "staddl Xs, [Xn|SP]" , "op": "11111000|011|Rs|0|00000|Rn|11111"}, {"inst": "staddb Ws, [Xn|SP]" , "op": "00111000|001|Rs|0|00000|Rn|11111"}, {"inst": "staddab Ws, [Xn|SP]" , "op": "00111000|101|Rs|0|00000|Rn|11111"}, {"inst": "staddalb Ws, [Xn|SP]" , "op": "00111000|111|Rs|0|00000|Rn|11111"}, {"inst": "staddlb Ws, [Xn|SP]" , "op": "00111000|011|Rs|0|00000|Rn|11111"}, {"inst": "staddh Ws, [Xn|SP]" , "op": "01111000|001|Rs|0|00000|Rn|11111"}, {"inst": "staddah Ws, [Xn|SP]" , "op": "01111000|101|Rs|0|00000|Rn|11111"}, {"inst": "staddalh Ws, [Xn|SP]" , "op": "01111000|111|Rs|0|00000|Rn|11111"}, {"inst": "staddlh Ws, [Xn|SP]" , "op": "01111000|011|Rs|0|00000|Rn|11111"}, {"inst": "stclr Ws, [Xn|SP]" , "op": "10111000|001|Rs|0|00100|Rn|11111"}, {"inst": "stclra Ws, [Xn|SP]" , "op": "10111000|101|Rs|0|00100|Rn|11111"}, {"inst": "stclral Ws, [Xn|SP]" , "op": "10111000|111|Rs|0|00100|Rn|11111"}, {"inst": "stclrl Ws, [Xn|SP]" , "op": "10111000|011|Rs|0|00100|Rn|11111"}, {"inst": "stclr Xs, [Xn|SP]" , "op": "11111000|001|Rs|0|00100|Rn|11111"}, {"inst": "stclra Xs, [Xn|SP]" , "op": "11111000|101|Rs|0|00100|Rn|11111"}, {"inst": "stclral Xs, [Xn|SP]" , "op": "11111000|111|Rs|0|00100|Rn|11111"}, {"inst": "stclrl Xs, [Xn|SP]" , "op": "11111000|011|Rs|0|00100|Rn|11111"}, {"inst": "stclrb Ws, [Xn|SP]" , "op": "00111000|001|Rs|0|00100|Rn|11111"}, {"inst": "stclrab Ws, [Xn|SP]" , "op": "00111000|101|Rs|0|00100|Rn|11111"}, {"inst": "stclralb Ws, [Xn|SP]" , "op": "00111000|111|Rs|0|00100|Rn|11111"}, {"inst": "stclrlb Ws, [Xn|SP]" , "op": "00111000|011|Rs|0|00100|Rn|11111"}, {"inst": "stclrh Ws, [Xn|SP]" , "op": "01111000|001|Rs|0|00100|Rn|11111"}, {"inst": "stclrah Ws, [Xn|SP]" , "op": "01111000|101|Rs|0|00100|Rn|11111"}, {"inst": "stclralh Ws, [Xn|SP]" , "op": "01111000|111|Rs|0|00100|Rn|11111"}, {"inst": "stclrlh Ws, [Xn|SP]" , "op": "01111000|011|Rs|0|00100|Rn|11111"}, {"inst": "steor Ws, [Xn|SP]" , "op": "10111000|001|Rs|0|01000|Rn|11111"}, {"inst": "steora Ws, [Xn|SP]" , "op": "10111000|101|Rs|0|01000|Rn|11111"}, {"inst": "steoral Ws, [Xn|SP]" , "op": "10111000|111|Rs|0|01000|Rn|11111"}, {"inst": "steorl Ws, [Xn|SP]" , "op": "10111000|011|Rs|0|01000|Rn|11111"}, {"inst": "steor Xs, [Xn|SP]" , "op": "11111000|001|Rs|0|01000|Rn|11111"}, {"inst": "steora Xs, [Xn|SP]" , "op": "11111000|101|Rs|0|01000|Rn|11111"}, {"inst": "steoral Xs, [Xn|SP]" , "op": "11111000|111|Rs|0|01000|Rn|11111"}, {"inst": "steorl Xs, [Xn|SP]" , "op": "11111000|011|Rs|0|01000|Rn|11111"}, {"inst": "steorb Ws, [Xn|SP]" , "op": "00111000|001|Rs|0|01000|Rn|11111"}, {"inst": "steorab Ws, [Xn|SP]" , "op": "00111000|101|Rs|0|01000|Rn|11111"}, {"inst": "steoralb Ws, [Xn|SP]" , "op": "00111000|111|Rs|0|01000|Rn|11111"}, {"inst": "steorlb Ws, [Xn|SP]" , "op": "00111000|011|Rs|0|01000|Rn|11111"}, {"inst": "steorh Ws, [Xn|SP]" , "op": "01111000|001|Rs|0|01000|Rn|11111"}, {"inst": "steorah Ws, [Xn|SP]" , "op": "01111000|101|Rs|0|01000|Rn|11111"}, {"inst": "steoralh Ws, [Xn|SP]" , "op": "01111000|111|Rs|0|01000|Rn|11111"}, {"inst": "steorlh Ws, [Xn|SP]" , "op": "01111000|011|Rs|0|01000|Rn|11111"}, {"inst": "stset Ws, [Xn|SP]" , "op": "10111000|001|Rs|0|01100|Rn|11111"}, {"inst": "stseta Ws, [Xn|SP]" , "op": "10111000|101|Rs|0|01100|Rn|11111"}, {"inst": "stsetal Ws, [Xn|SP]" , "op": "10111000|111|Rs|0|01100|Rn|11111"}, {"inst": "stsetl Ws, [Xn|SP]" , "op": "10111000|011|Rs|0|01100|Rn|11111"}, {"inst": "stset Xs, [Xn|SP]" , "op": "11111000|001|Rs|0|01100|Rn|11111"}, {"inst": "stseta Xs, [Xn|SP]" , "op": "11111000|101|Rs|0|01100|Rn|11111"}, {"inst": "stsetal Xs, [Xn|SP]" , "op": "11111000|111|Rs|0|01100|Rn|11111"}, {"inst": "stsetl Xs, [Xn|SP]" , "op": "11111000|011|Rs|0|01100|Rn|11111"}, {"inst": "stsetb Ws, [Xn|SP]" , "op": "00111000|001|Rs|0|01100|Rn|11111"}, {"inst": "stsetab Ws, [Xn|SP]" , "op": "00111000|101|Rs|0|01100|Rn|11111"}, {"inst": "stsetalb Ws, [Xn|SP]" , "op": "00111000|111|Rs|0|01100|Rn|11111"}, {"inst": "stsetlb Ws, [Xn|SP]" , "op": "00111000|011|Rs|0|01100|Rn|11111"}, {"inst": "stseth Ws, [Xn|SP]" , "op": "01111000|001|Rs|0|01100|Rn|11111"}, {"inst": "stsetah Ws, [Xn|SP]" , "op": "01111000|101|Rs|0|01100|Rn|11111"}, {"inst": "stsetalh Ws, [Xn|SP]" , "op": "01111000|111|Rs|0|01100|Rn|11111"}, {"inst": "stsetlh Ws, [Xn|SP]" , "op": "01111000|011|Rs|0|01100|Rn|11111"}, {"inst": "stsmax Ws, [Xn|SP]" , "op": "10111000|001|Rs|0|10000|Rn|11111"}, {"inst": "stsmaxa Ws, [Xn|SP]" , "op": "10111000|101|Rs|0|10000|Rn|11111"}, {"inst": "stsmaxal Ws, [Xn|SP]" , "op": "10111000|111|Rs|0|10000|Rn|11111"}, {"inst": "stsmaxl Ws, [Xn|SP]" , "op": "10111000|011|Rs|0|10000|Rn|11111"}, {"inst": "stsmax Xs, [Xn|SP]" , "op": "11111000|001|Rs|0|10000|Rn|11111"}, {"inst": "stsmaxa Xs, [Xn|SP]" , "op": "11111000|101|Rs|0|10000|Rn|11111"}, {"inst": "stsmaxal Xs, [Xn|SP]" , "op": "11111000|111|Rs|0|10000|Rn|11111"}, {"inst": "stsmaxl Xs, [Xn|SP]" , "op": "11111000|011|Rs|0|10000|Rn|11111"}, {"inst": "stsmaxb Ws, [Xn|SP]" , "op": "00111000|001|Rs|0|10000|Rn|11111"}, {"inst": "stsmaxab Ws, [Xn|SP]" , "op": "00111000|101|Rs|0|10000|Rn|11111"}, {"inst": "stsmaxalb Ws, [Xn|SP]" , "op": "00111000|111|Rs|0|10000|Rn|11111"}, {"inst": "stsmaxlb Ws, [Xn|SP]" , "op": "00111000|011|Rs|0|10000|Rn|11111"}, {"inst": "stsmaxh Ws, [Xn|SP]" , "op": "01111000|001|Rs|0|10000|Rn|11111"}, {"inst": "stsmaxah Ws, [Xn|SP]" , "op": "01111000|101|Rs|0|10000|Rn|11111"}, {"inst": "stsmaxalh Ws, [Xn|SP]" , "op": "01111000|111|Rs|0|10000|Rn|11111"}, {"inst": "stsmaxlh Ws, [Xn|SP]" , "op": "01111000|011|Rs|0|10000|Rn|11111"}, {"inst": "stsmin Ws, [Xn|SP]" , "op": "10111000|001|Rs|0|10100|Rn|11111"}, {"inst": "stsmina Ws, [Xn|SP]" , "op": "10111000|101|Rs|0|10100|Rn|11111"}, {"inst": "stsminal Ws, [Xn|SP]" , "op": "10111000|111|Rs|0|10100|Rn|11111"}, {"inst": "stsminl Ws, [Xn|SP]" , "op": "10111000|011|Rs|0|10100|Rn|11111"}, {"inst": "stsmin Xs, [Xn|SP]" , "op": "11111000|001|Rs|0|10100|Rn|11111"}, {"inst": "stsmina Xs, [Xn|SP]" , "op": "11111000|101|Rs|0|10100|Rn|11111"}, {"inst": "stsminal Xs, [Xn|SP]" , "op": "11111000|111|Rs|0|10100|Rn|11111"}, {"inst": "stsminl Xs, [Xn|SP]" , "op": "11111000|011|Rs|0|10100|Rn|11111"}, {"inst": "stsminb Ws, [Xn|SP]" , "op": "00111000|001|Rs|0|10100|Rn|11111"}, {"inst": "stsminab Ws, [Xn|SP]" , "op": "00111000|101|Rs|0|10100|Rn|11111"}, {"inst": "stsminalb Ws, [Xn|SP]" , "op": "00111000|111|Rs|0|10100|Rn|11111"}, {"inst": "stsminlb Ws, [Xn|SP]" , "op": "00111000|011|Rs|0|10100|Rn|11111"}, {"inst": "stsminh Ws, [Xn|SP]" , "op": "01111000|001|Rs|0|10100|Rn|11111"}, {"inst": "stsminah Ws, [Xn|SP]" , "op": "01111000|101|Rs|0|10100|Rn|11111"}, {"inst": "stsminalh Ws, [Xn|SP]" , "op": "01111000|111|Rs|0|10100|Rn|11111"}, {"inst": "stsminlh Ws, [Xn|SP]" , "op": "01111000|011|Rs|0|10100|Rn|11111"}, {"inst": "stumax Ws, [Xn|SP]" , "op": "10111000|001|Rs|0|11000|Rn|11111"}, {"inst": "stumaxa Ws, [Xn|SP]" , "op": "10111000|101|Rs|0|11000|Rn|11111"}, {"inst": "stumaxal Ws, [Xn|SP]" , "op": "10111000|111|Rs|0|11000|Rn|11111"}, {"inst": "stumaxl Ws, [Xn|SP]" , "op": "10111000|011|Rs|0|11000|Rn|11111"}, {"inst": "stumax Xs, [Xn|SP]" , "op": "11111000|001|Rs|0|11000|Rn|11111"}, {"inst": "stumaxa Xs, [Xn|SP]" , "op": "11111000|101|Rs|0|11000|Rn|11111"}, {"inst": "stumaxal Xs, [Xn|SP]" , "op": "11111000|111|Rs|0|11000|Rn|11111"}, {"inst": "stumaxl Xs, [Xn|SP]" , "op": "11111000|011|Rs|0|11000|Rn|11111"}, {"inst": "stumaxb Ws, [Xn|SP]" , "op": "00111000|001|Rs|0|11000|Rn|11111"}, {"inst": "stumaxab Ws, [Xn|SP]" , "op": "00111000|101|Rs|0|11000|Rn|11111"}, {"inst": "stumaxalb Ws, [Xn|SP]" , "op": "00111000|111|Rs|0|11000|Rn|11111"}, {"inst": "stumaxlb Ws, [Xn|SP]" , "op": "00111000|011|Rs|0|11000|Rn|11111"}, {"inst": "stumaxh Ws, [Xn|SP]" , "op": "01111000|001|Rs|0|11000|Rn|11111"}, {"inst": "stumaxah Ws, [Xn|SP]" , "op": "01111000|101|Rs|0|11000|Rn|11111"}, {"inst": "stumaxalh Ws, [Xn|SP]" , "op": "01111000|111|Rs|0|11000|Rn|11111"}, {"inst": "stumaxlh Ws, [Xn|SP]" , "op": "01111000|011|Rs|0|11000|Rn|11111"}, {"inst": "stumin Ws, [Xn|SP]" , "op": "10111000|001|Rs|0|11100|Rn|11111"}, {"inst": "stumina Ws, [Xn|SP]" , "op": "10111000|101|Rs|0|11100|Rn|11111"}, {"inst": "stuminal Ws, [Xn|SP]" , "op": "10111000|111|Rs|0|11100|Rn|11111"}, {"inst": "stuminl Ws, [Xn|SP]" , "op": "10111000|011|Rs|0|11100|Rn|11111"}, {"inst": "stumin Xs, [Xn|SP]" , "op": "11111000|001|Rs|0|11100|Rn|11111"}, {"inst": "stumina Xs, [Xn|SP]" , "op": "11111000|101|Rs|0|11100|Rn|11111"}, {"inst": "stuminal Xs, [Xn|SP]" , "op": "11111000|111|Rs|0|11100|Rn|11111"}, {"inst": "stuminl Xs, [Xn|SP]" , "op": "11111000|011|Rs|0|11100|Rn|11111"}, {"inst": "stuminb Ws, [Xn|SP]" , "op": "00111000|001|Rs|0|11100|Rn|11111"}, {"inst": "stuminab Ws, [Xn|SP]" , "op": "00111000|101|Rs|0|11100|Rn|11111"}, {"inst": "stuminalb Ws, [Xn|SP]" , "op": "00111000|111|Rs|0|11100|Rn|11111"}, {"inst": "stuminlb Ws, [Xn|SP]" , "op": "00111000|011|Rs|0|11100|Rn|11111"}, {"inst": "stuminh Ws, [Xn|SP]" , "op": "01111000|001|Rs|0|11100|Rn|11111"}, {"inst": "stuminah Ws, [Xn|SP]" , "op": "01111000|101|Rs|0|11100|Rn|11111"}, {"inst": "stuminalh Ws, [Xn|SP]" , "op": "01111000|111|Rs|0|11100|Rn|11111"}, {"inst": "stuminlh Ws, [Xn|SP]" , "op": "01111000|011|Rs|0|11100|Rn|11111"}, {"inst": "swp Ws, Wd, [Xn|SP]" , "op": "10111000|001|Rs|1|00000|Rn|Rd"}, {"inst": "swpa Ws, Wd, [Xn|SP]" , "op": "10111000|101|Rs|1|00000|Rn|Rd"}, {"inst": "swpal Ws, Wd, [Xn|SP]" , "op": "10111000|111|Rs|1|00000|Rn|Rd"}, {"inst": "swpl Ws, Wd, [Xn|SP]" , "op": "10111000|011|Rs|1|00000|Rn|Rd"}, {"inst": "swp Xs, Xd, [Xn|SP]" , "op": "11111000|001|Rs|1|00000|Rn|Rd"}, {"inst": "swpa Xs, Xd, [Xn|SP]" , "op": "11111000|101|Rs|1|00000|Rn|Rd"}, {"inst": "swpal Xs, Xd, [Xn|SP]" , "op": "11111000|111|Rs|1|00000|Rn|Rd"}, {"inst": "swpl Xs, Xd, [Xn|SP]" , "op": "11111000|011|Rs|1|00000|Rn|Rd"}, {"inst": "swpb Ws, Wd, [Xn|SP]" , "op": "00111000|001|Rs|1|00000|Rn|Rd"}, {"inst": "swpab Ws, Wd, [Xn|SP]" , "op": "00111000|101|Rs|1|00000|Rn|Rd"}, {"inst": "swpalb Ws, Wd, [Xn|SP]" , "op": "00111000|111|Rs|1|00000|Rn|Rd"}, {"inst": "swplb Ws, Wd, [Xn|SP]" , "op": "00111000|011|Rs|1|00000|Rn|Rd"}, {"inst": "swph Ws, Wd, [Xn|SP]" , "op": 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Xn" , "op": "11010110|000|11111|0000|10|Rn|11111" , "control": "call"}, {"inst": "brab Xn, Xm|SP" , "op": "11010111|000|11111|0000|11|Rn|Rm" , "control": "call"}, {"inst": "brabz Xn" , "op": "11010110|000|11111|0000|11|Rn|11111" , "control": "call"}, {"inst": "eretaa" , "op": "11010110|100|11111|0000|10|11111|11111" , "control": "return"}, {"inst": "eretab" , "op": "11010110|100|11111|0000|11|11111|11111" , "control": "return"}, {"inst": "ldraa Xd, [Xn|SP, #soff]{!}" , "op": "11111000|0|soff:1|1|soff:9|W1|Rn|Rd"}, {"inst": "ldrab Xd, [Xn|SP, #soff]{!}" , "op": "11111000|1|soff:1|1|soff:9|W1|Rn|Rd"}, {"inst": "pacda Xd, Xn|SP" , "op": "11011010|110|00001|0|00010|Rn|Rd"}, {"inst": "pacdb Xd, Xn|SP" , "op": "11011010|110|00001|0|00011|Rn|Rd"}, {"inst": "pacdza Xd" , "op": "11011010|110|00001|0|01010|11111|Rd"}, {"inst": "pacdzb Xd" , "op": "11011010|110|00001|0|01011|11111|Rd"}, {"inst": "pacga Xd, Xn, Xm|SP" , "op": "10011010|110|Rm|0|01100|Rn|Rd"}, {"inst": "pacia Xd, Xn|SP" , "op": "11011010|110|00001|0|00000|Rn|Rd"}, {"inst": "pacia1716" , "op": "11010101|000|00011|0010|0001|000|11111"}, {"inst": "paciasp" , "op": "11010101|000|00011|0010|0011|001|11111"}, {"inst": "paciaz" , "op": "11010101|000|00011|0010|0011|000|11111"}, {"inst": "pacib Xd, Xn|SP" , "op": "11011010|110|00001|0|00001|Rn|Rd"}, {"inst": "pacib1716" , "op": "11010101|000|00011|0010|0001|010|11111"}, {"inst": "pacibsp" , "op": "11010101|000|00011|0010|0011|011|11111"}, {"inst": "pacibz" , "op": "11010101|000|00011|0010|0011|010|11111"}, {"inst": "paciza Xd" , "op": "11011010|110|00001|0|01000|11111|Rd"}, {"inst": "pacizb Xd" , "op": "11011010|110|00001|0|01001|11111|Rd"}, {"inst": "retaa" , "op": "11010110|010|11111|0|00010|11111|11111" , "control": "return"}, {"inst": "retab" , "op": "11010110|010|11111|0|00011|11111|11111" , "control": "return"}, {"inst": "xpacd Xd" , "op": "11011010|110|00001|0|10001|11111|Rd"}, {"inst": "xpaci Xd" , "op": "11011010|110|00001|0|10000|11111|Rd"}, {"inst": "xpaclri Xd" , "op": "11010101|000|00011|0|01000|00111|11111"} ]}, {"category": "GP GP_EXT", "ext": "RAS", "data": [ {"inst": "esb" , "op": "11010101|000|00011|0010|0010|000|11111"} ]}, {"category": "GP GP_EXT", "ext": "RPRFM", "data": [ {"inst": "rprfm #rprf_op, Xm, [Xn|SP]" , "op": "11111000|101|Rm|imm:1|1|imm:2|10|Rn|11|imm:3" , "imm": "ImmRPRF(rprf_op)"} ]}, {"category": "GP GP_EXT", "ext": "SB", "data": [ {"inst": "sb" , "op": "11010101|000|00011|0011|0000|111|11111"} ]}, {"category": "GP GP_EXT", "ext": "SPE", "data": [ {"inst": "psb #psb_tsb_op" , "op": "11010101|000|00011|0010|0010|001|11111" , "imm": "ImmPSB_TSB(psb_tsb_op)"} ]}, {"category": "GP GP_EXT", "ext": "SPECRES", "data": [ {"inst": "cfp #rctx, Xt" , "op": "11010101|000|01011|0111|0011|100|Rt" , "imm": "ImmRCTX(rctx)"}, {"inst": "cpp #rctx, Xt" , "op": "11010101|000|01011|0111|0011|111|Rt" , "imm": "ImmRCTX(rctx)"}, {"inst": "dvp #rctx, Xt" , "op": "11010101|000|01|011|0111|0011|101|Rt" , "imm": "ImmRCTX(rctx)"} ]}, {"category": "GP GP_EXT", "ext": "SPECRES2", "data": [ {"inst": "cosp #rctx, Xt" , "op": "11010101|000|01011|0111|0011|110|Rt" , "imm": "ImmRCTX(rctx)"} ]}, {"category": "GP GP_EXT", "ext": "SYSINSTR128", "data": [ {"inst": "sysp #op1, #CRn, #CRm, #op2, 2x{Xt}+" , "op": "11010101|010|01|op1:3|CRn|CRm|op2:3|Rt"} ]}, {"category": "GP GP_EXT", "ext": "SYSREG128", "data": [ {"inst": "mrrs 2x{Xd}+, #sysreg" , "op": "11010101|011|1|sysreg:15|Rd"}, {"inst": "msrr 2x{Xs}+, #sysreg" , "op": "11010101|010|1|sysreg:15|Rd"} ]}, {"category": "GP GP_EXT", "ext": "THE", "data": [ {"inst": "rcwcas Xs, Xt, [Xn|SP]" , "op": "00011001|001|Rs|0|00010|Rn|Rt" , "io": "N=W Z=W C=W V=W"}, {"inst": "rcwcasa Xs, Xt, [Xn|SP]" , "op": "00011001|101|Rs|0|00010|Rn|Rt" , "io": "N=W Z=W C=W V=W"}, {"inst": "rcwcasal Xs, Xt, [Xn|SP]" , "op": "00011001|111|Rs|0|00010|Rn|Rt" , "io": "N=W Z=W C=W V=W"}, {"inst": "rcwcasl Xs, Xt, [Xn|SP]" , "op": "00011001|011|Rs|0|00010|Rn|Rt" , "io": "N=W Z=W C=W V=W"}, {"inst": "rcwcasp 2x{Xs}+, 2x{Xt}+, [Xn|SP]" , "op": "00011001|001|Rs|0|00011|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"}, {"inst": "rcwcaspa 2x{Xs}+, 2x{Xt}+, [Xn|SP]" , "op": "00011001|101|Rs|0|00011|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"}, {"inst": "rcwcaspal 2x{Xs}+, 2x{Xt}+, [Xn|SP]" , "op": "00011001|111|Rs|0|00011|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"}, {"inst": "rcwcaspl 2x{Xs}+, 2x{Xt}+, [Xn|SP]" , "op": "00011001|011|Rs|0|00011|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"}, {"inst": "rcwclr Xs, Xt, [Xn|SP]" , "op": "00111000|001|Rs|1|00100|Rn|Rt" , "io": "N=W Z=W C=W V=W"}, {"inst": "rcwclra Xs, Xt, [Xn|SP]" , "op": "00111000|101|Rs|1|00100|Rn|Rt" , "io": "N=W Z=W C=W V=W"}, {"inst": "rcwclral Xs, Xt, [Xn|SP]" , "op": "00111000|111|Rs|1|00100|Rn|Rt" , "io": "N=W Z=W C=W V=W"}, {"inst": "rcwclrl Xs, Xt, [Xn|SP]" , "op": "00111000|011|Rs|1|00100|Rn|Rt" , "io": "N=W Z=W C=W V=W"}, {"inst": "rcwclrp Xt, Xt2, [Xn|SP]" , "op": "00011001|001|Rt2|1|00100|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"}, {"inst": "rcwclrpa Xt, Xt2, [Xn|SP]" , "op": "00011001|101|Rt2|1|00100|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"}, {"inst": "rcwclrpal Xt, Xt2, [Xn|SP]" , "op": "00011001|111|Rt2|1|00100|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"}, {"inst": "rcwclrpl Xt, Xt2, [Xn|SP]" , "op": "00011001|011|Rt2|1|00100|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"}, {"inst": "rcwscas Xs, Xt, [Xn|SP]" , "op": "01011001|001|Rs|0|00010|Rn|Rt" , "io": "N=W Z=W C=W V=W"}, {"inst": "rcwscasa Xs, Xt, [Xn|SP]" , "op": "01011001|101|Rs|0|00010|Rn|Rt" , "io": "N=W Z=W C=W V=W"}, {"inst": "rcwscasal Xs, Xt, [Xn|SP]" , "op": "01011001|111|Rs|0|00010|Rn|Rt" , "io": "N=W Z=W C=W V=W"}, {"inst": "rcwscasl Xs, Xt, [Xn|SP]" , "op": "01011001|011|Rs|0|00010|Rn|Rt" , "io": "N=W Z=W C=W V=W"}, {"inst": "rcwscasp 2x{Xs}+, 2x{Xt}+, [Xn|SP]" , "op": "01011001|001|Rs|0|00011|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"}, {"inst": "rcwscaspa 2x{Xs}+, 2x{Xt}+, [Xn|SP]" , "op": "01011001|101|Rs|0|00011|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"}, {"inst": "rcwscaspal 2x{Xs}+, 2x{Xt}+, [Xn|SP]" , "op": "01011001|111|Rs|0|00011|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"}, {"inst": "rcwscaspl 2x{Xs}+, 2x{Xt}+, [Xn|SP]" , "op": "01011001|011|Rs|0|00011|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"}, {"inst": "rcwsclr Xs, Xt, [Xn|SP]" , "op": "01111000|001|Rs|1|00100|Rn|Rt" , "io": "N=W Z=W C=W V=W"}, {"inst": "rcwsclra Xs, Xt, [Xn|SP]" , "op": "01111000|101|Rs|1|00100|Rn|Rt" , "io": "N=W Z=W C=W V=W"}, {"inst": "rcwsclral Xs, Xt, [Xn|SP]" , "op": "01111000|111|Rs|1|00100|Rn|Rt" , "io": "N=W Z=W C=W V=W"}, {"inst": "rcwsclrl Xs, Xt, [Xn|SP]" , "op": "01111000|011|Rs|1|00100|Rn|Rt" , "io": "N=W Z=W C=W V=W"}, {"inst": "rcwsclrp Xt, Xt2, [Xn|SP]" , "op": "01011001|001|Rt2|1|00100|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"}, {"inst": "rcwsclrpa Xt, Xt2, [Xn|SP]" , "op": "01011001|101|Rt2|1|00100|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"}, {"inst": "rcwsclrpal Xt, Xt2, [Xn|SP]" , "op": "01011001|111|Rt2|1|00100|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"}, {"inst": "rcwsclrpl Xt, Xt2, [Xn|SP]" , "op": "01011001|011|Rt2|1|00100|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"}, {"inst": "rcwset Xs, Xt, [Xn|SP]" , "op": "00111000|001|Rs|1|01100|Rn|Rt" , "io": "N=W Z=W C=W V=W"}, {"inst": "rcwseta Xs, Xt, [Xn|SP]" , "op": "00111000|101|Rs|1|01100|Rn|Rt" , "io": "N=W Z=W C=W V=W"}, {"inst": "rcwsetal Xs, Xt, [Xn|SP]" , "op": "00111000|111|Rs|1|01100|Rn|Rt" , "io": "N=W Z=W C=W V=W"}, {"inst": "rcwsetl Xs, Xt, [Xn|SP]" , "op": "00111000|011|Rs|1|01100|Rn|Rt" , "io": "N=W Z=W C=W V=W"}, {"inst": "rcwsetp Xt, Xt2, [Xn|SP]" , "op": "00011001|001|Rt2|1|01100|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"}, {"inst": "rcwsetpa Xt, Xt2, [Xn|SP]" , "op": "00011001|101|Rt2|1|01100|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"}, {"inst": "rcwsetpal Xt, Xt2, [Xn|SP]" , "op": "00011001|111|Rt2|1|01100|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"}, {"inst": "rcwsetpl Xt, Xt2, [Xn|SP]" , "op": "00011001|011|Rt2|1|01100|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"}, {"inst": "rcwsset Xs, Xt, [Xn|SP]" , "op": "01111000|001|Rs|1|01100|Rn|Rt" , "io": "N=W Z=W C=W V=W"}, {"inst": "rcwsseta Xs, Xt, [Xn|SP]" , "op": "01111000|101|Rs|1|01100|Rn|Rt" , "io": "N=W Z=W C=W V=W"}, {"inst": "rcwssetal Xs, Xt, [Xn|SP]" , "op": "01111000|111|Rs|1|01100|Rn|Rt" , "io": "N=W Z=W C=W V=W"}, {"inst": "rcwssetl Xs, Xt, [Xn|SP]" , "op": "01111000|011|Rs|1|01100|Rn|Rt" , "io": "N=W Z=W C=W V=W"}, {"inst": "rcwssetp Xt, Xt2, [Xn|SP]" , "op": "01011001|001|Rt2|1|01100|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"}, {"inst": "rcwssetpa Xt, Xt2, [Xn|SP]" , "op": "01011001|101|Rt2|1|01100|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"}, {"inst": "rcwssetpal Xt, Xt2, [Xn|SP]" , "op": "01011001|111|Rt2|1|01100|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"}, {"inst": "rcwssetpl Xt, Xt2, [Xn|SP]" , "op": "01011001|011|Rt2|1|01100|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"}, {"inst": "rcwsswp Xs, Xt, [Xn|SP]" , "op": "01111000|001|Rs|1|01000|Rn|Rt" , "io": "N=W Z=W C=W V=W"}, {"inst": "rcwsswpa Xs, Xt, [Xn|SP]" , "op": "01111000|101|Rs|1|01000|Rn|Rt" , "io": "N=W Z=W C=W V=W"}, {"inst": "rcwsswpal Xs, Xt, [Xn|SP]" , "op": "01111000|111|Rs|1|01000|Rn|Rt" , "io": "N=W Z=W C=W V=W"}, {"inst": "rcwsswpl Xs, Xt, [Xn|SP]" , "op": "01111000|011|Rs|1|01000|Rn|Rt" , "io": "N=W Z=W C=W V=W"}, {"inst": "rcwsswpp Xt, Xt2, [Xn|SP]" , "op": "01011001|001|Rt2|1|01000|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"}, {"inst": "rcwsswppa Xt, Xt2, [Xn|SP]" , "op": "01011001|101|Rt2|1|01000|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"}, {"inst": "rcwsswppal Xt, Xt2, [Xn|SP]" , "op": "01011001|111|Rt2|1|01000|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"}, {"inst": "rcwsswppl Xt, Xt2, [Xn|SP]" , "op": "01011001|011|Rt2|1|01000|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"}, {"inst": "rcwswp Xs, Xt, [Xn|SP]" , "op": "00111000|001|Rs|1|01000|Rn|Rt" , "io": "N=W Z=W C=W V=W"}, {"inst": "rcwswpa Xs, Xt, [Xn|SP]" , "op": "00111000|101|Rs|1|01000|Rn|Rt" , "io": "N=W Z=W C=W V=W"}, {"inst": "rcwswpal Xs, Xt, [Xn|SP]" , "op": "00111000|111|Rs|1|01000|Rn|Rt" , "io": "N=W Z=W C=W V=W"}, {"inst": "rcwswpl Xs, Xt, [Xn|SP]" , "op": "00111000|011|Rs|1|01000|Rn|Rt" , "io": "N=W Z=W C=W V=W"}, {"inst": "rcwswpp Xt, Xt2, [Xn|SP]" , "op": "00011001|001|Rt2|1|01000|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"}, {"inst": "rcwswppa Xt, Xt2, [Xn|SP]" , "op": "00011001|101|Rt2|1|01000|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"}, {"inst": "rcwswppal Xt, Xt2, [Xn|SP]" , "op": "00011001|111|Rt2|1|01000|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"}, {"inst": "rcwswppl Xt, Xt2, [Xn|SP]" , "op": "00011001|011|Rt2|1|01000|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"} ]}, {"category": "GP GP_EXT", "ext": "TME", "data": [ {"inst": "tcancel #imm" , "op": "11010100|011|imm:16|00000"}, {"inst": "tcommit" , "op": "11010101|000|00011|0011|0000|011|11111"}, {"inst": "tstart Xt" , "op": "11010101|001|00011|0011|0000|011|Rt"}, {"inst": "ttest Xd" , "op": "11010101|001|00011|0011|0001|011|Rd"} ]}, {"category": "GP GP_EXT", "ext": "TRF", "data": [ {"inst": "tsb #psb_tsb_op" , "op": "11010101|000|00011|0010|0010|010|11111" , "imm": "ImmPSB_TSB(psb_tsb_op)"} ]}, {"category": "GP GP_EXT", "ext": "WFXT", "data": [ {"inst": "wfet Xs" , "op": "11010101|000|00011|0001|0000|000|Rs"}, {"inst": "wfit Xs" , "op": "11010101|000|00011|0001|0000|001|Rs"} ]}, {"category": "ASIMD", "ext": "ASIMD", "data": [ {"inst": "abs Dd, Dn" , "op": "01011110|11|10000|01011|10|Vn|Vd"}, {"inst": "abs Vd.t, Vn.t" , "op": "00001110|sz|10000|01011|10|Vn|Vd" , "t": "8B 4H 2S"}, {"inst": "abs Vd.t, Vn.t" , "op": "01001110|sz|10000|01011|10|Vn|Vd" , "t": "16B 8H 4S 2D"}, {"inst": "add Dd, Dn, Dm" , "op": "01011110|11|1|Vm|10000|1|Vn|Vd"}, {"inst": "add Vd.t, Vn.t, Vm.t" , "op": "00001110|sz|1|Vm|10000|1|Vn|Vd" , "t": "8B 4H 2S"}, {"inst": "add Vd.t, Vn.t, Vm.t" , "op": "01001110|sz|1|Vm|10000|1|Vn|Vd" , "t": "16B 8H 4S 2D"}, {"inst": "addhn Vd.ta, Vn.tb, Vm.tb" , "op": "00001110|sz|1|Vm|01000|0|Vn|Vd" , "ta.tb": "8B.8H 4H.4S 2S.2D"}, {"inst": "addhn2 Vx.ta, Vn.tb, Vm.tb" , "op": "01001110|sz|1|Vm|01000|0|Vn|Vx" , "ta.tb": "16B.8H 8H.4S 4S.2D"}, {"inst": "addp Dd, Vn.2D" , "op": "01011110|sz|11000|11011|10|Vn|Vd"}, {"inst": "addp Vd.t, Vn.t, Vm.t" , "op": "00001110|sz|1|Vm|10111|1|Vn|Vd" , "t": "8B 4H 2S"}, {"inst": "addp Vd.t, Vn.t, Vm.t" , "op": "01001110|sz|1|Vm|10111|1|Vn|Vd" , "t": "16B 8H 4S 2D"}, {"inst": "addv Bd, Vn.8B" , "op": "00001110|00|11000|11011|10|Vn|Vd"}, {"inst": "addv Bd, Vn.16B" , "op": "01001110|00|11000|11011|10|Vn|Vd"}, {"inst": "addv Hd, Vn.4H" , "op": "00001110|01|11000|11011|10|Vn|Vd"}, {"inst": "addv Hd, Vn.8H" , "op": "01001110|01|11000|11011|10|Vn|Vd"}, {"inst": "addv Sd, Vn.4S" , "op": "01001110|10|11000|11011|10|Vn|Vd"}, {"inst": "and Vd.8B, Vn.8B, Vm.8B" , "op": "00001110|00|1|Vm|00011|1|Vn|Vd"}, {"inst": "and Vd.16B, Vn.16B, Vm.16B" , "op": "01001110|00|1|Vm|00011|1|Vn|Vd"}, {"inst": "bic Vd.8B, Vn.8B, Vm.8B" , "op": "00001110|01|1|Vm|00011|1|Vn|Vd"}, {"inst": "bic Vd.16B, Vn.16B, Vm.16B" , "op": "01001110|01|1|Vm|00011|1|Vn|Vd"}, {"inst": "bic Vd.t, #imm, {lsl #n}" , "op": "00101111|00000|abc:3|cmode:4|01|defgh:5|Vd" , "t": "4H 2S", "imm": "ASimdLogicalImm(sz, 1, imm, lsl)"}, {"inst": "bic Vd.t, #imm, {lsl #n}" , "op": "01101111|00000|abc:3|cmode:4|01|defgh:5|Vd" , "t": "8H 4S", "imm": "ASimdLogicalImm(sz, 1, imm, lsl)"}, {"inst": "bif Dx.8B, Vn.8B, Vm.8B" , "op": "00101111|11|1|Vm|00011|1|Vn|Vx"}, {"inst": "bif Vx.16B, Vn.16B, Vm.16B" , "op": "01101111|11|1|Vm|00011|1|Vn|Vx"}, {"inst": "bit Dx.8B, Vn.8B, Vm.8B" , "op": "00101111|10|1|Vm|00011|1|Vn|Vx"}, {"inst": "bit Vx.16B, Vn.16B, Vm.16B" , "op": "01101111|10|1|Vm|00011|1|Vn|Vx"}, {"inst": "bsl Dx.8B, Vn.8B, Vm.8B" , "op": "00101111|01|1|Vm|00011|1|Vn|Vx"}, {"inst": "bsl Vx.16B, Vn.16B, Vm.16B" , "op": "01101111|01|1|Vm|00011|1|Vn|Vx"}, {"inst": "cls Vd.t, Vn.t" , "op": "00001110|sz|10000|00100|10|Vn|Vd" , "t": "8B 4H 2S"}, {"inst": "cls Vd.t, Vn.t" , "op": "01001110|sz|10000|00100|10|Vn|Vd" , "t": "16B 8H 4S"}, {"inst": "clz Vd.t, Vn.t" , "op": "00101110|sz|10000|00100|10|Vn|Vd" , "t": "8B 4H 2S"}, {"inst": "clz Vd.t, Vn.t" , "op": "01101110|sz|10000|00100|10|Vn|Vd" , "t": "16B 8H 4S"}, {"inst": "cmeq Dd, Dn, Dm" , "op": "01111110|11|1|Vm|10001|1|Vn|Vd"}, {"inst": "cmeq Dd, Dn, #0" , "op": "01011110|11|10000|01001|10|Vn|Vd"}, {"inst": "cmeq Vd.t, Vn.t, Vm.t" , "op": "00101110|sz|1|Vm|10001|1|Vn|Vd" , "t": "8B 4H 2S"}, {"inst": "cmeq Vd.t, Vn.t, #0" , "op": "00101110|sz|10000|01001|10|Vn|Vd" , "t": "8B 4H 2S"}, {"inst": "cmeq Vd.t, Vn.t, Vm.t" , "op": "01101110|sz|1|Vm|10001|1|Vn|Vd" , "t": "16B 8H 4S 2D"}, {"inst": "cmeq Vd.t, Vn.t, #0" , "op": "01101110|sz|10000|01001|10|Vn|Vd" , "t": "16B 8H 4S 2D"}, {"inst": "cmge Dd, Dn, Dm" , "op": "01011110|11|1|Vm|00111|1|Vn|Vd"}, {"inst": "cmge Dd, Dn, #0" , "op": "01111110|11|10000|01000|10|Vn|Vd"}, {"inst": "cmge Vd.t, Vn.t, Vm.t" , "op": "00001110|sz|1|Vm|00111|1|Vn|Vd" , "t": "8B 4H 2S"}, {"inst": "cmge Vd.t, Vn.t, #0" , "op": "00101110|sz|10000|01000|10|Vn|Vd" , "t": "8B 4H 2S"}, {"inst": "cmge Vd.t, Vn.t, Vm.t" , "op": "01001110|sz|1|Vm|00111|1|Vn|Vd" , "t": "16B 8H 4S 2D"}, {"inst": "cmge Vd.t, Vn.t, #0" , "op": "01101110|sz|10000|01000|10|Vn|Vd" , "t": "16B 8H 4S 2D"}, {"inst": "cmgt Dd, Dn, Dm" , "op": "01011110|11|1|Vm|00110|1|Vn|Vd"}, {"inst": "cmgt Dd, Dn, #0" , "op": "01011110|11|10000|01000|10|Vn|Vd"}, {"inst": "cmgt Vd.t, Vn.t, Vm.t" , "op": "00001110|sz|1|Vm|00110|1|Vn|Vd" , "t": "8B 4H 2S"}, {"inst": "cmgt Vd.t, Vn.t, #0" , "op": "00001110|sz|10000|01000|10|Vn|Vd" , "t": "8B 4H 2S"}, {"inst": "cmgt Vd.t, Vn.t, Vm.t" , "op": "01001110|sz|1|Vm|00110|1|Vn|Vd" , "t": "16B 8H 4S 2D"}, {"inst": "cmgt Vd.t, Vn.t, #0" , "op": "01001110|sz|10000|01000|10|Vn|Vd" , "t": "16B 8H 4S 2D"}, {"inst": "cmhi Dd, Dn, Dm" , "op": "01111110|11|1|Vm|00110|1|Vn|Vd"}, {"inst": "cmhi Vd.t, Vn.t, Vm.t" , "op": "00101110|sz|1|Vm|00110|1|Vn|Vd" , "t": "8B 4H 2S"}, {"inst": "cmhi Vd.t, Vn.t, Vm.t" , "op": "01101110|sz|1|Vm|00110|1|Vn|Vd" , "t": "16B 8H 4S 2D"}, {"inst": "cmhs Dd, Dn, Dm" , "op": "01111110|11|1|Vm|00111|1|Vn|Vd"}, {"inst": "cmhs Vd.t, Vn.t, Vm.t" , "op": "00101110|sz|1|Vm|00111|1|Vn|Vd" , "t": "8B 4H 2S"}, {"inst": "cmhs Vd.t, Vn.t, Vm.t" , "op": "01101110|sz|1|Vm|00111|1|Vn|Vd" , "t": "16B 8H 4S 2D"}, {"inst": "cmle Dd, Dn, #0" , "op": "01111110|11|10000|01001|10|Vn|Vd"}, {"inst": "cmle Vd.t, Vn.t, #0" , "op": "00101110|sz|10000|01001|10|Vn|Vd" , "t": "8B 4H 2S"}, {"inst": "cmle Vd.t, Vn.t, #0" , "op": "01101110|sz|10000|01001|10|Vn|Vd" , "t": "16B 8H 4S 2D"}, {"inst": "cmlt Dd, Dn, #0" , "op": "01011110|11|10000|01010|10|Vn|Vd"}, {"inst": "cmlt Vd.t, Vn.t, #0" , "op": "00001110|sz|10000|01010|10|Vn|Vd" , "t": "8B 4H 2S"}, {"inst": "cmlt Vd.t, Vn.t, #0" , "op": "01001110|sz|10000|01010|10|Vn|Vd" , "t": "16B 8H 4S 2D"}, {"inst": "cmtst Dd, Dn, Dm" , "op": "01011110|11|1|Vm|10001|1|Vn|Vd"}, {"inst": "cmtst Vd.t, Vn.t, Vm.t" , "op": "00001110|sz|1|Vm|10001|1|Vn|Vd" , "t": "8B 4H 2S"}, {"inst": "cmtst Vd.t, Vn.t, Vm.t" , "op": "01001110|sz|1|Vm|10001|1|Vn|Vd" , "t": "16B 8H 4S 2D"}, {"inst": "cnt Vd.8B, Vn.8B" , "op": "00001110|sz|10000|00101|10|Vn|Vd"}, {"inst": "cnt Vd.16B, Vn.16B" , "op": "01001110|sz|10000|00101|10|Vn|Vd"}, {"inst": "dup|mov Bd, Vn.B[#idx]" , "op": "01011110|00|0|idx:4| 1|00000|1|Vn|Vd"}, {"inst": "dup|mov Hd, Vn.H[#idx]" , "op": "01011110|00|0|idx:3| 10|00000|1|Vn|Vd"}, {"inst": "dup|mov Sd, Vn.S[#idx]" , "op": "01011110|00|0|idx:2| 100|00000|1|Vn|Vd"}, {"inst": "dup|mov Dd, Vn.D[#idx]" , "op": "01011110|00|0|idx:1| 1000|00000|1|Vn|Vd"}, {"inst": "dup Vd.8B, Wn" , "op": "00001110|00|0|00001|00001|1|Rn|Vd"}, {"inst": "dup Vd.4H, Wn" , "op": "00001110|00|0|00010|00001|1|Rn|Vd"}, {"inst": "dup Vd.2S, Wn" , "op": "00001110|00|0|11011|00001|1|Rn|Vd"}, {"inst": "dup Vd.16B, Wn" , "op": "01001110|00|0|00001|00001|1|Rn|Vd"}, {"inst": "dup Vd.8H, Wn" , "op": "01001110|00|0|00010|00001|1|Rn|Vd"}, {"inst": "dup Vd.4S, Wn" , "op": "01001110|00|0|11011|00001|1|Rn|Vd"}, {"inst": "dup Vd.2D, Xn" , "op": "01001110|00|0|11011|00001|1|Rn|Vd"}, {"inst": "dup Vd.8B, Vn.B[#idx]" , "op": "00001110|00|0|idx:4| 1|00000|1|Vn|Vd"}, {"inst": "dup Vd.4H, Vn.H[#idx]" , "op": "00001110|00|0|idx:3| 10|00000|1|Vn|Vd"}, {"inst": "dup Vd.2S, Vn.S[#idx]" , "op": "00001110|00|0|idx:2| 100|00000|1|Vn|Vd"}, {"inst": "dup Vd.16B, Vn.B[#idx]" , "op": "01001110|00|0|idx:4| 1|00000|1|Vn|Vd"}, {"inst": "dup Vd.8H, Vn.H[#idx]" , "op": "01001110|00|0|idx:3| 10|00000|1|Vn|Vd"}, {"inst": "dup Vd.4S, Vn.S[#idx]" , "op": "01001110|00|0|idx:2| 100|00000|1|Vn|Vd"}, {"inst": "dup Vd.2D, Vn.D[#idx]" , "op": "01001110|00|0|idx:1| 1000|00000|1|Vn|Vd"}, {"inst": "eor Vd.8B, Vn.8B, Vm.8B" , "op": "00101110|00|1|Vm|00011|1|Vn|Vd"}, {"inst": "eor Vd.16B, Vn.16B, Vm.16B" , "op": "01101110|00|1|Vm|00011|1|Vn|Vd"}, {"inst": "ext Vd.8B, Vn.8B, Vm.8B, #idx" , "op": "00101110|00|0|Vm|00|idx:3|0|Vn|Vd"}, {"inst": "ext Vd.16B, Vn.16B, Vm.16B, #idx" , "op": "01101110|00|0|Vm|0|idx:4|0|Vn|Vd"}, {"inst": "fabd Sd, Sn, Sm" , "op": "01111110|10|1|Vm|11010|1|Vn|Vd"}, {"inst": "fabd Dd, Dn, Dm" , "op": "01111110|11|1|Vm|11010|1|Vn|Vd"}, {"inst": "fabd Vd.2S, Vn.2S, Vm.2S" , "op": "00101110|10|0|Vm|11010|1|Vn|Vd"}, {"inst": "fabd Vd.4S, Vn.4S, Vm.4S" , "op": "00101110|10|0|Vm|11010|1|Vn|Vd"}, {"inst": "fabd Vd.2D, Vn.2D, Vm.2D" , "op": "01101110|11|0|Vm|11010|1|Vn|Vd"}, {"inst": "fabs Sd, Sn" , "op": "00011110|00|10000|01100|00|Vn|Vd"}, {"inst": "fabs Dd, Dn" , "op": "00011110|01|10000|01100|00|Vn|Vd"}, {"inst": "fabs Vd.2S, Vn.2S" , "op": "00001110|10|10000|01111|10|Vn|Vd"}, {"inst": "fabs Vd.4S, Vn.4S" , "op": "01001110|10|10000|01111|10|Vn|Vd"}, {"inst": "fabs Vd.2D, Vn.2D" , "op": "01001110|11|10000|01111|10|Vn|Vd"}, {"inst": "facge Sd, Sn, Sm" , "op": "01111110|00|1|Vm|11101|1|Vn|Vd"}, {"inst": "facge Dd, Dn, Dm" , "op": "01111110|01|0|Vm|11101|1|Vn|Vd"}, {"inst": "facge Vd.2S, Vn.2S, Vm.2S" , "op": "00101110|00|1|Vm|11101|1|Vn|Vd"}, {"inst": "facge Vd.4S, Vn.4S, Vm.4S" , "op": "01101110|00|1|Vm|11101|1|Vn|Vd"}, {"inst": "facge Vd.2D, Vn.2D, Vm.2D" , "op": "01101110|01|1|Vm|11101|1|Vn|Vd"}, {"inst": "facgt Sd, Sn, Sm" , "op": "01111110|10|1|Vm|11101|1|Vn|Vd"}, {"inst": "facgt Dd, Dn, Dm" , "op": "01111110|11|0|Vm|11101|1|Vn|Vd"}, {"inst": "facgt Vd.2S, Vn.2S, Vm.2S" , "op": "00101110|10|1|Vm|11101|1|Vn|Vd"}, {"inst": "facgt Vd.4S, Vn.4S, Vm.4S" , "op": "01101110|10|1|Vm|11101|1|Vn|Vd"}, {"inst": "facgt Vd.2D, Vn.2D, Vm.2D" , "op": "01101110|11|1|Vm|11101|1|Vn|Vd"}, {"inst": "fadd Sd, Sn, Sm" , "op": "00011110|00|1|Vm|00101|0|Vn|Vd"}, {"inst": "fadd Dd, Dn, Dm" , "op": "00011110|01|1|Vm|00101|0|Vn|Vd"}, {"inst": "fadd Vd.2S, Vn.2S, Vm.2S" , "op": "00001110|00|1|Vm|11010|1|Vn|Vd"}, {"inst": "fadd Vd.4S, Vn.4S, Vm.4S" , "op": "01001110|00|1|Vm|11010|1|Vn|Vd"}, {"inst": "fadd Vd.2D, Vn.2D, Vm.2D" , "op": "01001110|01|1|Vm|11010|1|Vn|Vd"}, {"inst": "faddp Sd, Vn.2S" , "op": "01111110|00|11000|01101|10|Vn|Vd"}, {"inst": "faddp Dd, Vn.2D" , "op": "01111110|01|11000|01101|10|Vn|Vd"}, {"inst": "faddp Vd.2S, Vn.2S, Vm.2S" , "op": "00101110|00|1|Vm|11010|1|Vn|Vd"}, {"inst": "faddp Vd.4S, Vn.4S, Vm.4S" , "op": "01101110|00|1|Vm|11010|1|Vn|Vd"}, {"inst": "faddp Vd.2D, Vn.2D, Vm.2D" , "op": "01101110|01|1|Vm|11010|1|Vn|Vd"}, {"inst": "fccmp Sn, Sm, #nzcv, #cond" , "op": "00011110|00|1|Vm|cond|01|Vn|0|nzcv" , "io": "N=W Z=W C=W V=W"}, {"inst": "fccmp Dn, Dm, #nzcv, #cond" , "op": "00011110|01|1|Vm|cond|01|Vn|0|nzcv" , "io": "N=W Z=W C=W V=W"}, {"inst": "fccmpe Sn, Sm, #nzcv, #cond" , "op": "00011110|00|1|Vm|cond|01|Vn|1|nzcv" , "io": "N=W Z=W C=W V=W"}, {"inst": "fccmpe Dn, Dm, #nzcv, #cond" , "op": "00011110|01|1|Vm|cond|01|Vn|1|nzcv" , "io": "N=W Z=W C=W V=W"}, {"inst": "fcmeq Sd, Sn, Sm" , "op": "01011110|00|1|Vm|11100|1|Vn|Vd"}, {"inst": "fcmeq Sd, Sn, #0" , "op": "01011110|10|10000|01101|10|Vn|Vd"}, {"inst": "fcmeq Dd, Dn, Dm" , "op": "01011110|01|1|Vm|11100|1|Vn|Vd"}, {"inst": "fcmeq Dd, Dn, #0" , "op": "01011110|11|10000|01101|10|Vn|Vd"}, {"inst": "fcmeq Vd.2S, Vn.2S, Vm.2S" , "op": "00001110|00|1|Vm|11100|1|Vn|Vd"}, {"inst": "fcmeq Vd.2S, Vn.2S, #0" , "op": "00001110|10|10000|01101|10|Vn|Vd"}, {"inst": "fcmeq Vd.4S, Vn.4S, Vm.4S" , "op": "01001110|00|1|Vm|11100|1|Vn|Vd"}, {"inst": "fcmeq Vd.4S, Vn.4S, #0" , "op": "01001110|10|10000|01101|10|Vn|Vd"}, {"inst": "fcmeq Vd.2D, Vn.2D, Vm.2D" , "op": "01001110|01|1|Vm|11100|1|Vn|Vd"}, {"inst": "fcmeq Vd.2D, Vn.2D, #0" , "op": "01001110|11|10000|01101|10|Vn|Vd"}, {"inst": "fcmge Sd, Sn, Sm" , "op": "01111110|00|1|Vm|11100|1|Vn|Vd"}, {"inst": "fcmge Sd, Sn, #0" , "op": "01111110|10|10000|01100|10|Vn|Vd"}, {"inst": "fcmge Dd, Dn, Dm" , "op": "01111110|01|1|Vm|11100|1|Vn|Vd"}, {"inst": "fcmge Dd, Dn, #0" , "op": "01111110|11|10000|01100|10|Vn|Vd"}, {"inst": "fcmge Vd.2S, Vn.2S, Vm.2S" , "op": "00101110|00|1|Vm|11100|1|Vn|Vd"}, {"inst": "fcmge Vd.2S, Vn.2S, #0" , "op": "00101110|10|10000|01100|10|Vn|Vd"}, {"inst": "fcmge Vd.4S, Vn.4S, Vm.4S" , "op": "01101110|00|1|Vm|11100|1|Vn|Vd"}, {"inst": "fcmge Vd.4S, Vn.4S, #0" , "op": "01101110|10|10000|01100|10|Vn|Vd"}, {"inst": "fcmge Vd.2D, Vn.2D, Vm.2D" , "op": "01101110|01|1|Vm|11100|1|Vn|Vd"}, {"inst": "fcmge Vd.2D, Vn.2D, #0" , "op": "01101110|11|10000|01100|10|Vn|Vd"}, {"inst": "fcmgt Sd, Sn, Sm" , "op": "01111110|10|1|Vm|11100|1|Vn|Vd"}, {"inst": "fcmgt Sd, Sn, #0" , "op": "01011110|10|10000|01100|10|Vn|Vd"}, {"inst": "fcmgt Dd, Dn, Dm" , "op": "01111110|11|1|Vm|11100|1|Vn|Vd"}, {"inst": "fcmgt Dd, Dn, #0" , "op": "01011110|11|10000|01100|10|Vn|Vd"}, {"inst": "fcmgt Vd.2S, Vn.2S, Vm.2S" , "op": "00101110|10|1|Vm|11100|1|Vn|Vd"}, {"inst": "fcmgt Vd.2S, Vn.2S, #0" , "op": "00001110|10|10000|01100|10|Vn|Vd"}, {"inst": "fcmgt Vd.4S, Vn.4S, Vm.4S" , "op": "01101110|10|1|Vm|11100|1|Vn|Vd"}, {"inst": "fcmgt Vd.4S, Vn.4S, #0" , "op": "01001110|10|10000|01100|10|Vn|Vd"}, {"inst": "fcmgt Vd.2D, Vn.2D, Vm.2D" , "op": "01101110|11|1|Vm|11100|1|Vn|Vd"}, {"inst": "fcmgt Vd.2D, Vn.2D, #0" , "op": "01001110|11|10000|01100|10|Vn|Vd"}, {"inst": "fcmle Sd, Sn, #0" , "op": "01111110|10|10000|01101|10|Vn|Vd"}, {"inst": "fcmle Dd, Dn, #0" , "op": "01111110|11|10000|01101|10|Vn|Vd"}, {"inst": "fcmle Vd.2S, Vn.2S, #0" , "op": "00101110|10|10000|01101|10|Vn|Vd"}, {"inst": "fcmle Vd.4S, Vn.4S, #0" , "op": "01101110|10|10000|01101|10|Vn|Vd"}, {"inst": "fcmle Vd.2D, Vn.2D, #0" , "op": "01101110|11|10000|01101|10|Vn|Vd"}, {"inst": "fcmlt Sd, Sn, #0" , "op": "01011110|10|10000|01110|10|Vn|Vd"}, {"inst": "fcmlt Dd, Dn, #0" , "op": "01011110|11|10000|01110|10|Vn|Vd"}, {"inst": "fcmlt Vd.2S, Vn.2S, #0" , "op": "00001110|10|10000|01110|10|Vn|Vd"}, {"inst": "fcmlt Vd.4S, Vn.4S, #0" , "op": "01001110|10|10000|01110|10|Vn|Vd"}, {"inst": "fcmlt Vd.2D, Vn.2D, #0" , "op": "01001110|11|10000|01110|10|Vn|Vd"}, {"inst": "fcmp Sn, Sm" , "op": "00011110|00|1|Vm|00100|0|Vn|00000" , "io": "N=W Z=W C=W V=W"}, {"inst": "fcmp Sn, #0" , "op": "00011110|00|1|00000|00100|0|Vn|01000" , "io": "N=W Z=W C=W V=W"}, {"inst": "fcmp Dn, Dm" , "op": "00011110|01|1|Vm|00100|0|Vn|00000" , "io": "N=W Z=W C=W V=W"}, {"inst": "fcmp Dn, #0" , "op": "00011110|01|1|00000|00100|0|Vn|01000" , "io": "N=W Z=W C=W V=W"}, {"inst": "fcmpe Sn, Sm" , "op": "00011110|00|1|Vm|00100|0|Vn|10000" , "io": "N=W Z=W C=W V=W"}, {"inst": "fcmpe Sn, #0" , "op": "00011110|00|1|00000|00100|0|Vn|11000" , "io": "N=W Z=W C=W V=W"}, {"inst": "fcmpe Dn, Dm" , "op": "00011110|01|1|Vm|00100|0|Vn|10000" , "io": "N=W Z=W C=W V=W"}, {"inst": "fcmpe Dn, #0" , "op": "00011110|01|1|00000|00100|0|Vn|11000" , "io": "N=W Z=W C=W V=W"}, {"inst": "fcsel Sd, Sn, Sm, #cond" , "op": "00011110|00|1|Vm|cond|11|Vn|Vd" , "io": "N=R Z=R C=R V=R"}, {"inst": "fcsel Dd, Dn, Dm, #cond" , "op": "00011110|01|1|Vm|cond|11|Vn|Vd" , "io": "N=R Z=R C=R V=R"}, {"inst": "fcvt Sd, Hn" , "op": "00011110|11|10001|00100|00|Vn|Vd"}, {"inst": "fcvt Dd, Hn" , "op": "00011110|11|10001|01100|00|Vn|Vd"}, {"inst": "fcvt Hd, Sn" , "op": "00011110|00|10001|11100|00|Vn|Vd"}, {"inst": "fcvt Dd, Sn" , "op": "00011110|00|10001|01100|00|Vn|Vd"}, {"inst": "fcvt Hd, Dn" , "op": "00011110|01|10001|11100|00|Vn|Vd"}, {"inst": "fcvt Sd, Dn" , "op": "00011110|01|10001|00100|00|Vn|Vd"}, {"inst": "fcvtas Wd, Sn" , "op": "00011110|00|10010|00000|00|Vn|Rd"}, {"inst": "fcvtas Xd, Sn" , "op": "10011110|00|10010|00000|00|Vn|Rd"}, {"inst": "fcvtas Wd, Dn" , "op": "00011110|01|10010|00000|00|Vn|Rd"}, {"inst": "fcvtas Xd, Dn" , "op": "10011110|01|10010|00000|00|Vn|Rd"}, {"inst": "fcvtas Sd, Sn" , "op": "01011110|00|10000|11100|10|Vn|Vd"}, {"inst": "fcvtas Dd, Dn" , "op": "01011110|01|10000|11100|10|Vn|Vd"}, {"inst": "fcvtas Vd.2S, Vn.2S" , "op": "00001110|00|10000|11100|10|Vn|Vd"}, {"inst": "fcvtas Vd.4S, Vn.4S" , "op": "01001110|00|10000|11100|10|Vn|Vd"}, {"inst": "fcvtas Vd.2D, Vn.2D" , "op": "01001110|01|10000|11100|10|Vn|Vd"}, {"inst": "fcvtau Wd, Sn" , "op": "00011110|00|10010|10000|00|Vn|Rd"}, {"inst": "fcvtau Xd, Sn" , "op": "10011110|00|10010|10000|00|Vn|Rd"}, {"inst": "fcvtau Wd, Dn" , "op": "00011110|01|10010|10000|00|Vn|Rd"}, {"inst": "fcvtau Xd, Dn" , "op": "10011110|01|10010|10000|00|Vn|Rd"}, {"inst": "fcvtau Sd, Sn" , "op": "01111110|00|10000|11100|10|Vn|Vd"}, {"inst": "fcvtau Dd, Dn" , "op": "01111110|01|10000|11100|10|Vn|Vd"}, {"inst": "fcvtau Vd.2S, Vn.2S" , "op": "00101110|00|10000|11100|10|Vn|Vd"}, {"inst": "fcvtau Vd.4S, Vn.4S" , "op": "01101110|00|10000|11100|10|Vn|Vd"}, {"inst": "fcvtau Vd.2D, Vn.2D" , "op": "01101110|01|10000|11100|10|Vn|Vd"}, {"inst": "fcvtl Vd.4S, Vn.4H" , "op": "00001110|00|10000|10111|10|Vn|Vd"}, {"inst": "fcvtl2 Vd.4S, Vn.8H" , "op": "01001110|00|10000|10111|10|Vn|Vd"}, {"inst": "fcvtl Vd.2D, Vn.2S" , "op": "00001110|01|10000|10111|10|Vn|Vd"}, {"inst": "fcvtl2 Vd.2D, Vn.4S" , "op": "01001110|01|10000|10111|10|Vn|Vd"}, {"inst": "fcvtms Wd, Sn" , "op": "00011110|00|11000|00000|00|Vn|Rd"}, {"inst": "fcvtms Xd, Sn" , "op": "10011110|00|11000|00000|00|Vn|Rd"}, {"inst": "fcvtms Wd, Dn" , "op": "00011110|01|11000|00000|00|Vn|Rd"}, {"inst": "fcvtms Xd, Dn" , "op": "10011110|01|11000|00000|00|Vn|Rd"}, {"inst": "fcvtms Sd, Sn" , "op": "01011110|00|10000|11011|10|Vn|Vd"}, {"inst": "fcvtms Dd, Dn" , "op": "01011110|01|10000|11011|10|Vn|Vd"}, {"inst": "fcvtms Vd.2S, Vn.2S" , "op": "00001110|00|10000|11011|10|Vn|Vd"}, {"inst": "fcvtms Vd.4S, Vn.4S" , "op": "01001110|00|10000|11011|10|Vn|Vd"}, {"inst": "fcvtms Vd.2D, Vn.2D" , "op": "01001110|01|10000|11011|10|Vn|Vd"}, {"inst": "fcvtmu Wd, Sn" , "op": "00011110|00|11000|10000|00|Vn|Rd"}, {"inst": "fcvtmu Xd, Sn" , "op": "10011110|00|11000|10000|00|Vn|Rd"}, {"inst": "fcvtmu Wd, Dn" , "op": "00011110|01|11000|10000|00|Vn|Rd"}, {"inst": "fcvtmu Xd, Dn" , "op": "10011110|01|11000|10000|00|Vn|Rd"}, {"inst": "fcvtmu Sd, Sn" , "op": "01111110|00|10000|11011|10|Vn|Vd"}, {"inst": "fcvtmu Dd, Dn" , "op": "01111110|01|10000|11011|10|Vn|Vd"}, {"inst": "fcvtmu Vd.2S, Vn.2S" , "op": "00101110|00|10000|11011|10|Vn|Vd"}, {"inst": "fcvtmu Vd.4S, Vn.4S" , "op": "01101110|00|10000|11011|10|Vn|Vd"}, {"inst": "fcvtmu Vd.2D, Vn.2D" , "op": "01101110|01|10000|11011|10|Vn|Vd"}, {"inst": "fcvtn Vd.4S, Vn.4H" , "op": "00001110|00|10000|10110|10|Vn|Vd"}, {"inst": "fcvtn2 Vd.4S, Vn.8H" , "op": "01001110|00|10000|10110|10|Vn|Vd"}, {"inst": "fcvtn Vd.2D, Vn.2S" , "op": "00001110|01|10000|10110|10|Vn|Vd"}, {"inst": "fcvtn2 Vd.2D, Vn.4S" , "op": "01001110|01|10000|10110|10|Vn|Vd"}, {"inst": "fcvtns Wd, Sn" , "op": "00011110|00|10000|00000|00|Vn|Rd"}, {"inst": "fcvtns Xd, Sn" , "op": "10011110|00|10000|00000|00|Vn|Rd"}, {"inst": "fcvtns Wd, Dn" , "op": "00011110|01|10000|00000|00|Vn|Rd"}, {"inst": "fcvtns Xd, Dn" , "op": "10011110|01|10000|00000|00|Vn|Rd"}, {"inst": "fcvtns Sd, Sn" , "op": "01011110|00|10000|11010|10|Vn|Vd"}, {"inst": "fcvtns Dd, Dn" , "op": "01011110|01|10000|11010|10|Vn|Vd"}, {"inst": "fcvtns Vd.2S, Vn.2S" , "op": "00001110|00|10000|11010|10|Vn|Vd"}, {"inst": "fcvtns Vd.4S, Vn.4S" , "op": "01001110|00|10000|11010|10|Vn|Vd"}, {"inst": "fcvtns Vd.2D, Vn.2D" , "op": "01001110|01|10000|11010|10|Vn|Vd"}, {"inst": "fcvtnu Wd, Sn" , "op": "00011110|00|10000|10000|00|Vn|Rd"}, {"inst": "fcvtnu Xd, Sn" , "op": "10011110|00|10000|10000|00|Vn|Rd"}, {"inst": "fcvtnu Wd, Dn" , "op": "00011110|01|10000|10000|00|Vn|Rd"}, {"inst": "fcvtnu Xd, Dn" , "op": "10011110|01|10000|10000|00|Vn|Rd"}, {"inst": "fcvtnu Sd, Sn" , "op": "01111110|00|10000|11010|10|Vn|Vd"}, {"inst": "fcvtnu Dd, Dn" , "op": "01111110|01|10000|11010|10|Vn|Vd"}, {"inst": "fcvtnu Vd.2S, Vn.2S" , "op": "00101110|00|10000|11010|10|Vn|Vd"}, {"inst": "fcvtnu Vd.4S, Vn.4S" , "op": "01101110|00|10000|11010|10|Vn|Vd"}, {"inst": "fcvtnu Vd.2D, Vn.2D" , "op": "01101110|01|10000|11010|10|Vn|Vd"}, {"inst": "fcvtps Wd, Sn" , "op": "00011110|00|10100|00000|00|Vn|Rd"}, {"inst": "fcvtps Xd, Sn" , "op": "10011110|00|10100|00000|00|Vn|Rd"}, {"inst": "fcvtps Wd, Dn" , "op": "00011110|01|10100|00000|00|Vn|Rd"}, {"inst": "fcvtps Xd, Dn" , "op": "10011110|01|10100|00000|00|Vn|Rd"}, {"inst": "fcvtps Sd, Sn" , "op": "01011110|10|10000|11010|10|Vn|Vd"}, {"inst": "fcvtps Dd, Dn" , "op": "01011110|11|10000|11010|10|Vn|Vd"}, {"inst": "fcvtps Vd.2S, Vn.2S" , "op": "00001110|10|10000|11010|10|Vn|Vd"}, {"inst": "fcvtps Vd.4S, Vn.4S" , "op": "01001110|10|10000|11010|10|Vn|Vd"}, {"inst": "fcvtps Vd.2D, Vn.2D" , "op": "01001110|11|10000|11010|10|Vn|Vd"}, {"inst": "fcvtpu Wd, Sn" , "op": "00011110|00|10100|10000|00|Vn|Rd"}, {"inst": "fcvtpu Xd, Sn" , "op": "10011110|00|10100|10000|00|Vn|Rd"}, {"inst": "fcvtpu Wd, Dn" , "op": "00011110|01|10100|10000|00|Vn|Rd"}, {"inst": "fcvtpu Xd, Dn" , "op": "10011110|01|10100|10000|00|Vn|Rd"}, {"inst": "fcvtpu Sd, Sn" , "op": "01111110|10|10000|11010|10|Vn|Vd"}, {"inst": "fcvtpu Dd, Dn" , "op": "01111110|11|10000|11010|10|Vn|Vd"}, {"inst": "fcvtpu Vd.2S, Vn.2S" , "op": "00101110|10|10000|11010|10|Vn|Vd"}, {"inst": "fcvtpu Vd.4S, Vn.4S" , "op": "01101110|10|10000|11010|10|Vn|Vd"}, {"inst": "fcvtpu Vd.2D, Vn.2D" , "op": "01101110|11|10000|11010|10|Vn|Vd"}, {"inst": "fcvtx Sd, Dn" , "op": "01111110|01|10000|10110|10|Vn|Vd"}, {"inst": "fcvtx Vd.4S, Vn.4H" , "op": "00101110|00|10000|10110|10|Vn|Vd"}, {"inst": "fcvtx2 Vd.4S, Vn.8H" , "op": "01101110|00|10000|10110|10|Vn|Vd"}, {"inst": "fcvtx Vd.2D, Vn.2S" , "op": "00101110|01|10000|10110|10|Vn|Vd"}, {"inst": "fcvtx2 Vd.2D, Vn.4S" , "op": "01101110|01|10000|10110|10|Vn|Vd"}, {"inst": "fcvtzs Wd, Sn" , "op": "00011110|00|11100|00000|00|Vn|Rd"}, {"inst": "fcvtzs Xd, Sn" , "op": "10011110|00|11100|00000|00|Vn|Rd"}, {"inst": "fcvtzs Wd, Dn" , "op": "00011110|01|11100|00000|00|Vn|Rd"}, {"inst": "fcvtzs Xd, Dn" , "op": "10011110|01|11100|00000|00|Vn|Rd"}, {"inst": "fcvtzs Sd, Sn" , "op": "01011110|10|10000|11011|10|Vn|Vd"}, {"inst": "fcvtzs Dd, Dn" , "op": "01011110|11|10000|11011|10|Vn|Vd"}, {"inst": "fcvtzs Vd.2S, Vn.2S" , "op": "00001110|10|10000|11011|10|Vn|Vd"}, {"inst": "fcvtzs Vd.4S, Vn.4S" , "op": "01001110|10|10000|11011|10|Vn|Vd"}, {"inst": "fcvtzs Vd.2D, Vn.2D" , "op": "01001110|11|10000|11011|10|Vn|Vd"}, {"inst": "fcvtzs Wd, Sn, #fbits" , "op": "00011110|00|011000|scale:6|Vn|Vd" , "imm": "ASimdFBitsScaleImm(fbits, 32)"}, {"inst": "fcvtzs Xd, Sn, #fbits" , "op": "10011110|00|011000|scale:6|Vn|Vd" , "imm": "ASimdFBitsScaleImm(fbits, 64)"}, {"inst": "fcvtzs Wd, Dn, #fbits" , "op": "00011110|01|011000|scale:6|Vn|Vd" , "imm": "ASimdFBitsScaleImm(fbits, 32)"}, {"inst": "fcvtzs Xd, Dn, #fbits" , "op": "10011110|01|011000|scale:6|Vn|Vd" , "imm": "ASimdFBitsScaleImm(fbits, 64)"}, {"inst": "fcvtzs Sd, Sn, #fbits" , "op": "01011111|0|immh:4|immb:3|11111|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 32)"}, {"inst": "fcvtzs Dd, Dn, #fbits" , "op": "01011111|0|immh:4|immb:3|11111|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 64)"}, {"inst": "fcvtzs Vd.2S, Vn.2S, #fbits" , "op": "00001111|0|immh:4|immb:3|11111|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 32)"}, {"inst": "fcvtzs Vd.4S, Vn.4S, #fbits" , "op": "01001111|0|immh:4|immb:3|11111|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 32)"}, {"inst": "fcvtzs Vd.2D, Vn.2D, #fbits" , "op": "01001111|0|immh:4|immb:3|11111|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 64)"}, {"inst": "fcvtzu Wd, Sn" , "op": "00011110|00|11100|10000|00|Vn|Rd"}, {"inst": "fcvtzu Xd, Sn" , "op": "10011110|00|11100|10000|00|Vn|Rd"}, {"inst": "fcvtzu Wd, Dn" , "op": "00011110|01|11100|10000|00|Vn|Rd"}, {"inst": "fcvtzu Xd, Dn" , "op": "10011110|01|11100|10000|00|Vn|Rd"}, {"inst": "fcvtzu Sd, Sn" , "op": "01111110|10|10000|11011|10|Vn|Vd"}, {"inst": "fcvtzu Dd, Dn" , "op": "01111110|11|10000|11011|10|Vn|Vd"}, {"inst": "fcvtzu Vd.2S, Vn.2S" , "op": "00101110|10|10000|11011|10|Vn|Vd"}, {"inst": "fcvtzu Vd.4S, Vn.4S" , "op": "01101110|10|10000|11011|10|Vn|Vd"}, {"inst": "fcvtzu Vd.2D, Vn.2D" , "op": "01101110|11|10000|11011|10|Vn|Vd"}, {"inst": "fcvtzu Wd, Sn, #fbits" , "op": "00011110|00|011001|scale:6|Vn|Vd" , "imm": "ASimdFBitsScaleImm(fbits, 32)"}, {"inst": "fcvtzu Xd, Sn, #fbits" , "op": "10011110|00|011001|scale:6|Vn|Vd" , "imm": "ASimdFBitsScaleImm(fbits, 64)"}, {"inst": "fcvtzu Wd, Dn, #fbits" , "op": "00011110|01|011001|scale:6|Vn|Vd" , "imm": "ASimdFBitsScaleImm(fbits, 32)"}, {"inst": "fcvtzu Xd, Dn, #fbits" , "op": "10011110|01|011001|scale:6|Vn|Vd" , "imm": "ASimdFBitsScaleImm(fbits, 64)"}, {"inst": "fcvtzu Sd, Sn, #fbits" , "op": "01111111|0|immh:4|immb:3|11111|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 32)"}, {"inst": "fcvtzu Dd, Dn, #fbits" , "op": "01111111|0|immh:4|immb:3|11111|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 64)"}, {"inst": "fcvtzu Vd.2S, Vn.2S, #fbits" , "op": "00101111|0|immh:4|immb:3|11111|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 32)"}, {"inst": "fcvtzu Vd.4S, Vn.4S, #fbits" , "op": "01101111|0|immh:4|immb:3|11111|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 32)"}, {"inst": "fcvtzu Vd.2D, Vn.2D, #fbits" , "op": "01101111|0|immh:4|immb:3|11111|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 64)"}, {"inst": "fdiv Sd, Sn, Sm" , "op": "00011110|00|1|Vm|00011|0|Vn|Vd"}, {"inst": "fdiv Dd, Dn, Dm" , "op": "00011110|01|1|Vm|00011|0|Vn|Vd"}, {"inst": "fdiv Vd.2S, Vn.2S, Vm.2S" , "op": "00101110|00|1|Vm|11111|1|Vn|Vd"}, {"inst": "fdiv Vd.4S, Vn.4S, Vm.4S" , "op": "01101110|00|1|Vm|11111|1|Vn|Vd"}, {"inst": "fdiv Vd.2D, Vn.2D, Vm.2D" , "op": "01101110|01|1|Vm|11111|1|Vn|Vd"}, {"inst": "fmadd Sd, Sn, Sm, Sa" , "op": "00011111|00|0|Vm|0|Va|Vn|Vd"}, {"inst": "fmadd Dd, Dn, Dm, Da" , "op": "00011111|01|0|Vm|0|Va|Vn|Vd"}, {"inst": "fmax Sd, Sn, Sm" , "op": "00011110|00|1|Vm|01001|0|Vn|Vd"}, {"inst": "fmax Dd, Dn, Dm" , "op": "00011110|01|1|Vm|01001|0|Vn|Vd"}, {"inst": "fmax Vd.2S, Vn.2S, Vm.2S" , "op": "00001110|00|1|Vm|11110|1|Vn|Vd"}, {"inst": "fmax Vd.4S, Vn.4S, Vm.4S" , "op": "01001110|00|1|Vm|11110|1|Vn|Vd"}, {"inst": "fmax Vd.2D, Vn.2D, Vm.2D" , "op": "01001110|01|1|Vm|11110|1|Vn|Vd"}, {"inst": "fmaxnm Sd, Sn, Sm" , "op": "00011110|00|1|Vm|01101|0|Vn|Vd"}, {"inst": "fmaxnm Dd, Dn, Dm" , "op": "00011110|01|1|Vm|01101|0|Vn|Vd"}, {"inst": "fmaxnm Vd.2S, Vn.2S, Vm.2S" , "op": "00001110|00|1|Vm|11000|1|Vn|Vd"}, {"inst": "fmaxnm Vd.2D, Vn.2D, Vm.2D" , "op": "01001110|01|1|Vm|11000|1|Vn|Vd"}, {"inst": "fmaxnm Vd.4S, Vn.4S, Vm.4S" , "op": "01001110|00|1|Vm|11000|1|Vn|Vd"}, {"inst": "fmaxnmp Sd, Vn.2S" , "op": "01111110|00|11000|01100|10|Vn|Vd"}, {"inst": "fmaxnmp Dd, Vn.2D" , "op": "01111110|01|11000|01100|10|Vn|Vd"}, {"inst": "fmaxnmp Vd.2S, Vn.2S, Vm.2S" , "op": "00101110|00|1|Vm|11000|1|Vn|Vd"}, {"inst": "fmaxnmp Vd.4S, Vn.4S, Vm.4S" , "op": "01101110|00|1|Vm|11000|1|Vn|Vd"}, {"inst": "fmaxnmp Vd.2D, Vn.2D, Vm.2D" , "op": "01101110|01|1|Vm|11000|1|Vn|Vd"}, {"inst": "fmaxnmv Sd, Vn.4S" , "op": "01101110|00|11000|01100|10|Vn|Vd"}, {"inst": "fmaxp Sd, Vn.2S" , "op": "01111110|00|11000|01111|10|Vn|Vd"}, {"inst": "fmaxp Dd, Vn.2D" , "op": "01111110|01|11000|01111|10|Vn|Vd"}, {"inst": "fmaxp Vd.2S, Vn.2S, Vm.2S" , "op": "00101110|00|1|Vm|11110|1|Vn|Vd"}, {"inst": "fmaxp Vd.4S, Vn.4S, Vm.4S" , "op": "01101110|00|1|Vm|11110|1|Vn|Vd"}, {"inst": "fmaxp Vd.2D, Vn.2D, Vm.2D" , "op": "01101110|01|1|Vm|11110|1|Vn|Vd"}, {"inst": "fmaxv Sd, Vn.4S" , "op": "01101110|00|11000|01111|10|Vn|Vd"}, {"inst": "fmin Sd, Sn, Sm" , "op": "00011110|00|1|Vm|01011|0|Vn|Vd"}, {"inst": "fmin Dd, Dn, Dm" , "op": "00011110|01|1|Vm|01011|0|Vn|Vd"}, {"inst": "fmin Vd.2S, Vn.2S, Vm.2S" , "op": "00001110|10|1|Vm|11110|1|Vn|Vd"}, {"inst": "fmin Vd.4S, Vn.4S, Vm.4S" , "op": "01001110|10|1|Vm|11110|1|Vn|Vd"}, {"inst": "fmin Vd.2D, Vn.2D, Vm.2D" , "op": "01001110|11|1|Vm|11110|1|Vn|Vd"}, {"inst": "fminnm Sd, Sn, Sm" , "op": "00011110|00|1|Vm|01111|0|Vn|Vd"}, {"inst": "fminnm Dd, Dn, Dm" , "op": "00011110|01|1|Vm|01111|0|Vn|Vd"}, {"inst": "fminnm Vd.2S, Vn.2S, Vm.2S" , "op": "00001110|10|1|Vm|11000|1|Vn|Vd"}, {"inst": "fminnm Vd.2D, Vn.2D, Vm.2D" , "op": "01001110|11|1|Vm|11000|1|Vn|Vd"}, {"inst": "fminnm Vd.4S, Vn.4S, Vm.4S" , "op": "01001110|10|1|Vm|11000|1|Vn|Vd"}, {"inst": "fminnmp Sd, Vn.2S" , "op": "01111110|10|11000|01100|10|Vn|Vd"}, {"inst": "fminnmp Dd, Vn.2D" , "op": "01111110|11|11000|01100|10|Vn|Vd"}, {"inst": "fminnmp Vd.2S, Vn.2S, Vm.2S" , "op": "00101110|10|1|Vm|11000|1|Vn|Vd"}, {"inst": "fminnmp Vd.4S, Vn.4S, Vm.4S" , "op": "01101110|10|1|Vm|11000|1|Vn|Vd"}, {"inst": "fminnmp Vd.2D, Vn.2D, Vm.2D" , "op": "01101110|11|1|Vm|11000|1|Vn|Vd"}, {"inst": "fminnmv Sd, Vn.4S" , "op": "01101110|10|11000|01100|10|Vn|Vd"}, {"inst": "fminp Sd, Vn.2S" , "op": "01111110|10|11000|01111|10|Vn|Vd"}, {"inst": "fminp Dd, Vn.2D" , "op": "01111110|11|11000|01111|10|Vn|Vd"}, {"inst": "fminp Vd.2S, Vn.2S, Vm.2S" , "op": "00101110|10|1|Vm|11110|1|Vn|Vd"}, {"inst": "fminp Vd.4S, Vn.4S, Vm.4S" , "op": "01101110|10|1|Vm|11110|1|Vn|Vd"}, {"inst": "fminp Vd.2D, Vn.2D, Vm.2D" , "op": "01101110|11|1|Vm|11110|1|Vn|Vd"}, {"inst": "fminv Sd, Vn.4S" , "op": "01101110|10|11000|01111|10|Vn|Vd"}, {"inst": "fmla Sx, Sn, Vm.S[#idx]" , "op": "01011111|10|idx[0]|Vm|0001|idx[1]|0|Vn|Vx"}, {"inst": "fmla Dx, Dn, Vm.D[#idx]" , "op": "01011111|11|0|Vm|0001|idx[0]|0|Vn|Vx"}, {"inst": "fmla Vx.2S, Vn.2S, Vm.2S" , "op": "00001110|00|1|Vm|11001|1|Vn|Vx"}, {"inst": "fmla Vx.4S, Vn.4S, Vm.4S" , "op": "01001110|00|1|Vm|11001|1|Vn|Vx"}, {"inst": "fmla Vx.2D, Vn.2D, Vm.2D" , "op": "01001110|01|1|Vm|11001|1|Vn|Vx"}, {"inst": "fmla Vx.2S, Vn.2S, Vm.S[#idx]" , "op": "00001111|10|idx[0]|Vm|0001|idx[1]|0|Vn|Vx"}, {"inst": "fmla Vx.4S, Vn.4S, Vm.S[#idx]" , "op": "01001111|11|idx[0]|Vm|0001|idx[1]|0|Vn|Vx"}, {"inst": "fmla Vx.2D, Vn.2D, Vm.D[#idx]" , "op": "01001111|11|0|Vm|0001|idx[0]|0|Vn|Vx"}, {"inst": "fmls Sx, Sn, Vm.S[#idx]" , "op": "01011111|10|idx[0]|Vm|0101|idx[1]|0|Vn|Vx"}, {"inst": "fmls Dx, Dn, Vm.D[#idx]" , "op": "01011111|11|0|Vm|0101|idx[0]|0|Vn|Vx"}, {"inst": "fmls Vx.2S, Vn.2S, Vm.2S" , "op": "00001110|10|1|Vm|11001|1|Vn|Vx"}, {"inst": "fmls Vx.4S, Vn.4S, Vm.4S" , "op": "01001110|10|1|Vm|11001|1|Vn|Vx"}, {"inst": "fmls Vx.2D, Vn.2D, Vm.2D" , "op": "01001110|11|1|Vm|11001|1|Vn|Vx"}, {"inst": "fmls Vx.2S, Vn.2S, Vm.S[#idx]" , "op": "00001111|10|idx[0]|Vm|0101|idx[1]|0|Vn|Vx"}, {"inst": "fmls Vx.4S, Vn.4S, Vm.S[#idx]" , "op": "01001111|11|idx[0]|Vm|0101|idx[1]|0|Vn|Vx"}, {"inst": "fmls Vx.2D, Vn.2D, Vm.D[#idx]" , "op": "01001111|11|0|Vm|0101|idx[0]|0|Vn|Vx"}, {"inst": "fmov Wd, Sn" , "op": "00011110|00|10011|00000|00|Vn|Rd"}, {"inst": "fmov Xd, Dn" , "op": "10011110|01|10011|00000|00|Vn|Rd"}, {"inst": "fmov Xd, Vn.D[#1]" , "op": "10011110|10|10111|00000|00|Vn|Rd"}, {"inst": "fmov Sd, Wn" , "op": "00011110|00|10011|10000|00|Rn|Vd"}, {"inst": "fmov Sd, Sn" , "op": "00011110|00|10000|00100|00|Vn|Vd"}, {"inst": "fmov Sd, #fimm" , "op": "00011110|00|1|imm:8|100|00000|Vd" , "imm": "ASimdFMovImm(fimm)"}, {"inst": "fmov Dd, Xn" , "op": "10011110|01|10011|10000|00|Rn|Vd"}, {"inst": "fmov Dd, Dn" , "op": "00011110|01|10000|00100|00|Vn|Vd"}, {"inst": "fmov Dd, #fimm" , "op": "00011110|01|1|imm:8|100|00000|Vd" , "imm": "ASimdFMovImm(fimm)"}, {"inst": "fmov Vd.D[#1], Xn" , "op": "10011110|10|10111|10000|00|Rn|Vd"}, {"inst": "fmov Vd.2S, #fimm" , "op": "00001111|00|000|abc:3|111101|defgh:5|Vd" , "imm": "ASimdFMovImm(fimm)"}, {"inst": "fmov Vd.4S, #fimm" , "op": "01001111|00|000|abc:3|111101|defgh:5|Vd" , "imm": "ASimdFMovImm(fimm)"}, {"inst": "fmov Vd.2D, #fimm" , "op": "01101111|00|000|abc:3|111101|defgh:5|Vd" , "imm": "ASimdFMovImm(fimm)"}, {"inst": "fmsub Sd, Sn, Sm, Sa" , "op": "00011111|00|0|Vm|1|Va|Vn|Vd"}, {"inst": "fmsub Dd, Dn, Dm, Da" , "op": "00011111|01|0|Vm|1|Va|Vn|Vd"}, {"inst": "fmul Sd, Sn, Sm" , "op": "00011110|00|1|Vm|00001|0|Vn|Vd"}, {"inst": "fmul Dd, Dn, Dm" , "op": "00011110|01|1|Vm|00001|0|Vn|Vd"}, {"inst": "fmul Sd, Sn, Vm.S[#idx]" , "op": "01011111|10|idx[0]|Vm|1001|idx[1]|0|Vn|Vd"}, {"inst": "fmul Dd, Dn, Vm.D[#idx]" , "op": "01011111|11|0|Vm|1001|idx[0]|0|Vn|Vd"}, {"inst": "fmul Vd.2S, Vn.2S, Vm.2S" , "op": "00101110|00|1|Vm|11011|1|Vn|Vd"}, {"inst": "fmul Vd.4S, Vn.4S, Vm.4S" , "op": "01101110|00|1|Vm|11011|1|Vn|Vd"}, {"inst": "fmul Vd.2D, Vn.2D, Vm.2D" , "op": "01101110|01|1|Vm|11011|1|Vn|Vd"}, {"inst": "fmul Vd.2S, Vn.2S, Vm.S[#idx]" , "op": "00001111|10|idx[0]|Vm|1001|idx[1]|0|Vn|Vd"}, {"inst": "fmul Vd.4S, Vn.4S, Vm.S[#idx]" , "op": "01001111|11|idx[0]|Vm|1001|idx[1]|0|Vn|Vd"}, {"inst": "fmul Vd.2D, Vn.2D, Vm.D[#idx]" , "op": "01001111|11|0|Vm|1001|idx[0]|0|Vn|Vd"}, {"inst": "fmulx Sd, Sn, Sm" , "op": "01011110|00|1|Vm|11011|1|Vn|Vd"}, {"inst": "fmulx Dd, Dn, Dm" , "op": "01011110|01|1|Vm|11011|1|Vn|Vd"}, {"inst": "fmulx Sd, Sn, Vm.S[#idx]" , "op": "01111111|10|idx[0]|Vm|1001|idx[1]|0|Vn|Vd"}, {"inst": "fmulx Dd, Dn, Vm.D[#idx]" , "op": "01111111|11|0|Vm|1001|idx:1|0|Vn|Vd"}, {"inst": "fmulx Vd.2S, Vn.2S, Vm.2S" , "op": "00001110|00|1|Vm|11011|1|Vn|Vd"}, {"inst": "fmulx Vd.4S, Vn.4S, Vm.4S" , "op": "01001110|00|1|Vm|11011|1|Vn|Vd"}, {"inst": "fmulx Vd.2D, Vn.2D, Vm.2D" , "op": "01001110|01|1|Vm|11011|1|Vn|Vd"}, {"inst": "fmulx Vd.2S, Vn.2S, Vm.S[#idx]" , "op": "00101111|10|idx[0]|Vm|1001|idx[1]|0|Vn|Vd"}, {"inst": "fmulx Vd.4S, Vn.4S, Vm.S[#idx]" , "op": "01101111|10|idx[0]|Vm|1001|idx[1]|0|Vn|Vd"}, {"inst": "fmulx Vd.2D, Vn.2D, Vm.D[#idx]" , "op": "01101111|11|0|Vm|1001|idx:1|0|Vn|Vd"}, {"inst": "fneg Sd, Sn" , "op": "00011110|00|10000|10100|00|Vn|Vd"}, {"inst": "fneg Dd, Dn" , "op": "00011110|01|10000|10100|00|Vn|Vd"}, {"inst": "fneg Vd.2S, Vn.2S" , "op": "00101110|10|10000|01111|10|Vn|Vd"}, {"inst": "fneg Vd.4S, Vn.4S" , "op": "01101110|10|10000|01111|10|Vn|Vd"}, {"inst": "fneg Vd.2D, Vn.2D" , "op": "01101110|11|10000|01111|10|Vn|Vd"}, {"inst": "fnmadd Sd, Sn, Sm, Sa" , "op": "00011111|00|1|Vm|0|Va|Vn|Vd"}, {"inst": "fnmadd Dd, Dn, Dm, Da" , "op": "00011111|01|1|Vm|0|Va|Vn|Vd"}, {"inst": "fnmsub Sd, Sn, Sm, Sa" , "op": "00011111|00|1|Vm|1|Va|Vn|Vd"}, {"inst": "fnmsub Dd, Dn, Dm, Da" , "op": "00011111|01|1|Vm|1|Va|Vn|Vd"}, {"inst": "fnmul Sd, Sn, Sm" , "op": "00011110|00|1|Vm|10001|0|Vn|Vd"}, {"inst": "fnmul Dd, Dn, Dm" , "op": "00011110|01|1|Vm|10001|0|Vn|Vd"}, {"inst": "frecpe Sd, Sn" , "op": "01011110|10|10000|11101|10|Vn|Vd"}, {"inst": "frecpe Dd, Dn" , "op": "01011110|11|10000|11101|10|Vn|Vd"}, {"inst": "frecpe Vd.2S, Vn.2S" , "op": "00001110|10|10000|11101|10|Vn|Vd"}, {"inst": "frecpe Vd.4S, Vn.4S" , "op": "01001110|10|10000|11101|10|Vn|Vd"}, {"inst": "frecpe Vd.2D, Vn.2D" , "op": "01001110|11|10000|11101|10|Vn|Vd"}, {"inst": "frecps Sd, Sn, Sm" , "op": "01011110|00|1|Vm|11111|1|Vn|Vd"}, {"inst": "frecps Dd, Dn, Dm" , "op": "01011110|01|1|Vm|11111|1|Vn|Vd"}, {"inst": "frecps Vd.2S, Vn.2S, Vm.2S" , "op": "00001110|00|1|Vm|11111|1|Vn|Vd"}, {"inst": "frecps Vd.4S, Vn.4S, Vm.4S" , "op": "01001110|00|1|Vm|11111|1|Vn|Vd"}, {"inst": "frecps Vd.2D, Vn.2D, Vm.2D" , "op": "01001110|01|1|Vm|11111|1|Vn|Vd"}, {"inst": "frecpx Sd, Sn, Sm" , "op": "01011110|10|10000|11111|10|Vn|Vd"}, {"inst": "frecpx Dd, Dn, Dm" , "op": "01011110|11|10000|11111|10|Vn|Vd"}, {"inst": "frinta Sd, Sn" , "op": "00011110|00|10011|00100|00|Vn|Vd"}, {"inst": "frinta Dd, Dn" , "op": "00011110|01|10011|00100|00|Vn|Vd"}, {"inst": "frinta Vd.2S, Vn.2S" , "op": "00101110|00|10000|11000|10|Vn|Vd"}, {"inst": "frinta Vd.4S, Vn.4S" , "op": "01101110|00|10000|11000|10|Vn|Vd"}, {"inst": "frinta Vd.2D, Vn.2D" , "op": "01101110|01|10000|11000|10|Vn|Vd"}, {"inst": "frinti Sd, Sn" , "op": "00011110|00|10011|11100|00|Vn|Vd"}, {"inst": "frinti Dd, Dn" , "op": "00011110|01|10011|11100|00|Vn|Vd"}, {"inst": "frinti Vd.2S, Vn.2S" , "op": "00101110|10|10000|11001|10|Vn|Vd"}, {"inst": "frinti Vd.4S, Vn.4S" , "op": "01101110|10|10000|11001|10|Vn|Vd"}, {"inst": "frinti Vd.2D, Vn.2D" , "op": "01101110|11|10000|11001|10|Vn|Vd"}, {"inst": "frintm Sd, Sn" , "op": "00011110|00|10010|10100|00|Vn|Vd"}, {"inst": "frintm Dd, Dn" , "op": "00011110|01|10010|10100|00|Vn|Vd"}, {"inst": "frintm Vd.2S, Vn.2S" , "op": "00001110|00|10000|11001|10|Vn|Vd"}, {"inst": "frintm Vd.4S, Vn.4S" , "op": "01001110|00|10000|11001|10|Vn|Vd"}, {"inst": "frintm Vd.2D, Vn.2D" , "op": "01001110|01|10000|11001|10|Vn|Vd"}, {"inst": "frintn Sd, Sn" , "op": "00011110|00|10010|00100|00|Vn|Vd"}, {"inst": "frintn Dd, Dn" , "op": "00011110|01|10010|00100|00|Vn|Vd"}, {"inst": "frintn Vd.2S, Vn.2S" , "op": "00001110|00|10000|11000|10|Vn|Vd"}, {"inst": "frintn Vd.4S, Vn.4S" , "op": "01001110|00|10000|11000|10|Vn|Vd"}, {"inst": "frintn Vd.2D, Vn.2D" , "op": "01001110|01|10000|11000|10|Vn|Vd"}, {"inst": "frintp Sd, Sn" , "op": "00011110|00|10010|01100|00|Vn|Vd"}, {"inst": "frintp Dd, Dn" , "op": "00011110|01|10010|01100|00|Vn|Vd"}, {"inst": "frintp Vd.2S, Vn.2S" , "op": "00001110|10|10000|11000|10|Vn|Vd"}, {"inst": "frintp Vd.4S, Vn.4S" , "op": "01001110|10|10000|11000|10|Vn|Vd"}, {"inst": "frintp Vd.2D, Vn.2D" , "op": "01001110|11|10000|11000|10|Vn|Vd"}, {"inst": "frintx Sd, Sn" , "op": "00011110|00|10011|10100|00|Vn|Vd"}, {"inst": "frintx Dd, Dn" , "op": "00011110|01|10011|10100|00|Vn|Vd"}, {"inst": "frintx Vd.2S, Vn.2S" , "op": "00101110|00|10000|11001|10|Vn|Vd"}, {"inst": "frintx Vd.4S, Vn.4S" , "op": "01101110|00|10000|11001|10|Vn|Vd"}, {"inst": "frintx Vd.2D, Vn.2D" , "op": "01101110|01|10000|11001|10|Vn|Vd"}, {"inst": "frintz Sd, Sn" , "op": "00011110|00|10010|11100|00|Vn|Vd"}, {"inst": "frintz Dd, Dn" , "op": "00011110|01|10010|11100|00|Vn|Vd"}, {"inst": "frintz Vd.2S, Vn.2S" , "op": "00001110|10|10000|11001|10|Vn|Vd"}, {"inst": "frintz Vd.4S, Vn.4S" , "op": "01001110|10|10000|11001|10|Vn|Vd"}, {"inst": "frintz Vd.2D, Vn.2D" , "op": "01001110|11|10000|11001|10|Vn|Vd"}, {"inst": "frsqrte Sd, Sn" , "op": "01111110|10|10000|11101|10|Vn|Vd"}, {"inst": "frsqrte Dd, Dn" , "op": "01111110|11|10000|11101|10|Vn|Vd"}, {"inst": "frsqrte Vd.2S, Vn.2S" , "op": "00101110|10|10000|11101|10|Vn|Vd"}, {"inst": "frsqrte Vd.4S, Vn.4S" , "op": "01101110|10|10000|11101|10|Vn|Vd"}, {"inst": "frsqrte Vd.2D, Vn.2D" , "op": "01101110|11|10000|11101|10|Vn|Vd"}, {"inst": "frsqrts Sd, Sn, Sm" , "op": "01011110|10|1|Vm|11111|1|Vn|Vd"}, {"inst": "frsqrts Dd, Dn, Dm" , "op": "01011110|11|1|Vm|11111|1|Vn|Vd"}, {"inst": "frsqrts Vd.2S, Vn.2S, Vm.2S" , "op": "00001110|10|1|Vm|11111|1|Vn|Vd"}, {"inst": "frsqrts Vd.4S, Vn.4S, Vm.4S" , "op": "01001110|10|1|Vm|11111|1|Vn|Vd"}, {"inst": "frsqrts Vd.2D, Vn.2D, Vm.2D" , "op": "01001110|11|1|Vm|11111|1|Vn|Vd"}, {"inst": "fsqrt Sd, Sn" , "op": "00011110|10|10000|11100|00|Vn|Vd"}, {"inst": "fsqrt Dd, Dn" , "op": "00011110|11|10000|11100|00|Vn|Vd"}, {"inst": "fsqrt Vd.2S, Vn.2S" , "op": "00101110|10|10000|11111|10|Vn|Vd"}, {"inst": "fsqrt Vd.4S, Vn.4S" , "op": "01101110|10|10000|11111|10|Vn|Vd"}, {"inst": "fsqrt Vd.2D, Vn.2D" , "op": "01101110|11|10000|11111|10|Vn|Vd"}, {"inst": "fsub Sd, Sn, Sm" , "op": "00011110|00|1|Vm|00111|0|Vn|Vd"}, {"inst": "fsub Dd, Dn, Dm" , "op": "00011110|01|1|Vm|00111|0|Vn|Vd"}, {"inst": "fsub Vd.2S, Vn.2S, Vm.2S" , "op": "00001110|10|1|Vm|11010|1|Vn|Vd"}, {"inst": "fsub Vd.4S, Vn.4S, Vm.4S" , "op": "01001110|10|1|Vm|11010|1|Vn|Vd"}, {"inst": "fsub Vd.2D, Vn.2D, Vm.2D" , "op": "01001110|11|1|Vm|11010|1|Vn|Vd"}, {"inst": "ins|mov Vd.B[#idx], Wn" , "op": "01001110|00|0|idx:4|1 |00011|1|Rn|Vd"}, {"inst": "ins|mov Vd.H[#idx], Wn" , "op": "01001110|00|0|idx:3|10 |00011|1|Rn|Vd"}, {"inst": "ins|mov Vd.S[#idx], Wn" , "op": "01001110|00|0|idx:2|100 |00011|1|Rn|Vd"}, {"inst": "ins|mov Vd.D[#idx], Xn" , "op": "01001110|00|0|idx:1|1000|00011|1|Rn|Vd"}, {"inst": "ins|mov Vd.B[#idx1], Vn.B[#idx2]" , "op": "01101110|00|0|idx1:4|1 |0|idx2:4|1 |Rn|Vd"}, {"inst": "ins|mov Vd.H[#idx1], Vn.H[#idx2]" , "op": "01101110|00|0|idx1:3|10 |0|idx2:3|01 |Rn|Vd"}, {"inst": "ins|mov Vd.S[#idx1], Vn.S[#idx2]" , "op": "01101110|00|0|idx1:2|100 |0|idx2:2|001 |Rn|Vd"}, {"inst": "ins|mov Vd.D[#idx1], Vn.D[#idx2]" , "op": "01101110|00|0|idx1:1|1000|0|idx2:1|0001|Rn|Vd"}, {"inst": "ld1 Vx.B[#idx], [Xn|SP]" , "op": "0|idx:1|001101|010|00000|000|idx:3 |Rn|Vx"}, {"inst": "ld1 Vx.H[#idx], [Xn|SP]" , "op": "0|idx:1|001101|010|00000|010|idx:2| 0|Rn|Vx"}, {"inst": "ld1 Vx.S[#idx], [Xn|SP]" , "op": "0|idx:1|001101|010|00000|100|idx:1|00|Rn|Vx"}, {"inst": "ld1 Vx.D[#idx], [Xn|SP]" , "op": "0|idx:1|001101|010|00000|100| 001|Rn|Vx"}, {"inst": "ld1 Vx.B[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|110|Rm |000|idx:3 |Rn|Vx"}, {"inst": "ld1 Vx.H[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|110|Rm |010|idx:2| 0|Rn|Vx"}, {"inst": "ld1 Vx.S[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|110|Rm |100|idx:1|00|Rn|Vx"}, {"inst": "ld1 Vx.D[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|110|Rm |100| 001|Rn|Vx"}, {"inst": "ld1 Vx.B[#idx], [Xn|SP, #off=1]@" , "op": "0|idx:1|001101|110|11111|000|idx:3 |Rn|Vx"}, {"inst": "ld1 Vx.H[#idx], [Xn|SP, #off=2]@" , "op": "0|idx:1|001101|110|11111|010|idx:2| 0|Rn|Vx"}, {"inst": "ld1 Vx.S[#idx], [Xn|SP, #off=4]@" , "op": "0|idx:1|001101|110|11111|100|idx:1|00|Rn|Vx"}, {"inst": "ld1 Vx.D[#idx], [Xn|SP, #off=8]@" , "op": "0|idx:1|001101|110|11111|100| 001|Rn|Vx"}, {"inst": "ld1 1x{Vd.t}, [Xn|SP]" , "op": "00001100|010|00000|0111|sz|Rn|Vd" , "t": "8B 4H 2S 1D"}, {"inst": "ld1 1x{Vd.t}, [Xn|SP]" , "op": "01001100|010|00000|0111|sz|Rn|Vd" , "t": "16B 8H 4S 2D"}, {"inst": "ld1 2x{Vd.t}, [Xn|SP]" , "op": "00001100|010|00000|1010|sz|Rn|Vd" , "t": "8B 4H 2S 1D"}, {"inst": "ld1 2x{Vd.t}, [Xn|SP]" , "op": "01001100|010|00000|1010|sz|Rn|Vd" , "t": "16B 8H 4S 2D"}, {"inst": "ld1 3x{Vd.t}, [Xn|SP]" , "op": "00001100|010|00000|0110|sz|Rn|Vd" , "t": "8B 4H 2S 1D"}, {"inst": "ld1 3x{Vd.t}, [Xn|SP]" , "op": "01001100|010|00000|0110|sz|Rn|Vd" , "t": "16B 8H 4S 2D"}, {"inst": "ld1 4x{Vd.t}, [Xn|SP]" , "op": "00001100|010|00000|0010|sz|Rn|Vd" , "t": "8B 4H 2S 1D"}, {"inst": "ld1 4x{Vd.t}, [Xn|SP]" , "op": "01001100|010|00000|0010|sz|Rn|Vd" , "t": "16B 8H 4S 2D"}, {"inst": "ld1 1x{Vd.t}, [Xn|SP, Xm]@" , "op": "00001100|110|Rm |0111|sz|Rn|Vd" , "t": "8B 4H 2S 1D"}, {"inst": "ld1 1x{Vd.t}, [Xn|SP, Xm]@" , "op": "01001100|110|Rm |0111|sz|Rn|Vd" , "t": "16B 8H 4S 2D"}, {"inst": "ld1 2x{Vd.t}, [Xn|SP, Xm]@" , "op": "00001100|110|Rm |1010|sz|Rn|Vd" , "t": "8B 4H 2S 1D"}, {"inst": "ld1 2x{Vd.t}, [Xn|SP, Xm]@" , "op": "01001100|110|Rm |1010|sz|Rn|Vd" , "t": "16B 8H 4S 2D"}, {"inst": "ld1 3x{Vd.t}, [Xn|SP, Xm]@" , "op": "00001100|110|Rm |0110|sz|Rn|Vd" , "t": "8B 4H 2S 1D"}, {"inst": "ld1 3x{Vd.t}, [Xn|SP, Xm]@" , "op": "01001100|110|Rm |0110|sz|Rn|Vd" , "t": "16B 8H 4S 2D"}, {"inst": "ld1 4x{Vd.t}, [Xn|SP, Xm]@" , "op": "00001100|110|Rm |0010|sz|Rn|Vd" , "t": "8B 4H 2S 1D"}, {"inst": "ld1 4x{Vd.t}, [Xn|SP, Xm]@" , "op": "01001100|110|Rm |0010|sz|Rn|Vd" , "t": "16B 8H 4S 2D"}, {"inst": "ld1 1x{Vd.t}, [Xn|SP, #off==8]@" , "op": "00001100|110|11111|0111|sz|Rn|Vd" , "t": "8B 4H 2S 1D"}, {"inst": "ld1 1x{Vd.t}, [Xn|SP, #off==16]@" , "op": "01001100|110|11111|0111|sz|Rn|Vd" , "t": "16B 8H 4S 2D"}, {"inst": "ld1 2x{Vd.t}, [Xn|SP, #off==16]@" , "op": "00001100|110|11111|1010|sz|Rn|Vd" , "t": "8B 4H 2S 1D"}, {"inst": "ld1 2x{Vd.t}, [Xn|SP, #off==32]@" , "op": "01001100|110|11111|1010|sz|Rn|Vd" , "t": "16B 8H 4S 2D"}, {"inst": "ld1 3x{Vd.t}, [Xn|SP, #off==24]@" , "op": "00001100|110|11111|0110|sz|Rn|Vd" , "t": "8B 4H 2S 1D"}, {"inst": "ld1 3x{Vd.t}, [Xn|SP, #off==48]@" , "op": "01001100|110|11111|0110|sz|Rn|Vd" , "t": "16B 8H 4S 2D"}, {"inst": "ld1 4x{Vd.t}, [Xn|SP, #off==32]@" , "op": "00001100|110|11111|0010|sz|Rn|Vd" , "t": "8B 4H 2S 1D"}, {"inst": "ld1 4x{Vd.t}, [Xn|SP, #off==64]@" , "op": "01001100|110|11111|0010|sz|Rn|Vd" , "t": "16B 8H 4S 2D"}, {"inst": "ld1r 1x{Vd.t}, [Xn|SP]" , "op": "00001101|010|00000|1100|sz|Rn|Vd" , "t": "8B 4H 2S 1D"}, {"inst": "ld1r 1x{Vd.t}, [Xn|SP]" , "op": "01001101|010|00000|1100|sz|Rn|Vd" , "t": "16B 8H 4S 2D"}, {"inst": "ld1r 1x{Vd.t}, [Xn|SP, Xm]@" , "op": "00001101|110|Rm |1100|sz|Rn|Vd" , "t": "8B 4H 2S 1D"}, {"inst": "ld1r 1x{Vd.t}, [Xn|SP, Xm]@" , "op": "01001101|110|Rm |1100|sz|Rn|Vd" , "t": "16B 8H 4S 2D"}, {"inst": "ld1r 1x{Vd.t}, [Xn|SP, #off==1<