623 lines
21 KiB
Python
623 lines
21 KiB
Python
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# udis86 - scripts/ud_opcode.py
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#
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# Copyright (c) 2009, 2013 Vivek Thampi
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without modification,
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# are permitted provided that the following conditions are met:
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#
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# * Redistributions of source code must retain the above copyright notice,
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# this list of conditions and the following disclaimer.
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# * Redistributions in binary form must reproduce the above copyright notice,
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# this list of conditions and the following disclaimer in the documentation
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# and/or other materials provided with the distribution.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
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# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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import os
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# Some compatibility stuff for supporting python 2.x as well as python 3.x
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def itemslist(dict):
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try:
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return dict.iteritems() # python 2.x
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except AttributeError:
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return list(dict.items()) # python 3.x
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class UdInsnDef:
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"""An x86 instruction definition
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"""
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def __init__(self, **insnDef):
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self.mnemonic = insnDef['mnemonic']
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self.prefixes = insnDef['prefixes']
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self.opcodes = insnDef['opcodes']
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self.operands = insnDef['operands']
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self._cpuid = insnDef['cpuid']
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self._opcexts = {}
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for opc in self.opcodes:
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if opc.startswith('/'):
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e, v = opc.split('=')
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self._opcexts[e] = v
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def lookupPrefix(self, pfx):
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"""Lookup prefix (if any, None otherwise), by name"""
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return True if pfx in self.prefixes else None
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@property
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def vendor(self):
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return self._opcexts.get('/vendor', None)
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@property
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def mode(self):
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return self._opcexts.get('/m', None)
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@property
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def osize(self):
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return self._opcexts.get('/o', None)
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def isDef64(self):
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return 'def64' in self.prefixes
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def __str__(self):
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return self.mnemonic + " " + ', '.join(self.operands) + \
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" " + ' '.join(self.opcodes)
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class UdOpcodeTable:
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"""A single table of instruction definitions, indexed by
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a decode field.
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"""
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class CollisionError(Exception):
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pass
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class IndexError(Exception):
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"""Invalid Index Error"""
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pass
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@classmethod
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def vendor2idx(cls, v):
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return (0 if v == 'amd'
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else (1 if v == 'intel'
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else 2))
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@classmethod
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def vex2idx(cls, v):
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if v.startswith("none_"):
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v = v[5:]
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vexOpcExtMap = {
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'none' : 0x0,
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'0f' : 0x1,
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'0f38' : 0x2,
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'0f3a' : 0x3,
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'66' : 0x4,
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'66_0f' : 0x5,
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'66_0f38' : 0x6,
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'66_0f3a' : 0x7,
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'f3' : 0x8,
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'f3_0f' : 0x9,
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'f3_0f38' : 0xa,
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'f3_0f3a' : 0xb,
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'f2' : 0xc,
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'f2_0f' : 0xd,
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'f2_0f38' : 0xe,
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'f2_0f3a' : 0xf,
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}
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return vexOpcExtMap[v]
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# A mapping of opcode extensions to their representational
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# values used in the opcode map.
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OpcExtMap = {
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'/rm' : lambda v: int(v, 16),
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'/x87' : lambda v: int(v, 16),
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'/3dnow' : lambda v: int(v, 16),
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'/reg' : lambda v: int(v, 16),
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# modrm.mod
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# (!11, 11) => (00b, 01b)
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'/mod' : lambda v: 0 if v == '!11' else 1,
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# Mode extensions:
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# (16, 32, 64) => (00, 01, 02)
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'/o' : lambda v: (int(v) / 32),
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'/a' : lambda v: (int(v) / 32),
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# Disassembly mode
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# (!64, 64) => (00b, 01b)
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'/m' : lambda v: 1 if v == '64' else 0,
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# SSE
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# none => 0
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# f2 => 1
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# f3 => 2
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# 66 => 3
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'/sse' : lambda v: (0 if v == 'none'
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else (((int(v, 16) & 0xf) + 1) / 2)),
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# AVX
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'/vex' : lambda v: UdOpcodeTable.vex2idx(v),
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'/vexw' : lambda v: 0 if v == '0' else 1,
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'/vexl' : lambda v: 0 if v == '0' else 1,
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# Vendor
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'/vendor': lambda v: UdOpcodeTable.vendor2idx(v)
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}
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_TableInfo = {
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'opctbl' : { 'label' : 'UD_TAB__OPC_TABLE', 'size' : 256 },
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'/sse' : { 'label' : 'UD_TAB__OPC_SSE', 'size' : 4 },
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'/reg' : { 'label' : 'UD_TAB__OPC_REG', 'size' : 8 },
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'/rm' : { 'label' : 'UD_TAB__OPC_RM', 'size' : 8 },
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'/mod' : { 'label' : 'UD_TAB__OPC_MOD', 'size' : 2 },
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'/m' : { 'label' : 'UD_TAB__OPC_MODE', 'size' : 2 },
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'/x87' : { 'label' : 'UD_TAB__OPC_X87', 'size' : 64 },
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'/a' : { 'label' : 'UD_TAB__OPC_ASIZE', 'size' : 3 },
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'/o' : { 'label' : 'UD_TAB__OPC_OSIZE', 'size' : 3 },
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'/3dnow' : { 'label' : 'UD_TAB__OPC_3DNOW', 'size' : 256 },
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'/vendor' : { 'label' : 'UD_TAB__OPC_VENDOR', 'size' : 3 },
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'/vex' : { 'label' : 'UD_TAB__OPC_VEX', 'size' : 16 },
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'/vexw' : { 'label' : 'UD_TAB__OPC_VEX_W', 'size' : 2 },
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'/vexl' : { 'label' : 'UD_TAB__OPC_VEX_L', 'size' : 2 },
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}
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def __init__(self, typ):
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assert typ in self._TableInfo
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self._typ = typ
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self._entries = {}
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def size(self):
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return self._TableInfo[self._typ]['size']
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def entries(self):
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return itemslist(self._entries)
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def numEntries(self):
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return len(self._entries.keys())
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def label(self):
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return self._TableInfo[self._typ]['label']
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def typ(self):
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return self._typ
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def meta(self):
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return self._typ
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def __str__(self):
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return "table-%s" % self._typ
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def add(self, opc, obj):
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typ = UdOpcodeTable.getOpcodeTyp(opc)
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idx = UdOpcodeTable.getOpcodeIdx(opc)
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if self._typ != typ or idx in self._entries:
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raise CollisionError()
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self._entries[idx] = obj
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def lookup(self, opc):
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typ = UdOpcodeTable.getOpcodeTyp(opc)
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idx = UdOpcodeTable.getOpcodeIdx(opc)
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if self._typ != typ:
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raise UdOpcodeTable.CollisionError("%s <-> %s" % (self._typ, typ))
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return self._entries.get(idx, None)
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def entryAt(self, index):
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"""Returns the entry at a given index of the table,
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None if there is none. Raises an exception if the
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index is out of bounds.
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"""
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if index < self.size():
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return self._entries.get(index, None)
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raise self.IndexError("index out of bounds: %s" % index)
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def setEntryAt(self, index, obj):
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if index < self.size():
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self._entries[index] = obj
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else:
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raise self.IndexError("index out of bounds: %s" % index)
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@classmethod
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def getOpcodeTyp(cls, opc):
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if opc.startswith('/'):
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return opc.split('=')[0]
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else:
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return 'opctbl'
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@classmethod
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def getOpcodeIdx(cls, opc):
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if opc.startswith('/'):
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typ, v = opc.split('=')
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return cls.OpcExtMap[typ](v)
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else:
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# plain opctbl opcode
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return int(opc, 16)
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@classmethod
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def getLabels(cls):
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"""Returns a list of all labels"""
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return [cls._TableInfo[k]['label'] for k in cls._TableInfo.keys()]
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class UdOpcodeTables(object):
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"""Collection of opcode tables
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"""
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class CollisionError(Exception):
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def __init__(self, obj1, obj2):
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self.obj1, self.obj2 = obj1, obj2
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def newTable(self, typ):
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"""Create a new opcode table of a give type `typ`. """
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tbl = UdOpcodeTable(typ)
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self._tables.append(tbl)
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return tbl
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def mkTrie(self, opcodes, obj):
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"""Recursively contruct a trie entry mapping a string of
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opcodes to an object.
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"""
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if len(opcodes) == 0:
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return obj
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opc = opcodes[0]
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tbl = self.newTable(UdOpcodeTable.getOpcodeTyp(opc))
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tbl.add(opc, self.mkTrie(opcodes[1:], obj))
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return tbl
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def walk(self, tbl, opcodes):
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"""Walk down the opcode trie, starting at a given opcode
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table, given a string of opcodes. Return None if unable
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to walk, the object at the leaf otherwise.
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"""
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opc = opcodes[0]
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e = tbl.lookup(opc)
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if e is None:
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return None
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elif isinstance(e, UdOpcodeTable) and len(opcodes[1:]):
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return self.walk(e, opcodes[1:])
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return e
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def map(self, tbl, opcodes, obj):
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"""Create a mapping from a given string of opcodes to an
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object in the opcode trie. Constructs trie branches as
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needed.
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"""
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opc = opcodes[0]
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e = tbl.lookup(opc)
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if e is None:
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tbl.add(opc, self.mkTrie(opcodes[1:], obj))
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else:
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if len(opcodes[1:]) == 0:
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raise self.CollisionError(e, obj)
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self.map(e, opcodes[1:], obj)
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def __init__(self, xml):
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self._tables = []
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self._insns = []
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self._mnemonics = {}
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# The root table is always a 256 entry opctbl, indexed
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# by a plain opcode byte
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self.root = self.newTable('opctbl')
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if os.getenv("UD_OPCODE_DEBUG"):
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self._logFh = open("opcodeTables.log", "w")
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# add an invalid instruction entry without any mapping
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# in the opcode tables.
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self.invalidInsn = UdInsnDef(mnemonic="invalid", opcodes=[], cpuid=[],
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operands=[], prefixes=[])
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self._insns.append(self.invalidInsn)
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# Construct UdOpcodeTables object from the given
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# udis86 optable.xml
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for insn in self.__class__.parseOptableXML(xml):
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self.addInsnDef(insn)
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self.patchAvx2byte()
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self.mergeSSENONE()
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self.printStats()
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def log(self, s):
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if os.getenv("UD_OPCODE_DEBUG"):
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self._logFh.write(s + "\n")
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def mergeSSENONE(self):
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"""Merge sse tables with only one entry for /sse=none
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"""
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for table in self._tables:
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for k, e in table.entries():
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if isinstance(e, UdOpcodeTable) and e.typ() == '/sse':
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if e.numEntries() == 1:
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sse = e.lookup("/sse=none")
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if sse:
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table.setEntryAt(k, sse)
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uniqTables = {}
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def genTableList(tbl):
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if tbl not in uniqTables:
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self._tables.append(tbl)
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uniqTables[tbl] = 1
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for k, e in tbl.entries():
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if isinstance(e, UdOpcodeTable):
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genTableList(e)
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self._tables = []
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genTableList(self.root)
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def patchAvx2byte(self):
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# create avx tables
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for pp in (None, 'f2', 'f3', '66'):
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for m in (None, '0f', '0f38', '0f3a'):
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if pp is None and m is None:
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continue
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if pp is None:
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vex = m
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elif m is None:
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vex = pp
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else:
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vex = pp + '_' + m
|
||
|
|
table = self.walk(self.root, ('c4', '/vex=' + vex))
|
||
|
|
self.map(self.root, ('c5', '/vex=' + vex), table)
|
||
|
|
|
||
|
|
|
||
|
|
def addInsn(self, **insnDef):
|
||
|
|
|
||
|
|
# Canonicalize opcode list
|
||
|
|
opcexts = insnDef['opcexts']
|
||
|
|
opcodes = list(insnDef['opcodes'])
|
||
|
|
|
||
|
|
# Re-order vex
|
||
|
|
if '/vex' in opcexts:
|
||
|
|
assert opcodes[0] == 'c4' or opcodes[0] == 'c5'
|
||
|
|
opcodes.insert(1, '/vex=' + opcexts['/vex'])
|
||
|
|
|
||
|
|
# Add extensions. The order is important, and determines how
|
||
|
|
# well the opcode table is packed. Also note, /sse must be
|
||
|
|
# before /o, because /sse may consume operand size prefix
|
||
|
|
# affect the outcome of /o.
|
||
|
|
for ext in ('/mod', '/x87', '/reg', '/rm', '/sse', '/o', '/a', '/m',
|
||
|
|
'/vexw', '/vexl', '/3dnow', '/vendor'):
|
||
|
|
if ext in opcexts:
|
||
|
|
opcodes.append(ext + '=' + opcexts[ext])
|
||
|
|
|
||
|
|
insn = UdInsnDef(mnemonic = insnDef['mnemonic'],
|
||
|
|
prefixes = insnDef['prefixes'],
|
||
|
|
operands = insnDef['operands'],
|
||
|
|
opcodes = opcodes,
|
||
|
|
cpuid = insnDef['cpuid'])
|
||
|
|
try:
|
||
|
|
self.map(self.root, opcodes, insn)
|
||
|
|
except self.CollisionError as e:
|
||
|
|
self.pprint()
|
||
|
|
print(opcodes, insn, str(e.obj1), str(e.obj2))
|
||
|
|
raise
|
||
|
|
except Exception as e:
|
||
|
|
self.pprint()
|
||
|
|
raise
|
||
|
|
self._insns.append(insn)
|
||
|
|
# add to lookup by mnemonic structure
|
||
|
|
if insn.mnemonic not in self._mnemonics:
|
||
|
|
self._mnemonics[insn.mnemonic] = [ insn ]
|
||
|
|
else:
|
||
|
|
self._mnemonics[insn.mnemonic].append(insn)
|
||
|
|
|
||
|
|
|
||
|
|
def addInsnDef(self, insnDef):
|
||
|
|
opcodes = []
|
||
|
|
opcexts = {}
|
||
|
|
|
||
|
|
# pack plain opcodes first, and collect opcode
|
||
|
|
# extensions
|
||
|
|
for opc in insnDef['opcodes']:
|
||
|
|
if not opc.startswith('/'):
|
||
|
|
opcodes.append(opc)
|
||
|
|
else:
|
||
|
|
e, v = opc.split('=')
|
||
|
|
opcexts[e] = v
|
||
|
|
|
||
|
|
# treat vendor as an opcode extension
|
||
|
|
if len(insnDef['vendor']):
|
||
|
|
opcexts['/vendor'] = insnDef['vendor'][0]
|
||
|
|
|
||
|
|
if insnDef['mnemonic'] in ('lds', 'les'):
|
||
|
|
#
|
||
|
|
# Massage lds and les, which share the same prefix as AVX
|
||
|
|
# instructions, to work well with the opcode tree.
|
||
|
|
#
|
||
|
|
opcexts['/vex'] = 'none'
|
||
|
|
elif '/vex' in opcexts:
|
||
|
|
# A proper avx instruction definition; make sure there are
|
||
|
|
# no legacy opcode extensions
|
||
|
|
assert '/sse' not in opcodes
|
||
|
|
|
||
|
|
# make sure the opcode definitions don't already include
|
||
|
|
# the avx prefixes.
|
||
|
|
assert opcodes[0] not in ('c4', 'c5')
|
||
|
|
|
||
|
|
# An avx only instruction is defined by the /vex= opcode
|
||
|
|
# extension. They do not include the c4 (long form) or
|
||
|
|
# c5 (short form) prefix. As part of opcode table generate,
|
||
|
|
# here we create the long form definition, and then patch
|
||
|
|
# the table for c5 in a later stage.
|
||
|
|
# Construct a long-form definition of the avx instruction
|
||
|
|
opcodes.insert(0, 'c4')
|
||
|
|
elif (opcodes[0] == '0f' and opcodes[1] != '0f' and
|
||
|
|
'/sse' not in opcexts):
|
||
|
|
# Make all 2-byte opcode form isntructions play nice with sse
|
||
|
|
# opcode maps.
|
||
|
|
opcexts['/sse'] = 'none'
|
||
|
|
|
||
|
|
# legacy sse defs that get promoted to avx
|
||
|
|
fn = self.addInsn
|
||
|
|
if 'avx' in insnDef['cpuid'] and '/sse' in opcexts:
|
||
|
|
fn = self.addSSE2AVXInsn
|
||
|
|
|
||
|
|
fn(mnemonic = insnDef['mnemonic'],
|
||
|
|
prefixes = insnDef['prefixes'],
|
||
|
|
opcodes = opcodes,
|
||
|
|
opcexts = opcexts,
|
||
|
|
operands = insnDef['operands'],
|
||
|
|
cpuid = insnDef['cpuid'])
|
||
|
|
|
||
|
|
|
||
|
|
def addSSE2AVXInsn(self, **insnDef):
|
||
|
|
"""Add an instruction definition containing an avx cpuid bit, but
|
||
|
|
declared in its legacy SSE form. The function splits the
|
||
|
|
definition to create two new definitions, one for SSE and one
|
||
|
|
promoted to an AVX form.
|
||
|
|
"""
|
||
|
|
|
||
|
|
# SSE
|
||
|
|
ssemnemonic = insnDef['mnemonic']
|
||
|
|
sseopcodes = insnDef['opcodes']
|
||
|
|
# remove vex opcode extensions
|
||
|
|
sseopcexts = dict([(e, v) for e, v in itemslist(insnDef['opcexts'])
|
||
|
|
if not e.startswith('/vex')])
|
||
|
|
# strip out avx operands, preserving relative ordering
|
||
|
|
# of remaining operands
|
||
|
|
sseoperands = [opr for opr in insnDef['operands']
|
||
|
|
if opr not in ('H', 'L')]
|
||
|
|
# strip out avx prefixes
|
||
|
|
sseprefixes = [pfx for pfx in insnDef['prefixes']
|
||
|
|
if not pfx.startswith('vex')]
|
||
|
|
# strip out avx bits from cpuid
|
||
|
|
ssecpuid = [flag for flag in insnDef['cpuid']
|
||
|
|
if not flag.startswith('avx')]
|
||
|
|
|
||
|
|
self.addInsn(mnemonic = ssemnemonic,
|
||
|
|
prefixes = sseprefixes,
|
||
|
|
opcodes = sseopcodes,
|
||
|
|
opcexts = sseopcexts,
|
||
|
|
operands = sseoperands,
|
||
|
|
cpuid = ssecpuid)
|
||
|
|
|
||
|
|
# AVX
|
||
|
|
vexmnemonic = 'v' + insnDef['mnemonic']
|
||
|
|
vexprefixes = insnDef['prefixes']
|
||
|
|
vexopcodes = ['c4']
|
||
|
|
vexopcexts = dict([(e, insnDef['opcexts'][e])
|
||
|
|
for e in insnDef['opcexts'] if e != '/sse'])
|
||
|
|
vexopcexts['/vex'] = insnDef['opcexts']['/sse'] + '_' + '0f'
|
||
|
|
if insnDef['opcodes'][1] == '38' or insnDef['opcodes'][1] == '3a':
|
||
|
|
vexopcexts['/vex'] += insnDef['opcodes'][1]
|
||
|
|
vexopcodes.extend(insnDef['opcodes'][2:])
|
||
|
|
else:
|
||
|
|
vexopcodes.extend(insnDef['opcodes'][1:])
|
||
|
|
vexoperands = []
|
||
|
|
for o in insnDef['operands']:
|
||
|
|
# make the operand size explicit: x
|
||
|
|
if o in ('V', 'W', 'H', 'U'):
|
||
|
|
o = o + 'x'
|
||
|
|
vexoperands.append(o)
|
||
|
|
vexcpuid = [flag for flag in insnDef['cpuid']
|
||
|
|
if not flag.startswith('sse')]
|
||
|
|
|
||
|
|
self.addInsn(mnemonic = vexmnemonic,
|
||
|
|
prefixes = vexprefixes,
|
||
|
|
opcodes = vexopcodes,
|
||
|
|
opcexts = vexopcexts,
|
||
|
|
operands = vexoperands,
|
||
|
|
cpuid = vexcpuid)
|
||
|
|
|
||
|
|
def getInsnList(self):
|
||
|
|
"""Returns a list of all instructions in the collection"""
|
||
|
|
return self._insns
|
||
|
|
|
||
|
|
|
||
|
|
def getTableList(self):
|
||
|
|
"""Returns a list of all tables in the collection"""
|
||
|
|
return self._tables
|
||
|
|
|
||
|
|
def getMnemonicsList(self):
|
||
|
|
"""Returns a sorted list of mnemonics"""
|
||
|
|
return sorted(self._mnemonics.keys())
|
||
|
|
|
||
|
|
|
||
|
|
def pprint(self):
|
||
|
|
def printWalk(tbl, indent=""):
|
||
|
|
entries = tbl.entries()
|
||
|
|
for k, e in entries:
|
||
|
|
if isinstance(e, UdOpcodeTable):
|
||
|
|
self.log("%s |-<%02x> %s" % (indent, k, e))
|
||
|
|
printWalk(e, indent + " |")
|
||
|
|
elif isinstance(e, UdInsnDef):
|
||
|
|
self.log("%s |-<%02x> %s" % (indent, k, e))
|
||
|
|
printWalk(self.root)
|
||
|
|
|
||
|
|
|
||
|
|
def printStats(self):
|
||
|
|
tables = self.getTableList()
|
||
|
|
self.log("stats: ")
|
||
|
|
self.log(" Num tables = %d" % len(tables))
|
||
|
|
self.log(" Num insnDefs = %d" % len(self.getInsnList()))
|
||
|
|
self.log(" Num insns = %d" % len(self.getMnemonicsList()))
|
||
|
|
|
||
|
|
totalSize = 0
|
||
|
|
totalEntries = 0
|
||
|
|
for table in tables:
|
||
|
|
totalSize += table.size()
|
||
|
|
totalEntries += table.numEntries()
|
||
|
|
self.log(" Packing Ratio = %d%%" % ((totalEntries * 100) / totalSize))
|
||
|
|
self.log("--------------------")
|
||
|
|
|
||
|
|
self.pprint()
|
||
|
|
|
||
|
|
|
||
|
|
@staticmethod
|
||
|
|
def parseOptableXML(xml):
|
||
|
|
"""Parse udis86 optable.xml file and return list of
|
||
|
|
instruction definitions.
|
||
|
|
"""
|
||
|
|
from xml.dom import minidom
|
||
|
|
|
||
|
|
xmlDoc = minidom.parse(xml)
|
||
|
|
tlNode = xmlDoc.firstChild
|
||
|
|
insns = []
|
||
|
|
|
||
|
|
while tlNode and tlNode.localName != "x86optable":
|
||
|
|
tlNode = tlNode.nextSibling
|
||
|
|
|
||
|
|
for insnNode in tlNode.childNodes:
|
||
|
|
if not insnNode.localName:
|
||
|
|
continue
|
||
|
|
if insnNode.localName != "instruction":
|
||
|
|
raise Exception("warning: invalid insn node - %s" % insnNode.localName)
|
||
|
|
mnemonic = insnNode.getElementsByTagName('mnemonic')[0].firstChild.data
|
||
|
|
vendor, cpuid = '', []
|
||
|
|
|
||
|
|
for node in insnNode.childNodes:
|
||
|
|
if node.localName == 'vendor':
|
||
|
|
vendor = node.firstChild.data.split()
|
||
|
|
elif node.localName == 'cpuid':
|
||
|
|
cpuid = node.firstChild.data.split()
|
||
|
|
|
||
|
|
for node in insnNode.childNodes:
|
||
|
|
if node.localName == 'def':
|
||
|
|
insnDef = { 'pfx' : [] }
|
||
|
|
for node in node.childNodes:
|
||
|
|
if not node.localName:
|
||
|
|
continue
|
||
|
|
if node.localName in ('pfx', 'opc', 'opr', 'vendor', 'cpuid'):
|
||
|
|
insnDef[node.localName] = node.firstChild.data.split()
|
||
|
|
elif node.localName == 'mode':
|
||
|
|
insnDef['pfx'].extend(node.firstChild.data.split())
|
||
|
|
insns.append({'prefixes' : insnDef.get('pfx', []),
|
||
|
|
'mnemonic' : mnemonic,
|
||
|
|
'opcodes' : insnDef.get('opc', []),
|
||
|
|
'operands' : insnDef.get('opr', []),
|
||
|
|
'vendor' : insnDef.get('vendor', vendor),
|
||
|
|
'cpuid' : insnDef.get('cpuid', cpuid)})
|
||
|
|
return insns
|