164 lines
6.5 KiB
C
164 lines
6.5 KiB
C
// Copyright (c) 2022-2023 Cesanta Software Limited
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// All rights reserved
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//
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// Datasheet: RM0433, devboard manual: UM2407
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// https://www.st.com/resource/en/reference_manual/rm0433-stm32h742-stm32h743753-and-stm32h750-value-line-advanced-armbased-32bit-mcus-stmicroelectronics.pdf
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// Alternate functions: https://www.st.com/resource/en/datasheet/stm32h743vi.pdf
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#pragma once
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#include <stm32h743xx.h>
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#include <stdbool.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <string.h>
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#define BIT(x) (1UL << (x))
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#define SETBITS(R, CLEARMASK, SETMASK) (R) = ((R) & ~(CLEARMASK)) | (SETMASK)
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#define PIN(bank, num) ((((bank) - 'A') << 8) | (num))
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#define PINNO(pin) (pin & 255)
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#define PINBANK(pin) (pin >> 8)
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// System clock (2.1, Figure 1; 8.5, Figure 45; 8.5.5, Figure 47; 8.5.6, Figure
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// 49) CPU_FREQUENCY <= 480 MHz; hclk = CPU_FREQUENCY / HPRE ; hclk <= 240 MHz;
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// APB clocks <= 120 MHz. D1 domain bus matrix (and so flash) runs at hclk
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// frequency. Configure flash latency (WS) in accordance to hclk freq (4.3.8,
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// Table 17) The Ethernet controller is in D2 domain and runs at hclk frequency
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enum {
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D1CPRE = 1, // actual divisor value
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HPRE = 2, // actual divisor value
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D1PPRE = 4, // register values, divisor value = BIT(value - 3) = / 2
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D2PPRE1 = 4,
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D2PPRE2 = 4,
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D3PPRE = 4
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};
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// PLL1_P: odd division factors are not allowed (8.7.13) (according to Cube, '1'
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// is also an "odd division factor").
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// Make sure your chip is revision 'V', otherwise set PLL1_N = 400
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enum { PLL1_HSI = 64, PLL1_M = 32, PLL1_N = 480, PLL1_P = 2 };
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#define FLASH_LATENCY 0x24 // WRHIGHFREQ LATENCY
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#define CPU_FREQUENCY ((PLL1_HSI * PLL1_N / PLL1_M / PLL1_P / D1CPRE) * 1000000)
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// #define CPU_FREQUENCY ((PLL1_HSI / D1CPRE) * 1000000)
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#define AHB_FREQUENCY (CPU_FREQUENCY / HPRE)
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#define APB2_FREQUENCY (AHB_FREQUENCY / (BIT(D2PPRE2 - 3)))
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#define APB1_FREQUENCY (AHB_FREQUENCY / (BIT(D2PPRE1 - 3)))
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static inline void spin(volatile uint32_t n) {
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while (n--) (void) 0;
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}
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enum { GPIO_MODE_INPUT, GPIO_MODE_OUTPUT, GPIO_MODE_AF, GPIO_MODE_ANALOG };
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enum { GPIO_OTYPE_PUSH_PULL, GPIO_OTYPE_OPEN_DRAIN };
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enum { GPIO_SPEED_LOW, GPIO_SPEED_MEDIUM, GPIO_SPEED_HIGH, GPIO_SPEED_INSANE };
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enum { GPIO_PULL_NONE, GPIO_PULL_UP, GPIO_PULL_DOWN };
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#define GPIO(N) ((GPIO_TypeDef *) (0x40000000 + 0x18020000UL + 0x400 * (N)))
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static GPIO_TypeDef *gpio_bank(uint16_t pin) { return GPIO(PINBANK(pin)); }
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static inline void gpio_toggle(uint16_t pin) {
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GPIO_TypeDef *gpio = gpio_bank(pin);
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uint32_t mask = BIT(PINNO(pin));
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gpio->BSRR = mask << (gpio->ODR & mask ? 16 : 0);
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}
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static inline int gpio_read(uint16_t pin) {
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return gpio_bank(pin)->IDR & BIT(PINNO(pin)) ? 1 : 0;
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}
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static inline void gpio_write(uint16_t pin, bool val) {
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GPIO_TypeDef *gpio = gpio_bank(pin);
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gpio->BSRR = BIT(PINNO(pin)) << (val ? 0 : 16);
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}
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static inline void gpio_init(uint16_t pin, uint8_t mode, uint8_t type,
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uint8_t speed, uint8_t pull, uint8_t af) {
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GPIO_TypeDef *gpio = gpio_bank(pin);
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uint8_t n = (uint8_t) (PINNO(pin));
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RCC->AHB4ENR |= BIT(PINBANK(pin)); // Enable GPIO clock
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SETBITS(gpio->OTYPER, 1UL << n, ((uint32_t) type) << n);
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SETBITS(gpio->OSPEEDR, 3UL << (n * 2), ((uint32_t) speed) << (n * 2));
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SETBITS(gpio->PUPDR, 3UL << (n * 2), ((uint32_t) pull) << (n * 2));
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SETBITS(gpio->AFR[n >> 3], 15UL << ((n & 7) * 4),
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((uint32_t) af) << ((n & 7) * 4));
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SETBITS(gpio->MODER, 3UL << (n * 2), ((uint32_t) mode) << (n * 2));
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}
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static inline void gpio_input(uint16_t pin) {
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gpio_init(pin, GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
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GPIO_PULL_NONE, 0);
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}
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static inline void gpio_output(uint16_t pin) {
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gpio_init(pin, GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
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GPIO_PULL_NONE, 0);
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}
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#ifndef UART_DEBUG
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#define UART_DEBUG USART1
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#endif
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// D2 Kernel clock (8.7.21) USART1 defaults to pclk2 (APB2), while USART2,3
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// default to pclk1 (APB1). Even if using other kernel clocks, the APBx clocks
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// must be enabled for CPU access, as the kernel clock drives the BRR, not the
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// APB bus interface
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static inline void uart_init(USART_TypeDef *uart, unsigned long baud) {
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uint8_t af = 7; // Alternate function
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uint16_t rx = 0, tx = 0; // pins
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uint32_t freq = 0; // Bus frequency. UART1 is on APB2, rest on APB1
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if (uart == USART1) freq = APB2_FREQUENCY, RCC->APB2ENR |= BIT(4);
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if (uart == USART2) freq = APB1_FREQUENCY, RCC->APB1LENR |= BIT(17);
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if (uart == USART3) freq = APB1_FREQUENCY, RCC->APB1LENR |= BIT(18);
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if (uart == USART1) tx = PIN('A', 9), rx = PIN('A', 10);
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if (uart == USART2) tx = PIN('A', 2), rx = PIN('A', 3);
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if (uart == USART3) tx = PIN('D', 8), rx = PIN('D', 9);
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#if 0 // CONSTANT BAUD RATE FOR REMOTE DEBUGGING WHILE SETTING THE PLL
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SETBITS(RCC->D2CCIP2R, 7 << 3, 3 << 3); // use HSI for UART1
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freq = 64000000;
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#endif
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gpio_init(tx, GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, 0, af);
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gpio_init(rx, GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, 0, af);
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uart->CR1 = 0; // Disable this UART
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uart->BRR = freq / baud; // Set baud rate
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uart->CR1 = BIT(0) | BIT(2) | BIT(3); // Set UE, RE, TE
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}
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static inline void uart_write_byte(USART_TypeDef *uart, uint8_t byte) {
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uart->TDR = byte;
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while ((uart->ISR & BIT(7)) == 0) spin(1);
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}
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static inline void uart_write_buf(USART_TypeDef *uart, char *buf, size_t len) {
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while (len-- > 0) uart_write_byte(uart, *(uint8_t *) buf++);
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}
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static inline int uart_read_ready(USART_TypeDef *uart) {
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return uart->ISR & BIT(5); // If RXNE bit is set, data is ready
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}
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static inline uint8_t uart_read_byte(USART_TypeDef *uart) {
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return (uint8_t) (uart->RDR & 255);
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}
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static inline void rng_init(void) {
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RCC->D2CCIP2R |= RCC_D2CCIP2R_RNGSEL_0; // RNG clock source pll1_q_ck
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RCC->AHB2ENR |= RCC_AHB2ENR_RNGEN; // Enable RNG clock
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RNG->CR = RNG_CR_RNGEN; // Enable RNG
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}
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static inline uint32_t rng_read(void) {
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while ((RNG->SR & RNG_SR_DRDY) == 0) (void) 0;
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return RNG->DR;
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}
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static inline char chiprev(void) {
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uint16_t rev = (uint16_t) (((uint32_t) DBGMCU->IDCODE) >> 16);
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if (rev == 0x1003) return 'Y';
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if (rev == 0x2003) return 'V';
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return '?';
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}
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#define UUID ((uint8_t *) UID_BASE) // Unique 96-bit chip ID. TRM 61.1
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// Helper macro for MAC generation
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#define GENERATE_LOCALLY_ADMINISTERED_MAC() \
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{ \
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2, UUID[0] ^ UUID[1], UUID[2] ^ UUID[3], UUID[4] ^ UUID[5], \
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UUID[6] ^ UUID[7] ^ UUID[8], UUID[9] ^ UUID[10] ^ UUID[11] \
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}
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