2784 lines
414 KiB
JSON
2784 lines
414 KiB
JSON
{
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"instructions": [
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{"category": "GP", "data": [
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{"inst": "adc Rd!=PC, Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|0101|0|Rn|Rd|Rs|0|sop:2|1|Rm" , "io": "C=R"},
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{"inst": "adc Rd, Rn, Rm, {sop #n}" , "a32": "cond|000|0101|0|Rn|Rd|n:5|sop:2|0|Rm" , "io": "C=R"},
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{"inst": "adc Rd, Rn, #immA" , "a32": "cond|001|0101|0|Rn|Rd|imm:12" , "io": "C=R"},
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{"inst": "adcS Rd!=PC, Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|0101|1|Rn|Rd|Rs|0|sop:2|1|Rm" , "io": "N=W Z=W C=X V=W"},
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{"inst": "adcS Rd!=PC, Rn, Rm, {sop #n}" , "a32": "cond|000|0101|1|Rn|Rd|n:5|sop:2|0|Rm" , "io": "N=W Z=W C=X V=W"},
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{"inst": "adcS Rd!=PC, Rn, #immA" , "a32": "cond|001|0101|1|Rn|Rd|imm:12" , "io": "N=W Z=W C=X V=W"},
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{"inst": "add Rd!=PC, Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|0100|0|Rn|Rd|Rs|0|sop:2|1|Rm"},
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{"inst": "add Rd, Rn, Rm, {sop #n}" , "a32": "cond|000|0100|0|Rn|Rd|n:5|sop:2|0|Rm"},
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{"inst": "add Rd, Rn!=PC, #immA" , "a32": "cond|001|0100|0|Rn|Rd|imm:12"},
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{"inst": "addS Rd!=PC, Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|0100|1|Rn|Rd|Rs|0|sop:2|1|Rm" , "io": "N=W Z=W C=W V=W"},
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{"inst": "addS Rd!=PC, Rn, Rm, {sop #n}" , "a32": "cond|000|0100|1|Rn|Rd|n:5|sop:2|0|Rm" , "io": "N=W Z=W C=W V=W"},
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{"inst": "addS Rd!=PC, Rn, #immA" , "a32": "cond|001|0100|1|Rn|Rd|imm:12" , "io": "N=W Z=W C=W V=W"},
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{"inst": "adr Rd, #relA" , "a32": "cond|001|0PN0|0|1111|Rd|relA:12"},
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{"inst": "and Rd!=PC, Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|0000|0|Rn|Rd|Rs|0|sop:2|1|Rm"},
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{"inst": "and Rd, Rn, Rm, {sop #n}" , "a32": "cond|000|0000|0|Rn|Rd|n:5|sop:2|0|Rm"},
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{"inst": "and Rd, Rn, #immA" , "a32": "cond|001|0000|0|Rn|Rd|imm:12"},
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{"inst": "andS Rd!=PC, Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|0000|1|Rn|Rd|Rs|0|sop:2|1|Rm" , "io": "N=W Z=W C=W"},
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{"inst": "andS Rd!=PC, Rn, Rm, {sop #n}" , "a32": "cond|000|0000|1|Rn|Rd|n:5|sop:2|0|Rm" , "io": "N=W Z=W C=W"},
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{"inst": "andS Rd!=PC, Rn, #immA" , "a32": "cond|001|0000|1|Rn|Rd|imm:12" , "io": "N=W Z=W C=W"},
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{"inst": "asr Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1101|0|0000|Rd|Rm|0101|Rn"},
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{"inst": "asr Rd, Rn, #n" , "a32": "cond|000|1101|0|0000|Rd|n:5|100|Rn"},
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{"inst": "asrS Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1101|1|0000|Rd|Rm|0101|Rn" , "io": "N=W Z=W C=W"},
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{"inst": "asrS Rd, Rn, #n" , "a32": "cond|000|1101|1|0000|Rd|n:5|100|Rn" , "io": "N=W Z=W C=W"},
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{"inst": "b #relS*4" , "a32": "cond|101|0|relS:24"},
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{"inst": "bfc Rd!=PC, #lsb, #width" , "a32": "cond|011|1110|msb:5|Rd|lsb:5|001|1111" , "imm": "BfcBfiImm(lsb, width)"},
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{"inst": "bfi Rd!=PC, Rn!=PC, #lsb, #width" , "a32": "cond|011|1110|msb:5|Rd|lsb:5|001|Rn" , "imm": "BfcBfiImm(lsb, width)"},
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{"inst": "bic Rd!=PC, Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|1110|0|Rn|Rd|Rs|0|sop:2|1|Rm"},
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{"inst": "bic Rd, Rn, Rm, {sop #n}" , "a32": "cond|000|1110|0|Rn|Rd|n:5|sop:2|0|Rm"},
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{"inst": "bic Rd, Rn, #immA" , "a32": "cond|001|1110|0|Rn|Rd|imm:12"},
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{"inst": "bicS Rd!=PC, Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|1110|1|Rn|Rd|Rs|0|sop:2|1|Rm" , "io": "N=W Z=W C=W"},
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{"inst": "bicS Rd!=PC, Rn, Rm, {sop #n}" , "a32": "cond|000|1110|1|Rn|Rd|n:5|sop:2|0|Rm" , "io": "N=W Z=W C=W"},
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{"inst": "bicS Rd!=PC, Rn, #immA" , "a32": "cond|001|1110|1|Rn|Rd|imm:12" , "io": "N=W Z=W C=W"},
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{"inst": "bkpt #immZ" , "a32": "cond|000|1001|0|immZ:12|0111|immZ:4"},
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{"inst": "bl #relS*4" , "a32": "cond|101|1|relS:24"},
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{"inst": "blx Rm!=PC" , "a32": "cond|000|1001|0|1111|1111|1111|0011|Rm"},
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{"inst": "blx #relS*2" , "a32": "1111|101|relS[0]|relS[24:1]" },
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{"inst": "bx Rm" , "a32": "cond|000|1001|0|1111|1111|1111|0001|Rm"},
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{"inst": "bxj Rm!=PC" , "a32": "cond|000|1001|0|1111|1111|1111|0010|Rm"},
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{"inst": "clz Rd!=PC, Rn!=PC" , "a32": "cond|000|1011|0|1111|Rd|1111|0001|Rn"},
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{"inst": "cmn Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|1011|1|Rn|0000|Rs|0|sop:2|1|Rm" , "io": "N=W Z=W C=W V=W"},
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{"inst": "cmn Rn, Rm, {sop #n}" , "a32": "cond|000|1011|1|Rn|0000|n:5|sop:2|0|Rm" , "io": "N=W Z=W C=W V=W"},
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{"inst": "cmn Rn, #immA" , "a32": "cond|001|1011|1|Rn|0000|imm:12" , "io": "N=W Z=W C=W V=W"},
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{"inst": "cmp Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|1010|1|Rn|0000|Rs|0|sop:2|1|Rm" , "io": "N=W Z=W C=W V=W"},
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{"inst": "cmp Rn, Rm, {sop #n}" , "a32": "cond|000|1010|1|Rn|0000|n:5|sop:2|0|Rm" , "io": "N=W Z=W C=W V=W"},
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{"inst": "cmp Rn, #immA" , "a32": "cond|001|1010|1|Rn|0000|imm:12" , "io": "N=W Z=W C=W V=W"},
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{"inst": "cps #immZ" , "a32": "1111|000|1000|0|0010|0000|000|000|0|immZ:5"},
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{"inst": "cpsid #aif" , "a32": "1111|000|1000|0|1100|0000|000|aif:3|0|00000"},
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{"inst": "cpsid #aif, #immZ" , "a32": "1111|000|1000|0|1110|0000|000|aif:3|0|immZ:5"},
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{"inst": "cpsie #aif" , "a32": "1111|000|1000|0|1000|0000|000|aif:3|0|00000"},
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{"inst": "cpsie #aif, #immZ" , "a32": "1111|000|1000|0|1010|0000|000|aif:3|0|immZ:5"},
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{"inst": "eor Rd!=PC, Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|0001|0|Rn|Rd|Rs|0|sop:2|1|Rm"},
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{"inst": "eor Rd, Rn, Rm, {sop #n}" , "a32": "cond|000|0001|0|Rn|Rd|n:5|sop:2|0|Rm"},
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{"inst": "eor Rd, Rn, #immA" , "a32": "cond|001|0001|0|Rn|Rd|imm:12"},
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{"inst": "eorS Rd!=PC, Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|0001|1|Rn|Rd|Rs|0|sop:2|1|Rm" , "io": "N=W Z=W C=W"},
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{"inst": "eorS Rd!=PC, Rn, Rm, {sop #n}" , "a32": "cond|000|0001|1|Rn|Rd|n:5|sop:2|0|Rm" , "io": "N=W Z=W C=W"},
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{"inst": "eorS Rd!=PC, Rn, #immA" , "a32": "cond|001|0001|1|Rn|Rd|imm:12" , "io": "N=W Z=W C=W"},
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{"inst": "eret" , "a32": "cond|000|1011|0|0000|0000|0000|0110|1110"},
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{"inst": "hlt #immZ" , "a32": "1110|000|1000|0|immZ:12|0111|immZ:4"},
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{"inst": "hvc #immZ" , "a32": "cond|000|1010|0|immZ:12|0111|immZ:4"},
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{"inst": "ldmda [Rn!=PC]{!}, RdList" , "a32": "cond|100|000W|1|Rn|immMask:16" , "imm": "GpListImm(RdList)"},
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{"inst": "ldmdb [Rn!=PC]{!}, RdList" , "a32": "cond|100|100W|1|Rn|immMask:16" , "imm": "GpListImm(RdList)"},
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{"inst": "ldmia [Rn!=PC]{!}, RdList" , "a32": "cond|100|010W|1|Rn|immMask:16" , "imm": "GpListImm(RdList)"},
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{"inst": "ldmib [Rn!=PC]{!}, RdList" , "a32": "cond|100|110W|1|Rn|immMask:16" , "imm": "GpListImm(RdList)"},
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{"inst": "ldmda [Rn!=PC], RdList^" , "a32": "cond|100|0010|1|Rn|immMask:16" , "imm": "GpListImm(RdList)"},
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{"inst": "ldmdb [Rn!=PC], RdList^" , "a32": "cond|100|1010|1|Rn|immMask:16" , "imm": "GpListImm(RdList)"},
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{"inst": "ldmia [Rn!=PC], RdList^" , "a32": "cond|100|0110|1|Rn|immMask:16" , "imm": "GpListImm(RdList)"},
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{"inst": "ldmib [Rn!=PC], RdList^" , "a32": "cond|100|1110|1|Rn|immMask:16" , "imm": "GpListImm(RdList)"},
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{"inst": "ldr Rd, [Rn!=PC, +/-Rm!=PC, {sop #n}]{@}{!}" , "a32": "cond|011|PU0W|1|Rn|Rd|n:5|sop:2|0|Rm"},
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{"inst": "ldr Rd, [Rn!=PC, #+/-off]{@}{!}" , "a32": "cond|010|PU0W|1|Rn|Rd|off:12"},
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{"inst": "ldr Rd, [Rn==PC, #+/-off]" , "a32": "cond|010|1U00|1|Rn|Rd|off:12"},
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{"inst": "ldrb Rd!=PC, [Rn!=PC, +/-Rm!=PC, {sop #n}]{@}{!}" , "a32": "cond|011|PU1W|1|Rn|Rd|n:5|sop:2|0|Rm"},
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{"inst": "ldrb Rd!=PC, [Rn!=PC, #+/-off]{@}{!}" , "a32": "cond|010|PU1W|1|Rn|Rd|off:12"},
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{"inst": "ldrb Rd!=PC, [Rn==PC, #+/-off]" , "a32": "cond|010|1U10|1|Rn|Rd|off:12"},
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{"inst": "ldrbt Rd!=PC, [Rn!=PC, +/-Rm!=PC, {sop #n}]@" , "a32": "cond|011|0U11|1|Rn|Rd|n:5|sop:2|0|Rm"},
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{"inst": "ldrbt Rd!=PC, [Rn!=PC, #+/-off]@" , "a32": "cond|010|0U11|1|Rn|Rd|off:12"},
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{"inst": "ldrd Rd<=13, Rd2+, [Rn!=PC, +/-Rm]{@}{!}" , "a32": "cond|000|PU0W|0|Rn|Rd|0000|1101|Rm"},
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{"inst": "ldrd Rd<=13, Rd2+, [Rn!=PC, #+/-off]{!}" , "a32": "cond|000|PU1W|0|Rn|Rd|off:4|1101|off:4"},
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{"inst": "ldrd Rd<=13, Rd2+, [Rn==PC, #+/-off]" , "a32": "cond|000|1U10|0|Rn|Rd|off:4|1101|off:4"},
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{"inst": "ldrex Rd!=PC, [Rn!=PC]" , "a32": "cond|000|1100|1|Rn|Rd|1111|1001|1111"},
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{"inst": "ldrexb Rd!=PC, [Rn!=PC]" , "a32": "cond|000|1110|1|Rn|Rd|1111|1001|1111"},
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{"inst": "ldrexd Rd<=13, Rd2+, [Rn!=PC]" , "a32": "cond|000|1101|1|Rn|Rd|1111|1001|1111"},
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{"inst": "ldrexh Rd!=PC, [Rn!=PC]" , "a32": "cond|000|1111|1|Rn|Rd|1111|1001|1111"},
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{"inst": "ldrh Rd!=PC, [Rn!=PC, +/-Rm!=PC]{@}{!}" , "a32": "cond|000|PU0W|1|Rn|Rd|0000|1011|Rm"},
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{"inst": "ldrh Rd!=PC, [Rn!=PC, #+/-off]{@}{!}" , "a32": "cond|000|PU1W|1|Rn|Rd|off:4|1011|off:4"},
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{"inst": "ldrh Rd!=PC, [Rn==PC, #+/-off]" , "a32": "cond|000|1U10|1|Rn|Rd|off:4|1011|off:4"},
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{"inst": "ldrht Rd!=PC, [Rn!=PC, +/-Rm!=PC]@" , "a32": "cond|000|0U01|1|Rn|Rd|0000|1011|Rm"},
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{"inst": "ldrht Rd!=PC, [Rn!=PC, #+/-off]@" , "a32": "cond|000|0U11|1|Rn|Rd|off:4|1011|off:4"},
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{"inst": "ldrsb Rd!=PC, [Rn!=PC, +/-Rm!=PC]{@}{!}" , "a32": "cond|000|PU0W|1|Rn|Rd|0000|1101|Rm"},
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{"inst": "ldrsb Rd!=PC, [Rn!=PC, #+/-off]{@}{!}" , "a32": "cond|000|PU1W|1|Rn|Rd|off:4|1101|off:4"},
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{"inst": "ldrsb Rd!=PC, [Rn==PC, #+/-off]" , "a32": "cond|000|1U10|1|Rn|Rd|off:4|1101|off:4"},
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{"inst": "ldrsbt Rd!=PC, [Rn!=PC, +/-Rm]@" , "a32": "cond|000|0U01|1|Rn|Rd|0000|1101|Rm"},
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{"inst": "ldrsbt Rd!=PC, [Rn!=PC, #+/-off]@" , "a32": "cond|000|0U11|1|Rn|Rd|off:4|1101|off:4"},
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{"inst": "ldrsh Rd!=PC, [Rn!=PC, +/-Rm!=PC]{@}{!}" , "a32": "cond|000|PU0W|1|Rn|Rd|0000|1111|Rm"},
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{"inst": "ldrsh Rd!=PC, [Rn!=PC, #+/-off]{@}{!}" , "a32": "cond|000|PU1W|1|Rn|Rd|off:4|1111|off:4"},
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{"inst": "ldrsh Rd!=PC, [Rn==PC, #+/-off]" , "a32": "cond|000|1U10|1|Rn|Rd|off:4|1111|off:4"},
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{"inst": "ldrsht Rd!=PC, [Rn!=PC, #+/-off]@" , "a32": "cond|000|0U11|1|Rn|Rd|off:4|1111|off:4"},
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{"inst": "ldrsht Rd!=PC, [Rn!=PC, +/-Rm!=PC]@" , "a32": "cond|000|0U01|1|Rn|Rd|0000|1111|Rm"},
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{"inst": "ldrt Rd!=PC, [Rn!=PC, +/-Rm!=PC, {sop #n}]@" , "a32": "cond|011|0U01|1|Rn|Rd|n:5|sop:2|0|Rm"},
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{"inst": "ldrt Rd!=PC, [Rn!=PC, #+/-off]@" , "a32": "cond|010|0U01|1|Rn|Rd|off:12"},
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{"inst": "lsl Rd, Rn, #n" , "a32": "cond|000|1101|0|0000|Rd|n:5|000|Rn"},
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{"inst": "lsl Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1101|0|0000|Rd|Rm|0001|Rn"},
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{"inst": "lslS Rd, Rn, #n" , "a32": "cond|000|1101|1|0000|Rd|n:5|000|Rn" , "io": "N=W Z=W C=W"},
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{"inst": "lslS Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1101|1|0000|Rd|Rm|0001|Rn" , "io": "N=W Z=W C=W"},
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{"inst": "lsr Rd, Rn, #n" , "a32": "cond|000|1101|0|0000|Rd|n:5|010|Rn"},
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{"inst": "lsr Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1101|0|0000|Rd|Rm|0011|Rn"},
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{"inst": "lsrS Rd, Rn, #n" , "a32": "cond|000|1101|1|0000|Rd|n:5|010|Rn" , "io": "N=W Z=W C=W"},
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{"inst": "lsrS Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1101|1|0000|Rd|Rm|0011|Rn" , "io": "N=W Z=W C=W"},
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{"inst": "mcr #CP, #Op1, Rs!=PC, Cn, Cm, {#Op2}" , "a32": "cond|111|0|Op1:3|0|Cn:4|Rs|CP:4|Op2:3|1|Cm:4"},
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{"inst": "mcr2 #CP, #Op1, Rs!=PC, Cn, Cm, {#Op2}" , "a32": "1111|111|0|Op1:3|0|Cn:4|Rs|CP:4|Op2:3|1|Cm:4"},
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{"inst": "mcrr #CP, #Op1, Rs!=PC, Rs2!=PC, Cm" , "a32": "cond|110|0010|0|Rs2|Rs|CP:4|Op1:4|Cm:4"},
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{"inst": "mcrr2 #CP, #Op1, Rs!=PC, Rs2!=PC, Cm" , "a32": "1111|110|0010|0|Rs2|Rs|CP:4|Op1:4|Cm:4"},
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{"inst": "mla Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "a32": "cond|000|0001|0|Rd|Ra|Rm|1001|Rn"},
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{"inst": "mlaS Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "a32": "cond|000|0001|1|Rd|Ra|Rm|1001|Rn" , "io": "N=W Z=W"},
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{"inst": "mls Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "a32": "cond|000|0011|0|Rd|Ra|Rm|1001|Rn"},
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{"inst": "mov Rd, Rn, sop Rs" , "a32": "cond|000|1101|0|0000|Rd|Rs|0|sop:2|1|Rn"},
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{"inst": "mov Rd, Rn, {sop #n}" , "a32": "cond|000|1101|0|0000|Rd|n:5|sop:2|0|Rn"},
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{"inst": "mov Rd, #immA" , "a32": "cond|001|1101|0|0000|Rd|imm:12"},
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{"inst": "movS Rd!=PC, Rn, sop Rs" , "a32": "cond|000|1101|1|0000|Rd|Rs|0|sop:2|1|Rn" , "io": "N=W Z=W C=W"},
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{"inst": "movS Rd!=PC, Rn, {sop #n}" , "a32": "cond|000|1101|1|0000|Rd|n:5|sop:2|0|Rn" , "io": "N=W Z=W C=W"},
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{"inst": "movS Rd!=PC, #immA" , "a32": "cond|001|1101|1|0000|Rd|imm:12" , "io": "N=W Z=W C=W"},
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{"inst": "movt Rx!=PC, #immZ" , "a32": "cond|001|1010|0|immZ:4|Rx|immZ:12"},
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{"inst": "movw Rd!=PC, #immZ" , "a32": "cond|001|1000|0|immZ:4|Rd|immZ:12"},
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{"inst": "mrc #CP, #op1, Rd!=PC, Cn, Cm, {#op2}" , "a32": "cond|111|0|op1:3|1|Cn:4|Rd|CP:4|op2:3|1|Cm:4"},
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{"inst": "mrc2 #CP, #op1, Rd!=PC, Cn, Cm, {#op2}" , "a32": "1111|111|0|op1:3|1|Cn:4|Rd|CP:4|op2:3|1|Cm:4"},
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{"inst": "mrrc #CP, #op1, Rd!=PC, Rd2!=Rd, Cm" , "a32": "cond|110|0010|1|Rd2|Rd|CP:4|op1:4|Cm:4"},
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{"inst": "mrrc2 #CP, #op1, Rd!=PC, Rd2!=Rd, Cm" , "a32": "1111|110|0010|1|Rd2|Rd|CP:4|op1:4|Cm:4"},
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{"inst": "mrs Rd!=PC, #APSR" , "a32": "cond|000|10|APSR:1|0|0|1111|Rd|0000|0000|0000"},
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{"inst": "msr #APSR, Rn!=PC" , "a32": "cond|000|1001|0|APSR:2|00|1111|0000|0000|Rn"},
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{"inst": "msr #APSR, #immA" , "a32": "cond|001|1001|0|APSR:2|00|1111|imm:12"},
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{"inst": "mul Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|0000|0|Rd|0000|Rm|1001|Rn"},
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{"inst": "mulS Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|0000|1|Rd|0000|Rm|1001|Rn" , "io": "N=W Z=W"},
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{"inst": "mvn Rd!=PC, Rn!=PC, sop Rs!=PC" , "a32": "cond|000|1111|0|0000|Rd|Rs|0|sop:2|1|Rn"},
|
|
{"inst": "mvn Rd, Rn, {sop #n}" , "a32": "cond|000|1111|0|0000|Rd|n:5|sop:2|0|Rn"},
|
|
{"inst": "mvn Rd, #immA" , "a32": "cond|001|1111|0|0000|Rd|imm:12"},
|
|
{"inst": "mvnS Rd!=PC, Rn!=PC, sop Rs!=PC" , "a32": "cond|000|1111|1|0000|Rd|Rs|0|sop:2|1|Rn" , "io": "N=W Z=W C=W"},
|
|
{"inst": "mvnS Rd!=PC, Rn, {sop #n}" , "a32": "cond|000|1111|1|0000|Rd|n:5|sop:2|0|Rn" , "io": "N=W Z=W C=W"},
|
|
{"inst": "mvnS Rd!=PC, #immA" , "a32": "cond|001|1111|1|0000|Rd|imm:12" , "io": "N=W Z=W C=W"},
|
|
{"inst": "nop" , "a32": "cond|001|1001|0|0000|1111|0000|0000|0000"},
|
|
{"inst": "orr Rd!=PC, Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|1100|0|Rn|Rd|Rs|0|sop:2|1|Rm"},
|
|
{"inst": "orr Rd, Rn, Rm, {sop #n}" , "a32": "cond|000|1100|0|Rn|Rd|n:5|sop:2|0|Rm"},
|
|
{"inst": "orr Rd, Rn, #immA" , "a32": "cond|001|1100|0|Rn|Rd|imm:12"},
|
|
{"inst": "orrS Rd!=PC, Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|1100|1|Rn|Rd|Rs|0|sop:2|1|Rm" , "io": "N=W Z=W C=W"},
|
|
{"inst": "orrS Rd!=PC, Rn, Rm, {sop #n}" , "a32": "cond|000|1100|1|Rn|Rd|n:5|sop:2|0|Rm" , "io": "N=W Z=W C=W"},
|
|
{"inst": "orrS Rd!=PC, Rn, #immA" , "a32": "cond|001|1100|1|Rn|Rd|imm:12" , "io": "N=W Z=W C=W"},
|
|
{"inst": "pkhbt Rd!=PC, Rn!=PC, Rm!=PC, {lsl #n}" , "a32": "cond|011|0100|0|Rn|Rd|n:5|0|01|Rm"},
|
|
{"inst": "pkhtb Rd!=PC, Rn!=PC, Rm!=PC, {asr #n}" , "a32": "cond|011|0100|0|Rn|Rd|n:5|1|01|Rm"},
|
|
{"inst": "pld [Rn!=PC, +/-Rm!=PC, {sop #n}]" , "a32": "1111|011|1U10|1|Rn|1111|n:5|sop:2|0|Rm"},
|
|
{"inst": "pld [Rn, #+/-off]" , "a32": "1111|010|1U10|1|Rn|1111|off:12"},
|
|
{"inst": "pop Rd!=SP" , "a32": "cond|010|0100|1|1101|Rd|0000|0000|0100"},
|
|
{"inst": "pop RdList" , "a32": "cond|100|0101|1|1101|immMask:16" , "imm": "GpListImm(RdList)"},
|
|
{"inst": "push Rs!=SP" , "a32": "cond|010|1001|0|1101|Rs|0000|0000|0100"},
|
|
{"inst": "push RsList" , "a32": "cond|100|1001|0|1101|immMask:16" , "imm": "GpListImm(RsList)"},
|
|
{"inst": "qadd Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1000|0|Rm|Rd|0000|0101|Rn" , "io": "Q=X"},
|
|
{"inst": "qadd16 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0001|0|Rn|Rd|1111|0001|Rm"},
|
|
{"inst": "qadd8 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0001|0|Rn|Rd|1111|1001|Rm"},
|
|
{"inst": "qasx Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0001|0|Rn|Rd|1111|0011|Rm"},
|
|
{"inst": "qdadd Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1010|0|Rm|Rd|0000|0101|Rn" , "io": "Q=X"},
|
|
{"inst": "qdsub Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1011|0|Rm|Rd|0000|0101|Rn" , "io": "Q=X"},
|
|
{"inst": "qsax Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0001|0|Rn|Rd|1111|0101|Rm"},
|
|
{"inst": "qsub Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1001|0|Rm|Rd|0000|0101|Rn" , "io": "Q=X"},
|
|
{"inst": "qsub16 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0001|0|Rn|Rd|1111|0111|Rm"},
|
|
{"inst": "qsub8 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0001|0|Rn|Rd|1111|1111|Rm"},
|
|
{"inst": "rbit Rd!=PC, Rn!=PC" , "a32": "cond|011|0111|1|1111|Rd|1111|0011|Rn"},
|
|
{"inst": "rev Rd!=PC, Rn!=PC" , "a32": "cond|011|0101|1|1111|Rd|1111|0011|Rn"},
|
|
{"inst": "rev16 Rd!=PC, Rn!=PC" , "a32": "cond|011|0101|1|1111|Rd|1111|1011|Rn"},
|
|
{"inst": "revsh Rd!=PC, Rn!=PC" , "a32": "cond|011|0111|1|1111|Rd|1111|1011|Rn"},
|
|
{"inst": "rfeda [Rn!=PC]{!}" , "a32": "1111|100|000|W|1|Rn|0000|1010|0000|0000"},
|
|
{"inst": "rfedb [Rn!=PC]{!}" , "a32": "1111|100|100|W|1|Rn|0000|1010|0000|0000"},
|
|
{"inst": "rfeia [Rn!=PC]{!}" , "a32": "1111|100|010|W|1|Rn|0000|1010|0000|0000"},
|
|
{"inst": "rfeib [Rn!=PC]{!}" , "a32": "1111|100|110|W|1|Rn|0000|1010|0000|0000"},
|
|
{"inst": "ror Rd, Rn, #n" , "a32": "cond|000|1101|0|0000|Rd|n:5|110|Rn"},
|
|
{"inst": "ror Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1101|0|0000|Rd|Rm|0111|Rn"},
|
|
{"inst": "rorS Rd, Rn, #n" , "a32": "cond|000|1101|1|0000|Rd|n:5|110|Rn" , "io": "N=W Z=W C=W"},
|
|
{"inst": "rorS Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1101|1|0000|Rd|Rm|0111|Rn" , "io": "N=W Z=W C=W"},
|
|
{"inst": "rsb Rd!=PC, Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|0011|0|Rn|Rd|Rs|0|sop:2|1|Rm"},
|
|
{"inst": "rsb Rd, Rn, Rm, {sop #n}" , "a32": "cond|000|0011|0|Rn|Rd|n:5|sop:2|0|Rm"},
|
|
{"inst": "rsb Rd, Rn, #immA" , "a32": "cond|001|0011|0|Rn|Rd|imm:12"},
|
|
{"inst": "rsbS Rd!=PC, Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|0011|1|Rn|Rd|Rs|0|sop:2|1|Rm" , "io": "N=W Z=W C=W V=W"},
|
|
{"inst": "rsbS Rd!=PC, Rn, Rm, {sop #n}" , "a32": "cond|000|0011|1|Rn|Rd|n:5|sop:2|0|Rm" , "io": "N=W Z=W C=W V=W"},
|
|
{"inst": "rsbS Rd!=PC, Rn, #immA" , "a32": "cond|001|0011|1|Rn|Rd|imm:12" , "io": "N=W Z=W C=W V=W"},
|
|
{"inst": "rsc Rd!=PC, Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|0111|0|Rn|Rd|Rs|0|sop:2|1|Rm"},
|
|
{"inst": "rsc Rd, Rn, Rm, {sop #n}" , "a32": "cond|000|0111|0|Rn|Rd|n:5|sop:2|0|Rm"},
|
|
{"inst": "rsc Rd, Rn, #immA" , "a32": "cond|001|0111|0|Rn|Rd|imm:12"},
|
|
{"inst": "rscS Rd!=PC, Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|0111|1|Rn|Rd|Rs|0|sop:2|1|Rm" , "io": "N=W Z=W C=W V=W"},
|
|
{"inst": "rscS Rd!=PC, Rn, Rm, {sop #n}" , "a32": "cond|000|0111|1|Rn|Rd|n:5|sop:2|0|Rm" , "io": "N=W Z=W C=W V=W"},
|
|
{"inst": "rscS Rd!=PC, Rn, #immA" , "a32": "cond|001|0111|1|Rn|Rd|imm:12" , "io": "N=W Z=W C=W V=W"},
|
|
{"inst": "rrx Rd, Rn" , "a32": "cond|000|1101|0|0000|Rd|00000|110|Rn" , "io": "C=R"},
|
|
{"inst": "rrxS Rd, Rn" , "a32": "cond|000|1101|1|0000|Rd|00000|110|Rn" , "io": "N=W Z=W C=X"},
|
|
{"inst": "sadd16 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0000|1|Rn|Rd|1111|0001|Rm" , "io": "GE=W"},
|
|
{"inst": "sadd8 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0000|1|Rn|Rd|1111|1001|Rm" , "io": "GE=W"},
|
|
{"inst": "sasx Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0000|1|Rn|Rd|1111|0011|Rm" , "io": "GE=W"},
|
|
{"inst": "sbc Rd!=PC, Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|0110|0|Rn|Rd|Rs|0|sop:2|1|Rm" , "io": "C=R"},
|
|
{"inst": "sbc Rd, Rn, Rm, {sop #n}" , "a32": "cond|000|0110|0|Rn|Rd|n:5|sop:2|0|Rm" , "io": "C=R"},
|
|
{"inst": "sbc Rd, Rn, #immA" , "a32": "cond|001|0110|0|Rn|Rd|imm:12" , "io": "C=R"},
|
|
{"inst": "sbcS Rd!=PC, Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|0110|1|Rn|Rd|Rs|0|sop:2|1|Rm" , "io": "N=W Z=W C=X V=W"},
|
|
{"inst": "sbcS Rd!=PC, Rn, Rm, {sop #n}" , "a32": "cond|000|0110|1|Rn|Rd|n:5|sop:2|0|Rm" , "io": "N=W Z=W C=X V=W"},
|
|
{"inst": "sbcS Rd!=PC, Rn, #immA" , "a32": "cond|001|0110|1|Rn|Rd|imm:12" , "io": "N=W Z=W C=X V=W"},
|
|
{"inst": "sbfx Rd!=PC, Rn!=PC, #lsb, #width" , "a32": "cond|011|1101|widthM1:5|Rd|lsb:5|101|Rn" , "imm": "SbfxUbfxImm(lsb, width)"},
|
|
{"inst": "sel Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0100|0|Rn|Rd|1111|1011|Rm" , "io": "GE=R"},
|
|
{"inst": "setend #immZ" , "a32": "1111|000|1000|0|0001|0000|00|immZ:1|0|0000|0000" , "ext": "ARMv8-"},
|
|
{"inst": "shadd16 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0001|1|Rn|Rd|1111|0001|Rm"},
|
|
{"inst": "shadd8 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0001|1|Rn|Rd|1111|1001|Rm"},
|
|
{"inst": "shasx Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0001|1|Rn|Rd|1111|0011|Rm"},
|
|
{"inst": "shsax Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0001|1|Rn|Rd|1111|0101|Rm"},
|
|
{"inst": "shsub16 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0001|1|Rn|Rd|1111|0111|Rm"},
|
|
{"inst": "shsub8 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0001|1|Rn|Rd|1111|1111|Rm"},
|
|
{"inst": "smlabb Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "a32": "cond|000|1000|0|Rd|Ra|Rm|1000|Rn" , "io": "Q=X"},
|
|
{"inst": "smlabt Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "a32": "cond|000|1000|0|Rd|Ra|Rm|1100|Rn" , "io": "Q=X"},
|
|
{"inst": "smlatb Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "a32": "cond|000|1000|0|Rd|Ra|Rm|1010|Rn" , "io": "Q=X"},
|
|
{"inst": "smlatt Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "a32": "cond|000|1000|0|Rd|Ra|Rm|1110|Rn" , "io": "Q=X"},
|
|
{"inst": "smlad Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "a32": "cond|011|1000|0|Rd|Ra|Rm|0001|Rn" , "io": "Q=X"},
|
|
{"inst": "smladx Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "a32": "cond|011|1000|0|Rd|Ra|Rm|0011|Rn" , "io": "Q=X"},
|
|
{"inst": "smlal RxLo!=PC, RxHi!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|0111|0|RxHi|RxLo|Rm|1001|Rn"},
|
|
{"inst": "smlalS RxLo!=PC, RxHi!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|0111|1|RxHi|RxLo|Rm|1001|Rn" , "io": "N=W Z=W"},
|
|
{"inst": "smlalbb RxLo!=PC, RxHi!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1010|0|RxHi|RxLo|Rm|1000|Rn"},
|
|
{"inst": "smlalbt RxLo!=PC, RxHi!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1010|0|RxHi|RxLo|Rm|1100|Rn"},
|
|
{"inst": "smlaltb RxLo!=PC, RxHi!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1010|0|RxHi|RxLo|Rm|1010|Rn"},
|
|
{"inst": "smlaltt RxLo!=PC, RxHi!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1010|0|RxHi|RxLo|Rm|1110|Rn"},
|
|
{"inst": "smlald RxLo!=PC, RxHi!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|1010|0|RxHi|RxLo|Rm|0001|Rn"},
|
|
{"inst": "smlaldx RxLo!=PC, RxHi!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|1010|0|RxHi|RxLo|Rm|0011|Rn"},
|
|
{"inst": "smlawb Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "a32": "cond|000|1001|0|Rd|Ra|Rm|1000|Rn" , "io": "Q=X"},
|
|
{"inst": "smlawt Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "a32": "cond|000|1001|0|Rd|Ra|Rm|1100|Rn" , "io": "Q=X"},
|
|
{"inst": "smlsd Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "a32": "cond|011|1000|0|Rd|Ra|Rm|0101|Rn" , "io": "Q=X"},
|
|
{"inst": "smlsdx Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "a32": "cond|011|1000|0|Rd|Ra|Rm|0111|Rn" , "io": "Q=X"},
|
|
{"inst": "smlsld RxLo!=PC, RxHi!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|1010|0|RxHi|RxLo|Rm|0101|Rn"},
|
|
{"inst": "smlsldx RxLo!=PC, RxHi!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|1010|0|RxHi|RxLo|Rm|0111|Rn"},
|
|
{"inst": "smmla Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "a32": "cond|011|1010|1|Rd|Ra|Rm|0001|Rn"},
|
|
{"inst": "smmlar Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "a32": "cond|011|1010|1|Rd|Ra|Rm|0011|Rn"},
|
|
{"inst": "smmls Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "a32": "cond|011|1010|1|Rd|Ra|Rm|1101|Rn"},
|
|
{"inst": "smmlsr Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "a32": "cond|011|1010|1|Rd|Ra|Rm|1111|Rn"},
|
|
{"inst": "smmul Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|1010|1|Rd|1111|Rm|0001|Rn"},
|
|
{"inst": "smmulr Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|1010|1|Rd|1111|Rm|0011|Rn"},
|
|
{"inst": "smuad Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|1000|0|Rd|1111|Rm|0001|Rn" , "io": "Q=X"},
|
|
{"inst": "smuadx Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|1000|0|Rd|1111|Rm|0011|Rn" , "io": "Q=X"},
|
|
{"inst": "smulbb Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1011|0|Rd|0000|Rm|1000|Rn"},
|
|
{"inst": "smulbt Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1011|0|Rd|0000|Rm|1100|Rn"},
|
|
{"inst": "smultb Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1011|0|Rd|0000|Rm|1010|Rn"},
|
|
{"inst": "smultt Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1011|0|Rd|0000|Rm|1110|Rn"},
|
|
{"inst": "smull RdLo!=PC, RdHi!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|0110|0|RdHi|RdLo|Rm|1001|Rn"},
|
|
{"inst": "smullS RdLo!=PC, RdHi!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|0110|1|RdHi|RdLo|Rm|1001|Rn" , "io": "N=W Z=W"},
|
|
{"inst": "smulwb Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1001|0|Rd|0000|Rm|1010|Rn"},
|
|
{"inst": "smulwt Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1001|0|Rd|0000|Rm|1110|Rn"},
|
|
{"inst": "smusd Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|1000|0|Rd|1111|Rm|0101|Rn"},
|
|
{"inst": "smusdx Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|1000|0|Rd|1111|Rm|0111|Rn"},
|
|
{"inst": "srsda [Rn==SP]{!}, #mode" , "a32": "1111|100|001|W|0|1101|0000|0101|000|mode:5"},
|
|
{"inst": "srsdb [Rn==SP]{!}, #mode" , "a32": "1111|100|101|W|0|1101|0000|0101|000|mode:5"},
|
|
{"inst": "srsia [Rn==SP]{!}, #mode" , "a32": "1111|100|011|W|0|1101|0000|0101|000|mode:5"},
|
|
{"inst": "srsib [Rn==SP]{!}, #mode" , "a32": "1111|100|111|W|0|1101|0000|0101|000|mode:5"},
|
|
{"inst": "ssat Rd!=PC, #sat, Rn!=PC" , "a32": "cond|011|0101|imm:5|Rd|00000|00|1|Rn" , "imm": "SsatImm(sat)", "io": "Q=X"},
|
|
{"inst": "ssat Rd!=PC, #sat, Rn!=PC, lsl_or_asr #n" , "a32": "cond|011|0101|imm:5|Rd|n:5|sop:2|1|Rn" , "imm": "SsatImm(sat, n)", "io": "Q=X"},
|
|
{"inst": "ssat16 Rd!=PC, #sat, Rn!=PC" , "a32": "cond|011|0101|0|imm:4|Rd|1111|0011|Rn" , "imm": "Ssat16Imm(sat)", "io": "Q=X"},
|
|
{"inst": "ssax Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0000|1|Rn|Rd|1111|0101|Rm" , "io": "GE=W"},
|
|
{"inst": "ssub16 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0000|1|Rn|Rd|1111|0111|Rm" , "io": "GE=W"},
|
|
{"inst": "ssub8 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0000|1|Rn|Rd|1111|1111|Rm" , "io": "GE=W"},
|
|
{"inst": "stmda [Rn!=PC]{!}, RsList" , "a32": "cond|100|000W|0|Rn|immMask:16" , "imm": "GpListImm(RsList)"},
|
|
{"inst": "stmdb [Rn!=PC]{!}, RsList" , "a32": "cond|100|100W|0|Rn|immMask:16" , "imm": "GpListImm(RsList)"},
|
|
{"inst": "stmia [Rn!=PC]{!}, RsList" , "a32": "cond|100|010W|0|Rn|immMask:16" , "imm": "GpListImm(RsList)"},
|
|
{"inst": "stmib [Rn!=PC]{!}, RsList" , "a32": "cond|100|110W|0|Rn|immMask:16" , "imm": "GpListImm(RsList)"},
|
|
{"inst": "stmda [Rn!=PC], RsList^" , "a32": "cond|100|0010|0|Rn|immMask:16" , "imm": "GpListImm(RsList)"},
|
|
{"inst": "stmdb [Rn!=PC], RsList^" , "a32": "cond|100|1010|0|Rn|immMask:16" , "imm": "GpListImm(RsList)"},
|
|
{"inst": "stmia [Rn!=PC], RsList^" , "a32": "cond|100|0110|0|Rn|immMask:16" , "imm": "GpListImm(RsList)"},
|
|
{"inst": "stmib [Rn!=PC], RsList^" , "a32": "cond|100|1110|0|Rn|immMask:16" , "imm": "GpListImm(RsList)"},
|
|
{"inst": "str Rs, [Rn!=PC, +/-Rm!=PC, {sop #n}]{@}{!}" , "a32": "cond|011|PU0W|0|Rn|Rs|n:5|sop:2|0|Rm"},
|
|
{"inst": "str Rs, [Rn!=PC, #+/-off]{@}{!}" , "a32": "cond|010|PU0W|0|Rn|Rs|off:12"},
|
|
{"inst": "str Rs, [Rn==PC, #+/-off]" , "a32": "cond|010|1U00|0|Rn|Rs|off:12"},
|
|
{"inst": "strb Rs!=PC, [Rn!=PC, +/-Rm!=PC, {sop #n}]{@}{!}" , "a32": "cond|011|PU1W|0|Rn|Rs|n:5|sop:2|0|Rm"},
|
|
{"inst": "strb Rs!=PC, [Rn!=PC, #+/-off]{@}{!}" , "a32": "cond|010|PU1W|0|Rn|Rs|off:12"},
|
|
{"inst": "strb Rs!=PC, [Rn==PC, #+/-off]" , "a32": "cond|010|1U10|0|Rn|Rs|off:12"},
|
|
{"inst": "strbt Rs!=PC, [Rn!=PC, +/-Rm!=PC, {sop #n}]@" , "a32": "cond|011|0U11|0|Rn|Rs|n:5|sop:2|0|Rm"},
|
|
{"inst": "strbt Rs!=PC, [Rn!=PC, #+/-off]@" , "a32": "cond|010|0U11|0|Rn|Rs|off:12"},
|
|
{"inst": "strbt Rs!=PC, [Rn==PC, #+/-off]" , "a32": "cond|010|0U11|0|Rn|Rs|off:12"},
|
|
{"inst": "strd Rs<=13, Rs2+, [Rn!=PC, +/-Rm!=PC]{@}{!}" , "a32": "cond|000|PU0W|0|Rn|Rs|0000|1111|Rm"},
|
|
{"inst": "strd Rs<=13, Rs2+, [Rn!=PC, #+/-off]{@}{!}" , "a32": "cond|000|PU1W|0|Rn|Rs|off:4|1111|off:4"},
|
|
{"inst": "strd Rs<=13, Rs2+, [Rn==PC, #+/-off]" , "a32": "cond|000|1U10|0|Rn|Rs|off:4|1111|off:4"},
|
|
{"inst": "strex Rd!=PC, Rs!=PC, [Rn!=PC]" , "a32": "cond|000|1100|0|Rn|Rd|1111|1001|Rs"},
|
|
{"inst": "strexb Rd!=PC, Rs!=PC, [Rn!=PC]" , "a32": "cond|000|1110|0|Rn|Rd|1111|1001|Rs"},
|
|
{"inst": "strexd Rd!=PC, Rs!=PC, Rs2+, [Rn!=PC]" , "a32": "cond|000|1101|0|Rn|Rd|1111|1001|Rs"},
|
|
{"inst": "strexh Rd!=PC, Rs!=PC, [Rn!=PC]" , "a32": "cond|000|1111|0|Rn|Rd|1111|1001|Rs"},
|
|
{"inst": "strh Rs!=PC, [Rn!=PC, +/-Rm!=PC]{@}{!}" , "a32": "cond|000|PU0W|0|Rn|Rs|0000|1011|Rm"},
|
|
{"inst": "strh Rs!=PC, [Rn!=PC, #+/-off]{@}{!}" , "a32": "cond|000|PU1W|0|Rn|Rs|off:4|1011|off:4"},
|
|
{"inst": "strh Rs!=PC, [Rn==PC, #+/-off]" , "a32": "cond|000|1U10|0|Rn|Rs|off:4|1011|off:4"},
|
|
{"inst": "strht Rs!=PC, [Rn!=PC, +/-Rm!=PC]@" , "a32": "cond|000|0U01|0|Rn|Rs|0000|1011|Rm"},
|
|
{"inst": "strht Rs!=PC, [Rn!=PC, #+/-off]@" , "a32": "cond|000|0U11|0|Rn|Rs|off:4|1011|off:4"},
|
|
{"inst": "strt Rs, [Rn!=PC, +/-Rm!=PC, {sop #n}]@" , "a32": "cond|011|0U01|0|Rn|Rs|n:5|sop:2|0|Rm"},
|
|
{"inst": "strt Rs, [Rn!=PC, #+/-off]@" , "a32": "cond|010|0U01|0|Rn|Rs|off:12"},
|
|
{"inst": "sub Rd, Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|0010|0|Rn|Rd|Rs|0|sop:2|1|Rm"},
|
|
{"inst": "sub Rd, Rn, Rm, {sop #n}" , "a32": "cond|000|0010|0|Rn|Rd|n:5|sop:2|0|Rm"},
|
|
{"inst": "sub Rd, Rn, #immA" , "a32": "cond|001|0010|0|Rn|Rd|imm:12"},
|
|
{"inst": "subS Rd!=PC, Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|0010|1|Rn|Rd|Rs|0|sop:2|1|Rm" , "io": "N=W Z=W C=W V=W"},
|
|
{"inst": "subS Rd!=PC, Rn, Rm, {sop #n}" , "a32": "cond|000|0010|1|Rn|Rd|n:5|sop:2|0|Rm" , "io": "N=W Z=W C=W V=W"},
|
|
{"inst": "subS Rd!=PC, Rn, #immA" , "a32": "cond|001|0010|1|Rn|Rd|imm:12" , "io": "N=W Z=W C=W V=W"},
|
|
{"inst": "svc #immZ" , "a32": "cond|1111|immZ:24"},
|
|
{"inst": "sxtab Rd!=PC, Rn!=PC, Rm!=PC, {ror #n}" , "a32": "cond|011|0101|0|Rn|Rd|imm:2|00|0111|Rm" , "imm": "Ror8Imm(n)"},
|
|
{"inst": "sxtab16 Rd!=PC, Rn!=PC, Rm!=PC, {ror #n}" , "a32": "cond|011|0100|0|Rn|Rd|imm:2|00|0111|Rm" , "imm": "Ror8Imm(n)"},
|
|
{"inst": "sxtah Rd!=PC, Rn!=PC, Rm!=PC, {ror #n}" , "a32": "cond|011|0101|1|Rn|Rd|imm:2|00|0111|Rm" , "imm": "Ror8Imm(n)"},
|
|
{"inst": "sxtb Rd!=PC, Rn!=PC, {ror #n}" , "a32": "cond|011|0101|0|1111|Rd|imm:2|00|0111|Rn" , "imm": "Ror8Imm(n)"},
|
|
{"inst": "sxtb16 Rd!=PC, Rn!=PC, {ror #n}" , "a32": "cond|011|0100|0|1111|Rd|imm:2|00|0111|Rn" , "imm": "Ror8Imm(n)"},
|
|
{"inst": "sxth Rd!=PC, Rn!=PC, {ror #n}" , "a32": "cond|011|0101|1|1111|Rd|imm:2|00|0111|Rn" , "imm": "Ror8Imm(n)"},
|
|
{"inst": "teq Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|1001|1|Rn|0000|Rs|0|sop:2|1|Rm" , "io": "N=W Z=W C=W"},
|
|
{"inst": "teq Rn, Rm, {sop #n}" , "a32": "cond|000|1001|1|Rn|0000|n:5|sop:2|0|Rm" , "io": "N=W Z=W C=W"},
|
|
{"inst": "teq Rn, #immA" , "a32": "cond|001|1001|1|Rn|0000|imm:12" , "io": "N=W Z=W C=W"},
|
|
{"inst": "tst Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|1000|1|Rn|0000|Rs|0|sop:2|1|Rm" , "io": "N=W Z=W C=W"},
|
|
{"inst": "tst Rn, Rm, {sop #n}" , "a32": "cond|000|1000|1|Rn|0000|n:5|sop:2|0|Rm" , "io": "N=W Z=W C=W"},
|
|
{"inst": "tst Rn, #immA" , "a32": "cond|001|1000|1|Rn|0000|imm:12" , "io": "N=W Z=W C=W"},
|
|
{"inst": "uadd16 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0010|1|Rn|Rd|1111|0001|Rm" , "io": "GE=W"},
|
|
{"inst": "uadd8 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0010|1|Rn|Rd|1111|1001|Rm" , "io": "GE=W"},
|
|
{"inst": "uasx Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0010|1|Rn|Rd|1111|0011|Rm" , "io": "GE=W"},
|
|
{"inst": "ubfx Rd!=PC, Rn!=PC, #lsb, #width" , "a32": "cond|011|1111|widthM1:5|Rd|lsb:5|101|Rn" , "imm": "SbfxUbfxImm(lsb, width)"},
|
|
{"inst": "udf #immZ" , "a32": "1110|011|1111|1|immZ:12|1111|immZ:4"},
|
|
{"inst": "uhadd8 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0011|1|Rn|Rd|1111|1001|Rm"},
|
|
{"inst": "uhadd16 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0011|1|Rn|Rd|1111|0001|Rm"},
|
|
{"inst": "uhasx Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0011|1|Rn|Rd|1111|0011|Rm"},
|
|
{"inst": "uhsax Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0011|1|Rn|Rd|1111|0101|Rm"},
|
|
{"inst": "uhsub16 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0011|1|Rn|Rd|1111|0111|Rm"},
|
|
{"inst": "uhsub8 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0011|1|Rn|Rd|1111|1111|Rm"},
|
|
{"inst": "umaal RxLo!=PC, RxHi!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|0010|0|RxHi|RxLo|Rm|1001|Rn"},
|
|
{"inst": "umlal RxLo!=PC, RxHi!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|0101|0|RxHi|RxLo|Rm|1001|Rn"},
|
|
{"inst": "umlalS RxLo!=PC, RxHi!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|0101|1|RxHi|RxLo|Rm|1001|Rn" , "io": "N=W Z=W"},
|
|
{"inst": "umull RdLo!=PC, RdHi!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|0100|0|RdHi|RdLo|Rm|1001|Rn"},
|
|
{"inst": "umullS RdLo!=PC, RdHi!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|0100|1|RdHi|RdLo|Rm|1001|Rn" , "io": "N=W Z=W"},
|
|
{"inst": "uqadd16 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0011|0|Rn|Rd|1111|0001|Rm"},
|
|
{"inst": "uqadd8 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0011|0|Rn|Rd|1111|1001|Rm"},
|
|
{"inst": "uqasx Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0011|0|Rn|Rd|1111|0011|Rm"},
|
|
{"inst": "uqsax Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0011|0|Rn|Rd|1111|0101|Rm"},
|
|
{"inst": "uqsub16 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0011|0|Rn|Rd|1111|0111|Rm"},
|
|
{"inst": "uqsub8 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0011|0|Rn|Rd|1111|1111|Rm"},
|
|
{"inst": "usad8 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|1100|0|Rd|1111|Rm|0001|Rn"},
|
|
{"inst": "usada8 Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "a32": "cond|011|1100|0|Rd|Ra|Rm|0001|Rn"},
|
|
{"inst": "usat Rd!=PC, #sat, Rn!=PC, {lsl_or_asr #n}" , "a32": "cond|011|0111|sat:5|Rd|n:5|sop:2|1|Rn"},
|
|
{"inst": "usat16 Rd!=PC, #sat, Rn!=PC" , "a32": "cond|011|0111|0|sat:4|Rd|1111|0011|Rn"},
|
|
{"inst": "usax Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0010|1|Rn|Rd|1111|0101|Rm" , "io": "GE=W"},
|
|
{"inst": "usub16 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0010|1|Rn|Rd|1111|0111|Rm" , "io": "GE=W"},
|
|
{"inst": "usub8 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0010|1|Rn|Rd|1111|1111|Rm" , "io": "GE=W"},
|
|
{"inst": "uxtab Rd!=PC, Rn!=PC, Rm!=PC, {ror #n}" , "a32": "cond|011|0111|0|Rn|Rd|imm:2|00|0111|Rm" , "imm": "Ror8Imm(n)"},
|
|
{"inst": "uxtab16 Rd!=PC, Rn!=PC, Rm!=PC, {ror #n}" , "a32": "cond|011|0110|0|Rn|Rd|imm:2|00|0111|Rm" , "imm": "Ror8Imm(n)"},
|
|
{"inst": "uxtah Rd!=PC, Rn!=PC, Rm!=PC, {ror #n}" , "a32": "cond|011|0111|1|Rn|Rd|imm:2|00|0111|Rm" , "imm": "Ror8Imm(n)"},
|
|
{"inst": "uxtb Rd!=PC, Rn!=PC, {ror #n}" , "a32": "cond|011|0111|0|1111|Rd|imm:2|00|0111|Rn" , "imm": "Ror8Imm(n)"},
|
|
{"inst": "uxtb16 Rd!=PC, Rn!=PC, {ror #n}" , "a32": "cond|011|0110|0|1111|Rd|imm:2|00|0111|Rn" , "imm": "Ror8Imm(n)"},
|
|
{"inst": "uxth Rd!=PC, Rn!=PC, {ror #n}" , "a32": "cond|011|0111|1|1111|Rd|imm:2|00|0111|Rn" , "imm": "Ror8Imm(n)"},
|
|
{"inst": "wfe" , "a32": "cond|001|1001|0|0000|1111|0000|0000|0010"},
|
|
{"inst": "wfi" , "a32": "cond|001|1001|0|0000|1111|0000|0000|0011"},
|
|
{"inst": "yield" , "a32": "cond|001|1001|0|0000|1111|0000|0000|0001"}
|
|
]},
|
|
|
|
{"category": "GP", "data": [
|
|
{"inst": "adc Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|000|101|Rm:3|Rx:3" , "it": "in" , "io": "C=R"},
|
|
{"inst": "adc Rd!=XX, Rn!=XX, Rm!=XX, {sop #n}" , "t32": "1110|101|1010|0|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any", "io": "C=R"},
|
|
{"inst": "adc Rd!=XX, Rn!=XX, #immA" , "t32": "1111|0|imm:1|0|1010|0|Rn|0|imm:3|Rd|imm:8" , "it": "any", "io": "C=R"},
|
|
{"inst": "adcS Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|000|101|Rm:3|Rx:3" , "it": "out", "io": "N=W Z=W C=X V=W", "mod": "APSR_IF_NOT_PC"},
|
|
{"inst": "adcS Rd!=XX, Rn!=XX, Rm!=XX, {sop #n}" , "t32": "1110|101|1010|1|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any", "io": "N=W Z=W C=X V=W", "mod": "APSR_IF_NOT_PC"},
|
|
{"inst": "adcS Rd!=XX, Rn!=XX, #immA" , "t32": "1111|0|imm:1|0|1010|1|Rn|0|imm:3|Rd|imm:8" , "it": "any", "io": "N=W Z=W C=X V=W", "mod": "APSR_IF_NOT_PC"},
|
|
{"inst": "add Rd!=HI, Rn!=HI, Rm!=HI" , "t16": "0001|100|Rm:3|Rn:3|Rd:3" , "it": "in"},
|
|
{"inst": "add Rx!=XX, Rx!=XX, Rm!=XX" , "t16": "0100|010|0|Rx:1|Rm:4|Rx:3" , "it": "in"},
|
|
{"inst": "add Rx, Rx, Rm==SP" , "t16": "0100|010|0|Rx:1|Rm:4|Rx:3" , "it": "any"},
|
|
{"inst": "add Rx==SP, Rx==SP, Rm" , "t16": "0100|010|0|Rx:1|Rm:4|Rx:3" , "it": "any"},
|
|
{"inst": "add Rx!=HI, Rx!=HI, #immZ" , "t16": "0011|0|Rx:3|immZ:8" , "it": "in"},
|
|
{"inst": "add Rd!=HI, Rn!=HI, #immZ" , "t16": "0001|110|immZ:3|Rn:3|Rd:3" , "it": "in"},
|
|
{"inst": "add Rx==SP, Rx==SP, #immZ*4" , "t16": "1011|00000|immZ:7" , "it": "any"},
|
|
{"inst": "add Rd!=SP, Rn==SP, #immZ*4" , "t16": "1010|1|Rd:3|immZ:8" , "it": "any"},
|
|
{"inst": "add Rd!=XX, Rn!=PC, Rm!=XX, {sop #n}" , "t32": "1110|101|1000|0|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any"},
|
|
{"inst": "add Rd!=PC, Rn==SP, Rm!=XX, {sop #n}" , "t32": "1110|101|1000|0|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any", "mod": "LSL_3_IF_SP"},
|
|
{"inst": "add Rd!=XX, Rn!=PC, #immZ" , "t32": "1111|0|immZ:1|1|0000|0|Rn|0|immZ:3|Rd|immZ:8" , "it": "any"},
|
|
{"inst": "add Rd!=XX, Rn!=PC, #immA" , "t32": "1111|0|imm:1|0|1000|0|Rn|0|imm:3|Rd|imm:8" , "it": "any"},
|
|
{"inst": "add Rd!=PC, Rn==SP, #immZ" , "t32": "1111|0|immZ:1|1|0000|0|Rn|0|immZ:3|Rd|immZ:8" , "it": "any"},
|
|
{"inst": "add Rd!=PC, Rn==SP, #immA" , "t32": "1111|0|imm:1|0|1000|0|Rn|0|imm:3|Rd|imm:8" , "it": "any"},
|
|
{"inst": "addS Rx!=HI, Rx!=HI, #immZ" , "t16": "0011|0|Rx:3|immZ:8" , "it": "out", "io": "N=W Z=W C=W V=W"},
|
|
{"inst": "addS Rd!=HI, Rn!=HI, #immZ" , "t16": "0001|110|immZ:3|Rn:3|Rd:3" , "it": "out", "io": "N=W Z=W C=W V=W"},
|
|
{"inst": "addS Rd!=HI, Rn!=HI, Rm!=HI" , "t16": "0001|100|Rm:3|Rn:3|Rd:3" , "it": "out", "io": "N=W Z=W C=W V=W"},
|
|
{"inst": "addS Rd!=XX, Rn!=PC, Rm!=XX, {sop #n}" , "t32": "1110|101|1000|1|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any", "io": "N=W Z=W C=W V=W"},
|
|
{"inst": "addS Rd!=PC, Rn==SP, Rm!=XX, {sop #n}" , "t32": "1110|101|1000|1|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any", "io": "N=W Z=W C=W V=W", "mod": "LSL_3_IF_SP"},
|
|
{"inst": "addS Rd!=XX, Rn!=PC, #immA" , "t32": "1111|0|imm:1|0|1000|1|Rn|0|imm:3|Rd|imm:8" , "it": "any", "io": "N=W Z=W C=W V=W"},
|
|
{"inst": "addS Rd!=PC, Rn==SP, #immA" , "t32": "1111|0|imm:1|0|1000|1|Rn|0|imm:3|Rd|imm:8" , "it": "any", "io": "N=W Z=W C=W V=W"},
|
|
{"inst": "adr Rd!=HI, #relZ*4" , "t16": "1010|0|Rd:3|relZ:8" , "it": "any"},
|
|
{"inst": "adr Rd!=XX, #relZ" , "t32": "1111|0|relZ:1|10N0N|0|1111|0|relZ:3|Rd|relZ:8" , "it": "any"},
|
|
{"inst": "and Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|000|000|Rm:3|Rx:3" , "it": "in"},
|
|
{"inst": "and Rd!=XX, Rn!=XX, Rm!=XX, {sop #n}" , "t32": "1110|101|0000|0|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any"},
|
|
{"inst": "and Rd!=XX, Rn!=XX, #immA" , "t32": "1111|0|imm:1|0|1010|0|Rn|0|imm:3|Rd|imm:8" , "it": "any"},
|
|
{"inst": "andS Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|000|000|Rm:3|Rx:3" , "it": "out", "io": "N=W Z=W C=W"},
|
|
{"inst": "andS Rd!=XX, Rn!=XX, Rm!=XX, {sop #n}" , "t32": "1110|101|0000|1|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any", "io": "N=W Z=W C=W"},
|
|
{"inst": "andS Rd!=XX, Rn!=XX, #immA" , "t32": "1111|0|imm:1|0|1010|1|Rn|0|imm:3|Rd|imm:8" , "it": "any", "io": "N=W Z=W C=W", "mod": "APSR_IF_NOT_PC"},
|
|
{"inst": "asr Rd!=HI, Rn!=HI, #n" , "t16": "0001|0|n:5|Rn:3|Rd:3" , "it": "in"},
|
|
{"inst": "asr Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|000|100|Rm:3|Rx:3" , "it": "in"},
|
|
{"inst": "asr Rd!=XX, Rn!=XX, #n" , "t32": "1110|101|0010|0|1111|0|n:3|Rd|n:2|10|Rn" , "it": "any"},
|
|
{"inst": "asr Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0010|0|Rn|1111|Rd|0000|Rm" , "it": "any"},
|
|
{"inst": "asrS Rd!=HI, Rn!=HI, #n" , "t16": "0001|0|n:5|Rn:3|Rd:3" , "it": "out", "io": "N=W Z=W C=W"},
|
|
{"inst": "asrS Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|000|100|Rm:3|Rx:3" , "it": "out", "io": "N=W Z=W C=W"},
|
|
{"inst": "asrS Rd!=XX, Rn!=XX, #n" , "t32": "1110|101|0010|1|1111|0|n:3|Rd|n:2|10|Rn" , "it": "any", "io": "N=W Z=W C=W"},
|
|
{"inst": "asrS Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0010|1|Rn|1111|Rd|0000|Rm" , "it": "any", "io": "N=W Z=W C=W"},
|
|
{"inst": "b #relS*2" , "t16": "1110|0|relS:11" , "it": "out last"},
|
|
{"inst": "b #relS*2" , "t32": "1111|0|relS[23]|relS[20:11]|10|ja|1|jb|relS[10:0]" , "it": "out last", "calc": {"ja": "relS[23] ^ relS[22] ^ 1", "jb": "relS[23] ^ relS[21] ^ 1"}},
|
|
{"inst": "b #relS*2" , "t16": "1101|cond|relS:8" , "it": "out"},
|
|
{"inst": "b #relS*2" , "t32": "1111|0|relS[19]|cond|relS[16:11]|10|ja|0|jb|relS[10:0]" , "it": "out" , "calc": {"ja": "relS[19] ^ relS[18] ^ 1", "jb": "relS[19] ^ relS[17] ^ 1"}},
|
|
{"inst": "bfc Rd!=XX, #lsb, #width" , "t32": "1111|001|1011|0|1111|0|lsb:3|Rd|lsb:2|0|msb:5" , "it": "any", "imm": "BfcBfiImm(lsb, width)"},
|
|
{"inst": "bfi Rd!=XX, Rn!=XX, #lsb, #width" , "t32": "1111|001|1011|0|Rn|0|lsb:3|Rd|lsb:2|0|msb:5" , "it": "any", "imm": "BfcBfiImm(lsb, width)"},
|
|
{"inst": "bic Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|001|110|Rm:3|Rx:3" , "it": "in"},
|
|
{"inst": "bic Rd!=XX, Rn!=XX, Rm!=XX, {sop #n}" , "t32": "1110|101|0001|0|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any"},
|
|
{"inst": "bic Rd!=XX, Rn!=XX, #immA" , "t32": "1111|0|imm:1|0|0001|0|Rn|0|imm:3|Rd|imm:8" , "it": "any"},
|
|
{"inst": "bicS Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|001|110|Rm:3|Rx:3" , "it": "out", "io": "N=W Z=W C=W"},
|
|
{"inst": "bicS Rd!=XX, Rn!=XX, Rm!=XX, {sop #n}" , "t32": "1110|101|0001|1|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any", "io": "N=W Z=W C=W"},
|
|
{"inst": "bicS Rd!=XX, Rn!=XX, #immA" , "t32": "1111|0|imm:1|0|0001|1|Rn|0|imm:3|Rd|imm:8" , "it": "any", "io": "N=W Z=W C=W"},
|
|
{"inst": "bkpt #immZ" , "t16": "1011|111|0|immZ:8" , "it": "uncond"},
|
|
{"inst": "bl #relS*2" , "t32": "1111|0|relS[23]|relS[20:11]|11|ja|1|jb|relS[10:0]" , "it": "out last", "calc": {"ja": "relS[23] ^ relS[22] ^ 1", "jb": "relS[23] ^ relS[21] ^ 1"}},
|
|
{"inst": "blx Rm!=PC" , "t16": "0100|011|11|Rm:4|000" , "it": "out last"},
|
|
{"inst": "blx #relS*4" , "t32": "1111|0|relS[22]|relS[19:10]|11|ja|0|jb|relS[9:0]|0" , "it": "out last", "calc": {"ja": "relS[22] ^ relS[21] ^ 1", "jb": "relS[22] ^ relS[20] ^ 1"}},
|
|
{"inst": "bx Rm" , "t16": "0100|011|10|Rm:4|000" , "it": "out last"},
|
|
{"inst": "bxj Rm!=XX" , "t32": "1111|001|1110|0|Rm|1000|1111|00000000" , "it": "out last"},
|
|
{"inst": "cbz Rn!=HI, #relZ*2" , "t16": "1011|00|relZ:1|1|relZ:5|Rn:3" , "it": "out"},
|
|
{"inst": "cbnz Rn!=HI, #relZ*2" , "t16": "1011|10|relZ:1|1|relZ:5|Rn:3" , "it": "out"},
|
|
{"inst": "clz Rd!=XX, Rn!=XX" , "t32": "1111|101|0101|1|Rm|1111|Rd|1000|Rn" , "it": "any"},
|
|
{"inst": "cmn Rn!=HI, Rm!=HI" , "t16": "0100|001|011|Rm:3|Rn:3" , "it": "any", "io": "N=W Z=W C=W V=W"},
|
|
{"inst": "cmn Rn!=PC, Rm!=XX, {sop #n}" , "t32": "1110|101|1000|1|Rn|0|n:3|1111|n:2|sop:2|Rm" , "it": "any", "io": "N=W Z=W C=W V=W"},
|
|
{"inst": "cmn Rn!=PC, #immA" , "t32": "1111|0|imm:1|0|1000|1|Rn|0|imm:3|1111|imm:8" , "it": "any", "io": "N=W Z=W C=W V=W"},
|
|
{"inst": "cmp Rn!=HI, #immZ" , "t16": "0010|1|Rn:3|immZ:8" , "it": "any", "io": "N=W Z=W C=W V=W"},
|
|
{"inst": "cmp Rn!=HI, Rm!=HI" , "t16": "0100|001|010|Rm:3|Rn:3" , "it": "any", "io": "N=W Z=W C=W V=W"},
|
|
{"inst": "cmp Rn!=PC, Rm!=PC" , "t16": "0100|010|1|Rn:1|Rm:4|Rn:3" , "it": "any", "io": "N=W Z=W C=W V=W", "mod": "UNPRED_IF_ALL_LOW"},
|
|
{"inst": "cmp Rn!=PC, Rm!=XX, {sop #n}" , "t32": "1110|101|1101|1|Rn|0|n:3|1111|n:2|sop:2|Rm" , "it": "any", "io": "N=W Z=W C=W V=W"},
|
|
{"inst": "cmp Rn!=PC, #immA" , "t32": "1111|0|imm:1|0|1101|1|Rn|0|imm:3|1111|imm:8" , "it": "any", "io": "N=W Z=W C=W V=W"},
|
|
{"inst": "dbg #immZ" , "t32": "1111|001|1101|0|1111|1000|0000|1111|immZ:4" , "it": "any"},
|
|
{"inst": "eor Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|000|001|Rm:3|Rx:3" , "it": "in"},
|
|
{"inst": "eor Rd!=XX, Rn!=XX, Rm!=XX, {sop #n}" , "t32": "1110|101|0100|0|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any"},
|
|
{"inst": "eor Rd!=XX, Rn!=XX, #immA" , "t32": "1111|0|imm:1|0|0100|0|Rn|0|imm:3|Rd|imm:8" , "it": "any"},
|
|
{"inst": "eorS Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|000|001|Rm:3|Rx:3" , "it": "out", "io": "N=W Z=W C=W"},
|
|
{"inst": "eorS Rd!=XX, Rn!=XX, Rm!=XX, {sop #n}" , "t32": "1110|101|0100|1|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any", "io": "N=W Z=W C=W"},
|
|
{"inst": "eorS Rd!=XX, Rn!=XX, #immA" , "t32": "1111|0|imm:1|0|0100|1|Rn|0|imm:3|Rd|imm:8" , "it": "any", "io": "N=W Z=W C=W"},
|
|
{"inst": "hlt #immZ" , "t16": "1011|1010|10|immZ:6" , "it": "out", "ext": "ARMv8+"},
|
|
{"inst": "it #cond!=15" , "t16": "1011|111|1|cond[3:0]|1000" , "it": "out def"},
|
|
{"inst": "ite #cond!=15" , "t16": "1011|111|1|cond[3:0]|X100" , "it": "out def"},
|
|
{"inst": "itee #cond!=15" , "t16": "1011|111|1|cond[3:0]|XY10" , "it": "out def"},
|
|
{"inst": "iteee #cond!=15" , "t16": "1011|111|1|cond[3:0]|XYZ1" , "it": "out def"},
|
|
{"inst": "iteet #cond!=15" , "t16": "1011|111|1|cond[3:0]|XYZ1" , "it": "out def"},
|
|
{"inst": "itet #cond!=15" , "t16": "1011|111|1|cond[3:0]|XY10" , "it": "out def"},
|
|
{"inst": "itete #cond!=15" , "t16": "1011|111|1|cond[3:0]|XYZ1" , "it": "out def"},
|
|
{"inst": "itett #cond!=15" , "t16": "1011|111|1|cond[3:0]|XYZ1" , "it": "out def"},
|
|
{"inst": "itt #cond!=15" , "t16": "1011|111|1|cond[3:0]|X100" , "it": "out def"},
|
|
{"inst": "itte #cond!=15" , "t16": "1011|111|1|cond[3:0]|XY10" , "it": "out def"},
|
|
{"inst": "ittee #cond!=15" , "t16": "1011|111|1|cond[3:0]|XYZ1" , "it": "out def"},
|
|
{"inst": "ittet #cond!=15" , "t16": "1011|111|1|cond[3:0]|XYZ1" , "it": "out def"},
|
|
{"inst": "ittt #cond!=15" , "t16": "1011|111|1|cond[3:0]|XY10" , "it": "out def"},
|
|
{"inst": "ittte #cond!=15" , "t16": "1011|111|1|cond[3:0]|XYZ1" , "it": "out def"},
|
|
{"inst": "itttt #cond!=15" , "t16": "1011|111|1|cond[3:0]|XYZ1" , "it": "out def"},
|
|
{"inst": "ldmia [Rn!=HI]{!}, RdList" , "t16": "1100|1|Rn:3|imm:8" , "it": "any", "imm": "GpListImm(RdList, 0xFF)"},
|
|
{"inst": "ldmia [Rn!=PC]{!}, RdList" , "t32": "1110|100|010W|1|Rn|immMask[15:14]|0|immMask[12:0]" , "it": "any", "imm": "GpListImm(RdList, 0xDFFF)"},
|
|
{"inst": "ldmdb [Rn!=PC]{!}, RdList" , "t32": "1110|100|100W|1|Rn|immMask[15:14]|0|immMask[12:0]" , "it": "any", "imm": "GpListImm(RdList, 0xDFFF)"},
|
|
{"inst": "ldr Rd!=HI, [Rn!=HI, Rm!=HI]" , "t16": "0101|100|Rm:3|Rn:3|Rd:3" , "it": "any"},
|
|
{"inst": "ldr Rd, [Rn!=PC, Rm!=XX, {lsl #n}]" , "t32": "1111|100|0010|1|Rn|Rd|0|00000|n:2|Rm" , "it": "any"},
|
|
{"inst": "ldr Rd!=HI, [Rn!=HI, #off*4]" , "t16": "0110|1|off:5|Rn:3|Rd:3" , "it": "any"},
|
|
{"inst": "ldr Rd!=HI, [Rn==SP, #off*4]" , "t16": "1001|1|Rd:3|off:8" , "it": "any"},
|
|
{"inst": "ldr Rd!=HI, [Rn==PC, #off*4]" , "t16": "0100|1|Rd:3|off:8" , "it": "any"},
|
|
{"inst": "ldr Rd, [Rn!=PC, #off]" , "t32": "1111|100|0110|1|Rn|Rd|off:12" , "it": "any"},
|
|
{"inst": "ldr Rd, [Rn!=PC, #+/-off]{@}{!}" , "t32": "1111|100|0010|1|Rn|Rd|1PUW|off:8" , "it": "any"},
|
|
{"inst": "ldr Rd, [Rn==PC, #+/-off]" , "t32": "1111|100|0U10|1|Rn|Rd|off:12" , "it": "any"},
|
|
{"inst": "ldrb Rd!=HI, [Rn!=HI, Rm!=HI]" , "t16": "0101|110|Rm:3|Rn:3|Rd:3" , "it": "any"},
|
|
{"inst": "ldrb Rd!=XX, [Rn!=PC, Rm!=XX, {lsl #n}]" , "t32": "1111|100|0000|1|Rn|Rd|0|00000|n:2|Rm" , "it": "any"},
|
|
{"inst": "ldrb Rd!=HI, [Rn!=HI, #off*4]" , "t16": "0111|1|off:5|Rn:3|Rd:3" , "it": "any"},
|
|
{"inst": "ldrb Rd!=XX, [Rn!=PC, #off]" , "t32": "1111|100|0100|1|Rn|Rd|off:12" , "it": "any"},
|
|
{"inst": "ldrb Rd!=XX, [Rn!=PC, #+/-off]{!}" , "t32": "1111|100|0000|1|Rn|Rd|1PUW|off:8" , "it": "any"},
|
|
{"inst": "ldrb Rd!=XX, [Rn==PC, #+/-off]" , "t32": "1111|100|0U00|1|Rn|Rd|off:12" , "it": "any"},
|
|
{"inst": "ldrbt Rd!=XX, [Rn!=PC, #off]" , "t32": "1111|100|0000|1|Rn|Rd|1110|off:8" , "it": "any"},
|
|
{"inst": "ldrd Rd!=XX, Rd2!=XX, [Rn==PC, #+/-off*4]" , "t32": "1110|100|1U10|1|Rn|Rd|Rd2|off:8" , "it": "any"},
|
|
{"inst": "ldrd Rd!=XX, Rd2!=XX, [Rn!=PC, #+/-off*4]{@}{!}" , "t32": "1110|100|PU1W|1|Rn|Rd|Rd2|off:8" , "it": "any"},
|
|
{"inst": "ldrex Rd!=XX, [Rn!=PC, #off*4]" , "t32": "1110|100|0010|1|Rn|Rd|1111|off:8" , "it": "any"},
|
|
{"inst": "ldrh Rd!=HI, [Rn!=HI, Rm!=HI]" , "t16": "0101|101|Rm:3|Rn:3|Rd:3" , "it": "any"},
|
|
{"inst": "ldrh Rd!=XX, [Rn!=PC, Rm!=XX, {lsl #n}]" , "t32": "1111|100|0001|1|Rn|Rd|0|00000|n:2|Rm" , "it": "any"},
|
|
{"inst": "ldrh Rd!=HI, [Rn!=HI, #off*4]" , "t16": "1000|1|off:5|Rn:3|Rd:3" , "it": "any"},
|
|
{"inst": "ldrh Rd!=XX, [Rn!=PC, #off]" , "t32": "1111|100|0101|1|Rn|Rd|off:12" , "it": "any"},
|
|
{"inst": "ldrh Rd!=XX, [Rn!=PC, #+/-off]{@}{!}" , "t32": "1111|100|0001|1|Rn|Rd|1PUW|off:8" , "it": "any"},
|
|
{"inst": "ldrh Rd!=XX, [Rn==PC, #+/-off]" , "t32": "1111|100|0U01|1|Rn|Rd|off:12" , "it": "any"},
|
|
{"inst": "ldrht Rd!=XX, [Rn!=PC, #off]" , "t32": "1111|100|0001|1|Rn|Rd|1110|off:8" , "it": "any"},
|
|
{"inst": "ldrsb Rd!=HI, [Rn!=HI, Rm!=HI]" , "t16": "0101|011|Rm:3|Rn:3|Rd:3" , "it": "any"},
|
|
{"inst": "ldrsb Rd!=XX, [Rn!=PC, Rm!=XX, {lsl #n}]" , "t32": "1111|100|1000|1|Rn|Rd|0|00000|n:2|Rm" , "it": "any"},
|
|
{"inst": "ldrsb Rd!=XX, [Rn!=PC, #off]" , "t32": "1111|100|1100|1|Rn|Rd|off:12" , "it": "any"},
|
|
{"inst": "ldrsb Rd!=XX, [Rn!=PC, #+/-off]{@}{!}" , "t32": "1111|100|1000|1|Rn|Rd|1PUW|off:8" , "it": "any"},
|
|
{"inst": "ldrsb Rd!=XX, [Rn==PC, #+/-off]" , "t32": "1111|100|1U00|1|Rn|Rd|off:12" , "it": "any"},
|
|
{"inst": "ldrsbt Rd!=XX, [Rn!=PC, #off]" , "t32": "1111|100|1000|1|Rn|Rd|1110|off:8" , "it": "any"},
|
|
{"inst": "ldrsh Rd!=HI, [Rn!=HI, Rm!=HI]" , "t16": "0101|111|Rm:3|Rn:3|Rd:3" , "it": "any"},
|
|
{"inst": "ldrsh Rd!=XX, [Rn!=PC, Rm!=XX, {lsl #n}]" , "t32": "1111|100|1001|1|Rn|Rd|0|00000|n:2|Rm" , "it": "any"},
|
|
{"inst": "ldrsh Rd!=XX, [Rn!=PC, #off]" , "t32": "1111|100|1101|1|Rn|Rd|off:12" , "it": "any"},
|
|
{"inst": "ldrsh Rd!=XX, [Rn!=PC, #+/-off]{@}{!}" , "t32": "1111|100|1001|1|Rn|Rd|1PUW|off:8" , "it": "any"},
|
|
{"inst": "ldrsh Rd!=XX, [Rn==PC, #+/-off]" , "t32": "1111|100|1U01|1|Rn|Rd|off:12" , "it": "any"},
|
|
{"inst": "ldrsht Rd!=XX, [Rn!=PC, #off]" , "t32": "1111|100|1001|1|Rn|Rd|1110|off:8" , "it": "any"},
|
|
{"inst": "ldrt Rd!=XX, [Rn!=PC, #off]" , "t32": "1111|100|0010|1|Rn|Rd|1110|off:8" , "it": "any"},
|
|
{"inst": "lsl Rd!=HI, Rn!=HI, #n" , "t16": "0000|0|n:5|Rn:3|Rd:3" , "it": "in"},
|
|
{"inst": "lsl Rd!=XX, Rn!=XX, #n" , "t32": "1110|101|0010|0|1111|0|n:3|Rd|n:2|00|Rn" , "it": "any"},
|
|
{"inst": "lsl Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|000|010|Rm:3|Rx:3" , "it": "in"},
|
|
{"inst": "lsl Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0000|0|Rn|1111|Rd|0000|Rm" , "it": "any"},
|
|
{"inst": "lslS Rd!=HI, Rn!=HI, #n" , "t16": "0000|0|n:5|Rn:3|Rd:3" , "it": "out", "io": "N=W Z=W C=W"},
|
|
{"inst": "lslS Rd!=XX, Rn!=XX, #n" , "t32": "1110|101|0010|1|1111|0|n:3|Rd|n:2|00|Rn" , "it": "any", "io": "N=W Z=W C=W"},
|
|
{"inst": "lslS Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|000|010|Rm:3|Rx:3" , "it": "out", "io": "N=W Z=W C=W"},
|
|
{"inst": "lslS Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1110|101|0000|1|Rn|1111|Rd|0000|Rm" , "it": "any", "io": "N=W Z=W C=W"},
|
|
{"inst": "lsr Rd!=HI, Rn!=HI, #n" , "t16": "0000|1|n:5|Rn:3|Rd:3" , "it": "in"},
|
|
{"inst": "lsr Rd!=XX, Rn!=XX, #n" , "t32": "1110|101|0010|0|1111|0|n:3|Rd|n:2|01|Rn" , "it": "any"},
|
|
{"inst": "lsr Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|000|011|Rm:3|Rx:3" , "it": "in"},
|
|
{"inst": "lsr Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0001|0|Rn|1111|Rd|0000|Rm" , "it": "any"},
|
|
{"inst": "lsrS Rd!=HI, Rn!=HI, #n" , "t16": "0000|1|n:5|Rn:3|Rd:3" , "it": "out", "io": "N=W Z=W C=W"},
|
|
{"inst": "lsrS Rd!=XX, Rn!=XX, #n" , "t32": "1110|101|0010|1|1111|0|n:3|Rd|n:2|01|Rn" , "it": "any", "io": "N=W Z=W C=W"},
|
|
{"inst": "lsrS Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|000|011|Rm:3|Rx:3" , "it": "out", "io": "N=W Z=W C=W"},
|
|
{"inst": "lsrS Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1110|101|0001|1|Rn|1111|Rd|0000|Rm" , "it": "any", "io": "N=W Z=W C=W"},
|
|
{"inst": "mcr #CP, #Op1, Rs!=XX, Cn, Cm, {#Op2}" , "t32": "1110|111|0|Op1:3|0|Cn:4|Rs|CP:4|Op2:3|1|Cm:4" , "ext": "ARMv6T2+"},
|
|
{"inst": "mcr2 #CP, #Op1, Rs!=XX, Cn, Cm, {#Op2}" , "t32": "1111|111|0|Op1:3|0|Cn:4|Rs|CP:4|Op2:3|1|Cm:4" , "ext": "ARMv6T2+"},
|
|
{"inst": "mcrr #CP, #Op1, Rs!=XX, Rs2!=XX, Cm" , "t32": "1110|110|0010|0|Rs2|Rs|CP:4|Op1:4|Cm:4" , "ext": "ARMv6T2+"},
|
|
{"inst": "mcrr2 #CP, #Op1, Rs!=XX, Rs2!=XX, Cm" , "t32": "1111|110|0010|0|Rs2|Rs|CP:4|Op1:4|Cm:4" , "ext": "ARMv6T2+"},
|
|
{"inst": "mla Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "t32": "1111|101|1000|0|Rn|Ra|Rd|0000|Rm" , "it": "any"},
|
|
{"inst": "mls Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "t32": "1111|101|1000|0|Rn|Ra|Rd|0001|Rm" , "it": "any"},
|
|
{"inst": "mov Rd, Rn" , "t16": "0100|0110|Rd:1|Rn:4|Rd:3" , "it": "in", "mod": "ARMv6T2_IF_LOW"},
|
|
{"inst": "mov Rx!=HI, Rx!=HI, lsl Rm!=HI" , "t16": "0100|000|010|Rm:3|Rx:3" , "it": "in"},
|
|
{"inst": "mov Rx!=HI, Rx!=HI, lsr Rm!=HI" , "t16": "0100|000|011|Rm:3|Rx:3" , "it": "in"},
|
|
{"inst": "mov Rx!=HI, Rx!=HI, asr Rm!=HI" , "t16": "0100|000|100|Rm:3|Rx:3" , "it": "in"},
|
|
{"inst": "mov Rx!=HI, Rx!=HI, ror Rm!=HI" , "t16": "0100|000|111|Rm:3|Rx:3" , "it": "in"},
|
|
{"inst": "mov Rd!=HI, Rn!=HI, lsl #n" , "t16": "0000|0|n:5|Rn:3|Rd:3" , "it": "in"},
|
|
{"inst": "mov Rd!=HI, Rn!=HI, lsr #n" , "t16": "0000|1|n:5|Rn:3|Rd:3" , "it": "in"},
|
|
{"inst": "mov Rd!=HI, Rn!=HI, asr #n" , "t16": "0001|0|n:5|Rn:3|Rd:3" , "it": "in"},
|
|
{"inst": "mov Rd!=HI, #immZ" , "t16": "0010|0|Rd:3|immZ:8" , "it": "in"},
|
|
{"inst": "mov Rd!=PC, Rn" , "t32": "1110|101|0010|0|1111|0000|Rd|0000|Rn" , "it": "any", "mod": "UNPRED_COMPLEX"},
|
|
{"inst": "mov Rd!=XX, Rn!=XX, sop #n" , "t32": "1110|101|0010|0|1111|0|n:3|Rd|n:2|sop:2|Rn" , "it": "any"},
|
|
{"inst": "mov Rd!=XX, Rn!=XX, sop Rm!=XX" , "t32": "1111|101|00|sop:2|0|Rn|1111|Rd|0000|Rm" , "it": "any"},
|
|
{"inst": "mov Rd!=XX, #immA" , "t32": "1111|0|imm:1|0|0010|0|1111|0|imm:3|Rd|imm:8" , "it": "any"},
|
|
{"inst": "movS Rd!=HI, Rn!=HI" , "t16": "0000|0000|00|Rn:3|Rd:3" , "it": "out", "io": "N=W Z=W C=W"},
|
|
{"inst": "movS Rx!=HI, Rx!=HI, lsl Rm!=HI" , "t16": "0100|000|010|Rm:3|Rx:3" , "it": "out", "io": "N=W Z=W C=W"},
|
|
{"inst": "movS Rx!=HI, Rx!=HI, lsr Rm!=HI" , "t16": "0100|000|011|Rm:3|Rx:3" , "it": "out", "io": "N=W Z=W C=W"},
|
|
{"inst": "movS Rx!=HI, Rx!=HI, asr Rm!=HI" , "t16": "0100|000|100|Rm:3|Rx:3" , "it": "out", "io": "N=W Z=W C=W"},
|
|
{"inst": "movS Rx!=HI, Rx!=HI, ror Rm!=HI" , "t16": "0100|000|111|Rm:3|Rx:3" , "it": "out", "io": "N=W Z=W C=W"},
|
|
{"inst": "movS Rd!=HI, Rn!=HI, lsl #n" , "t16": "0000|0|n:5|Rn:3|Rd:3" , "it": "out", "io": "N=W Z=W C=W"},
|
|
{"inst": "movS Rd!=HI, Rn!=HI, lsr #n" , "t16": "0000|1|n:5|Rn:3|Rd:3" , "it": "out", "io": "N=W Z=W C=W"},
|
|
{"inst": "movS Rd!=HI, Rn!=HI, asr #n" , "t16": "0001|0|n:5|Rn:3|Rd:3" , "it": "out", "io": "N=W Z=W C=W"},
|
|
{"inst": "movS Rd!=HI, #immZ" , "t16": "0010|0|Rd:3|immZ:8" , "it": "out", "io": "N=W Z=W C=W"},
|
|
{"inst": "movS Rd!=XX, Rn" , "t32": "1110|101|0010|1|1111|0000|Rd|0000|Rn" , "it": "any", "io": "N=W Z=W C=W", "mod": "UNPRED_COMPLEX"},
|
|
{"inst": "movS Rd!=XX, Rn!=XX, sop Rm!=XX" , "t32": "1110|101|00|sop:2|1|Rn|1111|Rd|0000|Rm" , "it": "any", "io": "N=W Z=W C=W"},
|
|
{"inst": "movS Rd!=XX, Rn!=XX, sop #n" , "t32": "1110|101|0010|1|1111|0|n:3|Rd|n:2|sop:2|Rn" , "it": "any", "io": "N=W Z=W C=W"},
|
|
{"inst": "movS Rd!=XX, #immA" , "t32": "1111|0|imm:1|0|0010|1|1111|0|imm:3|Rd|imm:8" , "it": "any", "io": "N=W Z=W C=W"},
|
|
{"inst": "movt Rx!=XX, #immZ" , "t32": "1111|0|immZ:1|1|0110|0|immZ:4|0|immZ:3|Rx|immZ:8" , "it": "any"},
|
|
{"inst": "movw Rd!=XX, #immZ" , "t32": "1111|0|immZ:1|1|0010|0|immZ:4|0|immZ:3|Rd|immZ:8" , "it": "any"},
|
|
{"inst": "mrc #CP, #op1, Rd!=XX, Cn, Cm, {#op2}" , "t32": "1110|111|0|op1:3|1|Cn:4|Rd|CP:4|op2:3|1|Cm:4" , "it": "any"},
|
|
{"inst": "mrc2 #CP, #op1, Rd!=XX, Cn, Cm, {#op2}" , "t32": "1111|111|0|op1:3|1|Cn:4|Rd|CP:4|op2:3|1|Cm:4" , "it": "any"},
|
|
{"inst": "mrrc #CP, #op1, Rd!=XX, Rd2!=Rd, Cm" , "t32": "1110|110|0010|1|Rd2|Rd|CP:4|op1:4|Cm:4" , "it": "any"},
|
|
{"inst": "mrrc2 #CP, #op1, Rd!=XX, Rd2!=Rd, Cm" , "t32": "1111|110|0010|1|Rd2|Rd|CP:4|op1:4|Cm:4" , "it": "any"},
|
|
{"inst": "mrs Rd!=XX, #APSR" , "t32": "11110011111|APSR:1|1111|1000|Rd|0000|0000" , "it": "any"},
|
|
{"inst": "msr #APSR, Rn!=PC" , "t32": "1111|001|1100|0|Rn|1100|APSR:2|00|0000|0000" , "it": "any"},
|
|
{"inst": "mul Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|001|101|Rm:3|Rx:3" , "it": "in"},
|
|
{"inst": "mulS Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|001|101|Rm:3|Rx:3" , "it": "out", "io": "N=W Z=W"},
|
|
{"inst": "mul Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1000|0|Rn|1111|Rd|0000|Rm" , "it": "any"},
|
|
{"inst": "mvn Rd!=HI, Rn!=HI" , "t16": "0100|001|111|Rn:3|Rd:3" , "it": "in"},
|
|
{"inst": "mvn Rd!=XX, Rn!=XX, {sop #n}" , "t32": "1110|101|0011|0|1111|0|n:3|Rd|n:2|sop:2|Rn" , "it": "any"},
|
|
{"inst": "mvn Rd!=XX, #immA" , "t32": "1111|0|imm:1|0|0011|0|1111|0|imm:3|Rd|imm:8" , "it": "any"},
|
|
{"inst": "mvnS Rd!=HI, Rn!=HI" , "t16": "0100|001|111|Rn:3|Rd:3" , "it": "out", "io": "N=W Z=W C=W"},
|
|
{"inst": "mvnS Rd!=XX, Rn!=XX, {sop #n}" , "t32": "1110|101|0011|1|1111|0|n:3|Rd|n:2|sop:2|Rn" , "it": "any", "io": "N=W Z=W C=W"},
|
|
{"inst": "mvnS Rd!=XX, #immA" , "t32": "1111|0|imm:1|0|0011|1|1111|0|imm:3|Rd|imm:8" , "it": "any", "io": "N=W Z=W C=W"},
|
|
{"inst": "nop" , "t16": "1011|111|1000|0|0000" , "it": "any"},
|
|
{"inst": "nop" , "t32": "1111|001|1101|0|1111|1000|0000|0000|0000" , "it": "any"},
|
|
{"inst": "orn Rd!=XX, Rn!=XX, Rm!=XX, {sop #n}" , "t32": "1110|101|0011|0|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any"},
|
|
{"inst": "orn Rd!=XX, Rn!=XX, #immA" , "t32": "1111|0|imm:1|0|0011|0|Rn|0|imm:3|Rd|imm:8" , "it": "any"},
|
|
{"inst": "ornS Rd!=XX, Rn!=XX, Rm!=XX, {sop #n}" , "t32": "1110|101|0011|1|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any", "io": "N=W Z=W C=W"},
|
|
{"inst": "ornS Rd!=XX, Rn!=XX, #immA" , "t32": "1111|0|imm:1|0|0011|1|Rn|0|imm:3|Rd|imm:8" , "it": "any", "io": "N=W Z=W C=W"},
|
|
{"inst": "orr Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|001|100|Rm:3|Rx:3" , "it": "in"},
|
|
{"inst": "orr Rd!=XX, Rn!=XX, Rm!=XX, {sop #n}" , "t32": "1110|101|0010|0|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any"},
|
|
{"inst": "orr Rd!=XX, Rn!=XX, #immA" , "t32": "1111|0|imm:1|0|0010|0|Rn|0|imm:3|Rd|imm:8" , "it": "any"},
|
|
{"inst": "orrS Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|001|100|Rm:3|Rx:3" , "it": "out", "io": "N=W Z=W C=W"},
|
|
{"inst": "orrS Rd!=XX, Rn!=XX, Rm!=XX, {sop #n}" , "t32": "1110|101|0010|1|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any", "io": "N=W Z=W C=W"},
|
|
{"inst": "orrS Rd!=XX, Rn!=XX, #immA" , "t32": "1111|0|imm:1|0|0010|1|Rn|0|imm:3|Rd|imm:8" , "it": "any", "io": "N=W Z=W C=W"},
|
|
{"inst": "pkhbt Rd!=XX, Rn!=XX, Rm!=XX, {lsl #n}" , "t32": "1110|101|0110|0|Rn|0|n:3|Rd|n:2|00|Rm" , "it": "any"},
|
|
{"inst": "pkhtb Rd!=XX, Rn!=XX, Rm!=XX, {asr #n}" , "t32": "1110|101|0110|0|Rn|0|n:3|Rd|n:2|10|Rm" , "it": "any"},
|
|
{"inst": "pld [Rn!=PC, Rm!=XX, {lsl #n}]" , "t32": "1111|100|0000|1|Rn|1111|0000|00|n:2|Rm" , "it": "any"},
|
|
{"inst": "pld [Rn!=PC, #off]" , "t32": "1111|100|0100|1|Rn|1111|off:12" , "it": "any"},
|
|
{"inst": "pld [Rn!=PC, #-off]" , "t32": "1111|100|0000|1|Rn|1111|1100|off:8" , "it": "any"},
|
|
{"inst": "pld [Rn==PC, #+/-off]" , "t32": "1111|100|0U00|1|Rn|1111|off:12" , "it": "any"},
|
|
{"inst": "pldw [Rn!=PC, Rm!=XX, {lsl #n}]" , "t32": "1111|100|0001|1|Rn|1111|0000|00|n:2|Rm" , "it": "any"},
|
|
{"inst": "pldw [Rn!=PC, #off]" , "t32": "1111|100|0101|1|Rn|1111|off:12" , "it": "any"},
|
|
{"inst": "pldw [Rn!=PC, #-off]" , "t32": "1111|100|0001|1|Rn|1111|1100|off:8" , "it": "any"},
|
|
{"inst": "pop Rd!=SP" , "t32": "1111|100|0010|1|1101|Rd|1011|00000100" , "it": "any"},
|
|
{"inst": "pop RdList" , "t16": "1011|110|immMask[15]|immMask[7:0]" , "it": "any", "imm": "GpListImm(RsList, 0x80FF)"},
|
|
{"inst": "pop RdList" , "t32": "1110|100|0101|1|1101|immMask[15:14]|0|immMask[12:0]" , "it": "any", "imm": "GpListImm(RsList, 0xDFFF)"},
|
|
{"inst": "push Rs!=XX" , "t32": "1111|100|0010|0|1101|Rs|1101|0000|0100" , "it": "any"},
|
|
{"inst": "push RsList" , "t16": "1011|010|immMask[14]|immMask[7:0]" , "it": "any", "imm": "GpListImm(RsList, 0x40FF)"},
|
|
{"inst": "push RsList" , "t32": "1110|100|0101|0|1101|0|immMask[14]|0|immMask[12:0]" , "it": "any", "imm": "GpListImm(RsList, 0x5FFF)"},
|
|
{"inst": "qadd Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0100|0|Rm|1111|Rd|1000|Rn" , "it": "any", "io": "Q=X"},
|
|
{"inst": "qadd16 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0100|1|Rm|1111|Rd|0001|Rn" , "it": "any"},
|
|
{"inst": "qadd8 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0100|0|Rm|1111|Rd|0001|Rn" , "it": "any"},
|
|
{"inst": "qasx Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0101|0|Rm|1111|Rd|0001|Rn" , "it": "any"},
|
|
{"inst": "qdadd Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0100|0|Rm|1111|Rd|1001|Rn" , "it": "any", "io": "Q=X"},
|
|
{"inst": "qdsub Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0100|0|Rm|1111|Rd|1011|Rn" , "it": "any", "io": "Q=X"},
|
|
{"inst": "qsax Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0111|0|Rm|1111|Rd|0001|Rn" , "it": "any"},
|
|
{"inst": "qsub Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0100|0|Rm|1111|Rd|1010|Rn" , "it": "any", "io": "Q=X"},
|
|
{"inst": "qsub16 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0110|1|Rm|1111|Rd|0001|Rn" , "it": "any"},
|
|
{"inst": "qsub8 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0110|0|Rm|1111|Rd|0001|Rn" , "it": "any"},
|
|
{"inst": "rbit Rd!=XX, Rn!=XX" , "t32": "1111|101|0100|1|Rm|1111|Rd|1010|Rn" , "it": "any"},
|
|
{"inst": "rev Rd!=HI, Rn!=HI" , "t16": "1011|101|000|Rn:3|Rd:3" , "it": "any"},
|
|
{"inst": "rev Rd!=XX, Rn!=XX" , "t32": "1111|101|0100|1|Rm|1111|Rd|1000|Rn" , "it": "any"},
|
|
{"inst": "rev16 Rd!=HI, Rn!=HI" , "t16": "1011|101|001|Rn:3|Rd:3" , "it": "any"},
|
|
{"inst": "rev16 Rd!=XX, Rn!=XX" , "t32": "1111|101|0100|1|Rm|1111|Rd|1001|Rn" , "it": "any"},
|
|
{"inst": "revsh Rd!=HI, Rn!=HI" , "t16": "1011|101|011|Rn:3|Rd:3" , "it": "any"},
|
|
{"inst": "revsh Rd!=XX, Rn!=XX" , "t32": "1111|101|0100|1|Rm|1111|Rd|1011|Rn" , "it": "any"},
|
|
{"inst": "ror Rd!=XX, Rn!=XX, #n" , "t32": "1110|101|0010|0|1111|0|n:3|Rd|n:2|11|Rn" , "it": "any"},
|
|
{"inst": "ror Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|000|111|Rm:3|Rx:3" , "it": "in"},
|
|
{"inst": "ror Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0011|0|Rn|1111|Rd|0000|Rm" , "it": "any"},
|
|
{"inst": "rorS Rd!=XX, Rn!=XX, #n" , "t32": "1110|101|0010|1|1111|0|n:3|Rd|n:2|11|Rn" , "it": "any", "io": "N=W Z=W C=W"},
|
|
{"inst": "rorS Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|000|111|Rm:3|Rx:3" , "it": "out", "io": "N=W Z=W C=W"},
|
|
{"inst": "rorS Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0011|1|Rn|1111|Rd|0000|Rm" , "it": "any", "io": "N=W Z=W C=W"},
|
|
{"inst": "rsb Rd!=HI, Rn!=HI, #zero" , "t16": "0100|001001|Rn:3|Rd:3" , "it": "in"},
|
|
{"inst": "rsb Rd!=XX, Rn!=XX, Rm!=XX, {sop #n}" , "t32": "1110|101|1110|0|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any"},
|
|
{"inst": "rsb Rd!=XX, Rn!=XX, #immA" , "t32": "1111|0|imm:1|0|1110|0|Rn|0|imm:3|Rd|imm:8" , "it": "any"},
|
|
{"inst": "rsbS Rd!=HI, Rn!=HI, #zero" , "t16": "0100|001001|Rn:3|Rd:3" , "it": "out", "io": "N=W Z=W C=W V=W"},
|
|
{"inst": "rsbS Rd!=XX, Rn!=XX, Rm!=XX, {sop #n}" , "t32": "1110|101|1110|1|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any", "io": "N=W Z=W C=W V=W"},
|
|
{"inst": "rsbS Rd!=XX, Rn!=XX, #immA" , "t32": "1111|0|imm:1|0|1110|1|Rn|0|imm:3|Rd|imm:8" , "it": "any", "io": "N=W Z=W C=W V=W"},
|
|
{"inst": "rrx Rd!=XX, Rn!=XX" , "t32": "1110|101|0010|0|1111|0000|Rd|0011|Rn" , "it": "any", "io": "C=R"},
|
|
{"inst": "rrxS Rd!=XX, Rn!=XX" , "t32": "1110|101|0010|1|1111|0000|Rd|0011|Rn" , "it": "any", "io": "N=W Z=W C=W"},
|
|
{"inst": "sadd16 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0100|1|Rn|1111|Rd|0000|Rm" , "it": "any", "io": "GE=W"},
|
|
{"inst": "sadd8 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0100|0|Rn|1111|Rd|0000|Rm" , "it": "any", "io": "GE=W"},
|
|
{"inst": "sasx Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0101|0|Rn|1111|Rd|0000|Rm" , "it": "any", "io": "GE=W"},
|
|
{"inst": "sbc Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|000|110|Rm:3|Rx:3" , "it": "in"},
|
|
{"inst": "sbc Rd!=XX, Rn!=XX, Rm!=XX, {sop #n}" , "t32": "1110|101|1011|0|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any"},
|
|
{"inst": "sbc Rd!=XX, Rn!=XX, #immA" , "t32": "1111|0|imm:1|0|1011|0|Rn|0|imm:3|Rd|imm:8" , "it": "any"},
|
|
{"inst": "sbcS Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|000|110|Rm:3|Rx:3" , "it": "out", "io": "N=W Z=W C=W V=W"},
|
|
{"inst": "sbcS Rd!=XX, Rn!=XX, Rm!=XX, {sop #n}" , "t32": "1110|101|1011|1|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any", "io": "N=W Z=W C=W V=W"},
|
|
{"inst": "sbcS Rd!=XX, Rn!=XX, #immA" , "t32": "1111|0|imm:1|0|1011|1|Rn|0|imm:3|Rd|imm:8" , "it": "any", "io": "N=W Z=W C=W V=W"},
|
|
{"inst": "sbfx Rd!=XX, Rn!=XX, #lsb, #width" , "t32": "1111|001|1010|0|Rn|0|lsb:3|Rd|lsb:2|0|widthM1:5" , "it": "any", "imm": "SbfxUbfxImm(lsb, width)"},
|
|
{"inst": "sel Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0101|0|Rn|1111|Rd|1000|Rm" , "it": "any"},
|
|
{"inst": "setend #immZ" , "t16": "1011|0110|010|1|immZ:1|000" , "it": "out"},
|
|
{"inst": "shadd16 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0100|1|Rn|1111|Rd|0010|Rm" , "it": "any"},
|
|
{"inst": "shadd8 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0100|0|Rn|1111|Rd|0010|Rm" , "it": "any"},
|
|
{"inst": "shasx Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0101|0|Rn|1111|Rd|0010|Rm" , "it": "any"},
|
|
{"inst": "shsax Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0111|0|Rn|1111|Rd|0010|Rm" , "it": "any"},
|
|
{"inst": "shsub16 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0110|1|Rn|1111|Rd|0010|Rm" , "it": "any"},
|
|
{"inst": "shsub8 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0110|0|Rn|1111|Rd|0010|Rm" , "it": "any"},
|
|
{"inst": "smlabb Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "t32": "1111|101|1001|1|Rn|Ra|Rd|0000|Rm" , "it": "any", "io": "Q=X"},
|
|
{"inst": "smlabt Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "t32": "1111|101|1001|1|Rn|Ra|Rd|0001|Rm" , "it": "any", "io": "Q=X"},
|
|
{"inst": "smlatb Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "t32": "1111|101|1001|1|Rn|Ra|Rd|0010|Rm" , "it": "any", "io": "Q=X"},
|
|
{"inst": "smlatt Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "t32": "1111|101|1001|1|Rn|Ra|Rd|0011|Rm" , "it": "any", "io": "Q=X"},
|
|
{"inst": "smlad Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "t32": "1111|101|1001|0|Rn|Ra|Rd|0000|Rm" , "it": "any", "io": "Q=X"},
|
|
{"inst": "smladx Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "t32": "1111|101|1001|0|Rn|Ra|Rd|0001|Rm" , "it": "any", "io": "Q=X"},
|
|
{"inst": "smlal RxLo!=XX, RxHi!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1110|0|Rn|RxLo|RxHi|0000|Rm" , "it": "any"},
|
|
{"inst": "smlalbb RxLo!=XX, RxHi!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1110|0|Rn|RxLo|RxHi|1000|Rm" , "it": "any"},
|
|
{"inst": "smlalbt RxLo!=XX, RxHi!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1110|0|Rn|RxLo|RxHi|1001|Rm" , "it": "any"},
|
|
{"inst": "smlaltb RxLo!=XX, RxHi!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1110|0|Rn|RxLo|RxHi|1010|Rm" , "it": "any"},
|
|
{"inst": "smlaltt RxLo!=XX, RxHi!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1110|0|Rn|RxLo|RxHi|1011|Rm" , "it": "any"},
|
|
{"inst": "smlald RxLo!=XX, RxHi!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1110|0|Rn|RxLo|RxHi|1100|Rm" , "it": "any"},
|
|
{"inst": "smlaldx RxLo!=XX, RxHi!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1110|0|Rn|RxLo|RxHi|1101|Rm" , "it": "any"},
|
|
{"inst": "smlawb Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "t32": "1111|101|1001|1|Rn|Ra|Rd|0000|Rm" , "it": "any", "io": "Q=X"},
|
|
{"inst": "smlawt Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "t32": "1111|101|1001|1|Rn|Ra|Rd|0001|Rm" , "it": "any", "io": "Q=X"},
|
|
{"inst": "smlsd Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "t32": "1111|101|1010|1|Rn|Ra|Rd|0000|Rm" , "it": "any", "io": "Q=X"},
|
|
{"inst": "smlsdx Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "t32": "1111|101|1010|1|Rn|Ra|Rd|0001|Rm" , "it": "any", "io": "Q=X"},
|
|
{"inst": "smlsld RxLo!=XX, RxHi!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1110|1|Rn|RxLo|RxHi|1100|Rm" , "it": "any", "io": "Q=X"},
|
|
{"inst": "smlsldx RxLo!=XX, RxHi!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1110|1|Rn|RxLo|RxHi|1101|Rm" , "it": "any", "io": "Q=X"},
|
|
{"inst": "smmla Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "t32": "1111|101|1010|1|Rn|Ra|Rd|0000|Rm" , "it": "any"},
|
|
{"inst": "smmlar Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "t32": "1111|101|1010|1|Rn|Ra|Rd|0001|Rm" , "it": "any"},
|
|
{"inst": "smmls Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "t32": "1111|101|1011|0|Rn|Ra|Rd|0000|Rm" , "it": "any"},
|
|
{"inst": "smmlsr Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "t32": "1111|101|1011|0|Rn|Ra|Rd|0001|Rm" , "it": "any"},
|
|
{"inst": "smmul Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1010|1|Rn|1111|Rd|0000|Rm" , "it": "any"},
|
|
{"inst": "smmulr Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1010|1|Rn|1111|Rd|0001|Rm" , "it": "any"},
|
|
{"inst": "smuad Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1001|0|Rn|1111|Rd|0000|Rm" , "it": "any", "io": "Q=X"},
|
|
{"inst": "smuadx Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1001|0|Rn|1111|Rd|0001|Rm" , "it": "any", "io": "Q=X"},
|
|
{"inst": "smulbb Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1000|1|Rn|1111|Rd|0000|Rm" , "it": "any"},
|
|
{"inst": "smulbt Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1000|1|Rn|1111|Rd|0001|Rm" , "it": "any"},
|
|
{"inst": "smultb Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1000|1|Rn|1111|Rd|0010|Rm" , "it": "any"},
|
|
{"inst": "smultt Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1000|1|Rn|1111|Rd|0011|Rm" , "it": "any"},
|
|
{"inst": "smull RdLo!=XX, RdHi!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1100|0|Rn|RdLo|RdHi|0000|Rm" , "it": "any"},
|
|
{"inst": "smulwb Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1001|1|Rn|1111|Rd|0000|Rm" , "it": "any"},
|
|
{"inst": "smulwt Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1001|1|Rn|1111|Rd|0001|Rm" , "it": "any"},
|
|
{"inst": "smusd Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1010|0|Rn|1111|Rd|0000|Rm" , "it": "any"},
|
|
{"inst": "smusdx Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1010|0|Rn|1111|Rd|0001|Rm" , "it": "any"},
|
|
{"inst": "ssat Rd!=XX, #sat, Rn!=XX" , "t32": "1111|001|100|00|Rn|0|000|Rd|00|0|imm:5" , "it": "any", "imm": "SsatImm(sat)", "io": "Q=X"},
|
|
{"inst": "ssat Rd!=XX, #sat, Rn!=XX, lsl_or_asr #n" , "t32": "1111|001|100|sop:2|Rn|0|n:3|Rd|n:2|0|imm:5" , "it": "any", "imm": "SsatImm(sat, n)", "io": "Q=X"},
|
|
{"inst": "ssat16 Rd!=XX, #sat, Rn!=XX" , "t32": "1111|001|1001|0|Rn|0000|Rd|0000|imm:4" , "it": "any", "imm": "Ssat16Imm(sat)", "io": "Q=X"},
|
|
{"inst": "ssax Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0111|0|Rn|1111|Rd|0000|Rm" , "it": "any", "io": "GE=W"},
|
|
{"inst": "ssub16 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0110|1|Rn|1111|Rd|0000|Rm" , "it": "any", "io": "GE=W"},
|
|
{"inst": "ssub8 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0110|0|Rn|1111|Rd|0000|Rm" , "it": "any", "io": "GE=W"},
|
|
{"inst": "stmia [Rn!=HI]!, RsList" , "t16": "1100|0|Rn:3|immMask:8" , "it": "any", "imm": "GpListImm(RsList, 0xFF)"},
|
|
{"inst": "stmia [Rn!=PC]{!}, RsList" , "t32": "1110|100|010W|0|Rn|0|immMask[14]|0|immMask[12:0]" , "it": "any", "imm": "GpListImm(RsList, 0x5FFF)"},
|
|
{"inst": "stmdb [Rn!=PC]{!}, RsList" , "t32": "1110|100|100W|0|Rn|0|immMask[14]|0|immMask[12:0]" , "it": "any", "imm": "GpListImm(RsList, 0x5FFF)"},
|
|
{"inst": "str Rs!=HI, [Rn!=HI, Rm!=HI]" , "t16": "0101|000|Rm:3|Rn:3|Rs:3" , "it": "any"},
|
|
{"inst": "str Rs!=PC, [Rn!=PC, Rm!=XX, {lsl #n}]" , "t32": "1111|100|0010|0|Rn|Rs|0|00000|n:2|Rm" , "it": "any"},
|
|
{"inst": "str Rs!=HI, [Rn==SP, #off*4]" , "t16": "1001|0|Rs:3|off:8" , "it": "any"},
|
|
{"inst": "str Rs!=HI, [Rn!=HI, #off*4]" , "t16": "0110|0|off:5|Rn:3|Rs:3" , "it": "any"},
|
|
{"inst": "str Rs!=PC, [Rn!=PC, #off]" , "t32": "1111|100|0110|0|Rn|Rs|off:12" , "it": "any"},
|
|
{"inst": "str Rs!=PC, [Rn!=PC, #+/-off]{@}{!}" , "t32": "1111|100|0010|0|Rn|Rs|1PUW|off:8" , "it": "any"},
|
|
{"inst": "strb Rs!=HI, [Rn!=HI, Rm!=HI]" , "t16": "0101|010|Rm:3|Rn:3|Rs:3" , "it": "any"},
|
|
{"inst": "strb Rs!=XX, [Rn!=PC, Rm!=XX, {lsl #n}]" , "t32": "1111|100|0000|0|Rn|Rs|0|00000|n:2|Rm" , "it": "any"},
|
|
{"inst": "strb Rs!=HI, [Rn!=HI, #off*4]" , "t16": "0111|0|off:5|Rn:3|Rs:3" , "it": "any"},
|
|
{"inst": "strb Rs!=XX, [Rn!=PC, #off]" , "t32": "1111|100|0100|0|Rn|Rs|off:12" , "it": "any"},
|
|
{"inst": "strb Rs!=XX, [Rn!=PC, #+/-off]{@}{!}" , "t32": "1111|100|0000|0|Rn|Rs|1PUW|off:8" , "it": "any"},
|
|
{"inst": "strbt Rs!=XX, [Rn!=PC, #off]" , "t32": "1111|100|0000|0|Rn|Rs|1110|off:8" , "it": "any"},
|
|
{"inst": "strd Rs!=XX, Rs2!=XX, [Rn!=PC, #off]{@}{!}" , "t32": "1110|100|PU1W|0|Rn|Rs|Rs2|off:8" , "it": "any"},
|
|
{"inst": "strex Rd!=XX, Rs!=XX, [Rn!=PC, #off]" , "t32": "1110|100|0010|0|Rn|Rs|Rd|off:8" , "it": "any", "mod": "UNPRED_COMPLEX"},
|
|
{"inst": "strexb Rd!=XX, Rs!=XX, [Rn!=PC]" , "t32": "1110|100|0110|0|Rn|Rs|1111|0100|Rd" , "it": "any", "mod": "UNPRED_COMPLEX"},
|
|
{"inst": "strexd Rd!=XX, Rs!=XX, Rs2!=XX, [Rn!=PC]" , "t32": "1110|100|0110|0|Rn|Rs|Rs2|0111|Rd" , "it": "any", "mod": "UNPRED_COMPLEX"},
|
|
{"inst": "strexh Rd!=XX, Rs!=XX, [Rn!=PC]" , "t32": "1110|100|0110|0|Rn|Rs|1111|0101|Rd" , "it": "any", "mod": "UNPRED_COMPLEX"},
|
|
{"inst": "strh Rs!=HI, [Rn!=HI, Rm!=HI]" , "t16": "0101|001|Rm:3|Rn:3|Rs:3" , "it": "any"},
|
|
{"inst": "strh Rs!=XX, [Rn!=PC, Rm!=XX, {lsl #n}]" , "t32": "1111|100|0001|0|Rn|Rs|0|00000|n:2|Rm" , "it": "any"},
|
|
{"inst": "strh Rs!=HI, [Rn!=HI, #off*4]" , "t16": "1000|0|off:5|Rn:3|Rs:3" , "it": "any"},
|
|
{"inst": "strh Rs!=XX, [Rn!=PC, #off]" , "t32": "1111|100|0101|0|Rn|Rs|off:12" , "it": "any"},
|
|
{"inst": "strh Rs!=XX, [Rn!=PC, #+/-off]{@}{!}" , "t32": "1111|100|0001|0|Rn|Rs|1PUW|off:8" , "it": "any"},
|
|
{"inst": "strht Rs!=XX, [Rn!=PC, #off]" , "t32": "1111|100|0001|0|Rn|Rs|1110|off:8" , "it": "any"},
|
|
{"inst": "strt Rs!=XX, [Rn!=PC, #off]" , "t32": "1111|100|0010|0|Rn|Rs|1110|off:8" , "it": "any"},
|
|
{"inst": "sub Rd!=HI, Rn!=HI, Rm!=HI" , "t16": "0001|101|Rm:3|Rn:3|Rd:3" , "it": "in"},
|
|
{"inst": "sub Rd!=HI, Rn!=HI, #immZ" , "t16": "0001|111|immZ:3|Rn:3|Rd:3" , "it": "in"},
|
|
{"inst": "sub Rx!=HI, Rx!=HI, #immZ" , "t16": "0011|1|Rx:3|immZ:8" , "it": "in"},
|
|
{"inst": "sub Rx==SP, Rx==SP, #immZ*4" , "t16": "1011|00001|immZ:7" , "it": "any"},
|
|
{"inst": "sub Rd!=XX, Rn!=XX, Rm!=XX, {sop #n}" , "t32": "1110|101|1101|0|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any"},
|
|
{"inst": "sub Rd!=PC, Rn==SP, Rm!=XX, {sop #n}" , "t32": "1110|101|1101|0|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any"},
|
|
{"inst": "sub Rd!=XX, Rn!=XX, #immA" , "t32": "1111|0|imm:1|0|1101|0|Rn|0|imm:3|Rd|imm:8" , "it": "any"},
|
|
{"inst": "sub Rd!=PC, Rn==SP, #immA" , "t32": "1111|0|imm:1|0|1101|0|Rn|0|imm:3|Rd|imm:8" , "it": "any"},
|
|
{"inst": "sub Rd!=XX, Rn!=XX, #immZ" , "t32": "1111|0|immZ:1|1|0101|0|Rn|0|immZ:3|Rd|immZ:8" , "it": "any"},
|
|
{"inst": "sub Rd!=HI, Rn!=HI, Rm!=HI" , "t16": "0001|101|Rm:3|Rn:3|Rd:3" , "it": "in"},
|
|
{"inst": "subS Rd!=HI, Rn!=HI, #immZ" , "t16": "0001|111|immZ:3|Rn:3|Rd:3" , "it": "out", "io": "N=W Z=W C=W V=W"},
|
|
{"inst": "subS Rx!=HI, Rx!=HI, #immZ" , "t16": "0001|1|Rx:3|immZ:8" , "it": "out", "io": "N=W Z=W C=W V=W"},
|
|
{"inst": "subS Rd!=XX, Rn!=XX, Rm!=XX, {sop #n}" , "t32": "1110|101|1101|1|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any", "io": "N=W Z=W C=W V=W"},
|
|
{"inst": "subS Rd!=PC, Rn==SP, Rm!=XX, {sop #n}" , "t32": "1110|101|1101|1|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any", "io": "N=W Z=W C=W V=W"},
|
|
{"inst": "subS Rd!=XX, Rn!=XX, #immA" , "t32": "1111|0|imm:1|0|1101|1|Rn|0|imm:3|Rd|imm:8" , "it": "any", "io": "N=W Z=W C=W V=W"},
|
|
{"inst": "subS Rd!=PC, Rn==SP, #immA" , "t32": "1111|0|imm:1|0|1101|1|Rn|0|imm:3|Rd|imm:8" , "it": "any", "io": "N=W Z=W C=W V=W"},
|
|
{"inst": "subS Rd!=XX, Rn!=XX, #immZ" , "t32": "1111|0|immZ:1|1|0101|1|Rn|0|immZ:3|Rd|immZ:8" , "it": "any", "io": "N=W Z=W C=W V=W"},
|
|
{"inst": "svc #immZ" , "t16": "1101|1111|immZ:8" , "it": "any"},
|
|
{"inst": "sxtab Rd!=XX, Rn!=XX, Rm!=XX, {ror #n}" , "t32": "1111|101|0010|0|Rn|1111|Rd|1|0|imm:2|Rm" , "it": "any", "imm": "Ror8Imm(n)"},
|
|
{"inst": "sxtab16 Rd!=XX, Rn!=XX, Rm!=XX, {ror #n}" , "t32": "1111|101|0001|0|Rn|1111|Rd|1|0|imm:2|Rm" , "it": "any", "imm": "Ror8Imm(n)"},
|
|
{"inst": "sxtah Rd!=XX, Rn!=XX, Rm!=XX, {ror #n}" , "t32": "1111|101|0000|0|Rn|1111|Rd|1|0|imm:2|Rm" , "it": "any", "imm": "Ror8Imm(n)"},
|
|
{"inst": "sxtb Rd!=HI, Rn!=HI, {ror #zero}" , "t16": "1011|001|001|Rn:3|Rd:3" , "it": "any"},
|
|
{"inst": "sxtb Rd!=XX, Rn!=XX, {ror #n}" , "t32": "1111|101|0010|0|1111|1111|Rd|10|imm:2|Rn" , "it": "any", "imm": "Ror8Imm(n)"},
|
|
{"inst": "sxtb16 Rd!=XX, Rn!=XX, {ror #n}" , "t32": "1111|101|0001|0|1111|1111|Rd|10|imm:2|Rn" , "it": "any", "imm": "Ror8Imm(n)"},
|
|
{"inst": "sxth Rd!=HI, Rn!=HI, {ror #zero}" , "t16": "1011|001|000|Rn:3|Rd:3" , "it": "any"},
|
|
{"inst": "sxth Rd!=XX, Rn!=XX, {ror #n}" , "t32": "1111|101|0000|0|1111|1111|Rd|10|imm:2|Rn" , "it": "any", "imm": "Ror8Imm(n)"},
|
|
{"inst": "tbb Rn!=SP, Rn!=XX" , "t32": "1110|100|0110|1|Rn|1111|0000|0000|Rn" , "it": "out last"},
|
|
{"inst": "tbh Rn!=SP, Rn!=XX" , "t32": "1110|100|0110|1|Rn|1111|0000|0001|Rn" , "it": "out last"},
|
|
{"inst": "teq Rn!=XX, Rn!=XX, {sop #n}" , "t32": "1110|101|0100|1|Rn|0|n:3|1111|n:2|sop:2|Rn" , "it": "any", "io": "N=W Z=W C=W"},
|
|
{"inst": "teq Rn!=XX, #immA" , "t32": "1111|0|imm:1|0|0100|1|Rn|0|imm:3|1111|imm:8" , "it": "any", "io": "N=W Z=W C=W"},
|
|
{"inst": "tst Rn!=HI, Rn!=HI" , "t16": "0100|00|1000|Rn:3|Rn:3" , "it": "any", "io": "N=W Z=W C=W"},
|
|
{"inst": "tst Rn!=XX, Rn!=XX, {sop #n}" , "t32": "1110|101|0000|1|Rn|0|n:3|1111|n:2|sop:2|Rn" , "it": "any", "io": "N=W Z=W C=W"},
|
|
{"inst": "tst Rn!=XX, #immA" , "t32": "1111|0|imm:1|0|0000|1|Rn|0|imm:3|1111|imm:8" , "it": "any", "io": "N=W Z=W C=W"},
|
|
{"inst": "uadd16 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0100|1|Rn|1111|Rd|0100|Rm" , "it": "any", "io": "GE=W"},
|
|
{"inst": "uadd8 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0100|0|Rn|1111|Rd|0100|Rm" , "it": "any", "io": "GE=W"},
|
|
{"inst": "uasx Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0101|0|Rn|1111|Rd|0100|Rm" , "it": "any", "io": "GE=W"},
|
|
{"inst": "ubfx Rd!=XX, Rn!=XX, #lsb, #width" , "t32": "1111|001|1110|0|Rn|0|lsb:3|Rd|lsb:2|0|widthM1:5" , "it": "any", "imm": "SbfxUbfxImm(lsb, width)"},
|
|
{"inst": "uhadd8 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0100|0|Rn|1111|Rd|0110|Rm" , "it": "any"},
|
|
{"inst": "uhadd16 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0100|1|Rn|1111|Rd|0110|Rm" , "it": "any"},
|
|
{"inst": "uhasx Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0101|0|Rn|1111|Rd|0110|Rm" , "it": "any"},
|
|
{"inst": "uhsax Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0111|0|Rn|1111|Rd|0110|Rm" , "it": "any"},
|
|
{"inst": "uhsub16 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0110|1|Rn|1111|Rd|0110|Rm" , "it": "any"},
|
|
{"inst": "uhsub8 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0110|0|Rn|1111|Rd|0110|Rm" , "it": "any"},
|
|
{"inst": "umaal RxLo!=XX, RxHi!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1111|0|Rn|RxLo|RxHi|0110|Rm" , "it": "any"},
|
|
{"inst": "umlal RxLo!=XX, RxHi!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1111|0|Rn|RxLo|RxHi|0000|Rm" , "it": "any"},
|
|
{"inst": "umull RdLo!=XX, RdHi!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1101|0|Rn|RdLo|RdHi|0000|Rm" , "it": "any"},
|
|
{"inst": "uqadd16 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0100|1|Rn|1111|Rd|0101|Rm" , "it": "any"},
|
|
{"inst": "uqadd8 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0100|0|Rn|1111|Rd|0101|Rm" , "it": "any"},
|
|
{"inst": "uqasx Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0101|0|Rn|1111|Rd|0101|Rm" , "it": "any"},
|
|
{"inst": "uqsax Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0111|0|Rn|1111|Rd|0101|Rm" , "it": "any"},
|
|
{"inst": "uqsub16 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0110|1|Rn|1111|Rd|0101|Rm" , "it": "any"},
|
|
{"inst": "uqsub8 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0110|0|Rn|1111|Rd|0101|Rm" , "it": "any"},
|
|
{"inst": "usad8 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1011|1|Rn|1111|Rd|0000|Rm" , "it": "any"},
|
|
{"inst": "usada8 Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "t32": "1111|101|1011|1|Rn|Ra|Rd|0000|Rm" , "it": "any"},
|
|
{"inst": "usat Rd!=XX, #sat, Rn!=XX, {lsl_or_asr #n}" , "t32": "1111|001|110|sop:2|Rn|0|n:3|Rd|n:2|0|sat:5" , "it": "any", "io": "Q=X"},
|
|
{"inst": "usat16 Rd!=XX, #sat, Rn!=XX" , "t32": "1111|001|1101|0|Rn|0000|Rd|0000|sat:4" , "it": "any", "io": "Q=X"},
|
|
{"inst": "usax Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0111|0|Rn|1111|Rd|0100|Rm" , "it": "any", "io": "GE=W"},
|
|
{"inst": "usub16 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0110|1|Rn|1111|Rd|0100|Rm" , "it": "any", "io": "GE=W"},
|
|
{"inst": "usub8 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0110|0|Rn|1111|Rd|0100|Rm" , "it": "any", "io": "GE=W"},
|
|
{"inst": "uxtab Rd!=XX, Rn!=XX, Rm!=XX, {ror #n}" , "t32": "1111|101|0010|1|Rn|1111|Rd|10|imm:2|Rm" , "it": "any", "imm": "Ror8Imm(n)"},
|
|
{"inst": "uxtab16 Rd!=XX, Rn!=XX, Rm!=XX, {ror #n}" , "t32": "1111|101|0001|1|Rn|1111|Rd|10|imm:2|Rm" , "it": "any", "imm": "Ror8Imm(n)"},
|
|
{"inst": "uxtah Rd!=XX, Rn!=XX, Rm!=XX, {ror #n}" , "t32": "1111|101|0000|1|Rn|1111|Rd|10|imm:2|Rm" , "it": "any", "imm": "Ror8Imm(n)"},
|
|
{"inst": "uxtb Rd!=HI, Rn!=HI, {ror #zero}" , "t16": "1011|001|011|Rn:3|Rd:3" , "it": "any"},
|
|
{"inst": "uxtb Rd!=XX, Rn!=XX, {ror #n}" , "t32": "1111|101|0010|1|1111|1111|Rd|10|imm:2|Rn" , "it": "any", "imm": "Ror8Imm(n)"},
|
|
{"inst": "uxtb16 Rd!=XX, Rn!=XX, {ror #n}" , "t32": "1111|101|0001|1|1111|1111|Rd|10|imm:2|Rn" , "it": "any", "imm": "Ror8Imm(n)"},
|
|
{"inst": "uxth Rd!=HI, Rn!=HI, {ror #zero}" , "t16": "1011|001|010|Rn:3|Rd:3" , "it": "any"},
|
|
{"inst": "uxth Rd!=XX, Rn!=XX, {ror #n}" , "t32": "1111|101|0000|1|1111|1111|Rd|10|imm:2|Rn" , "it": "any", "imm": "Ror8Imm(n)"},
|
|
{"inst": "wfe" , "t16": "1011|1111|0010|0000" , "it": "any"},
|
|
{"inst": "wfe" , "t32": "1111|001|1101|0|1111|1000|0000|0000|0010" , "it": "any"},
|
|
{"inst": "wfi" , "t16": "1011|1111|0011|0000" , "it": "any"},
|
|
{"inst": "wfi" , "t32": "1111|001|1101|0|1111|1000|0000|0000|0011" , "it": "any"},
|
|
{"inst": "yield" , "t16": "1011|1111|0001|0000" , "it": "any"},
|
|
{"inst": "yield" , "t32": "1111|001|1101|0|1111|1000|0000|0000|0001" , "it": "any"}
|
|
]},
|
|
|
|
{"category": "GP GP_EXT", "level": "ARMv7+", "data": [
|
|
{"inst": "clrex" , "a32": "1111|010|1011|1|1111|1111|0000|0001|1111"},
|
|
{"inst": "dbg #immZ" , "a32": "cond|001|1001|0|0000|1111|0000|1111|immZ:4" , "ext": "ARMv8-"},
|
|
{"inst": "dmb #immZ" , "a32": "1111|010|1011|1|1111|1111|0000|0101|immZ:4"},
|
|
{"inst": "dsb #immZ" , "a32": "1111|010|1011|1|1111|1111|0000|0100|immZ:4"},
|
|
{"inst": "isb #immZ" , "a32": "1111|010|1011|1|1111|1111|0000|0110|immZ:4"},
|
|
{"inst": "pldw [Rn!=PC, +/-Rm!=PC, {sop #n}]" , "a32": "1111|011|1U00|1|Rn|1111|n:5|sop:2|0|Rm" , "ext": "MP"},
|
|
{"inst": "pldw [Rn!=PC, #+/-off]" , "a32": "1111|010|1U00|1|Rn|1111|off:12" , "ext": "MP"},
|
|
{"inst": "pli [Rn, +/-Rm!=PC, {sop #n}]" , "a32": "1111|011|0U10|1|Rn|1111|n:5|sop:2|0|Rm"},
|
|
{"inst": "pli [Rn, #+/-off]" , "a32": "1111|010|0U10|1|Rn|1111|off:12"},
|
|
{"inst": "sev" , "a32": "cond|001|1001|0|0000|1111|0000|0000|0100"},
|
|
{"inst": "sevl" , "a32": "cond|001|1001|0|0000|1111|0000|0000|0101"}
|
|
]},
|
|
|
|
{"category": "GP GP_EXT", "level": "ARMv7+", "data": [
|
|
{"inst": "clrex" , "t32": "1111|001|1101|1|1111|1000|1111|0010|1111" , "it": "any"},
|
|
{"inst": "dmb #immZ" , "t32": "1111|001|1101|1|1111|1000|1111|0101|immZ:4" , "it": "any"},
|
|
{"inst": "dsb #immZ" , "t32": "1111|001|1101|1|1111|1000|1111|0100|immZ:4" , "it": "any"},
|
|
{"inst": "ldrexb Rd!=XX, [Rn!=PC]" , "t32": "1110|100|0110|1|Rn|Rd|1111|0100|1111" , "it": "any"},
|
|
{"inst": "ldrexd Rd!=XX, Rd2!=XX, [Rn!=PC]" , "t32": "1110|100|0110|1|Rn|Rd|Rd2 |0111|1111" , "it": "any"},
|
|
{"inst": "ldrexh Rd!=XX, [Rn!=PC]" , "t32": "1110|100|0110|1|Rn|Rd|1111|0101|1111" , "it": "any"},
|
|
{"inst": "isb #immZ" , "t32": "1111|001|1101|1|1111|1000|1111|0110|immZ:4" , "it": "any"},
|
|
{"inst": "pli [Rn!=PC, Rm!=XX, {lsl #n}]" , "t32": "1111|100|1000|1|Rn|1111|0000|00|n:2|Rm" , "it": "any"},
|
|
{"inst": "pli [Rn!=PC, #off]" , "t32": "1111|100|1100|1|Rn|1111|off:12" , "it": "any"},
|
|
{"inst": "pli [Rn!=PC, #-off]" , "t32": "1111|100|1000|1|Rn|1111|1100|off:8" , "it": "any"},
|
|
{"inst": "pli [Rn==PC, #+/-off]" , "t32": "1111|100|1U00|1|Rn|1111|off:12" , "it": "any"},
|
|
{"inst": "sev" , "t16": "1011|1111|0100|0000" , "it": "any"},
|
|
{"inst": "sev" , "t32": "1111|001|1101|0|1111|1000|0000|0000|0000" , "it": "any"},
|
|
{"inst": "sevl" , "t16": "1011|1111|0101|0000" , "it": "any"},
|
|
{"inst": "sevl" , "t32": "1111|001|1101|0|1111|1000|0000|0000|0101" , "it": "any"}
|
|
]},
|
|
|
|
{"category": "GP GP_EXT", "level": "ARMv8+", "data": [
|
|
{"inst": "lda Rd!=PC, [Rn!=PC]" , "a32": "cond|000|1100|1|Rn|Rd|1100|1001|1111"},
|
|
{"inst": "ldab Rd!=PC, [Rn!=PC]" , "a32": "cond|000|1110|1|Rn|Rd|1100|1001|1111"},
|
|
{"inst": "ldaex Rd!=PC, [Rn!=PC]" , "a32": "cond|000|1100|1|Rn|Rd|1110|1001|1111"},
|
|
{"inst": "ldaexb Rd!=PC, [Rn!=PC]" , "a32": "cond|000|1110|1|Rn|Rd|1110|1001|1111"},
|
|
{"inst": "ldaexd Rd<=13, Rd2+, [Rn!=PC]" , "a32": "cond|000|1101|1|Rn|Rd|1110|1001|1111"},
|
|
{"inst": "ldaexh Rd!=PC, [Rn!=PC]" , "a32": "cond|000|1111|1|Rn|Rd|1110|1001|1111"},
|
|
{"inst": "ldah Rd!=PC, [Rn!=PC]" , "a32": "cond|000|1111|1|Rn|Rd|1100|1001|1111"},
|
|
{"inst": "stl Rs!=PC, [Rn!=PC]" , "a32": "cond|000|1100|0|Rn|1111|1100|1001|Rs"},
|
|
{"inst": "stlb Rs!=PC, [Rn!=PC]" , "a32": "cond|000|1110|0|Rn|1111|1100|1001|Rs"},
|
|
{"inst": "stlex Rd!=PC, Rs!=PC, [Rn!=PC]" , "a32": "cond|000|1100|0|Rn|Rd|1110|1001|Rs"},
|
|
{"inst": "stlexb Rd!=PC, Rs!=PC, [Rn!=PC]" , "a32": "cond|000|1110|0|Rn|Rd|1110|1001|Rs"},
|
|
{"inst": "stlexd Rd!=PC, Rs!=PC, Rs2+, [Rn!=PC]" , "a32": "cond|000|1101|0|Rn|Rd|1110|1001|Rs"},
|
|
{"inst": "stlexh Rd!=PC, Rs!=PC, [Rn!=PC]" , "a32": "cond|000|1111|0|Rn|Rd|1110|1001|Rs"},
|
|
{"inst": "stlh Rs!=PC, [Rn!=PC]" , "a32": "cond|000|1111|0|Rn|1111|1100|1001|Rs"}
|
|
]},
|
|
|
|
{"category": "GP GP_EXT", "level": "ARMv8+", "data": [
|
|
{"inst": "dcps1" , "t32": "1111|011|1100|0|1111|1000|0000|0000|0001" , "it": "out"},
|
|
{"inst": "dcps2" , "t32": "1111|011|1100|0|1111|1000|0000|0000|0010" , "it": "out"},
|
|
{"inst": "dcps3" , "t32": "1111|011|1100|0|1111|1000|0000|0000|0011" , "it": "out"},
|
|
{"inst": "lda Rd!=PC, [Rn!=PC]" , "t32": "1110|100|0110|1|Rn|Rd|1111|1010|1111" , "it": "any"},
|
|
{"inst": "ldab Rd!=PC, [Rn!=PC]" , "t32": "1110|100|0110|1|Rn|Rd|1111|1000|1111" , "it": "any"},
|
|
{"inst": "ldaex Rd!=PC, [Rn!=PC]" , "t32": "1110|100|0110|1|Rn|Rd|1111|1110|1111" , "it": "any"},
|
|
{"inst": "ldaexb Rd!=PC, [Rn!=PC]" , "t32": "1110|100|0110|1|Rn|Rd|1111|1100|1111" , "it": "any"},
|
|
{"inst": "ldaexd Rd!=PC, Rd2!=PC, [Rn!=PC]" , "t32": "1110|100|0110|1|Rn|Rd|Rd2|1111|1111" , "it": "any"},
|
|
{"inst": "ldaexh Rd!=PC, [Rn!=PC]" , "t32": "1110|100|0110|1|Rn|Rd|1111|1101|1111" , "it": "any"},
|
|
{"inst": "ldah Rd!=PC, [Rn!=PC]" , "t32": "1110|100|0110|1|Rn|Rd|1111|1001|1111" , "it": "any"},
|
|
{"inst": "stl Rs!=PC, [Rn!=PC]" , "t32": "1110|100|0110|0|Rn|Rs|1111|1010|1111" , "it": "any"},
|
|
{"inst": "stlb Rs!=PC, [Rn!=PC]" , "t32": "1110|100|0110|0|Rn|Rs|1111|1000|1111" , "it": "any"},
|
|
{"inst": "stlex Rd!=PC, Rs!=PC, [Rn!=PC]" , "t32": "1110|100|0110|0|Rn|Rs|1111|1110|Rd" , "it": "any"},
|
|
{"inst": "stlexb Rd!=PC, Rs!=PC, [Rn!=PC]" , "t32": "1110|100|0110|0|Rn|Rs|1111|1100|Rd" , "it": "any"},
|
|
{"inst": "stlexd Rd!=PC, Rs!=PC, Rs2!=PC, [Rn!=PC]" , "t32": "1110|100|0110|0|Rn|Rs|Rs2|1111|Rd" , "it": "any"},
|
|
{"inst": "stlexh Rd!=PC, Rs!=PC, [Rn!=PC]" , "t32": "1110|100|0110|0|Rn|Rs|1111|1101|Rd" , "it": "any"},
|
|
{"inst": "stlh Rs!=PC, [Rn!=PC]" , "t32": "1110|100|0110|0|Rn|Rs|1111|1001|1111" , "it": "any"}
|
|
]},
|
|
|
|
{"category": "GP GP_EXT", "ext": "IDIVA", "data": [
|
|
{"inst": "sdiv Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|1000|1|Rd|1111|Rm|0001|Rn"},
|
|
{"inst": "udiv Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|1001|1|Rd|1111|Rm|0001|Rn"}
|
|
]},
|
|
|
|
{"category": "GP GP_EXT", "ext": "IDIVT", "data": [
|
|
{"inst": "sdiv Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1100|1|Rn|1111|Rd|1111|Rm" , "it": "any"},
|
|
{"inst": "udiv Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1101|1|Rn|1111|Rd|1111|Rm" , "it": "any"}
|
|
]},
|
|
|
|
{"category": "GP GP_EXT", "data": [
|
|
{"inst": "csdb" , "a32": "cond|001|1001|0|0000|1111|0000|0001|0100"},
|
|
{"inst": "ssbb" , "a32": "1111|010|1011|1|1111|1111|0000|0100|0000"},
|
|
{"inst": "pssbb" , "a32": "1111|010|1011|1|1111|1111|0000|0100|0100"}
|
|
]},
|
|
|
|
{"category": "GP GP_EXT", "data": [
|
|
{"inst": "csdb" , "t32": "1111|001|1101|0|1111|1000|0000|0001|0100" , "it": "out"},
|
|
{"inst": "ssbb" , "t32": "1111|001|1101|1|1111|1000|1111|0100|0000" , "it": "any"},
|
|
{"inst": "pssbb" , "t32": "1111|001|1101|1|1111|1000|1111|0100|0100" , "it": "any"}
|
|
]},
|
|
|
|
{"category": "GP GP_EXT", "ext": "CLRBHB", "data": [
|
|
{"inst": "clrbhb" , "a32": "cond|001|1001|0|0000|1111|0000|0001|0110"}
|
|
]},
|
|
|
|
{"category": "GP GP_EXT", "ext": "CLRBHB", "data": [
|
|
{"inst": "clrbhb" , "t32": "1111|001|1101|0|1111|1000|0000|0001|0110" , "it": "any"}
|
|
]},
|
|
|
|
{"category": "GP GP_EXT CRYPTO_HASH", "ext": "CRC32", "data": [
|
|
{"inst": "crc32b Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1000|0|Rn|Rd|0000|0100|Rm"},
|
|
{"inst": "crc32h Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1001|0|Rn|Rd|0000|0100|Rm"},
|
|
{"inst": "crc32w Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1010|0|Rn|Rd|0000|0100|Rm"},
|
|
{"inst": "crc32cb Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1000|0|Rn|Rd|0010|0100|Rm"},
|
|
{"inst": "crc32ch Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1001|0|Rn|Rd|0010|0100|Rm"},
|
|
{"inst": "crc32cw Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1010|0|Rn|Rd|0010|0100|Rm"}
|
|
]},
|
|
|
|
{"category": "GP GP_EXT CRYPTO_HASH", "ext": "CRC32", "data": [
|
|
{"inst": "crc32b Rd!=PC, Rn!=PC, Rm!=PC" , "t32": "1111|101|0110|0|Rn|1111|Rd|10|00|Rm" , "it": "out"},
|
|
{"inst": "crc32h Rd!=PC, Rn!=PC, Rm!=PC" , "t32": "1111|101|0110|0|Rn|1111|Rd|10|01|Rm" , "it": "out"},
|
|
{"inst": "crc32w Rd!=PC, Rn!=PC, Rm!=PC" , "t32": "1111|101|0110|0|Rn|1111|Rd|10|10|Rm" , "it": "out"},
|
|
{"inst": "crc32cb Rd!=PC, Rn!=PC, Rm!=PC" , "t32": "1111|101|0110|1|Rn|1111|Rd|10|00|Rm" , "it": "out"},
|
|
{"inst": "crc32ch Rd!=PC, Rn!=PC, Rm!=PC" , "t32": "1111|101|0110|1|Rn|1111|Rd|10|01|Rm" , "it": "out"},
|
|
{"inst": "crc32cw Rd!=PC, Rn!=PC, Rm!=PC" , "t32": "1111|101|0110|1|Rn|1111|Rd|10|10|Rm" , "it": "out"}
|
|
]},
|
|
|
|
{"category": "GP GP_EXT", "ext": "PAN", "data": [
|
|
{"inst": "setpan #immZ" , "a32": "1111|000|1000|1|0000|0000|00|immZ:1|0|0000|0000"}
|
|
]},
|
|
|
|
{"category": "GP GP_EXT", "ext": "PAN", "data": [
|
|
{"inst": "setpan #immZ" , "t16": "1011|0110|0001|immZ:1|000" , "it": "out"}
|
|
]},
|
|
|
|
{"category": "GP GP_EXT", "ext": "RAS", "data": [
|
|
{"inst": "esb" , "a32": "cond|001|1001|0|0000|1111|0000|0001|0000"}
|
|
]},
|
|
|
|
{"category": "GP GP_EXT", "ext": "RAS", "data": [
|
|
{"inst": "esb" , "t32": "1111|001|1101|0|1111|1000|0000|0001|0000" , "it": "any"}
|
|
]},
|
|
|
|
{"category": "GP GP_EXT", "ext": "SB", "data": [
|
|
{"inst": "sb" , "a32": "1111|010|1011|1|1111|1111|0000|0111|0000"}
|
|
]},
|
|
|
|
{"category": "GP GP_EXT", "ext": "SB", "data": [
|
|
{"inst": "sb" , "t32": "1111|001|1101|1|1111|1000|1111|0111|0000" , "it": "out"}
|
|
]},
|
|
|
|
{"category": "GP GP_EXT", "ext": "SECURITY", "data": [
|
|
{"inst": "smc #immZ" , "a32": "cond|000|1011|0|000000000000|0111|immZ:4"}
|
|
]},
|
|
|
|
{"category": "GP GP_EXT", "ext": "SECURITY", "data": [
|
|
{"inst": "smc #immZ" , "t32": "1111|011|1111|1|immZ:4|1000|000000000000" , "it": "any"}
|
|
]},
|
|
|
|
{"category": "FP", "ext": "FP", "data": [
|
|
{"inst": "vabs.f32 Sd, Sn" , "a32": "cond|11101|'Vd|11|00|00|Vd|10|10|1|1|'Vn|0|Vn"},
|
|
{"inst": "vabs.f64 Dd, Dn" , "a32": "cond|11101|Vd'|11|00|00|Vd|10|11|1|1|Vn'|0|Vn"},
|
|
{"inst": "vadd.f32 Sd, Sn, Sm" , "a32": "cond|11100|'Vd|11|Vn|Vd|1010|'Vn|0|'Vm|0|Vm"},
|
|
{"inst": "vadd.f64 Dd, Dn, Dm" , "a32": "cond|11100|Vd'|11|Vn|Vd|1011|Vn'|0|Vm'|0|Vm"},
|
|
{"inst": "vcmp.f32 Sn, Sm" , "a32": "cond|11101|'Vn|11|01|00|Vn|10|10|01|'Vm|0|Vm"},
|
|
{"inst": "vcmp.f32 Sn, #zero" , "a32": "cond|11101|'Vn|11|01|01|Vn|10|10|01|00|0000"},
|
|
{"inst": "vcmp.f64 Dn, Dm" , "a32": "cond|11101|Vn'|11|01|00|Vn|10|11|01|Vm'|0|Vm"},
|
|
{"inst": "vcmp.f64 Dn, #zero" , "a32": "cond|11101|Vn'|11|01|01|Vn|10|11|01|00|0000"},
|
|
{"inst": "vcmpe.f32 Sn, Sm" , "a32": "cond|11101|'Vn|11|01|00|Vn|10|10|11|'Vm|0|Vm"},
|
|
{"inst": "vcmpe.f32 Sn, #zero" , "a32": "cond|11101|'Vn|11|01|01|Vn|10|10|11|00|0000"},
|
|
{"inst": "vcmpe.f64 Dn, Dm" , "a32": "cond|11101|Vn'|11|01|00|Vn|10|11|11|Vm'|0|Vm"},
|
|
{"inst": "vcmpe.f64 Dn, #zero" , "a32": "cond|11101|Vn'|11|01|01|Vn|10|11|11|00|0000"},
|
|
{"inst": "vcvt.f32.f64 Sd, Dn" , "a32": "cond|11101|'Vd|11|01|11|Vd|10111|1|Vn'|0|Vn"},
|
|
{"inst": "vcvt.f64.f32 Dd, Sn" , "a32": "cond|11101|Vd'|11|01|11|Vd|10101|1|'Vn|0|Vn"},
|
|
{"inst": "vcvt.f32.s32 Sd, Sn" , "a32": "cond|11101|'Vd|11|10|00|Vd|10101|1|'Vn|0|Vn"},
|
|
{"inst": "vcvt.f32.u32 Sd, Sn" , "a32": "cond|11101|'Vd|11|10|00|Vd|10100|1|'Vn|0|Vn"},
|
|
{"inst": "vcvt.f64.s32 Dd, Sn" , "a32": "cond|11101|Vd'|11|10|00|Vd|10111|1|'Vn|0|Vn"},
|
|
{"inst": "vcvt.f64.u32 Dd, Sn" , "a32": "cond|11101|Vd'|11|10|00|Vd|10110|1|'Vn|0|Vn"},
|
|
{"inst": "vcvt.f32.s16 Sx, Sx, #fbits" , "a32": "cond|11101|'Vx|11|10|10|Vx|10100|1|imm[0]|0|imm[4:1]" , "imm": "VecFBitsVFP(16, fbits)"},
|
|
{"inst": "vcvt.s16.f32 Sx, Sx, #fbits" , "a32": "cond|11101|'Vx|11|11|10|Vx|10100|1|imm[0]|0|imm[4:1]" , "imm": "VecFBitsVFP(16, fbits)"},
|
|
{"inst": "vcvt.f32.u16 Sx, Sx, #fbits" , "a32": "cond|11101|'Vx|11|10|11|Vx|10100|1|imm[0]|0|imm[4:1]" , "imm": "VecFBitsVFP(16, fbits)"},
|
|
{"inst": "vcvt.u16.f32 Sx, Sx, #fbits" , "a32": "cond|11101|'Vx|11|11|11|Vx|10100|1|imm[0]|0|imm[4:1]" , "imm": "VecFBitsVFP(16, fbits)"},
|
|
{"inst": "vcvt.f32.s32 Sx, Sx, #fbits" , "a32": "cond|11101|'Vx|11|10|10|Vx|10101|1|imm[0]|0|imm[4:1]" , "imm": "VecFBitsVFP(32, fbits)"},
|
|
{"inst": "vcvt.s32.f32 Sx, Sx, #fbits" , "a32": "cond|11101|'Vx|11|11|10|Vx|10101|1|imm[0]|0|imm[4:1]" , "imm": "VecFBitsVFP(32, fbits)"},
|
|
{"inst": "vcvt.f32.u32 Sx, Sx, #fbits" , "a32": "cond|11101|'Vx|11|10|11|Vx|10101|1|imm[0]|0|imm[4:1]" , "imm": "VecFBitsVFP(32, fbits)"},
|
|
{"inst": "vcvt.u32.f32 Sx, Sx, #fbits" , "a32": "cond|11101|'Vx|11|11|11|Vx|10101|1|imm[0]|0|imm[4:1]" , "imm": "VecFBitsVFP(32, fbits)"},
|
|
{"inst": "vcvt.f64.s16 Dx, Dx, #fbits" , "a32": "cond|11101|Vx'|11|10|10|Vx|10110|1|imm[0]|0|imm[4:1]" , "imm": "VecFBitsVFP(16, fbits)"},
|
|
{"inst": "vcvt.s16.f64 Dx, Dx, #fbits" , "a32": "cond|11101|Vx'|11|11|10|Vx|10110|1|imm[0]|0|imm[4:1]" , "imm": "VecFBitsVFP(16, fbits)"},
|
|
{"inst": "vcvt.f64.u16 Dx, Dx, #fbits" , "a32": "cond|11101|Vx'|11|10|11|Vx|10110|1|imm[0]|0|imm[4:1]" , "imm": "VecFBitsVFP(16, fbits)"},
|
|
{"inst": "vcvt.u16.f64 Dx, Dx, #fbits" , "a32": "cond|11101|Vx'|11|11|11|Vx|10110|1|imm[0]|0|imm[4:1]" , "imm": "VecFBitsVFP(16, fbits)"},
|
|
{"inst": "vcvt.f64.s32 Dx, Dx, #fbits" , "a32": "cond|11101|Vx'|11|10|10|Vx|10111|1|imm[0]|0|imm[4:1]" , "imm": "VecFBitsVFP(32, fbits)"},
|
|
{"inst": "vcvt.s32.f64 Dx, Dx, #fbits" , "a32": "cond|11101|Vx'|11|11|10|Vx|10111|1|imm[0]|0|imm[4:1]" , "imm": "VecFBitsVFP(32, fbits)"},
|
|
{"inst": "vcvt.f64.u32 Dx, Dx, #fbits" , "a32": "cond|11101|Vx'|11|10|11|Vx|10111|1|imm[0]|0|imm[4:1]" , "imm": "VecFBitsVFP(32, fbits)"},
|
|
{"inst": "vcvt.u32.f64 Dx, Dx, #fbits" , "a32": "cond|11101|Vx'|11|11|11|Vx|10111|1|imm[0]|0|imm[4:1]" , "imm": "VecFBitsVFP(32, fbits)"},
|
|
{"inst": "vcvtr.s32.f32 Sd, Sn" , "a32": "cond|11101|'Vd|11|11|01|Vd|10100|1|'Vn|0|Vn"},
|
|
{"inst": "vcvtr.s32.f64 Sd, Dn" , "a32": "cond|11101|'Vd|11|11|01|Vd|10110|1|Vn'|0|Vn"},
|
|
{"inst": "vcvtr.u32.f32 Sd, Sn" , "a32": "cond|11101|'Vd|11|11|00|Vd|10100|1|'Vn|0|Vn"},
|
|
{"inst": "vcvtr.u32.f64 Sd, Dn" , "a32": "cond|11101|'Vd|11|11|00|Vd|10110|1|Vn'|0|Vn"},
|
|
{"inst": "vdiv.f32 Sd, Sn, Sm" , "a32": "cond|11101|'Vd|00|Vn|Vd|10|10|'Vn|0|'Vm|0|Vm"},
|
|
{"inst": "vdiv.f64 Dd, Dn, Dm" , "a32": "cond|11101|Vd'|00|Vn|Vd|10|11|Vn'|0|Vm'|0|Vm"},
|
|
{"inst": "vldr.32 Sd, [Rn, #+/-off*4]" , "a32": "cond|1101U|'Vd|01|Rn|Vd|1010|off:8"},
|
|
{"inst": "vldr.64 Dd, [Rn, #+/-off*4]" , "a32": "cond|1101U|Vd'|01|Rn|Vd|1011|off:8"},
|
|
{"inst": "vmla.f32 Sx, Sn, Sm" , "a32": "cond|11100|'Vx|00|Vn|Vx|10|10|'Vn|0|'Vm|0|Vm"},
|
|
{"inst": "vmla.f64 Dx, Dn, Dm" , "a32": "cond|11100|Vx'|00|Vn|Vx|10|11|Vn'|0|Vm'|0|Vm"},
|
|
{"inst": "vmls.f32 Sx, Sn, Sm" , "a32": "cond|11100|'Vx|00|Vn|Vx|10|10|'Vn|1|'Vm|0|Vm"},
|
|
{"inst": "vmls.f64 Dx, Dn, Dm" , "a32": "cond|11100|Vx'|00|Vn|Vx|10|11|Vn'|1|Vm'|0|Vm"},
|
|
{"inst": "vmov.f32 Sd, Sn" , "a32": "cond|11101|'Vd|11|0000|Vd|1010|0|1|'Vn|0|Vn"},
|
|
{"inst": "vmov.f64 Dd, Dn" , "a32": "cond|11101|Vd'|11|0000|Vd|1011|0|1|Vn'|0|Vn"},
|
|
{"inst": "vmov.f32 Sd, #immVFP" , "a32": "cond|11101|'Vd|11|imm:4|Vd|1010|0000|imm:4" , "imm": "VecVFPImm(immVFP)"},
|
|
{"inst": "vmov.f64 Dd, #immVFP" , "a32": "cond|11101|Vd'|11|imm:4|Vd|1011|0000|imm:4" , "imm": "VecVFPImm(immVFP)"},
|
|
{"inst": "vmul.f32 Sd, Sn, Sm" , "a32": "cond|11100|'Vd|10|Vn|Vd|10|10|'Vn|0|'Vm|0|Vm"},
|
|
{"inst": "vmul.f64 Dd, Dn, Dm" , "a32": "cond|11100|Vd'|10|Vn|Vd|10|11|Vn'|0|Vm'|0|Vm"},
|
|
{"inst": "vneg.f32 Sd, Sn" , "a32": "cond|11101|'Vd|11|0001|Vd|10|10|01|'Vn|0|Vn"},
|
|
{"inst": "vneg.f64 Dd, Dn" , "a32": "cond|11101|Vd'|11|0001|Vd|10|11|01|Vn'|0|Vn"},
|
|
{"inst": "vnmla.f32 Sx, Sn, Sm" , "a32": "cond|11100|'Vx|01|Vn|Vx|10|10|'Vn|1|'Vm|0|Vm"},
|
|
{"inst": "vnmla.f64 Dx, Dn, Dm" , "a32": "cond|11100|Vx'|01|Vn|Vx|10|11|Vn'|1|Vm'|0|Vm"},
|
|
{"inst": "vnmls.f32 Sx, Sn, Sm" , "a32": "cond|11100|'Vx|01|Vn|Vx|10|10|'Vn|0|'Vm|0|Vm"},
|
|
{"inst": "vnmls.f64 Dx, Dn, Dm" , "a32": "cond|11100|Vx'|01|Vn|Vx|10|11|Vn'|0|Vm'|0|Vm"},
|
|
{"inst": "vnmul.f32 Sd, Sn, Sm" , "a32": "cond|11100|'Vd|10|Vn|Vd|10|10|'Vn|1|'Vm|0|Vm"},
|
|
{"inst": "vnmul.f64 Dd, Dn, Dm" , "a32": "cond|11100|Vd'|10|Vn|Vd|10|11|Vn'|1|Vm'|0|Vm"},
|
|
{"inst": "vsqrt.f32 Sd, Sn" , "a32": "cond|11101|'Vd|11|0001|Vd|10|10|11|'Vn|0|Vn"},
|
|
{"inst": "vsqrt.f64 Dd, Dn" , "a32": "cond|11101|Vd'|11|0001|Vd|10|11|11|Vn'|0|Vn"},
|
|
{"inst": "vstr.32 Ss, [Rn, #+/-off*4]" , "a32": "cond|1101U|'Vs|00|Rn|Vs|1010|off:8"},
|
|
{"inst": "vstr.64 Ds, [Rn, #+/-off*4]" , "a32": "cond|1101U|Vs'|00|Rn|Vs|1011|off:8"},
|
|
{"inst": "vsub.f32 Sd, Sn, Sm" , "a32": "cond|11100|'Vd|11|Vn|Vd|10|10|'Vn|1|'Vm|0|Vm"},
|
|
{"inst": "vsub.f64 Dd, Dn, Dm" , "a32": "cond|11100|Vd'|11|Vn|Vd|10|11|Vn'|1|Vm'|0|Vm"}
|
|
]},
|
|
|
|
{"category": "FP", "ext": "FP", "data": [
|
|
{"inst": "vabs.f32 Sd, Sn" , "t32": "1110|11101|'Vd|11|00|00|Vd|10|10|1|1|'Vn|0|Vn" , "it": "any"},
|
|
{"inst": "vabs.f64 Dd, Dn" , "t32": "1110|11101|Vd'|11|00|00|Vd|10|11|1|1|Vn'|0|Vn" , "it": "any"},
|
|
{"inst": "vadd.f32 Sd, Sn, Sm" , "t32": "1110|11100|'Vd|11|Vn|Vd|1010|'Vn|0|'Vm|0|Vm" , "it": "any"},
|
|
{"inst": "vadd.f64 Dd, Dn, Dm" , "t32": "1110|11100|Vd'|11|Vn|Vd|1011|Vn'|0|Vm'|0|Vm" , "it": "any"},
|
|
{"inst": "vcmp.f32 Sn, Sm" , "t32": "1110|11101|'Vn|11|01|00|Vn|10|10|01|'Vm|0|Vm" , "it": "any"},
|
|
{"inst": "vcmp.f32 Sn, #zero" , "t32": "1110|11101|'Vn|11|01|01|Vn|10|10|01|00|0000" , "it": "any"},
|
|
{"inst": "vcmp.f64 Dn, Dm" , "t32": "1110|11101|Vn'|11|01|00|Vn|10|11|01|Vm'|0|Vm" , "it": "any"},
|
|
{"inst": "vcmp.f64 Dn, #zero" , "t32": "1110|11101|Vn'|11|01|01|Vn|10|11|01|00|0000" , "it": "any"},
|
|
{"inst": "vcmpe.f32 Sn, Sm" , "t32": "1110|11101|'Vn|11|01|00|Vn|10|10|11|'Vm|0|Vm" , "it": "any"},
|
|
{"inst": "vcmpe.f32 Sn, #zero" , "t32": "1110|11101|'Vn|11|01|01|Vn|10|10|11|00|0000" , "it": "any"},
|
|
{"inst": "vcmpe.f64 Dn, Dm" , "t32": "1110|11101|Vn'|11|01|00|Vn|10|11|11|Vm'|0|Vm" , "it": "any"},
|
|
{"inst": "vcmpe.f64 Dn, #zero" , "t32": "1110|11101|Vn'|11|01|01|Vn|10|11|11|00|0000" , "it": "any"},
|
|
{"inst": "vcvt.f32.f64 Sd, Dn" , "t32": "1110|11101|'Vd|11|01|11|Vd|10111|1|Vn'|0|Vn" , "it": "any"},
|
|
{"inst": "vcvt.f64.f32 Dd, Sn" , "t32": "1110|11101|Vd'|11|01|11|Vd|10101|1|'Vn|0|Vn" , "it": "any"},
|
|
{"inst": "vcvt.f32.s32 Sd, Sn" , "t32": "1110|11101|'Vd|11|10|00|Vd|10101|1|'Vn|0|Vn" , "it": "any"},
|
|
{"inst": "vcvt.f32.u32 Sd, Sn" , "t32": "1110|11101|'Vd|11|10|00|Vd|10100|1|'Vn|0|Vn" , "it": "any"},
|
|
{"inst": "vcvt.f64.s32 Dd, Sn" , "t32": "1110|11101|Vd'|11|10|00|Vd|10111|1|'Vn|0|Vn" , "it": "any"},
|
|
{"inst": "vcvt.f64.u32 Dd, Sn" , "t32": "1110|11101|Vd'|11|10|00|Vd|10110|1|'Vn|0|Vn" , "it": "any"},
|
|
{"inst": "vcvt.f32.s16 Sx, Sx, #fbits" , "t32": "1110|11101|'Vx|11|10|10|Vx|10100|1|imm[0]|0|imm[4:1]" , "it": "any", "imm": "VecFBitsVFP(16, fbits)"},
|
|
{"inst": "vcvt.s16.f32 Sx, Sx, #fbits" , "t32": "1110|11101|'Vx|11|11|10|Vx|10100|1|imm[0]|0|imm[4:1]" , "it": "any", "imm": "VecFBitsVFP(16, fbits)"},
|
|
{"inst": "vcvt.f32.u16 Sx, Sx, #fbits" , "t32": "1110|11101|'Vx|11|10|11|Vx|10100|1|imm[0]|0|imm[4:1]" , "it": "any", "imm": "VecFBitsVFP(16, fbits)"},
|
|
{"inst": "vcvt.u16.f32 Sx, Sx, #fbits" , "t32": "1110|11101|'Vx|11|11|11|Vx|10100|1|imm[0]|0|imm[4:1]" , "it": "any", "imm": "VecFBitsVFP(16, fbits)"},
|
|
{"inst": "vcvt.f32.s32 Sx, Sx, #fbits" , "t32": "1110|11101|'Vx|11|10|10|Vx|10101|1|imm[0]|0|imm[4:1]" , "it": "any", "imm": "VecFBitsVFP(32, fbits)"},
|
|
{"inst": "vcvt.s32.f32 Sx, Sx, #fbits" , "t32": "1110|11101|'Vx|11|11|10|Vx|10101|1|imm[0]|0|imm[4:1]" , "it": "any", "imm": "VecFBitsVFP(32, fbits)"},
|
|
{"inst": "vcvt.f32.u32 Sx, Sx, #fbits" , "t32": "1110|11101|'Vx|11|10|11|Vx|10101|1|imm[0]|0|imm[4:1]" , "it": "any", "imm": "VecFBitsVFP(32, fbits)"},
|
|
{"inst": "vcvt.u32.f32 Sx, Sx, #fbits" , "t32": "1110|11101|'Vx|11|11|11|Vx|10101|1|imm[0]|0|imm[4:1]" , "it": "any", "imm": "VecFBitsVFP(32, fbits)"},
|
|
{"inst": "vcvt.f64.s16 Dx, Dx, #fbits" , "t32": "1110|11101|Vx'|11|10|10|Vx|10110|1|imm[0]|0|imm[4:1]" , "it": "any", "imm": "VecFBitsVFP(16, fbits)"},
|
|
{"inst": "vcvt.s16.f64 Dx, Dx, #fbits" , "t32": "1110|11101|Vx'|11|11|10|Vx|10110|1|imm[0]|0|imm[4:1]" , "it": "any", "imm": "VecFBitsVFP(16, fbits)"},
|
|
{"inst": "vcvt.f64.u16 Dx, Dx, #fbits" , "t32": "1110|11101|Vx'|11|10|11|Vx|10110|1|imm[0]|0|imm[4:1]" , "it": "any", "imm": "VecFBitsVFP(16, fbits)"},
|
|
{"inst": "vcvt.u16.f64 Dx, Dx, #fbits" , "t32": "1110|11101|Vx'|11|11|11|Vx|10110|1|imm[0]|0|imm[4:1]" , "it": "any", "imm": "VecFBitsVFP(16, fbits)"},
|
|
{"inst": "vcvt.f64.s32 Dx, Dx, #fbits" , "t32": "1110|11101|Vx'|11|10|10|Vx|10111|1|imm[0]|0|imm[4:1]" , "it": "any", "imm": "VecFBitsVFP(32, fbits)"},
|
|
{"inst": "vcvt.s32.f64 Dx, Dx, #fbits" , "t32": "1110|11101|Vx'|11|11|10|Vx|10111|1|imm[0]|0|imm[4:1]" , "it": "any", "imm": "VecFBitsVFP(32, fbits)"},
|
|
{"inst": "vcvt.f64.u32 Dx, Dx, #fbits" , "t32": "1110|11101|Vx'|11|10|11|Vx|10111|1|imm[0]|0|imm[4:1]" , "it": "any", "imm": "VecFBitsVFP(32, fbits)"},
|
|
{"inst": "vcvt.u32.f64 Dx, Dx, #fbits" , "t32": "1110|11101|Vx'|11|11|11|Vx|10111|1|imm[0]|0|imm[4:1]" , "it": "any", "imm": "VecFBitsVFP(32, fbits)"},
|
|
{"inst": "vcvtr.s32.f32 Sd, Sn" , "t32": "1110|11101|'Vd|11|11|01|Vd|10100|1|'Vn|0|Vn" , "it": "any"},
|
|
{"inst": "vcvtr.s32.f64 Sd, Dn" , "t32": "1110|11101|'Vd|11|11|01|Vd|10110|1|Vn'|0|Vn" , "it": "any"},
|
|
{"inst": "vcvtr.u32.f32 Sd, Sn" , "t32": "1110|11101|'Vd|11|11|00|Vd|10100|1|'Vn|0|Vn" , "it": "any"},
|
|
{"inst": "vcvtr.u32.f64 Sd, Dn" , "t32": "1110|11101|'Vd|11|11|00|Vd|10110|1|Vn'|0|Vn" , "it": "any"},
|
|
{"inst": "vdiv.f32 Sd, Sn, Sm" , "t32": "1110|11101|'Vd|00|Vn|Vd|10|10|'Vn|0|'Vm|0|Vm" , "it": "any"},
|
|
{"inst": "vdiv.f64 Dd, Dn, Dm" , "t32": "1110|11101|Vd'|00|Vn|Vd|10|11|Vn'|0|Vm'|0|Vm" , "it": "any"},
|
|
{"inst": "vldr.32 Sd, [Rn, #+/-off*4]" , "t32": "1110|1101U|'Vd|01|Rn|Vd|1010|off:8" , "it": "any"},
|
|
{"inst": "vldr.64 Dd, [Rn, #+/-off*4]" , "t32": "1110|1101U|Vd'|01|Rn|Vd|1011|off:8" , "it": "any"},
|
|
{"inst": "vmla.f64 Dx, Dn, Dm" , "t32": "1110|11100|Vx'|00|Vn|Vx|10|11|Vn'|0|Vm'|0|Vm" , "it": "any"},
|
|
{"inst": "vmls.f64 Dx, Dn, Dm" , "t32": "1110|11100|Vx'|00|Vn|Vx|10|11|Vn'|1|Vm'|0|Vm" , "it": "any"},
|
|
{"inst": "vmov.f32 Sd, Sn" , "t32": "1110|11101|'Vd|11|0000|Vd|1010|0|1|'Vn|0|Vn" , "it": "any"},
|
|
{"inst": "vmov.f64 Dd, Dn" , "t32": "1110|11101|Vd'|11|0000|Vd|1011|0|1|Vn'|0|Vn" , "it": "any"},
|
|
{"inst": "vmov.f32 Sd, #immVFP" , "t32": "1110|11101|'Vd|11|imm:4|Vd|1010|0000|imm:4" , "it": "any", "imm": "VecVFPImm(immVFP)"},
|
|
{"inst": "vmov.f64 Dd, #immVFP" , "t32": "1110|11101|Vd'|11|imm:4|Vd|1011|0000|imm:4" , "it": "any", "imm": "VecVFPImm(immVFP)"},
|
|
{"inst": "vmul.f32 Sd, Sn, Sm" , "t32": "1110|11100|'Vd|10|Vn|Vd|10|10|'Vn|0|'Vm|0|Vm" , "it": "any"},
|
|
{"inst": "vmul.f64 Dd, Dn, Dm" , "t32": "1110|11100|Vd'|10|Vn|Vd|10|11|Vn'|0|Vm'|0|Vm" , "it": "any"},
|
|
{"inst": "vneg.f32 Sd, Sn" , "t32": "1110|11101|'Vd|11|0001|Vd|10|10|01|'Vn|0|Vn" , "it": "any"},
|
|
{"inst": "vneg.f64 Dd, Dn" , "t32": "1110|11101|Vd'|11|0001|Vd|10|11|01|Vn'|0|Vn" , "it": "any"},
|
|
{"inst": "vnmla.f32 Sx, Sn, Sm" , "t32": "1110|11100|'Vx|01|Vn|Vx|10|10|'Vn|1|'Vm|0|Vm" , "it": "any"},
|
|
{"inst": "vnmla.f64 Dx, Dn, Dm" , "t32": "1110|11100|Vx'|01|Vn|Vx|10|11|Vn'|1|Vm'|0|Vm" , "it": "any"},
|
|
{"inst": "vnmls.f32 Sx, Sn, Sm" , "t32": "1110|11100|'Vx|01|Vn|Vx|10|10|'Vn|0|'Vm|0|Vm" , "it": "any"},
|
|
{"inst": "vnmls.f64 Dx, Dn, Dm" , "t32": "1110|11100|Vx'|01|Vn|Vx|10|11|Vn'|0|Vm'|0|Vm" , "it": "any"},
|
|
{"inst": "vnmul.f32 Sd, Sn, Sm" , "t32": "1110|11100|'Vd|10|Vn|Vd|10|10|'Vn|1|'Vm|0|Vm" , "it": "any"},
|
|
{"inst": "vnmul.f64 Dd, Dn, Dm" , "t32": "1110|11100|Vd'|10|Vn|Vd|10|11|Vn'|1|Vm'|0|Vm" , "it": "any"},
|
|
{"inst": "vsqrt.f32 Sd, Sn" , "t32": "1110|11101|'Vd|11|0001|Vd|10|10|11|'Vn|0|Vn" , "it": "any"},
|
|
{"inst": "vsqrt.f64 Dd, Dn" , "t32": "1110|11101|Vd'|11|0001|Vd|1011|1|1|Vn'|0|Vn" , "it": "any"},
|
|
{"inst": "vstr.32 Ss, [Rn, #+/-off*4]" , "t32": "1110|1101U|'Vs|00|Rn|Vs|1010|off:8" , "it": "any"},
|
|
{"inst": "vstr.64 Ds, [Rn, #+/-off*4]" , "t32": "1110|1101U|Vs'|00|Rn|Vs|1011|off:8" , "it": "any"},
|
|
{"inst": "vsub.f32 Sd, Sn, Sm" , "t32": "1110|11100|'Vd|11|Vn|Vd|10|10|'Vn|1|'Vm|0|Vm" , "it": "any"},
|
|
{"inst": "vsub.f64 Dd, Dn, Dm" , "t32": "1110|11100|Vd'|11|Vn|Vd|10|11|Vn'|1|Vm'|0|Vm" , "it": "any"}
|
|
]},
|
|
|
|
{"category": "FP", "ext": "FP FP16", "data": [
|
|
{"inst": "vabs.f16 Sd, Sn" , "a32": "1110|11101|'Vd|11|00|00|Vd|10|01|1|1|'Vn|0|Vn"},
|
|
{"inst": "vadd.f16 Sd, Sn, Sm" , "a32": "1110|11100|'Vd|11|Vn|Vd|1001|'Vn|0|'Vm|0|Vm"},
|
|
{"inst": "vcmp.f16 Sn, Sm" , "a32": "1110|11101|'Vn|11|01|00|Vn|10|01|01|'Vm|0|Vm"},
|
|
{"inst": "vcmp.f16 Sn, #zero" , "a32": "1110|11101|'Vn|11|01|01|Vn|10|01|01|00|0000"},
|
|
{"inst": "vcmpe.f16 Sn, Sm" , "a32": "1110|11101|'Vn|11|01|00|Vn|10|01|11|'Vm|0|Vm"},
|
|
{"inst": "vcmpe.f16 Sn, #zero" , "a32": "1110|11101|'Vn|11|01|01|Vn|10|01|11|00|0000"},
|
|
{"inst": "vdiv.f16 Sd, Sn, Sm" , "a32": "1110|11101|'Vd|00|Vn|Vd|10|01|'Vn|0|'Vm|0|Vm"},
|
|
{"inst": "vldr.16 Sd, [Rn, #+/-off*2]" , "a32": "1110|1101U|'Vd|01|Rn|Vd|1001|off:8"},
|
|
{"inst": "vmla.f16 Sx, Sn, Sm" , "a32": "1110|11100|'Vx|00|Vn|Vx|10|01|'Vn|0|'Vm|0|Vm"},
|
|
{"inst": "vmls.f16 Sx, Sn, Sm" , "a32": "1110|11100|'Vx|00|Vn|Vx|10|01|'Vn|1|'Vm|0|Vm"},
|
|
{"inst": "vmov.f16 Rd!=PC, Sn" , "a32": "1110|11100|0|01|Vn|Rd|1001|'Vn|00|1|0000"},
|
|
{"inst": "vmov.f16 Sd, Rn!=PC" , "a32": "1110|11100|0|00|Vd|Rn|1001|'Vd|00|1|0000"},
|
|
{"inst": "vmov.f16 Sd, #immVFP" , "a32": "1110|11101|'Vd|11|imm:4|Vd|1001|0000|imm:4" , "imm": "VecVFPImm(immVFP)"},
|
|
{"inst": "vmovx.f16 Sd, Sn" , "a32": "1111|11101|'Vd|11|00|00|Vd|1010|01|'Vn|0|Vn"},
|
|
{"inst": "vmul.f16 Sd, Sn, Sm" , "a32": "1110|11100|'Vd|10|Vn|Vd|10|01|'Vn|0|'Vm|0|Vm"},
|
|
{"inst": "vmul.f16 Dd, Dn, Dm<=07[#i]" , "a32": "1111|00101|Vd'|01|Vn|Vd|1001|Vn'|1|i:1|0|i:1|Vm:3"},
|
|
{"inst": "vmul.f16 Vd, Vn, Dm<=07[#i]" , "a32": "1111|00111|Vd'|01|Vn|Vd|1001|Vn'|1|i:1|0|i:1|Vm:3"},
|
|
{"inst": "vneg.f16 Sd, Sn" , "a32": "1110|11101|'Vd|11|0001|Vd|10|01|01|'Vn|0|Vn"},
|
|
{"inst": "vnmla.f16 Sx, Sn, Sm" , "a32": "1110|11100|'Vx|01|Vn|Vx|10|01|'Vn|1|'Vm|0|Vm"},
|
|
{"inst": "vnmls.f16 Sx, Sn, Sm" , "a32": "1110|11100|'Vx|01|Vn|Vx|10|01|'Vn|0|'Vm|0|Vm"},
|
|
{"inst": "vnmul.f16 Sd, Sn, Sm" , "a32": "1110|11100|'Vd|10|Vn|Vd|10|01|'Vn|1|'Vm|0|Vm"},
|
|
{"inst": "vsqrt.f16 Sd, Sn" , "a32": "1110|11101|'Vd|11|0001|Vd|10|01|11|'Vn|0|Vn"},
|
|
{"inst": "vstr.16 Ss, [Rn, #+/-off*2]" , "a32": "1110|1101U|'Vs|00|Rn|Vs|1001|off:8"},
|
|
{"inst": "vsub.f16 Sd, Sn, Sm" , "a32": "1110|11100|'Vd|11|Vn|Vd|10|01|'Vn|1|'Vm|0|Vm"}
|
|
]},
|
|
|
|
{"category": "FP", "ext": "FP FP16", "data": [
|
|
{"inst": "vabs.f16 Sd, Sn" , "t32": "1110|11101|'Vd|11|00|00|Vd|10|01|1|1|'Vn|0|Vn" , "it": "out"},
|
|
{"inst": "vadd.f16 Sd, Sn, Sm" , "t32": "1110|11100|'Vd|11|Vn|Vd|1001|'Vn|0|'Vm|0|Vm" , "it": "out"},
|
|
{"inst": "vcmp.f16 Sn, Sm" , "t32": "1110|11101|'Vn|11|01|00|Vn|10|01|01|'Vm|0|Vm" , "it": "out"},
|
|
{"inst": "vcmp.f16 Sn, #zero" , "t32": "1110|11101|'Vn|11|01|01|Vn|10|01|01|00|0000" , "it": "out"},
|
|
{"inst": "vcmpe.f16 Sn, Sm" , "t32": "1110|11101|'Vn|11|01|00|Vn|10|01|11|'Vm|0|Vm" , "it": "out"},
|
|
{"inst": "vcmpe.f16 Sn, #zero" , "t32": "1110|11101|'Vn|11|01|01|Vn|10|01|11|00|0000" , "it": "out"},
|
|
{"inst": "vdiv.f16 Sd, Sn, Sm" , "t32": "1110|11101|'Vd|00|Vn|Vd|10|01|'Vn|0|'Vm|0|Vm" , "it": "out"},
|
|
{"inst": "vldr.16 Sd, [Rn, #+/-off*2]" , "t32": "1110|1101U|'Vd|01|Rn|Vd|1001|off:8" , "it": "out"},
|
|
{"inst": "vmla.f16-32 Sx, Sn, Sm" , "t32": "1110|11100|'Vx|00|Vn|Vx|10|sz|'Vn|0|'Vm|0|Vm" , "it": "out"},
|
|
{"inst": "vmls.f16-32 Sx, Sn, Sm" , "t32": "1110|11100|'Vx|00|Vn|Vx|10|sz|'Vn|1|'Vm|0|Vm" , "it": "out"},
|
|
{"inst": "vmov.f16 Rd!=PC, Sn" , "t32": "1110|11100|0|01|Vn|Rd|1001|'Vn|00|1|0000" , "it": "out"},
|
|
{"inst": "vmov.f16 Sd, Rn!=PC" , "t32": "1110|11100|0|00|Vd|Rn|1001|'Vd|00|1|0000" , "it": "out"},
|
|
{"inst": "vmov.f16 Sd, #immVFP" , "t32": "1110|11101|'Vd|11|imm:4|Vd|1001|0000|imm:4" , "it": "out", "imm": "VecVFPImm(immVFP)"},
|
|
{"inst": "vmovx.f16 Sd, Sn" , "t32": "1111|11101|'Vd|11|00|00|Vd|1010|01|'Vn|0|Vn" , "it": "out"},
|
|
{"inst": "vmul.f16 Sd, Sn, Sm" , "t32": "1110|11100|'Vd|10|Vn|Vd|10|01|'Vn|0|'Vm|0|Vm" , "it": "out"},
|
|
{"inst": "vmul.f16 Dd, Dn, Dm<=07[#i]" , "t32": "1110|11111|Vd'|01|Vn|Vd|1001|Vn'|1|i:1|0|i:1|Vm:3" , "it": "out"},
|
|
{"inst": "vmul.f16 Vd, Vn, Dm<=07[#i]" , "t32": "1111|11111|Vd'|01|Vn|Vd|1001|Vn'|1|i:1|0|i:1|Vm:3" , "it": "out"},
|
|
{"inst": "vneg.f16 Sd, Sn" , "t32": "1110|11101|'Vd|11|0001|Vd|10|01|01|'Vn|0|Vn" , "it": "out"},
|
|
{"inst": "vnmla.f16 Sx, Sn, Sm" , "t32": "1110|11100|'Vx|01|Vn|Vx|10|01|'Vn|1|'Vm|0|Vm" , "it": "out"},
|
|
{"inst": "vnmls.f16 Sx, Sn, Sm" , "t32": "1110|11100|'Vx|01|Vn|Vx|10|01|'Vn|0|'Vm|0|Vm" , "it": "out"},
|
|
{"inst": "vnmul.f16 Sd, Sn, Sm" , "t32": "1110|11100|'Vd|10|Vn|Vd|10|01|'Vn|1|'Vm|0|Vm" , "it": "out"},
|
|
{"inst": "vsqrt.f16 Sd, Sn" , "t32": "1110|11101|'Vd|11|0001|Vd|10|01|11|'Vn|0|Vn" , "it": "out"},
|
|
{"inst": "vstr.16 Ss, [Rn, #+/-off*2]" , "t32": "1110|1101U|'Vs|00|Rn|Vs|1001|off:8" , "it": "out"},
|
|
{"inst": "vsub.f16 Sd, Sn, Sm" , "t32": "1110|11100|'Vd|11|Vn|Vd|10|01|'Vn|1|'Vm|0|Vm" , "it": "out"}
|
|
]},
|
|
|
|
{"category": "ASIMD", "ext": "VFPv4", "data": [
|
|
{"inst": "vfma.f16 Sx, Sn, Sm" , "a32": "1110|11101|'Vx|10|Vn|Vx|10|01|'Vn|0|'Vm|0|Vm" , "ext": "VFPv4 FP16"},
|
|
{"inst": "vfma.f32 Sx, Sn, Sm" , "a32": "cond|11101|'Vx|10|Vn|Vx|10|10|'Vn|0|'Vm|0|Vm" , "ext": "VFPv4"},
|
|
{"inst": "vfma.f64 Dx, Dn, Dm" , "a32": "cond|11101|Vx'|10|Vn|Vx|10|11|Vn'|0|Vm'|0|Vm" , "ext": "VFPv4"},
|
|
{"inst": "vfms.f16 Sx, Sn, Sm" , "a32": "1110|11101|'Vx|10|Vn|Vx|10|01|'Vn|1|'Vm|0|Vm" , "ext": "VFPv4 FP16"},
|
|
{"inst": "vfms.f32 Sx, Sn, Sm" , "a32": "cond|11101|'Vx|10|Vn|Vx|10|10|'Vn|1|'Vm|0|Vm" , "ext": "VFPv4"},
|
|
{"inst": "vfms.f64 Dx, Dn, Dm" , "a32": "cond|11101|Vx'|10|Vn|Vx|10|11|Vn'|1|Vm'|0|Vm" , "ext": "VFPv4"},
|
|
{"inst": "vfnma.f16 Sx, Sn, Sm" , "a32": "1110|11101|'Vx|01|Vn|Vx|10|01|'Vn|1|'Vm|0|Vm" , "ext": "VFPv4 FP16"},
|
|
{"inst": "vfnma.f32 Sx, Sn, Sm" , "a32": "cond|11101|'Vx|01|Vn|Vx|10|10|'Vn|1|'Vm|0|Vm" , "ext": "VFPv4"},
|
|
{"inst": "vfnma.f64 Dx, Dn, Dm" , "a32": "cond|11101|Vx'|01|Vn|Vx|10|11|Vn'|1|Vm'|0|Vm" , "ext": "VFPv4"},
|
|
{"inst": "vfnms.f16 Sx, Sn, Sm" , "a32": "1110|11101|'Vx|01|Vn|Vx|10|01|'Vn|0|'Vm|0|Vm" , "ext": "VFPv4 FP16"},
|
|
{"inst": "vfnms.f32 Sx, Sn, Sm" , "a32": "cond|11101|'Vx|01|Vn|Vx|10|10|'Vn|0|'Vm|0|Vm" , "ext": "VFPv4"},
|
|
{"inst": "vfnms.f64 Dx, Dn, Dm" , "a32": "cond|11101|Vx'|01|Vn|Vx|10|11|Vn'|0|Vm'|0|Vm" , "ext": "VFPv4"}
|
|
]},
|
|
|
|
{"category": "ASIMD", "ext": "VFPv4", "data": [
|
|
{"inst": "vfma.f16 Sx, Sn, Sm" , "t32": "1110|11101|'Vx|10|Vn|Vx|10|01|'Vn|0|'Vm|0|Vm" , "it": "out", "ext": "VFPv4 FP16"},
|
|
{"inst": "vfma.f32 Sx, Sn, Sm" , "t32": "1110|11101|'Vx|10|Vn|Vx|10|10|'Vn|0|'Vm|0|Vm" , "it": "any", "ext": "VFPv4"},
|
|
{"inst": "vfma.f64 Dx, Dn, Dm" , "t32": "1110|11101|Vx'|10|Vn|Vx|10|11|Vn'|0|Vm'|0|Vm" , "it": "any", "ext": "VFPv4"},
|
|
{"inst": "vfms.f16 Sx, Sn, Sm" , "t32": "1110|11101|'Vx|10|Vn|Vx|10|01|'Vn|1|'Vm|0|Vm" , "it": "out", "ext": "VFPv4 FP16"},
|
|
{"inst": "vfms.f32 Sx, Sn, Sm" , "t32": "1110|11101|'Vx|10|Vn|Vx|10|10|'Vn|1|'Vm|0|Vm" , "it": "any", "ext": "VFPv4"},
|
|
{"inst": "vfms.f64 Dx, Dn, Dm" , "t32": "1110|11101|Vx'|10|Vn|Vx|10|11|Vn'|1|Vm'|0|Vm" , "it": "any", "ext": "VFPv4"},
|
|
{"inst": "vfnma.f16 Sx, Sn, Sm" , "t32": "1110|11101|'Vx|01|Vn|Vx|10|01|'Vn|1|'Vm|0|Vm" , "it": "out", "ext": "VFPv4 FP16"},
|
|
{"inst": "vfnma.f32 Sx, Sn, Sm" , "t32": "1110|11101|'Vx|01|Vn|Vx|10|10|'Vn|1|'Vm|0|Vm" , "it": "any", "ext": "VFPv4"},
|
|
{"inst": "vfnma.f64 Dx, Dn, Dm" , "t32": "1110|11101|Vx'|01|Vn|Vx|10|11|Vn'|1|Vm'|0|Vm" , "it": "any", "ext": "VFPv4"},
|
|
{"inst": "vfnms.f16 Sx, Sn, Sm" , "t32": "1110|11101|'Vx|01|Vn|Vx|10|01|'Vn|0|'Vm|0|Vm" , "it": "out", "ext": "VFPv4 FP16"},
|
|
{"inst": "vfnms.f32 Sx, Sn, Sm" , "t32": "1110|11101|'Vx|01|Vn|Vx|10|10|'Vn|0|'Vm|0|Vm" , "it": "any", "ext": "VFPv4"},
|
|
{"inst": "vfnms.f64 Dx, Dn, Dm" , "t32": "1110|11101|Vx'|01|Vn|Vx|10|11|Vn'|0|Vm'|0|Vm" , "it": "any", "ext": "VFPv4"}
|
|
]},
|
|
|
|
{"category": "ASIMD", "ext": "ASIMD", "data": [
|
|
{"inst": "vaba.x8-32 Dd, Dn, Dm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|0111|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vaba.x8-32 Vd, Vn, Vm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|0111|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vabal.x8-32 Vd, Dn, Dm" , "a32": "1111|001U1|Vd'|sz|Vn|Vd|0101|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vabd.f16 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|11|Vn|Vd|1101|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vabd.f16 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|11|Vn|Vd|1101|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vabd.f32 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|10|Vn|Vd|1101|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vabd.f32 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|10|Vn|Vd|1101|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vabd.x8-32 Dd, Dn, Dm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|0111|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vabd.x8-32 Vd, Vn, Vm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|0111|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vabdl.x8-32 Vd, Dn, Dm" , "a32": "1111|001U1|Vd'|sz|Vn|Vd|0111|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vabs.f16 Dd, Dn" , "a32": "1111|00111|Vd'|11|01|01|Vd|01|11|0|0|Vn'|0|Vn" , "ext": "ASIMD FP16"},
|
|
{"inst": "vabs.f16 Vd, Vn" , "a32": "1111|00111|Vd'|11|01|01|Vd|01|11|0|1|Vn'|0|Vn" , "ext": "ASIMD FP16"},
|
|
{"inst": "vabs.f32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|01|Vd|01|11|0|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vabs.f32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|01|Vd|01|11|0|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vabs.s8-32 Dd, Dn" , "a32": "1111|00111|Vd'|11|sz|01|Vd|00|11|0|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vabs.s8-32 Vd, Vn" , "a32": "1111|00111|Vd'|11|sz|01|Vd|00|11|0|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vacge.f16 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|01|Vn|Vd|1110|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vacge.f16 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|01|Vn|Vd|1110|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vacge.f32 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|00|Vn|Vd|1110|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vacge.f32 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|00|Vn|Vd|1110|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vacgt.f16 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|11|Vn|Vd|1110|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vacgt.f16 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|11|Vn|Vd|1110|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vacgt.f32 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|10|Vn|Vd|1110|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vacgt.f32 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|10|Vn|Vd|1110|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vacle.f16 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|01|Vm|Vd|1110|Vm'|0|Vn'|1|Vn" , "ext": "ASIMD FP16"},
|
|
{"inst": "vacle.f16 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|01|Vm|Vd|1110|Vm'|1|Vn'|1|Vn" , "ext": "ASIMD FP16"},
|
|
{"inst": "vacle.f32 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|00|Vm|Vd|1110|Vm'|0|Vn'|1|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vacle.f32 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|00|Vm|Vd|1110|Vm'|1|Vn'|1|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vaclt.f16 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|11|Vm|Vd|1110|Vm'|0|Vn'|1|Vn" , "ext": "ASIMD FP16"},
|
|
{"inst": "vaclt.f16 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|11|Vm|Vd|1110|Vm'|1|Vn'|1|Vn" , "ext": "ASIMD FP16"},
|
|
{"inst": "vaclt.f32 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|10|Vm|Vd|1110|Vm'|0|Vn'|1|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vaclt.f32 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|10|Vm|Vd|1110|Vm'|1|Vn'|1|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vadd.f16 Dd, Dn, Dm" , "a32": "1111|00100|Vd'|01|Vn|Vd|1101|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vadd.f16 Vd, Vn, Vm" , "a32": "1111|00100|Vd'|01|Vn|Vd|1101|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vadd.f32 Dd, Dn, Dm" , "a32": "1111|00100|Vd'|00|Vn|Vd|1101|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vadd.f32 Vd, Vn, Vm" , "a32": "1111|00100|Vd'|00|Vn|Vd|1101|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vadd.x8-64 Dd, Dn, Dm" , "a32": "1111|00100|Vd'|sz|Vn|Vd|1000|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vadd.x8-64 Vd, Vn, Vm" , "a32": "1111|00100|Vd'|sz|Vn|Vd|1000|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vaddhn.x16-64 Dd, Vn, Vm" , "a32": "1111|00101|Vd'|szM1:2|Vn|Vd|0100|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "narrow"},
|
|
{"inst": "vaddl.x8-32 Vd, Dn, Dm" , "a32": "1111|001U1|Vd'|sz|Vn|Vd|0000|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "widen"},
|
|
{"inst": "vaddw.x8-32 Vd, Vn, Dm" , "a32": "1111|001U1|Vd'|sz|Vn|Vd|0001|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "widen"},
|
|
{"inst": "vand.any Dd, Dn, Dm" , "a32": "1111|00100|Vd'|00|Vn|Vd|0001|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vand.any Vd, Vn, Vm" , "a32": "1111|00100|Vd'|00|Vn|Vd|0001|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vand.x16-64 Dx, #immV" , "a32": "1111|001|imm:1|1|Vx'|000|imm:3|Vx|cmode:4|0011|imm:4" , "ext": "ASIMD", "imm": "VecBicOrrImm(sz, 1, immV)", "pseudoOf": "vbic"},
|
|
{"inst": "vand.x16-64 Vx, #immV" , "a32": "1111|001|imm:1|1|Vx'|000|imm:3|Vx|cmode:4|0111|imm:4" , "ext": "ASIMD", "imm": "VecBicOrrImm(sz, 1, immV)", "pseudoOf": "vbic"},
|
|
{"inst": "vbic.any Dd, Dn, Dm" , "a32": "1111|00100|Vd'|01|Vn|Vd|0001|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vbic.any Vd, Vn, Vm" , "a32": "1111|00100|Vd'|01|Vn|Vd|0001|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vbic.x16-64 Dx, #immV" , "a32": "1111|001|imm:1|1|Vx'|000|imm:3|Vx|cmode:4|0011|imm:4" , "ext": "ASIMD", "imm": "VecBicOrrImm(sz, 0, immV)"},
|
|
{"inst": "vbic.x16-64 Vx, #immV" , "a32": "1111|001|imm:1|1|Vx'|000|imm:3|Vx|cmode:4|0111|imm:4" , "ext": "ASIMD", "imm": "VecBicOrrImm(sz, 0, immV)"},
|
|
{"inst": "vbif.any Dd, Dn, Dm" , "a32": "1111|00110|Vd'|11|Vn|Vd|0001|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vbif.any Vd, Vn, Vm" , "a32": "1111|00110|Vd'|11|Vn|Vd|0001|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vbit.any Dd, Dn, Dm" , "a32": "1111|00110|Vd'|10|Vn|Vd|0001|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vbit.any Vd, Vn, Vm" , "a32": "1111|00110|Vd'|10|Vn|Vd|0001|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vbsl.any Dd, Dn, Dm" , "a32": "1111|00110|Vd'|01|Vn|Vd|0001|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vbsl.any Vd, Vn, Vm" , "a32": "1111|00110|Vd'|01|Vn|Vd|0001|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vceq.f16 Dd, Dn, Dm" , "a32": "1111|00100|Vd'|01|Vn|Vd|1110|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vceq.f16 Vd, Vn, Vm" , "a32": "1111|00100|Vd'|01|Vn|Vd|1110|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vceq.f32 Dd, Dn, Dm" , "a32": "1111|00100|Vd'|00|Vn|Vd|1110|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vceq.f32 Vd, Vn, Vm" , "a32": "1111|00100|Vd'|00|Vn|Vd|1110|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vceq.f16 Dd, Dn, #zero" , "a32": "1111|00111|Vd'|11|01|01|Vd|01010|0|Vn'|0|Vn" , "ext": "ASIMD FP16"},
|
|
{"inst": "vceq.f16 Vd, Vn, #zero" , "a32": "1111|00111|Vd'|11|01|01|Vd|01010|1|Vn'|0|Vn" , "ext": "ASIMD FP16"},
|
|
{"inst": "vceq.f32 Dd, Dn, #zero" , "a32": "1111|00111|Vd'|11|10|01|Vd|01010|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vceq.f32 Vd, Vn, #zero" , "a32": "1111|00111|Vd'|11|10|01|Vd|01010|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vceq.x8-32 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|sz|Vn|Vd|1000|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vceq.x8-32 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|sz|Vn|Vd|1000|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vceq.x8-32 Dd, Dn, #zero" , "a32": "1111|00111|Vd'|11|sz|01|Vd|00010|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vceq.x8-32 Vd, Vn, #zero" , "a32": "1111|00111|Vd'|11|sz|01|Vd|00010|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vcge.f16 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|01|Vn|Vd|1110|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vcge.f16 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|01|Vn|Vd|1110|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vcge.f32 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|00|Vn|Vd|1110|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vcge.f32 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|00|Vn|Vd|1110|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vcge.f16 Dd, Dn, #zero" , "a32": "1111|00111|Vd'|11|01|01|Vd|01001|0|Vn'|0|Vn" , "ext": "ASIMD FP16"},
|
|
{"inst": "vcge.f16 Vd, Vn, #zero" , "a32": "1111|00111|Vd'|11|01|01|Vd|01001|1|Vn'|0|Vn" , "ext": "ASIMD FP16"},
|
|
{"inst": "vcge.f32 Dd, Dn, #zero" , "a32": "1111|00111|Vd'|11|10|01|Vd|01001|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vcge.f32 Vd, Vn, #zero" , "a32": "1111|00111|Vd'|11|10|01|Vd|01001|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vcge.x8-32 Dd, Dn, Dm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|0011|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vcge.x8-32 Vd, Vn, Vm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|0011|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vcge.s8-32 Dd, Dn, #zero" , "a32": "1111|00111|Vd'|11|sz|01|Vd|00001|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vcge.s8-32 Vd, Vn, #zero" , "a32": "1111|00111|Vd'|11|sz|01|Vd|00001|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vcgt.f16 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|11|Vn|Vd|1110|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vcgt.f16 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|11|Vn|Vd|1110|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vcgt.f32 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|10|Vn|Vd|1110|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vcgt.f32 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|10|Vn|Vd|1110|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vcgt.f16 Dd, Dn, #zero" , "a32": "1111|00111|Vd'|11|01|01|Vd|01000|0|Vn'|0|Vn" , "ext": "ASIMD FP16"},
|
|
{"inst": "vcgt.f16 Vd, Vn, #zero" , "a32": "1111|00111|Vd'|11|01|01|Vd|01000|1|Vn'|0|Vn" , "ext": "ASIMD FP16"},
|
|
{"inst": "vcgt.f32 Dd, Dn, #zero" , "a32": "1111|00111|Vd'|11|10|01|Vd|01000|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vcgt.f32 Vd, Vn, #zero" , "a32": "1111|00111|Vd'|11|10|01|Vd|01000|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vcgt.x8-32 Dd, Dn, Dm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|0011|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vcgt.x8-32 Vd, Vn, Vm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|0011|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vcgt.s8-32 Dd, Dn, #zero" , "a32": "1111|00111|Vd'|11|sz|01|Vd|00000|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vcgt.s8-32 Vd, Vn, #zero" , "a32": "1111|00111|Vd'|11|sz|01|Vd|00000|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vcle.f16 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|01|Vm|Vd|1110|Vm'|0|Vn'|0|Vn" , "ext": "ASIMD FP16"},
|
|
{"inst": "vcle.f16 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|01|Vm|Vd|1110|Vm'|1|Vn'|0|Vn" , "ext": "ASIMD FP16"},
|
|
{"inst": "vcle.f32 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|00|Vm|Vd|1110|Vm'|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vcle.f32 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|00|Vm|Vd|1110|Vm'|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vcle.f16 Dd, Dn, #zero" , "a32": "1111|00111|Vd'|11|01|01|Vd|01011|0|Vn'|0|Vn" , "ext": "ASIMD FP16"},
|
|
{"inst": "vcle.f16 Vd, Vn, #zero" , "a32": "1111|00111|Vd'|11|01|01|Vd|01011|1|Vn'|0|Vn" , "ext": "ASIMD FP16"},
|
|
{"inst": "vcle.f32 Dd, Dn, #zero" , "a32": "1111|00111|Vd'|11|10|01|Vd|01011|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vcle.f32 Vd, Vn, #zero" , "a32": "1111|00111|Vd'|11|10|01|Vd|01011|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vcle.x8-32 Dd, Dn, Dm" , "a32": "1111|001U0|Vd'|sz|Vm|Vd|0011|Vm'|0|Vn'|1|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vcle.x8-32 Vd, Vn, Vm" , "a32": "1111|001U0|Vd'|sz|Vm|Vd|0011|Vm'|1|Vn'|1|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vcle.s8-32 Dd, Dn, #zero" , "a32": "1111|00111|Vd'|11|sz|01|Vd|00011|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vcle.s8-32 Vd, Vn, #zero" , "a32": "1111|00111|Vd'|11|sz|01|Vd|00011|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vcls.x8-32 Dd, Dn" , "a32": "1111|00111|Vd'|11|sz|00|Vd|01000|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vcls.x8-32 Vd, Vn" , "a32": "1111|00111|Vd'|11|sz|00|Vd|01000|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vclt.f16 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|11|Vm|Vd|1110|Vm'|0|Vn'|0|Vn" , "ext": "ASIMD FP16"},
|
|
{"inst": "vclt.f16 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|11|Vm|Vd|1110|Vm'|1|Vn'|0|Vn" , "ext": "ASIMD FP16"},
|
|
{"inst": "vclt.f32 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|10|Vm|Vd|1110|Vm'|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vclt.f32 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|10|Vm|Vd|1110|Vm'|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vclt.f16 Dd, Dn, #zero" , "a32": "1111|00111|Vd'|11|01|01|Vd|01100|0|Vn'|0|Vn" , "ext": "ASIMD FP16"},
|
|
{"inst": "vclt.f16 Vd, Vn, #zero" , "a32": "1111|00111|Vd'|11|01|01|Vd|01100|1|Vn'|0|Vn" , "ext": "ASIMD FP16"},
|
|
{"inst": "vclt.f32 Dd, Dn, #zero" , "a32": "1111|00111|Vd'|11|10|01|Vd|01100|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vclt.f32 Vd, Vn, #zero" , "a32": "1111|00111|Vd'|11|10|01|Vd|01100|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vclt.x8-32 Dd, Dn, Dm" , "a32": "1111|001U0|Vd'|sz|Vm|Vd|0011|Vm'|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vclt.x8-32 Vd, Vn, Vm" , "a32": "1111|001U0|Vd'|sz|Vm|Vd|0011|Vm'|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vclt.s8-32 Dd, Dn, #zero" , "a32": "1111|00111|Vd'|11|sz|01|Vd|00100|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vclt.s8-32 Vd, Vn, #zero" , "a32": "1111|00111|Vd'|11|sz|01|Vd|00100|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vclz.x8-32 Dd, Dn" , "a32": "1111|00111|Vd'|11|sz|00|Vd|01001|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vclz.x8-32 Vd, Vn" , "a32": "1111|00111|Vd'|11|sz|00|Vd|01001|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vcnt.x8 Dd, Dn" , "a32": "1111|00111|Vd'|11|00|00|Vd|01010|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vcnt.x8 Vd, Vn" , "a32": "1111|00111|Vd'|11|00|00|Vd|01010|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vcvt.s32.f32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|11|Vd|01110|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vcvt.s32.f32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|11|Vd|01110|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vcvt.u32.f32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|11|Vd|01111|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vcvt.u32.f32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|11|Vd|01111|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vcvt.f32.s32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|11|Vd|01100|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vcvt.f32.s32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|11|Vd|01100|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vcvt.f32.u32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|11|Vd|01101|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vcvt.f32.u32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|11|Vd|01101|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vcvt.f32.s32 Dd, Dn, #fbits" , "a32": "1111|00101|Vd'|imm:6|Vd|11100|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecFBitsASIMD(fbits)"},
|
|
{"inst": "vcvt.f32.s32 Vd, Vn, #fbits" , "a32": "1111|00101|Vd'|imm:6|Vd|11100|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecFBitsASIMD(fbits)"},
|
|
{"inst": "vcvt.s32.f32 Dd, Dn, #fbits" , "a32": "1111|00101|Vd'|imm:6|Vd|11110|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecFBitsASIMD(fbits)"},
|
|
{"inst": "vcvt.s32.f32 Vd, Vn, #fbits" , "a32": "1111|00101|Vd'|imm:6|Vd|11110|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecFBitsASIMD(fbits)"},
|
|
{"inst": "vcvt.f32.u32 Dd, Dn, #fbits" , "a32": "1111|00111|Vd'|imm:6|Vd|11100|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecFBitsASIMD(fbits)"},
|
|
{"inst": "vcvt.f32.u32 Vd, Vn, #fbits" , "a32": "1111|00111|Vd'|imm:6|Vd|11100|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecFBitsASIMD(fbits)"},
|
|
{"inst": "vcvt.u32.f32 Dd, Dn, #fbits" , "a32": "1111|00111|Vd'|imm:6|Vd|11110|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecFBitsASIMD(fbits)"},
|
|
{"inst": "vcvt.u32.f32 Vd, Vn, #fbits" , "a32": "1111|00111|Vd'|imm:6|Vd|11110|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecFBitsASIMD(fbits)"},
|
|
{"inst": "vcvta.s32.f32 Sd, Sn" , "a32": "1111|11101|'Vd|11|11|00|Vd|10101|1|'Vn|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vcvta.s32.f64 Sd, Dn" , "a32": "1111|11101|'Vd|11|11|00|Vd|10111|1|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vcvta.u32.f32 Sd, Sn" , "a32": "1111|11101|'Vd|11|11|00|Vd|10100|1|'Vn|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vcvta.u32.f64 Sd, Dn" , "a32": "1111|11101|'Vd|11|11|00|Vd|10110|1|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vcvtm.s32.f32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|11|Vd|00110|0|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vcvtm.s32.f32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|11|Vd|00110|1|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vcvtm.u32.f32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|11|Vd|00111|0|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vcvtm.u32.f32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|11|Vd|00111|1|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vcvtm.s32.f32 Sd, Sn" , "a32": "1111|11101|'Vd|11|11|11|Vd|10101|1|'Vn|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vcvtm.s32.f64 Sd, Dn" , "a32": "1111|11101|'Vd|11|11|11|Vd|10111|1|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vcvtm.u32.f32 Sd, Sn" , "a32": "1111|11101|'Vd|11|11|11|Vd|10100|1|'Vn|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vcvtm.u32.f64 Sd, Dn" , "a32": "1111|11101|'Vd|11|11|11|Vd|10110|1|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vcvtn.s32.f32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|11|Vd|00010|0|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vcvtn.s32.f32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|11|Vd|00010|1|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vcvtn.u32.f32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|11|Vd|00011|0|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vcvtn.u32.f32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|11|Vd|00011|1|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vcvtn.s32.f32 Sd, Sn" , "a32": "1111|11101|'Vd|11|11|01|Vd|10101|1|'Vn|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vcvtn.s32.f64 Sd, Dn" , "a32": "1111|11101|'Vd|11|11|01|Vd|10111|1|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vcvtn.u32.f32 Sd, Sn" , "a32": "1111|11101|'Vd|11|11|01|Vd|10100|1|'Vn|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vcvtn.u32.f64 Sd, Dn" , "a32": "1111|11101|'Vd|11|11|01|Vd|10110|1|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vcvtp.s32.f32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|11|Vd|00100|0|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vcvtp.s32.f32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|11|Vd|00100|1|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vcvtp.u32.f32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|11|Vd|00101|0|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vcvtp.u32.f32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|11|Vd|00101|1|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vcvtp.s32.f32 Sd, Sn" , "a32": "1111|11101|'Vd|11|11|10|Vd|10101|1|'Vn|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vcvtp.s32.f64 Sd, Dn" , "a32": "1111|11101|'Vd|11|11|10|Vd|10111|1|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vcvtp.u32.f32 Sd, Sn" , "a32": "1111|11101|'Vd|11|11|10|Vd|10100|1|'Vn|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vcvtp.u32.f64 Sd, Dn" , "a32": "1111|11101|'Vd|11|11|10|Vd|10110|1|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vdup.8 Dd, Rn!=PC" , "a32": "cond|11101|1|00|Vd|Rn|1011|Vd'|0|0|1|0000" , "ext": "ASIMD"},
|
|
{"inst": "vdup.8 Vd, Rn!=PC" , "a32": "cond|11101|1|10|Vd|Rn|1011|Vd'|0|0|1|0000" , "ext": "ASIMD"},
|
|
{"inst": "vdup.16 Dd, Rn!=PC" , "a32": "cond|11101|0|00|Vd|Rn|1011|Vd'|0|1|1|0000" , "ext": "ASIMD"},
|
|
{"inst": "vdup.16 Vd, Rn!=PC" , "a32": "cond|11101|0|10|Vd|Rn|1011|Vd'|0|1|1|0000" , "ext": "ASIMD"},
|
|
{"inst": "vdup.32 Dd, Rn!=PC" , "a32": "cond|11101|0|00|Vd|Rn|1011|Vd'|0|0|1|0000" , "ext": "ASIMD"},
|
|
{"inst": "vdup.32 Vd, Rn!=PC" , "a32": "cond|11101|0|10|Vd|Rn|1011|Vd'|0|0|1|0000" , "ext": "ASIMD"},
|
|
{"inst": "vdup.8 Dd, Dn[#i]" , "a32": "1111|00111|Vd'|11|i:3|1|Vd|1100|0|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vdup.8 Vd, Dn[#i]" , "a32": "1111|00111|Vd'|11|i:3|1|Vd|1100|0|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vdup.16 Dd, Dn[#i]" , "a32": "1111|00111|Vd'|11|i:2|10|Vd|1100|0|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vdup.16 Vd, Dn[#i]" , "a32": "1111|00111|Vd'|11|i:2|10|Vd|1100|0|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vdup.32 Dd, Dn[#i]" , "a32": "1111|00111|Vd'|11|i:1|100|Vd|1100|0|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vdup.32 Vd, Dn[#i]" , "a32": "1111|00111|Vd'|11|i:1|100|Vd|1100|0|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "veor.any Dd, Dn, Dm" , "a32": "1111|00110|Vd'|00|Vn|Vd|0001|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "veor.any Vd, Vn, Vm" , "a32": "1111|00110|Vd'|00|Vn|Vd|0001|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vext.8 Dd, Dn, Dm, #immZ<=07" , "a32": "1111|00101|Vd'|11|Vn|Vd|immZ:4|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vext.8 Vd, Vn, Vm, #immZ<=15" , "a32": "1111|00101|Vd'|11|Vn|Vd|immZ:4|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vfma.f16 Dx, Dn, Dm" , "a32": "1111|00100|Vx'|01|Vn|Vx|1100|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vfma.f16 Vx, Vn, Vm" , "a32": "1111|00100|Vx'|01|Vn|Vx|1100|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vfma.f32 Dx, Dn, Dm" , "a32": "1111|00100|Vx'|00|Vn|Vx|1100|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vfma.f32 Vx, Vn, Vm" , "a32": "1111|00100|Vx'|00|Vn|Vx|1100|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vfms.f16 Dx, Dn, Dm" , "a32": "1111|00100|Vx'|11|Vn|Vx|1100|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vfms.f16 Vx, Vn, Vm" , "a32": "1111|00100|Vx'|11|Vn|Vx|1100|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vfms.f32 Dx, Dn, Dm" , "a32": "1111|00100|Vx'|10|Vn|Vx|1100|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vfms.f32 Vx, Vn, Vm" , "a32": "1111|00100|Vx'|10|Vn|Vx|1100|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vhadd.x8-32 Dd, Dn, Dm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|0000|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vhadd.x8-32 Vd, Vn, Vm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|0000|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vhsub.x8-32 Dd, Dn, Dm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|0010|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vhsub.x8-32 Vd, Vn, Vm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|0010|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vins.f16 Sd, Sn" , "a32": "1111|11101|'Vd|11|0000|Vd|1010|11|'Vn|0|Vn" , "ext": "FP16"},
|
|
{"inst": "vld1.8-64 Dd, [Rn!=PC]" , "a32": "1111|01000|Vd'|10|Rn|Vd|0111|sz|0|align:1|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld1.8-64 Dd, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01000|Vd'|10|Rn|Vd|0111|sz|0|align:1|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld1.8-64 Dd, [Rn!=PC, #off==8]@" , "a32": "1111|01000|Vd'|10|Rn|Vd|0111|sz|0|align:1|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld1.8-64 2x{Dd<=30}+, [Rn!=PC]" , "a32": "1111|01000|Vd'|10|Rn|Vd|1010|sz|0|align:1|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld1.8-64 2x{Dd<=30}+, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01000|Vd'|10|Rn|Vd|1010|sz|0|align:1|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld1.8-64 2x{Dd<=30}+, [Rn!=PC, #off==16]@" , "a32": "1111|01000|Vd'|10|Rn|Vd|1010|sz|0|align:1|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld1.8-64 3x{Dd<=29}+, [Rn!=PC]" , "a32": "1111|01000|Vd'|10|Rn|Vd|0110|sz|0|align:1|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld1.8-64 3x{Dd<=29}+, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01000|Vd'|10|Rn|Vd|0110|sz|0|align:1|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld1.8-64 3x{Dd<=29}+, [Rn!=PC, #off==24]@" , "a32": "1111|01000|Vd'|10|Rn|Vd|0110|sz|0|align:1|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld1.8-64 4x{Dd<=28}+, [Rn!=PC]" , "a32": "1111|01000|Vd'|10|Rn|Vd|0010|sz|0|align:1|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld1.8-64 4x{Dd<=28}+, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01000|Vd'|10|Rn|Vd|0010|sz|0|align:1|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld1.8-64 4x{Dd<=28}+, [Rn!=PC, #off==32]@" , "a32": "1111|01000|Vd'|10|Rn|Vd|0010|sz|0|align:1|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld1.8 Dd[#i], [Rn!=PC]" , "a32": "1111|01001|Vd'|10|Rn|Vd|0000|i:3|align:1|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld1.8 Dd[#i], [Rn!=PC, Rm!=XX]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|0000|i:3|align:1|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld1.8 Dd[#i], [Rn!=PC, #off==1]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|0000|i:3|align:1|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld1.16 Dd[#i], [Rn!=PC]" , "a32": "1111|01001|Vd'|10|Rn|Vd|0100|i:2|0|align:1|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld1.16 Dd[#i], [Rn!=PC, Rm!=XX]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|0100|i:2|0|align:1|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld1.16 Dd[#i], [Rn!=PC, #off==2]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|0100|i:2|0|align:1|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld1.32 Dd[#i], [Rn!=PC]" , "a32": "1111|01001|Vd'|10|Rn|Vd|1000|i:1|0|align:2|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld1.32 Dd[#i], [Rn!=PC, Rm!=XX]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|1000|i:1|0|align:2|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld1.32 Dd[#i], [Rn!=PC, #off==4]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|1000|i:1|0|align:2|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld1r.8-32 Dd, [Rn!=PC]" , "a32": "1111|01001|Vd'|10|Rn|Vd|1100|sz|0|align:1|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld1r.8-32 Dd, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|1100|sz|0|align:1|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld1r.8-32 Dd, [Rn!=PC, #off==1<<sz]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|1100|sz|0|align:1|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld1r.8-32 2x{Dd<=30}+, [Rn!=PC]" , "a32": "1111|01001|Vd'|10|Rn|Vd|1100|sz|1|align:1|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld1r.8-32 2x{Dd<=30}+, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|1100|sz|1|align:1|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld1r.8-32 2x{Dd<=30}+, [Rn!=PC, #off==1<<sz]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|1100|sz|1|align:1|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld2.8-32 2x{Dd<=30}+, [Rn!=PC]" , "a32": "1111|01000|Vd'|10|Rn|Vd|1000|sz|align:2|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld2.8-32 2x{Dd<=30}+, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01000|Vd'|10|Rn|Vd|1000|sz|align:2|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld2.8-32 2x{Dd<=30}+, [Rn!=PC, #off==16]@" , "a32": "1111|01000|Vd'|10|Rn|Vd|1000|sz|align:2|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld2.8-32 2x{Dd<=29}++, [Rn!=PC]" , "a32": "1111|01000|Vd'|10|Rn|Vd|1001|sz|align:2|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld2.8-32 2x{Dd<=29}++, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01000|Vd'|10|Rn|Vd|1001|sz|align:2|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld2.8-32 2x{Dd<=29}++, [Rn!=PC, #off==16]@" , "a32": "1111|01000|Vd'|10|Rn|Vd|1001|sz|align:2|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld2.8-32 4x{Dd<=28}+, [Rn!=PC]" , "a32": "1111|01000|Vd'|10|Rn|Vd|0011|sz|align:2|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld2.8-32 4x{Dd<=28}+, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01000|Vd'|10|Rn|Vd|0011|sz|align:2|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld2.8-32 4x{Dd<=28}+, [Rn!=PC, #off==32]@" , "a32": "1111|01000|Vd'|10|Rn|Vd|0011|sz|align:2|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld2.8 2x{Dd<=30[#i]}+, [Rn!=PC]" , "a32": "1111|01001|Vd'|10|Rn|Vd|0001|i:3|align:1|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld2.8 2x{Dd<=30[#i]}+, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|0001|i:3|align:1|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld2.8 2x{Dd<=30[#i]}+, [Rn!=PC, #off==2]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|0001|i:3|align:1|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld2.16 2x{Dd<=30[#i]}+, [Rn!=PC]" , "a32": "1111|01001|Vd'|10|Rn|Vd|0101|i:2|0|align:1|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld2.16 2x{Dd<=30[#i]}+, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|0101|i:2|0|align:1|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld2.16 2x{Dd<=30[#i]}+, [Rn!=PC, #off==4]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|0101|i:2|0|align:1|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld2.16 2x{Dd<=29[#i]}++, [Rn!=PC]" , "a32": "1111|01001|Vd'|10|Rn|Vd|0101|i:2|1|align:1|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld2.16 2x{Dd<=29[#i]}++, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|0101|i:2|1|align:1|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld2.16 2x{Dd<=29[#i]}++, [Rn!=PC, #off==4]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|0101|i:2|1|align:1|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld2.32 2x{Dd<=30[#i]}+, [Rn!=PC]" , "a32": "1111|01001|Vd'|10|Rn|Vd|1001|i:1|0|0|align:1|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld2.32 2x{Dd<=30[#i]}+, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|1001|i:1|0|0|align:1|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld2.32 2x{Dd<=30[#i]}+, [Rn!=PC, #off==8]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|1001|i:1|0|0|align:1|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld2.32 2x{Dd<=29[#i]}++, [Rn!=PC]" , "a32": "1111|01001|Vd'|10|Rn|Vd|1001|i:1|1|0|align:1|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld2.32 2x{Dd<=29[#i]}++, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|1001|i:1|1|0|align:1|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld2.32 2x{Dd<=29[#i]}++, [Rn!=PC, #off==8]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|1001|i:1|1|0|align:1|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld2r.8-32 2x{Dd<=30}+, [Rn!=PC]" , "a32": "1111|01001|Vd'|10|Rn|Vd|1101|sz|0|align:1|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld2r.8-32 2x{Dd<=30}+, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|1101|sz|0|align:1|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld2r.8-32 2x{Dd<=30}+, [Rn!=PC, #off==2<<sz]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|1101|sz|0|align:1|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld2r.8-32 2x{Dd<=29}++, [Rn!=PC]" , "a32": "1111|01001|Vd'|10|Rn|Vd|1101|sz|1|align:1|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld2r.8-32 2x{Dd<=29}++, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|1101|sz|1|align:1|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld2r.8-32 2x{Dd<=29}++, [Rn!=PC, #off==2<<sz]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|1101|sz|1|align:1|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld3.8-32 3x{Dd<=29}+, [Rn!=PC]" , "a32": "1111|01000|Vd'|10|Rn|Vd|0100|sz|0|align:1|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld3.8-32 3x{Dd<=29}+, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01000|Vd'|10|Rn|Vd|0100|sz|0|align:1|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld3.8-32 3x{Dd<=29}+, [Rn!=PC, #off==24]@" , "a32": "1111|01000|Vd'|10|Rn|Vd|0100|sz|0|align:1|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld3.8-32 3x{Dd<=27}++, [Rn!=PC]" , "a32": "1111|01000|Vd'|10|Rn|Vd|0101|sz|1|align:1|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld3.8-32 3x{Dd<=27}++, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01000|Vd'|10|Rn|Vd|0101|sz|1|align:1|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld3.8-32 3x{Dd<=27}++, [Rn!=PC, #off==24]@" , "a32": "1111|01000|Vd'|10|Rn|Vd|0101|sz|1|align:1|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld3.8 3x{Dd<=29[#i]}+, [Rn!=PC]" , "a32": "1111|01001|Vd'|10|Rn|Vd|0010|i:3|0|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld3.8 3x{Dd<=29[#i]}+, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|0010|i:3|0|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld3.8 3x{Dd<=29[#i]}+, [Rn!=PC, #off==3]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|0010|i:3|0|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld3.16 3x{Dd<=29[#i]}+, [Rn!=PC]" , "a32": "1111|01001|Vd'|10|Rn|Vd|0110|i:2|00|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld3.16 3x{Dd<=29[#i]}+, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|0110|i:2|00|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld3.16 3x{Dd<=29[#i]}+, [Rn!=PC, #off==6]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|0110|i:2|00|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld3.16 3x{Dd<=27[#i]}++, [Rn!=PC]" , "a32": "1111|01001|Vd'|10|Rn|Vd|0110|i:2|10|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld3.16 3x{Dd<=27[#i]}++, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|0110|i:2|10|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld3.16 3x{Dd<=27[#i]}++, [Rn!=PC, #off==6]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|0110|i:2|10|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld3.32 3x{Dd<=29[#i]}+, [Rn!=PC]" , "a32": "1111|01001|Vd'|10|Rn|Vd|1010|i:1|000|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld3.32 3x{Dd<=29[#i]}+, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|1010|i:1|000|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld3.32 3x{Dd<=29[#i]}+, [Rn!=PC, #off==12]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|1010|i:1|000|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld3.32 3x{Dd<=27[#i]}++, [Rn!=PC]" , "a32": "1111|01001|Vd'|10|Rn|Vd|1010|i:1|100|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld3.32 3x{Dd<=27[#i]}++, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|1010|i:1|100|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld3.32 3x{Dd<=27[#i]}++, [Rn!=PC, #off==12]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|1010|i:1|100|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld3r.8-32 3x{Dd<=29}+, [Rn!=PC]" , "a32": "1111|01001|Vd'|10|Rn|Vd|1110|sz|0|0|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld3r.8-32 3x{Dd<=29}+, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|1110|sz|0|0|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld3r.8-32 3x{Dd<=29}+, [Rn!=PC, #off==3<<sz]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|1110|sz|0|0|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld3r.8-32 3x{Dd<=27}++, [Rn!=PC]" , "a32": "1111|01001|Vd'|10|Rn|Vd|1110|sz|1|0|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld3r.8-32 3x{Dd<=27}++, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|1110|sz|1|0|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld3r.8-32 3x{Dd<=27}++, [Rn!=PC, #off==3<<sz]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|1110|sz|1|0|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld4.8-32 4x{Dd<=29}+, [Rn!=PC]" , "a32": "1111|01000|Vd'|10|Rn|Vd|0000|sz|align:2|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld4.8-32 4x{Dd<=29}+, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01000|Vd'|10|Rn|Vd|0000|sz|align:2|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld4.8-32 4x{Dd<=29}+, [Rn!=PC, #off==32]@" , "a32": "1111|01000|Vd'|10|Rn|Vd|0000|sz|align:2|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld4.8-32 4x{Dd<=27}++, [Rn!=PC]" , "a32": "1111|01000|Vd'|10|Rn|Vd|0001|sz|align:2|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld4.8-32 4x{Dd<=27}++, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01000|Vd'|10|Rn|Vd|0001|sz|align:2|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld4.8-32 4x{Dd<=27}++, [Rn!=PC, #off==32]@" , "a32": "1111|01000|Vd'|10|Rn|Vd|0001|sz|align:2|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld4.8 4x{Dd<=29[#i]}+, [Rn!=PC]" , "a32": "1111|01001|Vd'|10|Rn|Vd|0011|i:3|align:1|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld4.8 4x{Dd<=29[#i]}+, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|0011|i:3|align:1|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld4.8 4x{Dd<=29[#i]}+, [Rn!=PC, #off==4]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|0011|i:3|align:1|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld4.16 4x{Dd<=29[#i]}+, [Rn!=PC]" , "a32": "1111|01001|Vd'|10|Rn|Vd|0111|i:2|0|align:1|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld4.16 4x{Dd<=29[#i]}+, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|0111|i:2|0|align:1|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld4.16 4x{Dd<=29[#i]}+, [Rn!=PC, #off==8]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|0111|i:2|0|align:1|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld4.16 4x{Dd<=27[#i]}++, [Rn!=PC]" , "a32": "1111|01001|Vd'|10|Rn|Vd|0111|i:2|1|align:1|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld4.16 4x{Dd<=27[#i]}++, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|0111|i:2|1|align:1|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld4.16 4x{Dd<=27[#i]}++, [Rn!=PC, #off==8]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|0111|i:2|1|align:1|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld4.32 4x{Dd<=29[#i]}+, [Rn!=PC]" , "a32": "1111|01001|Vd'|10|Rn|Vd|1011|i:1|0|align:2|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld4.32 4x{Dd<=29[#i]}+, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|1011|i:1|0|align:2|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld4.32 4x{Dd<=29[#i]}+, [Rn!=PC, #off==16]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|1011|i:1|0|align:2|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld4.32 4x{Dd<=27[#i]}++, [Rn!=PC]" , "a32": "1111|01001|Vd'|10|Rn|Vd|1011|i:1|1|align:2|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld4.32 4x{Dd<=27[#i]}++, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|1011|i:1|1|align:2|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld4.32 4x{Dd<=27[#i]}++, [Rn!=PC, #off==16]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|1011|i:1|1|align:2|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld4r.8-32 4x{Dd<=28}+, [Rn!=PC]" , "a32": "1111|01001|Vd'|10|Rn|Vd|1111|sz|0|align:1|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld4r.8-32 4x{Dd<=28}+, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|1111|sz|0|align:1|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld4r.8-32 4x{Dd<=28}+, [Rn!=PC, #off==4<<sz]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|1111|sz|0|align:1|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld4r.8-32 4x{Dd<=25}++, [Rn!=PC]" , "a32": "1111|01001|Vd'|10|Rn|Vd|1111|sz|1|align:1|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld4r.8-32 4x{Dd<=25}++, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|1111|sz|1|align:1|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld4r.8-32 4x{Dd<=25}++, [Rn!=PC, #off==4<<sz]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|1111|sz|1|align:1|1101" , "ext": "ASIMD"},
|
|
{"inst": "vldmdb.32 [Rn]!, SdList" , "a32": "cond|11010|immVd[0]|11|Rn|immVd[4:1]|1010|immCount:8" , "ext": "ASIMD", "imm": "VecSListImm(SdList)"},
|
|
{"inst": "vldmdb.64 [Rn]!, DdList" , "a32": "cond|11010|immVd[4]|11|Rn|immVd[3:0]|1011|immCount:8" , "ext": "ASIMD", "imm": "VecDListImm(SdList)"},
|
|
{"inst": "vldmia.32 [Rn!=PC]{!}, SdList" , "a32": "cond|11001|immVd[0]|W1|Rn|immVd[4:1]|1010|immCount:8" , "ext": "ASIMD", "imm": "VecSListImm(SdList)"},
|
|
{"inst": "vldmia.64 [Rn!=PC]{!}, DdList" , "a32": "cond|11001|immVd[4]|W1|Rn|immVd[3:0]|1011|immCount:8" , "ext": "ASIMD", "imm": "VecDListImm(SdList)"},
|
|
{"inst": "vldmia.32 [Rn==PC], SdList" , "a32": "cond|11001|immVd[0]|01|Rn|immVd[4:1]|1010|immCount:8" , "ext": "ASIMD", "imm": "VecSListImm(SdList)"},
|
|
{"inst": "vldmia.64 [Rn==PC], DdList" , "a32": "cond|11001|immVd[4]|01|Rn|immVd[3:0]|1011|immCount:8" , "ext": "ASIMD", "imm": "VecDListImm(SdList)"},
|
|
{"inst": "vmax.f16 Dd, Dn, Dm" , "a32": "1111|00100|Vd'|01|Vn|Vd|1111|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vmax.f16 Vd, Vn, Vm" , "a32": "1111|00100|Vd'|01|Vn|Vd|1111|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vmax.f32 Dd, Dn, Dm" , "a32": "1111|00100|Vd'|00|Vn|Vd|1111|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vmax.f32 Vd, Vn, Vm" , "a32": "1111|00100|Vd'|00|Vn|Vd|1111|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vmax.x8-32 Dd, Dn, Dm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|0110|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vmax.x8-32 Vd, Vn, Vm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|0110|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vmaxnm.f16 Sd, Sn, Sm" , "a32": "1111|11101|'Vd|00|Vn|Vd|10|01|'Vn|0|'Vm|0|Vm" , "ext": "ARMv8+ FP16"},
|
|
{"inst": "vmaxnm.f32 Sd, Sn, Sm" , "a32": "1111|11101|'Vd|00|Vn|Vd|10|10|'Vn|0|'Vm|0|Vm" , "ext": "ARMv8+"},
|
|
{"inst": "vmaxnm.f64 Dd, Dn, Dm" , "a32": "1111|11101|Vd'|00|Vn|Vd|10|11|Vn'|0|Vm'|0|Vm" , "ext": "ARMv8+"},
|
|
{"inst": "vmaxnm.f16 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|01|Vn|Vd|1111|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vmaxnm.f16 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|01|Vn|Vd|1111|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vmaxnm.f32 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|00|Vn|Vd|1111|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vmaxnm.f32 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|00|Vn|Vd|1111|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vmin.f16 Dd, Dn, Dm" , "a32": "1111|00100|Vd'|11|Vn|Vd|1111|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vmin.f16 Vd, Vn, Vm" , "a32": "1111|00100|Vd'|11|Vn|Vd|1111|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vmin.f32 Dd, Dn, Dm" , "a32": "1111|00100|Vd'|10|Vn|Vd|1111|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vmin.f32 Vd, Vn, Vm" , "a32": "1111|00100|Vd'|10|Vn|Vd|1111|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vmin.x8-32 Dd, Dn, Dm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|0110|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vmin.x8-32 Vd, Vn, Vm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|0110|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vminnm.f16 Sd, Sn, Sm" , "a32": "1111|11101|'Vd|00|Vn|Vd|10|01|'Vn|1|'Vm|0|Vm" , "ext": "ARMv8+ FP16"},
|
|
{"inst": "vminnm.f32 Sd, Sn, Sm" , "a32": "1111|11101|'Vd|00|Vn|Vd|10|10|'Vn|1|'Vm|0|Vm" , "ext": "ARMv8+"},
|
|
{"inst": "vminnm.f64 Dd, Dn, Dm" , "a32": "1111|11101|Vd'|00|Vn|Vd|10|11|Vn'|1|Vm'|0|Vm" , "ext": "ARMv8+"},
|
|
{"inst": "vminnm.f16 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|11|Vn|Vd|1111|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vminnm.f16 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|11|Vn|Vd|1111|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vminnm.f32 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|10|Vn|Vd|1111|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vminnm.f32 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|10|Vn|Vd|1111|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vmla.f16 Dx, Dn, Dm" , "a32": "1111|00100|Vx'|01|Vn|Vx|1101|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vmla.f16 Vx, Vn, Vm" , "a32": "1111|00100|Vx'|01|Vn|Vx|1101|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vmla.f32 Dx, Dn, Dm" , "a32": "1111|00100|Vx'|00|Vn|Vx|1101|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vmla.f32 Vx, Vn, Vm" , "a32": "1111|00100|Vx'|00|Vn|Vx|1101|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vmla.x8-32 Dx, Dn, Dm" , "a32": "1111|00100|Vx'|sz|Vn|Vx|1001|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vmla.x8-32 Vx, Vn, Vm" , "a32": "1111|00100|Vx'|sz|Vn|Vx|1001|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vmla.f16 Dx, Dn, Dm<=07[#i]" , "a32": "1111|00101|Vx'|01|Vn|Vx|0001|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "FP16"},
|
|
{"inst": "vmla.f16 Vx, Vn, Dm<=07[#i]" , "a32": "1111|00111|Vx'|01|Vn|Vx|0001|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "FP16"},
|
|
{"inst": "vmla.f32 Dx, Dn, Dm<=15[#i]" , "a32": "1111|00101|Vx'|10|Vn|Vx|0001|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vmla.f32 Vx, Vn, Dm<=15[#i]" , "a32": "1111|00111|Vx'|10|Vn|Vx|0001|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vmla.x16 Dx, Dn, Dm<=07[#i]" , "a32": "1111|00101|Vx'|01|Vn|Vx|0000|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD"},
|
|
{"inst": "vmla.x16 Vx, Vn, Dm<=07[#i]" , "a32": "1111|00111|Vx'|01|Vn|Vx|0000|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD"},
|
|
{"inst": "vmla.x32 Dx, Dn, Dm<=15[#i]" , "a32": "1111|00101|Vx'|10|Vn|Vx|0000|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vmla.x32 Vx, Vn, Dm<=15[#i]" , "a32": "1111|00111|Vx'|10|Vn|Vx|0000|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vmlal.x8-32 Vx, Dn, Dm" , "a32": "1111|001U1|Vx'|sz|Vn|Vx|1000|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "widen"},
|
|
{"inst": "vmlal.x16 Vx, Dn, Dm<=07[#i]" , "a32": "1111|001U1|Vx'|01|Vn|Vx|0010|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD", "vecOp": "widen"},
|
|
{"inst": "vmlal.x32 Vx, Dn, Dm<=15[#i]" , "a32": "1111|001U1|Vx'|10|Vn|Vx|0010|Vn'|1|i:1|0|Vm" , "ext": "ASIMD", "vecOp": "widen"},
|
|
{"inst": "vmls.f16 Dx, Dn, Dm" , "a32": "1111|00100|Vx'|11|Vn|Vx|1101|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vmls.f16 Vx, Vn, Vm" , "a32": "1111|00100|Vx'|11|Vn|Vx|1101|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vmls.f32 Dx, Dn, Dm" , "a32": "1111|00100|Vx'|10|Vn|Vx|1101|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vmls.f32 Vx, Vn, Vm" , "a32": "1111|00100|Vx'|10|Vn|Vx|1101|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vmls.x8-32 Dx, Dn, Dm" , "a32": "1111|00110|Vx'|sz|Vn|Vx|1001|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vmls.x8-32 Vx, Vn, Vm" , "a32": "1111|00110|Vx'|sz|Vn|Vx|1001|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vmls.f16 Dx, Dn, Dm<=07[#i]" , "a32": "1111|00101|Vx'|01|Vn|Vx|0101|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD"},
|
|
{"inst": "vmls.f16 Vx, Vn, Dm<=07[#i]" , "a32": "1111|00111|Vx'|01|Vn|Vx|0101|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD"},
|
|
{"inst": "vmls.f32 Dx, Dn, Dm<=15[#i]" , "a32": "1111|00101|Vx'|10|Vn|Vx|0101|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vmls.f32 Vx, Vn, Dm<=15[#i]" , "a32": "1111|00111|Vx'|10|Vn|Vx|0101|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vmls.x16 Dx, Dn, Dm<=07[#i]" , "a32": "1111|00101|Vx'|01|Vn|Vx|0100|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD"},
|
|
{"inst": "vmls.x16 Vx, Vn, Dm<=07[#i]" , "a32": "1111|00111|Vx'|01|Vn|Vx|0100|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD"},
|
|
{"inst": "vmls.x32 Dx, Dn, Dm<=15[#i]" , "a32": "1111|00101|Vx'|10|Vn|Vx|0100|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vmls.x32 Vx, Vn, Dm<=15[#i]" , "a32": "1111|00111|Vx'|10|Vn|Vx|0100|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vmlsl.x8-32 Vx, Dn, Dm" , "a32": "1111|001U1|Vx'|sz|Vn|Vx|1010|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "widen"},
|
|
{"inst": "vmlsl.x16 Vx, Dn, Dm<=07[#i]" , "a32": "1111|001U1|Vx'|01|Vn|Vx|0110|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD", "vecOp": "widen"},
|
|
{"inst": "vmlsl.x32 Vx, Dn, Dm<=15[#i]" , "a32": "1111|001U1|Vx'|10|Vn|Vx|0110|Vn'|1|i:1|0|Vm" , "ext": "ASIMD", "vecOp": "widen"},
|
|
{"inst": "vmov Rd!=PC, Sn" , "a32": "cond|11100|0|01|Vn|Rd|1010|'Vn|00|1|0000" , "ext": "ASIMD"},
|
|
{"inst": "vmov Sd, Rn!=PC" , "a32": "cond|11100|0|00|Vd|Rn|1010|'Vd|00|1|0000" , "ext": "ASIMD"},
|
|
{"inst": "vmov Rd!=PC, Rd2!=PC, Ss!=31, Ss2+" , "a32": "cond|11000|1|01|Rd2|Rd|101|000|'Vs|1|Vs" , "ext": "ASIMD"},
|
|
{"inst": "vmov Sd!=31, Sd2+, Rs!=PC, Rs2!=PC" , "a32": "cond|11000|1|00|Rs2|Rs|101|000|'Vd|1|Vd" , "ext": "ASIMD"},
|
|
{"inst": "vmov Rd!=PC, Rd2!=PC, Ds" , "a32": "cond|11000|1|01|Rd2|Rd|1011|0|0|Vs'|1|Vs" , "ext": "ASIMD"},
|
|
{"inst": "vmov Dd, Rs!=PC, Rs2!=PC" , "a32": "cond|11000|1|00|Rs2|Rs|1011|0|0|Vd'|1|Vd" , "ext": "ASIMD"},
|
|
{"inst": "vmov.x8 Dd[#i], Rn!=PC" , "a32": "cond|11100|1|i:1|0|Vd|Rn|1011|Vd'|i:2|1|0000" , "ext": "ASIMD"},
|
|
{"inst": "vmov.x16 Dd[#i], Rn!=PC" , "a32": "cond|11100|0|i:1|0|Vd|Rn|1011|Vd'|i:1|110000" , "ext": "ASIMD"},
|
|
{"inst": "vmov.x32 Dd[#i], Rn!=PC" , "a32": "cond|11100|0|i:1|0|Vd|Rn|1011|Vd'|001|0000" , "ext": "ASIMD"},
|
|
{"inst": "vmov.x8 Rd!=PC, Dn[#i]" , "a32": "cond|1110U|1|i:1|1|Vn|Rd|1011|Vn'|i:2|1|0000" , "ext": "ASIMD"},
|
|
{"inst": "vmov.x16 Rd!=PC, Dn[#i]" , "a32": "cond|1110U|0|i:1|1|Vn|Rd|1011|Vn'|i:1|110000" , "ext": "ASIMD"},
|
|
{"inst": "vmov.x32 Rd!=PC, Dn[#i]" , "a32": "cond|11100|0|i:1|1|Vn|Rd|1011|Vn'|001|0000" , "ext": "ASIMD"},
|
|
{"inst": "vmov.any Dd, Dn" , "a32": "1111|00100|Vd'|10|Vn[3:0]|Vd|0001|Vn[4]|0|Vn[4]|1|Vn[3:0]", "ext": "ASIMD", "aliasOf": "vorr"},
|
|
{"inst": "vmov.any Vd, Vn" , "a32": "1111|00100|Vd'|10|Vn[3:0]|Vd|0001|Vn[4]|1|Vn[4]|1|Vn[3:0]", "ext": "ASIMD", "aliasOf": "vorr"},
|
|
{"inst": "vmov.x8-64 Dd, #immV" , "a32": "1111|001|imm:1|1|Vd'|000|imm:3|Vd|cmode:4|00|op|1|imm:4" , "ext": "ASIMD", "imm": "VecMovImm(sz, 0, immV)"},
|
|
{"inst": "vmov.x8-64 Vd, #immV" , "a32": "1111|001|imm:1|1|Vd'|000|imm:3|Vd|cmode:4|01|op|1|imm:4" , "ext": "ASIMD", "imm": "VecMovImm(sz, 0, immV)"},
|
|
{"inst": "vmovl.x8 Vd, Dn" , "a32": "1111|001U1|Vd'|00|1000|Vd|1010|0|0|Vn'|1|Vn" , "ext": "ASIMD", "vecOp": "widen"},
|
|
{"inst": "vmovl.x16 Vd, Dn" , "a32": "1111|001U1|Vd'|01|0000|Vd|1010|0|0|Vn'|1|Vn" , "ext": "ASIMD", "vecOp": "widen"},
|
|
{"inst": "vmovl.x32 Vd, Dn" , "a32": "1111|001U1|Vd'|10|0000|Vd|1010|0|0|Vn'|1|Vn" , "ext": "ASIMD", "vecOp": "widen"},
|
|
{"inst": "vmovn.x16-64 Dd, Vn" , "a32": "1111|00111|Vd'|11|szM1:2|10|Vd|0010|00|Vn'|0|Vn" , "ext": "ASIMD", "vecOp": "narrow"},
|
|
{"inst": "vmul.f16 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|01|Vn|Vd|1101|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vmul.f16 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|01|Vn|Vd|1101|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vmul.f32 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|00|Vn|Vd|1101|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vmul.f32 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|00|Vn|Vd|1101|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vmul.x8-32|p8 Dd, Dn, Dm" , "a32": "1111|001P0|Vd'|sz|Vn|Vd|1001|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vmul.x8-32|p8 Vd, Vn, Vm" , "a32": "1111|001P0|Vd'|sz|Vn|Vd|1001|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vmul.f32 Dd, Dn, Dm<=15[#i]" , "a32": "1111|00101|Vd'|10|Vn|Vd|1001|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vmul.f32 Vd, Vn, Dm<=15[#i]" , "a32": "1111|00111|Vd'|10|Vn|Vd|1001|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vmul.x16 Dd, Dn, Dm<=07[#i]" , "a32": "1111|00101|Vd'|01|Vn|Vd|1000|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD"},
|
|
{"inst": "vmul.x16 Vd, Vn, Dm<=07[#i]" , "a32": "1111|00111|Vd'|01|Vn|Vd|1000|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD"},
|
|
{"inst": "vmul.x32 Dd, Dn, Dm<=15[#i]" , "a32": "1111|00101|Vd'|10|Vn|Vd|1000|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vmul.x32 Vd, Vn, Dm<=15[#i]" , "a32": "1111|00111|Vd'|10|Vn|Vd|1000|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vmull.x8-32|p8 Vd, Dn, Dm" , "a32": "1111|001U1|Vd'|sz|Vn|Vd|11P0|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "widen"},
|
|
{"inst": "vmull.p64 Vd, Dn, Dm" , "a32": "1111|00101|Vd'|10|Vn|Vd|11P0|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "widen"},
|
|
{"inst": "vmull.x16 Vd, Dn, Dm<=07[#i]" , "a32": "1111|001U1|Vd'|01|Vn|Vd|1010|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD", "vecOp": "widen"},
|
|
{"inst": "vmull.x32 Vd, Dn, Dm<=15[#i]" , "a32": "1111|001U1|Vd'|10|Vn|Vd|1010|Vn'|1|i:1|0|Vm" , "ext": "ASIMD", "vecOp": "widen"},
|
|
{"inst": "vmvn.any Dd, #immV" , "a32": "1111|001|imm:1|1|Vd'|000|imm:3|Vd|cmode:4|00|op|1|imm:4" , "ext": "ASIMD", "imm": "VecMovImm(sz, 1, immV)"},
|
|
{"inst": "vmvn.any Vd, #immV" , "a32": "1111|001|imm:1|1|Vd'|000|imm:3|Vd|cmode:4|01|op|1|imm:4" , "ext": "ASIMD", "imm": "VecMovImm(sz, 1, immV)"},
|
|
{"inst": "vmvn.any Dd, Dn" , "a32": "1111|00111|Vd'|11|0000|Vd|0101|10|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vmvn.any Vd, Vn" , "a32": "1111|00111|Vd'|11|0000|Vd|0101|11|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vneg.f16 Dd, Dn" , "a32": "1111|00111|Vd'|11|01|01|Vd|0111|10|Vn'|0|Vn" , "ext": "ASIMD FP16"},
|
|
{"inst": "vneg.f16 Vd, Vn" , "a32": "1111|00111|Vd'|11|01|01|Vd|0111|11|Vn'|0|Vn" , "ext": "ASIMD FP16"},
|
|
{"inst": "vneg.f32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|01|Vd|0111|10|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vneg.f32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|01|Vd|0111|11|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vneg.s8-32 Dd, Dn" , "a32": "1111|00111|Vd'|11|sz|01|Vd|0011|10|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vneg.s8-32 Vd, Vn" , "a32": "1111|00111|Vd'|11|sz|01|Vd|0011|11|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vorn.x16-64 Dx, #immV" , "a32": "1111|001|imm:1|1|Vx'|000|imm:3|Vx|cmode:4|0001|imm:4" , "ext": "ASIMD", "imm": "VecBicOrrImm(sz, 1, immV)", "pseudoOf": "vorr"},
|
|
{"inst": "vorn.x16-64 Vx, #immV" , "a32": "1111|001|imm:1|1|Vx'|000|imm:3|Vx|cmode:4|0101|imm:4" , "ext": "ASIMD", "imm": "VecBicOrrImm(sz, 1, immV)", "pseudoOf": "vorr"},
|
|
{"inst": "vorn.any Dd, Dn, Dm" , "a32": "1111|00100|Vd'|11|Vn|Vd|0001|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vorn.any Vd, Vn, Vm" , "a32": "1111|00100|Vd'|11|Vn|Vd|0001|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vorr.x16-64 Dx, #immV" , "a32": "1111|001|imm:1|1|Vx'|000|imm:3|Vx|cmode:4|0001|imm:4" , "ext": "ASIMD", "imm": "VecBicOrrImm(sz, 0, immV)"},
|
|
{"inst": "vorr.x16-64 Vx, #immV" , "a32": "1111|001|imm:1|1|Vx'|000|imm:3|Vx|cmode:4|0101|imm:4" , "ext": "ASIMD", "imm": "VecBicOrrImm(sz, 0, immV)"},
|
|
{"inst": "vorr.any Dd, Dn, Dm" , "a32": "1111|00100|Vd'|10|Vn|Vd|0001|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vorr.any Vd, Vn, Vm" , "a32": "1111|00100|Vd'|10|Vn|Vd|0001|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vpadal.x8-32 Dx, Dn" , "a32": "1111|00111|Vx'|11|sz|00|Vx|0110|U|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vpadal.x8-32 Vx, Vn" , "a32": "1111|00111|Vx'|11|sz|00|Vx|0110|U|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vpadd.f16 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|01|Vn|Vd|1101|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vpadd.f32 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|00|Vn|Vd|1101|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vpaddl.x8-32 Dd, Dn" , "a32": "1111|00111|Vd'|11|sz|00|Vd|0010|U|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vpaddl.x8-32 Vd, Vn" , "a32": "1111|00111|Vd'|11|sz|00|Vd|0010|U|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vpmax.f16 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|01|Vn|Vd|1111|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vpmax.f32 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|00|Vn|Vd|1111|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vpmax.x8-32 Dd, Dn, Dm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|1010|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vpmin.f16 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|11|Vn|Vd|1111|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vpmin.f32 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|10|Vn|Vd|1111|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vpmin.x8-32 Dd, Dn, Dm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|1010|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vpop.32 SdList" , "a32": "cond|11001|immVd[0]|11|1101|immVd[4:1]|1010|immCount:8" , "ext": "ASIMD", "imm": "VecSListImm(SdList)"},
|
|
{"inst": "vpop.64 DdList" , "a32": "cond|11001|immVd[4]|11|1101|immVd[3:0]|1011|immCount:8" , "ext": "ASIMD", "imm": "VecDListImm(SdList)"},
|
|
{"inst": "vpush.32 SdList" , "a32": "cond|11010|immVd[0]|10|1101|immVd[4:1]|1010|immCount:8" , "ext": "ASIMD", "imm": "VecSListImm(SdList)"},
|
|
{"inst": "vpush.64 DdList" , "a32": "cond|11010|immVd[4]|10|1101|immVd[3:0]|1011|immCount:8" , "ext": "ASIMD", "imm": "VecDListImm(SdList)"},
|
|
{"inst": "vqabs.s8-32 Dd, Dn" , "a32": "1111|00111|Vd'|11|sz|00|Vd|0111|0|0|Vn'|0|Vn" , "ext": "ASIMD", "fpcsr": "Q=X"},
|
|
{"inst": "vqabs.s8-32 Vd, Vn" , "a32": "1111|00111|Vd'|11|sz|00|Vd|0111|0|1|Vn'|0|Vn" , "ext": "ASIMD", "fpcsr": "Q=X"},
|
|
{"inst": "vqadd.x8-64 Dd, Dn, Dm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|0000|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"},
|
|
{"inst": "vqadd.x8-64 Vd, Vn, Vm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|0000|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"},
|
|
{"inst": "vqdmlal.s16-32 Vx, Dn, Dm" , "a32": "1111|00101|Vx'|sz|Vn|Vx|1001|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "widen"},
|
|
{"inst": "vqdmlal.s16 Vx, Dn, Dm<=07[#i]" , "a32": "1111|00101|Vx'|01|Vn|Vx|0011|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "widen"},
|
|
{"inst": "vqdmlal.s32 Vx, Dn, Dm<=15[#i]" , "a32": "1111|00101|Vx'|10|Vn|Vx|0011|Vn'|1|i:1|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "widen"},
|
|
{"inst": "vqdmlsl.s16-32 Vx, Dn, Dm" , "a32": "1111|00101|Vx'|sz|Vn|Vx|1011|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "widen"},
|
|
{"inst": "vqdmlsl.s16 Vx, Dn, Dm<=07[#i]" , "a32": "1111|00101|Vx'|01|Vn|Vx|0111|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "widen"},
|
|
{"inst": "vqdmlsl.s32 Vx, Dn, Dm<=15[#i]" , "a32": "1111|00101|Vx'|10|Vn|Vx|0111|Vn'|1|i:1|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "widen"},
|
|
{"inst": "vqdmulh.s16-32 Dd, Dn, Dm" , "a32": "1111|00100|Vd'|sz|Vn|Vd|1011|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"},
|
|
{"inst": "vqdmulh.s16-32 Vd, Vn, Vm" , "a32": "1111|00100|Vd'|sz|Vn|Vd|1011|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"},
|
|
{"inst": "vqdmulh.s16 Dd, Dn, Dm<=07[#i]" , "a32": "1111|00101|Vd'|01|Vn|Vd|1100|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD", "fpcsr": "Q=X"},
|
|
{"inst": "vqdmulh.s16 Vd, Vn, Dm<=07[#i]" , "a32": "1111|00111|Vd'|01|Vn|Vd|1100|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD", "fpcsr": "Q=X"},
|
|
{"inst": "vqdmulh.s32 Dd, Dn, Dm<=15[#i]" , "a32": "1111|00101|Vd'|10|Vn|Vd|1100|Vn'|1|i:1|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"},
|
|
{"inst": "vqdmulh.s32 Vd, Vn, Dm<=15[#i]" , "a32": "1111|00111|Vd'|10|Vn|Vd|1100|Vn'|1|i:1|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"},
|
|
{"inst": "vqdmull.s16-32 Vd, Dn, Dm" , "a32": "1111|00101|Vd'|sz|Vn|Vd|1101|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "widen"},
|
|
{"inst": "vqdmull.s16 Vd, Dn, Dm<=07[#i]" , "a32": "1111|00101|Vd'|01|Vn|Vd|1011|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "widen"},
|
|
{"inst": "vqdmull.s32 Vd, Dn, Dm<=15[#i]" , "a32": "1111|00101|Vd'|10|Vn|Vd|1011|Vn'|1|i:1|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "widen"},
|
|
{"inst": "vqmovn.x16-64 Dd, Vn" , "a32": "1111|00111|Vd'|11|szM1:2|10|Vd|0010|1|U|Vn'|0|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "narrow"},
|
|
{"inst": "vqmovun.s16-64 Dd, Vn" , "a32": "1111|00111|Vd'|11|szM1:2|10|Vd|0010|0|1|Vn'|0|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "narrow"},
|
|
{"inst": "vqneg.s8-32 Dd, Dn" , "a32": "1111|00111|Vd'|11|sz|00|Vd|0111|1|0|Vn'|0|Vn" , "ext": "ASIMD", "fpcsr": "Q=X"},
|
|
{"inst": "vqneg.s8-32 Vd, Vn" , "a32": "1111|00111|Vd'|11|sz|00|Vd|0111|1|1|Vn'|0|Vn" , "ext": "ASIMD", "fpcsr": "Q=X"},
|
|
{"inst": "vqrdmulh.s16-32 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|sz|Vn|Vd|1011|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"},
|
|
{"inst": "vqrdmulh.s16-32 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|sz|Vn|Vd|1011|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"},
|
|
{"inst": "vqrdmulh.s16 Dd, Dn, Dm<=07[#i]" , "a32": "1111|00101|Vd'|01|Vn|Vd|1101|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD", "fpcsr": "Q=X"},
|
|
{"inst": "vqrdmulh.s16 Vd, Vn, Dm<=07[#i]" , "a32": "1111|00111|Vd'|01|Vn|Vd|1101|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD", "fpcsr": "Q=X"},
|
|
{"inst": "vqrdmulh.s32 Dd, Dn, Dm<=15[#i]" , "a32": "1111|00101|Vd'|10|Vn|Vd|1101|Vn'|1|i:1|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"},
|
|
{"inst": "vqrdmulh.s32 Vd, Vn, Dm<=15[#i]" , "a32": "1111|00111|Vd'|10|Vn|Vd|1101|Vn'|1|i:1|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"},
|
|
{"inst": "vqrshl.x8-64 Dd, Dn, Dm" , "a32": "1111|001U0|Vd'|sz|Vm|Vd|0101|Vm'|0|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X"},
|
|
{"inst": "vqrshl.x8-64 Vd, Vn, Vm" , "a32": "1111|001U0|Vd'|sz|Vm|Vd|0101|Vm'|1|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X"},
|
|
{"inst": "vqrshrn.x16-64 Dd, Vn, #zero" , "a32": "1111|00111|Vd'|11|szM1:2|10|Vd|0010|1U|Vn'|0|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "narrow"},
|
|
{"inst": "vqrshrn.x16-64 Dd, Vn, #n" , "a32": "1111|001U1|Vd'|imm:6|Vd|1001|01|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "imm": "VecShiftNarrowImm(sz, n)", "vecOp": "narrow"},
|
|
{"inst": "vqrshrun.s16-64 Dd, Vn, #zero" , "a32": "1111|00111|Vd'|11|szM1:2|10|Vd|0010|01|Vn'|0|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "narrow"},
|
|
{"inst": "vqrshrun.s16-64 Dd, Vn, #n" , "a32": "1111|00111|Vd'|imm:6|Vd|1000|01|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "imm": "VecShiftNarrowImm(sz, n)", "vecOp": "narrow"},
|
|
{"inst": "vqshl.x8-64 Dd, Dn, Dm" , "a32": "1111|001U0|Vd'|sz|Vm|Vd|0100|Vm'|0|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X"},
|
|
{"inst": "vqshl.x8-64 Vd, Vn, Vm" , "a32": "1111|001U0|Vd'|sz|Vm|Vd|0100|Vm'|1|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X"},
|
|
{"inst": "vqshl.x8-64 Dd, Dn, #n" , "a32": "1111|001U1|Vd'|imm[5:0]|Vd|0111|imm[6]|0|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "imm": "VecShiftPImm(sz, n)"},
|
|
{"inst": "vqshl.x8-64 Vd, Vn, #n" , "a32": "1111|001U1|Vd'|imm[5:0]|Vd|0111|imm[6]|1|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "imm": "VecShiftPImm(sz, n)"},
|
|
{"inst": "vqshlu.s8-64 Dd, Dn, #n" , "a32": "1111|00111|Vd'|imm[5:0]|Vd|0110|imm[6]|0|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "imm": "VecShiftPImm(sz, n)"},
|
|
{"inst": "vqshlu.s8-64 Vd, Vn, #n" , "a32": "1111|00111|Vd'|imm[5:0]|Vd|0110|imm[6]|1|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "imm": "VecShiftPImm(sz, n)"},
|
|
{"inst": "vqshrn.x16-64 Dd, Vn, #zero" , "a32": "1111|00111|Vd'|11|szM1:2|10|Vd|0010|1U|Vn'|0|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "narrow"},
|
|
{"inst": "vqshrn.x16-64 Dd, Vn, #n" , "a32": "1111|001U1|Vd'|imm:6|Vd|1001|0|0|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "imm": "VecShiftNarrowImm(sz, n)", "vecOp": "narrow"},
|
|
{"inst": "vqshrun.s16-64 Dd, Vn, #zero" , "a32": "1111|00111|Vd'|11|szM1:2|10|Vd|0010|01|Vn'|0|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "narrow"},
|
|
{"inst": "vqshrun.s16-64 Dd, Vn, #n" , "a32": "1111|00111|Vd'|imm:6|Vd|1000|0|0|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "imm": "VecShiftNarrowImm(sz, n)", "vecOp": "narrow"},
|
|
{"inst": "vqsub.x8-64 Dd, Dn, Dm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|0010|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"},
|
|
{"inst": "vqsub.x8-64 Vd, Vn, Vm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|0010|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"},
|
|
{"inst": "vraddhn.x16-64 Dd, Vn, Vm" , "a32": "1111|00111|Vd'|szM1:2|Vn|Vd|0100|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "narrow"},
|
|
{"inst": "vrecpe.f16 Dd, Dn" , "a32": "1111|00111|Vd'|11|01|11|Vd|0101|0|0|Vn'|0|Vn" , "ext": "ASIMD FP16"},
|
|
{"inst": "vrecpe.f16 Vd, Vn" , "a32": "1111|00111|Vd'|11|01|11|Vd|0101|0|1|Vn'|0|Vn" , "ext": "ASIMD FP16"},
|
|
{"inst": "vrecpe.f32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|11|Vd|0101|0|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vrecpe.f32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|11|Vd|0101|0|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vrecpe.u32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|11|Vd|0100|0|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vrecpe.u32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|11|Vd|0100|0|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vrecps.f16 Dd, Dn, Dm" , "a32": "1111|00100|Vd'|01|Vn|Vd|1111|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vrecps.f16 Vd, Vn, Vm" , "a32": "1111|00100|Vd'|01|Vn|Vd|1111|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vrecps.f32 Dd, Dn, Dm" , "a32": "1111|00100|Vd'|00|Vn|Vd|1111|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vrecps.f32 Vd, Vn, Vm" , "a32": "1111|00100|Vd'|00|Vn|Vd|1111|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vrev16.x8 Dd, Dn" , "a32": "1111|00111|Vd'|11|00|00|Vd|0001|0|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vrev16.x8 Vd, Vn" , "a32": "1111|00111|Vd'|11|00|00|Vd|0001|0|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vrev32.x8-16 Dd, Dn" , "a32": "1111|00111|Vd'|11|sz|00|Vd|0000|1|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vrev32.x8-16 Vd, Vn" , "a32": "1111|00111|Vd'|11|sz|00|Vd|0000|1|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vrev64.x8-32 Dd, Dn" , "a32": "1111|00111|Vd'|11|sz|00|Vd|0000|0|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vrev64.x8-32 Vd, Vn" , "a32": "1111|00111|Vd'|11|sz|00|Vd|0000|0|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vrhadd.x8-32 Dd, Dn, Dm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|0001|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vrhadd.x8-32 Vd, Vn, Vm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|0001|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vrinta.f16 Sd, Sn" , "a32": "1111|11101|'Vd|11|10|00|Vd|10|01|01|'Vn|0|Vn" , "ext": "ARMv8+ FP16"},
|
|
{"inst": "vrinta.f32 Sd, Sn" , "a32": "1111|11101|'Vd|11|10|00|Vd|10|10|01|'Vn|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vrinta.f64 Dd, Dn" , "a32": "1111|11101|Vd'|11|10|00|Vd|10|11|01|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vrinta.f16 Dd, Dn" , "a32": "1111|00111|Vd'|11|01|10|Vd|01|01|00|Vn'|0|Vn" , "ext": "ARMv8+ FP16"},
|
|
{"inst": "vrinta.f16 Vd, Vn" , "a32": "1111|00111|Vd'|11|01|10|Vd|01|01|01|Vn'|0|Vn" , "ext": "ARMv8+ FP16"},
|
|
{"inst": "vrinta.f32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|10|Vd|01|01|00|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vrinta.f32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|10|Vd|01|01|01|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vrintm.f16 Sd, Sn" , "a32": "1111|11101|'Vd|11|10|11|Vd|10|01|01|'Vn|0|Vn" , "ext": "ARMv8+ FP16"},
|
|
{"inst": "vrintm.f32 Sd, Sn" , "a32": "1111|11101|'Vd|11|10|11|Vd|10|10|01|'Vn|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vrintm.f64 Dd, Dn" , "a32": "1111|11101|Vd'|11|10|11|Vd|10|11|01|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vrintm.f16 Dd, Dn" , "a32": "1111|00111|Vd'|11|01|10|Vd|01|10|10|Vn'|0|Vn" , "ext": "ARMv8+ FP16"},
|
|
{"inst": "vrintm.f16 Vd, Vn" , "a32": "1111|00111|Vd'|11|01|10|Vd|01|10|11|Vn'|0|Vn" , "ext": "ARMv8+ FP16"},
|
|
{"inst": "vrintm.f32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|10|Vd|01|10|10|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vrintm.f32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|10|Vd|01|10|11|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vrintn.f16 Sd, Sn" , "a32": "1111|11101|'Vd|11|10|01|Vd|10|01|01|'Vn|0|Vn" , "ext": "ARMv8+ FP16"},
|
|
{"inst": "vrintn.f32 Sd, Sn" , "a32": "1111|11101|'Vd|11|10|01|Vd|10|10|01|'Vn|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vrintn.f64 Dd, Dn" , "a32": "1111|11101|Vd'|11|10|01|Vd|10|11|01|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vrintn.f16 Dd, Dn" , "a32": "1111|00111|Vd'|11|01|10|Vd|01|00|00|Vn'|0|Vn" , "ext": "ARMv8+ FP16"},
|
|
{"inst": "vrintn.f16 Vd, Vn" , "a32": "1111|00111|Vd'|11|01|10|Vd|01|00|01|Vn'|0|Vn" , "ext": "ARMv8+ FP16"},
|
|
{"inst": "vrintn.f32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|10|Vd|01|00|00|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vrintn.f32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|10|Vd|01|00|01|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vrintp.f16 Sd, Sn" , "a32": "1111|11101|'Vd|11|10|10|Vd|10|01|01|'Vn|0|Vn" , "ext": "ARMv8+ FP16"},
|
|
{"inst": "vrintp.f32 Sd, Sn" , "a32": "1111|11101|'Vd|11|10|10|Vd|10|10|01|'Vn|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vrintp.f64 Dd, Dn" , "a32": "1111|11101|Vd'|11|10|10|Vd|10|11|01|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vrintp.f16 Dd, Dn" , "a32": "1111|00111|Vd'|11|01|10|Vd|01|11|10|Vn'|0|Vn" , "ext": "ARMv8+ FP16"},
|
|
{"inst": "vrintp.f16 Vd, Vn" , "a32": "1111|00111|Vd'|11|01|10|Vd|01|11|11|Vn'|0|Vn" , "ext": "ARMv8+ FP16"},
|
|
{"inst": "vrintp.f32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|10|Vd|01|11|10|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vrintp.f32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|10|Vd|01|11|11|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vrintr.f16 Sd, Sn" , "a32": "1110|11101|'Vd|11|01|10|Vd|10|01|01|'Vn|0|Vn" , "ext": "ARMv8+ FP16"},
|
|
{"inst": "vrintr.f32 Sd, Sn" , "a32": "cond|11101|'Vd|11|01|10|Vd|10|10|01|'Vn|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vrintr.f64 Dd, Dn" , "a32": "cond|11101|Vd'|11|01|10|Vd|10|11|01|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vrintx.f16 Sd, Sn" , "a32": "1110|11101|'Vd|11|01|11|Vd|10|01|01|'Vn|0|Vn" , "ext": "ARMv8+ FP16"},
|
|
{"inst": "vrintx.f32 Sd, Sn" , "a32": "cond|11101|'Vd|11|01|11|Vd|10|10|01|'Vn|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vrintx.f64 Dd, Dn" , "a32": "cond|11101|Vd'|11|01|11|Vd|10|11|01|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vrintx.f16 Dd, Dn" , "a32": "1111|00111|Vd'|11|01|10|Vd|01|00|10|Vn'|0|Vn" , "ext": "ARMv8+ FP16"},
|
|
{"inst": "vrintx.f16 Vd, Vn" , "a32": "1111|00111|Vd'|11|01|10|Vd|01|00|11|Vn'|0|Vn" , "ext": "ARMv8+ FP16"},
|
|
{"inst": "vrintx.f32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|10|Vd|01|00|10|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vrintx.f32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|10|Vd|01|00|11|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vrintz.f16 Sd, Sn" , "a32": "1110|11101|'Vd|11|01|10|Vd|10|01|11|'Vn|0|Vn" , "ext": "ARMv8+ FP16"},
|
|
{"inst": "vrintz.f32 Sd, Sn" , "a32": "cond|11101|'Vd|11|01|10|Vd|10|10|11|'Vn|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vrintz.f64 Dd, Dn" , "a32": "cond|11101|Vd'|11|01|10|Vd|10|11|11|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vrintz.f16 Dd, Dn" , "a32": "1111|00111|Vd'|11|01|10|Vd|01|01|10|Vn'|0|Vn" , "ext": "ARMv8+ FP16"},
|
|
{"inst": "vrintz.f16 Vd, Vn" , "a32": "1111|00111|Vd'|11|01|10|Vd|01|01|11|Vn'|0|Vn" , "ext": "ARMv8+ FP16"},
|
|
{"inst": "vrintz.f32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|10|Vd|01|01|10|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vrintz.f32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|10|Vd|01|01|11|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vrshl.x8-64 Dd, Dn, Dm" , "a32": "1111|001U0|Vd'|sz|Vm|Vd|0101|Vm'|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vrshl.x8-64 Vd, Vn, Vm" , "a32": "1111|001U0|Vd'|sz|Vm|Vd|0101|Vm'|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vrshr.x8-32 Dd, Dn, #zero" , "a32": "1111|00100|Vd'|10|Vn[3:0]|Vd|0001|Vn[4]|0|Vn[4]|1|Vn[3:0]", "ext": "ASIMD", "pseudoOf": "vorr"},
|
|
{"inst": "vrshr.x8-32 Vd, Vn, #zero" , "a32": "1111|00100|Vd'|10|Vn[3:0]|Vd|0001|Vn[4]|1|Vn[4]|1|Vn[3:0]", "ext": "ASIMD", "pseudoOf": "vorr"},
|
|
{"inst": "vrshr.x8-32 Dd, Dn, #n" , "a32": "1111|001U1|Vd'|imm:6|Vd|0010|0|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNImm(sz, n)"},
|
|
{"inst": "vrshr.x8-32 Vd, Vn, #n" , "a32": "1111|001U1|Vd'|imm:6|Vd|0010|0|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNImm(sz, n)"},
|
|
{"inst": "vrshrn.x16-64 Dd, Vn, #zero" , "a32": "1111|00111|Vd'|11|sz|10|Vd|0010|00|Vn'|1|Vn" , "ext": "ASIMD", "vecOp": "narrow", "pseudoOf": "vmovn"},
|
|
{"inst": "vrshrn.x16-64 Dd, Vn, #n" , "a32": "1111|00101|Vd'|imm:6|Vd|1000|0|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNarrowImm(sz, n)", "vecOp": "narrow"},
|
|
{"inst": "vrsqrte.f16 Dd, Dn" , "a32": "1111|00111|Vd'|11|01|11|Vd|01|01|10|Vn'|0|Vn" , "ext": "ASIMD FP16"},
|
|
{"inst": "vrsqrte.f16 Vd, Vn" , "a32": "1111|00111|Vd'|11|01|11|Vd|01|01|11|Vn'|0|Vn" , "ext": "ASIMD FP16"},
|
|
{"inst": "vrsqrte.f32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|11|Vd|01|01|10|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vrsqrte.f32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|11|Vd|01|01|11|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vrsqrte.u32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|11|Vd|01|00|10|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vrsqrte.u32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|11|Vd|01|00|11|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vrsqrts.f16 Dd, Dn, Dm" , "a32": "1111|00100|Vd'|11|Vn|Vd|1111|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vrsqrts.f16 Vd, Vn, Vm" , "a32": "1111|00100|Vd'|11|Vn|Vd|1111|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vrsqrts.f32 Dd, Dn, Dm" , "a32": "1111|00100|Vd'|10|Vn|Vd|1111|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vrsqrts.f32 Vd, Vn, Vm" , "a32": "1111|00100|Vd'|10|Vn|Vd|1111|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vrsra.x8-64 Dx, Dn, #n" , "a32": "1111|001U1|Vx'|imm[5:0]|Vx|0011|imm[6]|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNImm(sz, n)"},
|
|
{"inst": "vrsra.x8-64 Vx, Vn, #n" , "a32": "1111|001U1|Vx'|imm[5:0]|Vx|0011|imm[6]|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNImm(sz, n)"},
|
|
{"inst": "vrsubhn.x16-64 Dd, Vn, Vm" , "a32": "1111|00111|Vd'|szM1:2|Vn|Vd|0110|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "narrow"},
|
|
{"inst": "vseleq.f16 Sd, Sn, Sm" , "a32": "1111|11100|'Vd|00|Vn|Vd|10|01|'Vn|0|'Vm|0|Vm" , "ext": "ARMv8+ FP16"},
|
|
{"inst": "vseleq.f32 Sd, Sn, Sm" , "a32": "1111|11100|'Vd|00|Vn|Vd|10|10|'Vn|0|'Vm|0|Vm" , "ext": "ARMv8+"},
|
|
{"inst": "vseleq.f64 Dd, Dn, Dm" , "a32": "1111|11100|Vd'|00|Vn|Vd|10|11|Vn'|0|Vm'|0|Vm" , "ext": "ARMv8+"},
|
|
{"inst": "vselge.f16 Sd, Sn, Sm" , "a32": "1111|11100|'Vd|10|Vn|Vd|10|01|'Vn|0|'Vm|0|Vm" , "ext": "ARMv8+ FP16"},
|
|
{"inst": "vselge.f32 Sd, Sn, Sm" , "a32": "1111|11100|'Vd|10|Vn|Vd|10|10|'Vn|0|'Vm|0|Vm" , "ext": "ARMv8+"},
|
|
{"inst": "vselge.f64 Dd, Dn, Dm" , "a32": "1111|11100|Vd'|10|Vn|Vd|10|11|Vn'|0|Vm'|0|Vm" , "ext": "ARMv8+"},
|
|
{"inst": "vselgt.f16 Sd, Sn, Sm" , "a32": "1111|11100|'Vd|11|Vn|Vd|10|01|'Vn|0|'Vm|0|Vm" , "ext": "ARMv8+ FP16"},
|
|
{"inst": "vselgt.f32 Sd, Sn, Sm" , "a32": "1111|11100|'Vd|11|Vn|Vd|10|10|'Vn|0|'Vm|0|Vm" , "ext": "ARMv8+"},
|
|
{"inst": "vselgt.f64 Dd, Dn, Dm" , "a32": "1111|11100|Vd'|11|Vn|Vd|10|11|Vn'|0|Vm'|0|Vm" , "ext": "ARMv8+"},
|
|
{"inst": "vselvs.f16 Sd, Sn, Sm" , "a32": "1111|11100|'Vd|01|Vn|Vd|10|01|'Vn|0|'Vm|0|Vm" , "ext": "ARMv8+ FP16"},
|
|
{"inst": "vselvs.f32 Sd, Sn, Sm" , "a32": "1111|11100|'Vd|01|Vn|Vd|10|10|'Vn|0|'Vm|0|Vm" , "ext": "ARMv8+"},
|
|
{"inst": "vselvs.f64 Dd, Dn, Dm" , "a32": "1111|11100|Vd'|01|Vn|Vd|10|11|Vn'|0|Vm'|0|Vm" , "ext": "ARMv8+"},
|
|
{"inst": "vshl.x8-64 Dd, Dn, Dm" , "a32": "1111|001U0|Vd'|sz|Vm|Vd|0100|Vm'|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vshl.x8-64 Vd, Vn, Vm" , "a32": "1111|001U0|Vd'|sz|Vm|Vd|0100|Vm'|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vshl.x8-64 Dd, Dn, #n" , "a32": "1111|00101|Vd'|imm[5:0]|Vd|0101|imm[6]|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftPImm(sz, n)"},
|
|
{"inst": "vshl.x8-64 Vd, Vn, #n" , "a32": "1111|00101|Vd'|imm[5:0]|Vd|0101|imm[6]|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftPImm(sz, n)"},
|
|
{"inst": "vshll.x8-32 Vd, Dn, #n" , "a32": "1111|001U1|Vd'|imm[5:0]|Vd|1010|0|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftPImm(sz, n)", "vecOp": "widen"},
|
|
{"inst": "vshr.x8-64 Dd, Dn, #zero" , "a32": "1111|00100|Vd'|10|Vn[3:0]|Vd|0001|Vn[4]|0|Vn[4]|1|Vn[3:0]", "ext": "ASIMD", "pseudoOf": "vorr"},
|
|
{"inst": "vshr.x8-64 Vd, Vn, #zero" , "a32": "1111|00100|Vd'|10|Vn[3:0]|Vd|0001|Vn[4]|1|Vn[4]|1|Vn[3:0]", "ext": "ASIMD", "pseudoOf": "vorr"},
|
|
{"inst": "vshr.x8-64 Dd, Dn, #n" , "a32": "1111|001U1|Vd'|imm[5:0]|Vd|0000|imm[6]|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNImm(sz, n)"},
|
|
{"inst": "vshr.x8-64 Vd, Vn, #n" , "a32": "1111|001U1|Vd'|imm[5:0]|Vd|0000|imm[6]|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNImm(sz, n)"},
|
|
{"inst": "vshrn.x16-64 Dd, Vn, #zero" , "a32": "1111|11111|Vd'|11|sz|10|Vd|0010|00|Vn'|1|Vn" , "ext": "ASIMD", "vecOp": "narrow"},
|
|
{"inst": "vshrn.x16-64 Dd, Vn, #n" , "a32": "1111|00101|Vd'|imm:6|Vd|1000|00|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNarrowImm(sz, n)", "vecOp": "narrow"},
|
|
{"inst": "vsli.x8-64 Dx, Dn, #n" , "a32": "1111|00111|Vx'|imm[5:0]|Vx|0101|imm[6]|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftPImm(sz, n)"},
|
|
{"inst": "vsli.x8-64 Vx, Vn, #n" , "a32": "1111|00111|Vx'|imm[5:0]|Vx|0101|imm[6]|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftPImm(sz, n)"},
|
|
{"inst": "vsra.x8-64 Dx, Dn, #n" , "a32": "1111|001U1|Vx'|imm[5:0]|Vx|0001|imm[6]|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNImm(sz, n)"},
|
|
{"inst": "vsra.x8-64 Vx, Vn, #n" , "a32": "1111|001U1|Vx'|imm[5:0]|Vx|0001|imm[6]|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNImm(sz, n)"},
|
|
{"inst": "vsri.x8-64 Dx, Dn, #n" , "a32": "1111|00111|Vx'|imm[5:0]|Vx|0100|imm[6]|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNImm(sz, n)"},
|
|
{"inst": "vsri.x8-64 Vx, Vn, #n" , "a32": "1111|00111|Vx'|imm[5:0]|Vx|0100|imm[6]|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNImm(sz, n)"},
|
|
{"inst": "vst1.8-64 Ds, [Rn!=PC]" , "a32": "1111|01000|Vs'|00|Rn|Vs|0111|sz|0|align:1|1111" , "ext": "ASIMD"},
|
|
{"inst": "vst1.8-64 Ds, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|0111|sz|0|align:1|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vst1.8-64 Ds, [Rn!=PC, #off==8]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|0111|sz|0|align:1|1101" , "ext": "ASIMD"},
|
|
{"inst": "vst1.8-64 2x{Ds<=30}+, [Rn!=PC]" , "a32": "1111|01000|Vs'|00|Rn|Vs|1010|sz|0|align:1|1111" , "ext": "ASIMD"},
|
|
{"inst": "vst1.8-64 2x{Ds<=30}+, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|1010|sz|0|align:1|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vst1.8-64 2x{Ds<=30}+, [Rn!=PC, #off==16]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|1010|sz|0|align:1|1101" , "ext": "ASIMD"},
|
|
{"inst": "vst1.8-64 3x{Ds<=29}+, [Rn!=PC]" , "a32": "1111|01000|Vs'|00|Rn|Vs|0110|sz|0|align:1|1111" , "ext": "ASIMD"},
|
|
{"inst": "vst1.8-64 3x{Ds<=29}+, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|0110|sz|0|align:1|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vst1.8-64 3x{Ds<=29}+, [Rn!=PC, #off==24]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|0110|sz|0|align:1|1101" , "ext": "ASIMD"},
|
|
{"inst": "vst1.8-64 4x{Ds<=28}+, [Rn!=PC]" , "a32": "1111|01000|Vs'|00|Rn|Vs|0010|sz|0|align:1|1111" , "ext": "ASIMD"},
|
|
{"inst": "vst1.8-64 4x{Ds<=28}+, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|0010|sz|0|align:1|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vst1.8-64 4x{Ds<=28}+, [Rn!=PC, #off==32]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|0010|sz|0|align:1|1101" , "ext": "ASIMD"},
|
|
{"inst": "vst2.8-32 2x{Ds<=30}+, [Rn!=PC]" , "a32": "1111|01000|Vs'|00|Rn|Vs|1000|sz|align:2|1111" , "ext": "ASIMD"},
|
|
{"inst": "vst2.8-32 2x{Ds<=30}+, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|1000|sz|align:2|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vst2.8-32 2x{Ds<=30}+, [Rn!=PC, #off==16]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|1000|sz|align:2|1101" , "ext": "ASIMD"},
|
|
{"inst": "vst2.8-32 2x{Ds<=29}++, [Rn!=PC]" , "a32": "1111|01000|Vs'|00|Rn|Vs|1001|sz|align:2|1111" , "ext": "ASIMD"},
|
|
{"inst": "vst2.8-32 2x{Ds<=29}++, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|1001|sz|align:2|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vst2.8-32 2x{Ds<=29}++, [Rn!=PC, #off==16]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|1001|sz|align:2|1101" , "ext": "ASIMD"},
|
|
{"inst": "vst2.8-32 4x{Ds<=28}+, [Rn!=PC]" , "a32": "1111|01000|Vs'|00|Rn|Vs|0011|sz|align:2|1111" , "ext": "ASIMD"},
|
|
{"inst": "vst2.8-32 4x{Ds<=28}+, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|0011|sz|align:2|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vst2.8-32 4x{Ds<=28}+, [Rn!=PC, #off==32]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|0011|sz|align:2|1101" , "ext": "ASIMD"},
|
|
{"inst": "vst3.8-32 3x{Ds<=29}+, [Rn!=PC]" , "a32": "1111|01000|Vs'|00|Rn|Vs|0100|sz|0|align:1|1111" , "ext": "ASIMD"},
|
|
{"inst": "vst3.8-32 3x{Ds<=29}+, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|0100|sz|0|align:1|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vst3.8-32 3x{Ds<=29}+, [Rn!=PC, #off==24]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|0100|sz|0|align:1|1101" , "ext": "ASIMD"},
|
|
{"inst": "vst3.8-32 3x{Ds<=27}++, [Rn!=PC]" , "a32": "1111|01000|Vs'|00|Rn|Vs|0101|sz|1|align:1|1111" , "ext": "ASIMD"},
|
|
{"inst": "vst3.8-32 3x{Ds<=27}++, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|0101|sz|1|align:1|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vst3.8-32 3x{Ds<=27}++, [Rn!=PC, #off==24]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|0101|sz|1|align:1|1101" , "ext": "ASIMD"},
|
|
{"inst": "vst4.8-32 4x{Ds<=29}+, [Rn!=PC]" , "a32": "1111|01000|Vs'|00|Rn|Vs|0000|sz|align:2|1111" , "ext": "ASIMD"},
|
|
{"inst": "vst4.8-32 4x{Ds<=29}+, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|0000|sz|align:2|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vst4.8-32 4x{Ds<=29}+, [Rn!=PC, #off==32]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|0000|sz|align:2|1101" , "ext": "ASIMD"},
|
|
{"inst": "vst4.8-32 4x{Ds<=27}++, [Rn!=PC]" , "a32": "1111|01000|Vs'|00|Rn|Vs|0001|sz|align:2|1111" , "ext": "ASIMD"},
|
|
{"inst": "vst4.8-32 4x{Ds<=27}++, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|0001|sz|align:2|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vst4.8-32 4x{Ds<=27}++, [Rn!=PC, #off==32]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|0001|sz|align:2|1101" , "ext": "ASIMD"},
|
|
{"inst": "vstmdb.32 [Rn]!, SdList" , "a32": "cond|11010|immVd[0]|10|Rn|immVd[4:1]|1010|immCount:8" , "ext": "ASIMD", "imm": "VecSListImm(SdList)"},
|
|
{"inst": "vstmdb.64 [Rn]!, DdList" , "a32": "cond|11010|immVd[4]|10|Rn|immVd[3:0]|1011|immCount:8" , "ext": "ASIMD", "imm": "VecDListImm(SdList)"},
|
|
{"inst": "vstmia.32 [Rn!=PC]{!}, SdList" , "a32": "cond|11001|immVd[0]|W0|Rn|immVd[4:1]|1010|immCount:8" , "ext": "ASIMD", "imm": "VecSListImm(SdList)"},
|
|
{"inst": "vstmia.64 [Rn!=PC]{!}, DdList" , "a32": "cond|11001|immVd[4]|W0|Rn|immVd[3:0]|1011|immCount:8" , "ext": "ASIMD", "imm": "VecDListImm(SdList)"},
|
|
{"inst": "vstmia.32 [Rn==PC], SdList" , "a32": "cond|11001|immVd[0]|00|Rn|immVd[4:1]|1010|immCount:8" , "ext": "ASIMD", "imm": "VecSListImm(SdList)"},
|
|
{"inst": "vstmia.64 [Rn==PC], DdList" , "a32": "cond|11001|immVd[4]|00|Rn|immVd[3:0]|1011|immCount:8" , "ext": "ASIMD", "imm": "VecDListImm(SdList)"},
|
|
{"inst": "vsub.f16 Dd, Dn, Dm" , "a32": "1111|00100|Vd'|11|Vn|Vd|11|01|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vsub.f16 Vd, Vn, Vm" , "a32": "1111|00100|Vd'|11|Vn|Vd|11|01|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vsub.f32 Dd, Dn, Dm" , "a32": "1111|00100|Vd'|10|Vn|Vd|11|01|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vsub.f32 Vd, Vn, Vm" , "a32": "1111|00100|Vd'|10|Vn|Vd|11|01|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vsub.x8-64 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|sz|Vn|Vd|10|00|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vsub.x8-64 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|sz|Vn|Vd|10|00|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vsubhn.x16-64 Dd, Vn, Vm" , "a32": "1111|00101|Vd'|szM1:2|Vn|Vd|0110|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "narrow"},
|
|
{"inst": "vsubl.x8-32 Vd, Dn, Dm" , "a32": "1111|001U1|Vd'|sz|Vn|Vd|0010|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "widen"},
|
|
{"inst": "vsubw.x8-32 Vd, Vn, Dm" , "a32": "1111|001U1|Vd'|sz|Vn|Vd|0011|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "widen"},
|
|
{"inst": "vswp.any Dx, Dx2!=Dx" , "a32": "1111|00111|Vx'|11|00|10|Vx|0000|0|0|Vx2'|0|Vx2" , "ext": "ASIMD"},
|
|
{"inst": "vswp.any Vx, Vx2!=Vx" , "a32": "1111|00111|Vx'|11|00|10|Vx|0000|0|1|Vx2'|0|Vx2" , "ext": "ASIMD"},
|
|
{"inst": "vtbl.x8 Dd, Dn, Dm" , "a32": "1111|00111|Vd'|11|Vn|Vd|10|00|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vtbl.x8 Dd, Dn, Dn2+, Dm" , "a32": "1111|00111|Vd'|11|Vn|Vd|10|01|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vtbl.x8 Dd, Dn, Dn2+, Dn3+, Dm" , "a32": "1111|00111|Vd'|11|Vn|Vd|10|10|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vtbl.x8 Dd, Dn, Dn2+, Dn3+, Dn4+, Dm" , "a32": "1111|00111|Vd'|11|Vn|Vd|10|11|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vtbx.x8 Dd, Dn, Dm" , "a32": "1111|00111|Vd'|11|Vn|Vd|10|00|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vtbx.x8 Dd, Dn, Dn2+, Dm" , "a32": "1111|00111|Vd'|11|Vn|Vd|10|01|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vtbx.x8 Dd, Dn, Dn2+, Dn3+, Dm" , "a32": "1111|00111|Vd'|11|Vn|Vd|10|10|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vtbx.x8 Dd, Dn, Dn2+, Dn3+, Dn4+, Dm" , "a32": "1111|00111|Vd'|11|Vn|Vd|10|11|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vtrn.x8-32 Dx, Dx2" , "a32": "1111|00111|Vx'|11|sz|10|Vx|0000|1|0|Vx2'|0|Vx2" , "ext": "ASIMD"},
|
|
{"inst": "vtrn.x8-32 Vx, Vx2" , "a32": "1111|00111|Vx'|11|sz|10|Vx|0000|1|1|Vx2'|0|Vx2" , "ext": "ASIMD"},
|
|
{"inst": "vtst.x8-32 Dd, Dn, Dm" , "a32": "1111|00100|Vd'|sz|Vn|Vd|1000|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vtst.x8-32 Vd, Vn, Vm" , "a32": "1111|00100|Vd'|sz|Vn|Vd|1000|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vuzp.x8-16 Dx, Dx2" , "a32": "1111|00111|Vx'|11|sz|10|Vx|0001|0|0|Vx2'|0|Vx2" , "ext": "ASIMD"},
|
|
{"inst": "vuzp.x32 Dx, Dx2" , "a32": "1111|00111|Vx'|11|sz|10|Vx|0000|1|0|Vx2'|0|Vx2" , "ext": "ASIMD", "aliasOf": "vtrn"},
|
|
{"inst": "vuzp.x8-32 Vx, Vx2" , "a32": "1111|00111|Vx'|11|sz|10|Vx|0001|0|1|Vx2'|0|Vx2" , "ext": "ASIMD"},
|
|
{"inst": "vzip.x8-16 Dx, Dx2" , "a32": "1111|00111|Vx'|11|sz|10|Vx|0001|1|0|Vx2'|0|Vx2" , "ext": "ASIMD"},
|
|
{"inst": "vzip.x32 Dx, Dx2" , "a32": "1111|00111|Vx'|11|sz|10|Vx|0000|1|0|Vx2'|0|Vx2" , "ext": "ASIMD", "aliasOf": "vtrn"},
|
|
{"inst": "vzip.x8-32 Vx, Vx2" , "a32": "1111|00111|Vx'|11|sz|10|Vx|0001|1|1|Vx2'|0|Vx2" , "ext": "ASIMD"}
|
|
]},
|
|
|
|
{"category": "ASIMD", "ext": "ASIMD", "data": [
|
|
{"inst": "vaba.x8-32 Dd, Dn, Dm" , "t32": "111U|111U0|Vd'|sz|Vn|Vd|0111|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vaba.x8-32 Vd, Vn, Vm" , "t32": "111U|111U0|Vd'|sz|Vn|Vd|0111|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vabal.x8-32 Vd, Dn, Dm" , "t32": "111U|11111|Vd'|sz|Vn|Vd|0101|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vabd.f16 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|11|Vn|Vd|1101|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vabd.f16 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|11|Vn|Vd|1101|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vabd.f32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|10|Vn|Vd|1101|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vabd.f32 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|10|Vn|Vd|1101|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vabd.x8-32 Dd, Dn, Dm" , "t32": "111U|11110|Vd'|sz|Vn|Vd|0111|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vabd.x8-32 Vd, Vn, Vm" , "t32": "111U|11110|Vd'|sz|Vn|Vd|0111|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vabdl.x8-32 Vd, Dn, Dm" , "t32": "111U|11111|Vd'|sz|Vn|Vd|0111|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vabs.f16 Dd, Dn" , "t32": "1111|11111|Vd'|11|01|01|Vd|01|11|0|0|Vn'|0|Vn" , "ext": "ASIMD FP16"},
|
|
{"inst": "vabs.f16 Vd, Vn" , "t32": "1111|11111|Vd'|11|01|01|Vd|01|11|0|1|Vn'|0|Vn" , "ext": "ASIMD FP16"},
|
|
{"inst": "vabs.f32 Dd, Dn" , "t32": "1111|11111|Vd'|11|10|01|Vd|01|11|0|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vabs.f32 Vd, Vn" , "t32": "1111|11111|Vd'|11|10|01|Vd|01|11|0|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vabs.s8-32 Dd, Dn" , "t32": "1111|11111|Vd'|11|sz|01|Vd|00|11|0|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vabs.s8-32 Vd, Vn" , "t32": "1111|11111|Vd'|11|sz|01|Vd|00|11|0|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vacge.f16 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|01|Vn|Vd|1110|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vacge.f16 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|01|Vn|Vd|1110|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vacge.f32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|00|Vn|Vd|1110|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vacge.f32 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|00|Vn|Vd|1110|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vacgt.f16 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|11|Vn|Vd|1110|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vacgt.f16 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|11|Vn|Vd|1110|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vacgt.f32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|10|Vn|Vd|1110|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vacgt.f32 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|10|Vn|Vd|1110|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vacle.f16 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|01|Vm|Vd|1110|Vm'|0|Vn'|1|Vn" , "ext": "ASIMD FP16"},
|
|
{"inst": "vacle.f16 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|01|Vm|Vd|1110|Vm'|1|Vn'|1|Vn" , "ext": "ASIMD FP16"},
|
|
{"inst": "vacle.f32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|00|Vm|Vd|1110|Vm'|0|Vn'|1|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vacle.f32 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|00|Vm|Vd|1110|Vm'|1|Vn'|1|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vaclt.f16 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|11|Vm|Vd|1110|Vm'|0|Vn'|1|Vn" , "ext": "ASIMD FP16"},
|
|
{"inst": "vaclt.f16 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|11|Vm|Vd|1110|Vm'|1|Vn'|1|Vn" , "ext": "ASIMD FP16"},
|
|
{"inst": "vaclt.f32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|10|Vm|Vd|1110|Vm'|0|Vn'|1|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vaclt.f32 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|10|Vm|Vd|1110|Vm'|1|Vn'|1|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vadd.f16 Dd, Dn, Dm" , "t32": "1110|11110|Vd'|01|Vn|Vd|1101|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vadd.f16 Vd, Vn, Vm" , "t32": "1110|11110|Vd'|01|Vn|Vd|1101|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vadd.f32 Dd, Dn, Dm" , "t32": "1110|11110|Vd'|00|Vn|Vd|1101|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vadd.f32 Vd, Vn, Vm" , "t32": "1110|11110|Vd'|00|Vn|Vd|1101|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vadd.x8-64 Dd, Dn, Dm" , "t32": "1110|11110|Vd'|sz|Vn|Vd|1000|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vadd.x8-64 Vd, Vn, Vm" , "t32": "1110|11110|Vd'|sz|Vn|Vd|1000|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vaddhn.x16-64 Dd, Vn, Vm" , "t32": "1110|11111|Vd'|szM1:2|Vn|Vd|0100|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "narrow"},
|
|
{"inst": "vaddl.x8-32 Vd, Dn, Dm" , "t32": "111U|11111|Vd'|sz|Vn|Vd|0000|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "widen"},
|
|
{"inst": "vaddw.x8-32 Vd, Vn, Dm" , "t32": "111U|11111|Vd'|sz|Vn|Vd|0001|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "widen"},
|
|
{"inst": "vand.any Dd, Dn, Dm" , "t32": "1110|11110|Vd'|00|Vn|Vd|0001|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vand.any Vd, Vn, Vm" , "t32": "1110|11110|Vd'|00|Vn|Vd|0001|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vand.x16-64 Dx, #immV" , "t32": "111|imm:1|11111|Vx'|000|imm:3|Vx|cmode:4|0011|imm:4" , "ext": "ASIMD", "imm": "VecBicOrrImm(sz, 1, immV)", "pseudoOf": "vbic"},
|
|
{"inst": "vand.x16-64 Vx, #immV" , "t32": "111|imm:1|11111|Vx'|000|imm:3|Vx|cmode:4|0111|imm:4" , "ext": "ASIMD", "imm": "VecBicOrrImm(sz, 1, immV)", "pseudoOf": "vbic"},
|
|
{"inst": "vbic.any Dd, Dn, Dm" , "t32": "1110|11110|Vd'|01|Vn|Vd|0001|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vbic.any Vd, Vn, Vm" , "t32": "1110|11110|Vd'|01|Vn|Vd|0001|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vbic.x16-64 Dx, #immV" , "t32": "111|imm:1|11111|Vx'|000|imm:3|Vx|cmode:4|0011|imm:4" , "ext": "ASIMD", "imm": "VecBicOrrImm(sz, 0, immV)"},
|
|
{"inst": "vbic.x16-64 Vx, #immV" , "t32": "111|imm:1|11111|Vx'|000|imm:3|Vx|cmode:4|0111|imm:4" , "ext": "ASIMD", "imm": "VecBicOrrImm(sz, 0, immV)"},
|
|
{"inst": "vbif.any Dd, Dn, Dm" , "t32": "1111|11110|Vd'|11|Vn|Vd|0001|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vbif.any Vd, Vn, Vm" , "t32": "1111|11110|Vd'|11|Vn|Vd|0001|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vbit.any Dd, Dn, Dm" , "t32": "1111|11110|Vd'|10|Vn|Vd|0001|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vbit.any Vd, Vn, Vm" , "t32": "1111|11110|Vd'|10|Vn|Vd|0001|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vbsl.any Dd, Dn, Dm" , "t32": "1111|11110|Vd'|01|Vn|Vd|0001|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vbsl.any Vd, Vn, Vm" , "t32": "1111|11110|Vd'|01|Vn|Vd|0001|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vceq.f16-32 Dd, Dn, Dm" , "t32": "1110|11110|Vd'|01|Vn|Vd|1110|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vceq.f16-32 Vd, Vn, Vm" , "t32": "1110|11110|Vd'|01|Vn|Vd|1110|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vceq.f16-32 Dd, Dn, Dm" , "t32": "1110|11110|Vd'|00|Vn|Vd|1110|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vceq.f16-32 Vd, Vn, Vm" , "t32": "1110|11110|Vd'|00|Vn|Vd|1110|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vceq.f16-32 Dd, Dn, #zero" , "t32": "1111|11111|Vd'|11|01|01|Vd|01010|0|Vn'|0|Vn" , "ext": "ASIMD FP16"},
|
|
{"inst": "vceq.f16-32 Vd, Vn, #zero" , "t32": "1111|11111|Vd'|11|01|01|Vd|01010|1|Vn'|0|Vn" , "ext": "ASIMD FP16"},
|
|
{"inst": "vceq.f16-32 Dd, Dn, #zero" , "t32": "1111|11111|Vd'|11|10|01|Vd|01010|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vceq.f16-32 Vd, Vn, #zero" , "t32": "1111|11111|Vd'|11|10|01|Vd|01010|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vceq.x8-32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|sz|Vn|Vd|1000|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vceq.x8-32 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|sz|Vn|Vd|1000|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vceq.x8-32 Dd, Dn, #zero" , "t32": "1111|11111|Vd'|11|sz|01|Vd|00010|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vceq.x8-32 Vd, Vn, #zero" , "t32": "1111|11111|Vd'|11|sz|01|Vd|00010|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vcge.f16-32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|01|Vn|Vd|1110|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vcge.f16-32 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|01|Vn|Vd|1110|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vcge.f16-32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|00|Vn|Vd|1110|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vcge.f16-32 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|00|Vn|Vd|1110|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vcge.f16-32 Dd, Dn, #zero" , "t32": "1111|11111|Vd'|11|01|01|Vd|01001|0|Vn'|0|Vn" , "ext": "ASIMD FP16"},
|
|
{"inst": "vcge.f16-32 Vd, Vn, #zero" , "t32": "1111|11111|Vd'|11|01|01|Vd|01001|1|Vn'|0|Vn" , "ext": "ASIMD FP16"},
|
|
{"inst": "vcge.f16-32 Dd, Dn, #zero" , "t32": "1111|11111|Vd'|11|10|01|Vd|01001|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vcge.f16-32 Vd, Vn, #zero" , "t32": "1111|11111|Vd'|11|10|01|Vd|01001|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vcge.x8-32 Dd, Dn, Dm" , "t32": "111U|11110|Vd'|sz|Vn|Vd|0011|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vcge.x8-32 Vd, Vn, Vm" , "t32": "111U|11110|Vd'|sz|Vn|Vd|0011|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vcge.s8-32 Dd, Dn, #zero" , "t32": "1111|11111|Vd'|11|sz|01|Vd|00001|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vcge.s8-32 Vd, Vn, #zero" , "t32": "1111|11111|Vd'|11|sz|01|Vd|00001|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vcgt.f16-32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|11|Vn|Vd|1110|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vcgt.f16-32 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|11|Vn|Vd|1110|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vcgt.f16-32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|10|Vn|Vd|1110|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vcgt.f16-32 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|10|Vn|Vd|1110|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vcgt.f16-32 Dd, Dn, #zero" , "t32": "1111|11111|Vd'|11|01|01|Vd|01000|0|Vn'|0|Vn" , "ext": "ASIMD FP16"},
|
|
{"inst": "vcgt.f16-32 Vd, Vn, #zero" , "t32": "1111|11111|Vd'|11|01|01|Vd|01000|1|Vn'|0|Vn" , "ext": "ASIMD FP16"},
|
|
{"inst": "vcgt.f16-32 Dd, Dn, #zero" , "t32": "1111|11111|Vd'|11|10|01|Vd|01000|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vcgt.f16-32 Vd, Vn, #zero" , "t32": "1111|11111|Vd'|11|10|01|Vd|01000|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vcgt.x8-32 Dd, Dn, Dm" , "t32": "111U|11110|Vd'|sz|Vn|Vd|0011|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vcgt.x8-32 Vd, Vn, Vm" , "t32": "111U|11110|Vd'|sz|Vn|Vd|0011|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vcgt.s8-32 Dd, Dn, #zero" , "t32": "1111|11111|Vd'|11|sz|01|Vd|00000|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vcgt.s8-32 Vd, Vn, #zero" , "t32": "1111|11111|Vd'|11|sz|01|Vd|00000|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vcle.f16-32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|01|Vm|Vd|1110|Vm'|0|Vn'|0|Vn" , "ext": "ASIMD FP16"},
|
|
{"inst": "vcle.f16-32 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|01|Vm|Vd|1110|Vm'|1|Vn'|0|Vn" , "ext": "ASIMD FP16"},
|
|
{"inst": "vcle.f16-32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|00|Vm|Vd|1110|Vm'|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vcle.f16-32 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|00|Vm|Vd|1110|Vm'|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vcle.f16-32 Dd, Dn, #zero" , "t32": "1111|11111|Vd'|11|01|01|Vd|01011|0|Vn'|0|Vn" , "ext": "ASIMD FP16"},
|
|
{"inst": "vcle.f16-32 Vd, Vn, #zero" , "t32": "1111|11111|Vd'|11|01|01|Vd|01011|1|Vn'|0|Vn" , "ext": "ASIMD FP16"},
|
|
{"inst": "vcle.f16-32 Dd, Dn, #zero" , "t32": "1111|11111|Vd'|11|10|01|Vd|01011|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vcle.f16-32 Vd, Vn, #zero" , "t32": "1111|11111|Vd'|11|10|01|Vd|01011|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vcle.x8-32 Dd, Dn, Dm" , "t32": "111U|11110|Vd'|sz|Vm|Vd|0011|Vm'|0|Vn'|1|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vcle.x8-32 Vd, Vn, Vm" , "t32": "111U|11110|Vd'|sz|Vm|Vd|0011|Vm'|1|Vn'|1|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vcle.s8-32 Dd, Dn, #zero" , "t32": "1111|11111|Vd'|11|sz|01|Vd|00011|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vcle.s8-32 Vd, Vn, #zero" , "t32": "1111|11111|Vd'|11|sz|01|Vd|00011|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vcls.x8-32 Dd, Dn" , "t32": "1111|11111|Vd'|11|sz|00|Vd|01000|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vcls.x8-32 Vd, Vn" , "t32": "1111|11111|Vd'|11|sz|00|Vd|01000|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vclt.f16-32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|11|Vm|Vd|1110|Vm'|0|Vn'|0|Vn" , "ext": "ASIMD FP16"},
|
|
{"inst": "vclt.f16-32 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|11|Vm|Vd|1110|Vm'|1|Vn'|0|Vn" , "ext": "ASIMD FP16"},
|
|
{"inst": "vclt.f16-32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|10|Vm|Vd|1110|Vm'|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vclt.f16-32 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|10|Vm|Vd|1110|Vm'|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vclt.f16-32 Dd, Dn, #zero" , "t32": "1111|11111|Vd'|11|01|01|Vd|01100|0|Vn'|0|Vn" , "ext": "ASIMD FP16"},
|
|
{"inst": "vclt.f16-32 Vd, Vn, #zero" , "t32": "1111|11111|Vd'|11|01|01|Vd|01100|1|Vn'|0|Vn" , "ext": "ASIMD FP16"},
|
|
{"inst": "vclt.f16-32 Dd, Dn, #zero" , "t32": "1111|11111|Vd'|11|10|01|Vd|01100|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vclt.f16-32 Vd, Vn, #zero" , "t32": "1111|11111|Vd'|11|10|01|Vd|01100|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vclt.x8-32 Dd, Dn, Dm" , "t32": "111U|11110|Vd'|sz|Vm|Vd|0011|Vm'|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vclt.x8-32 Vd, Vn, Vm" , "t32": "111U|11110|Vd'|sz|Vm|Vd|0011|Vm'|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vclt.s8-32 Dd, Dn, #zero" , "t32": "1111|11111|Vd'|11|sz|01|Vd|00100|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vclt.s8-32 Vd, Vn, #zero" , "t32": "1111|11111|Vd'|11|sz|01|Vd|00100|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vclz.x8-32 Dd, Dn" , "t32": "1111|11111|Vd'|11|sz|00|Vd|01001|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vclz.x8-32 Vd, Vn" , "t32": "1111|11111|Vd'|11|sz|00|Vd|01001|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vcnt.x8 Dd, Dn" , "t32": "1111|11111|Vd'|11|00|00|Vd|01010|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vcnt.x8 Vd, Vn" , "t32": "1111|11111|Vd'|11|00|00|Vd|01010|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vcvt.s32.f32 Dd, Dn" , "t32": "1111|11111|Vd'|11|10|11|Vd|01110|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vcvt.s32.f32 Vd, Vn" , "t32": "1111|11111|Vd'|11|10|11|Vd|01110|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vcvt.u32.f32 Dd, Dn" , "t32": "1111|11111|Vd'|11|10|11|Vd|01111|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vcvt.u32.f32 Vd, Vn" , "t32": "1111|11111|Vd'|11|10|11|Vd|01111|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vcvt.f32.s32 Dd, Dn" , "t32": "1111|11111|Vd'|11|10|11|Vd|01100|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vcvt.f32.s32 Vd, Vn" , "t32": "1111|11111|Vd'|11|10|11|Vd|01100|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vcvt.f32.u32 Dd, Dn" , "t32": "1111|11111|Vd'|11|10|11|Vd|01101|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vcvt.f32.u32 Vd, Vn" , "t32": "1111|11111|Vd'|11|10|11|Vd|01101|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vcvt.f32.s32 Dd, Dn, #fbits" , "t32": "1110|11111|Vd'|imm:6|Vd|11100|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecFBitsASIMD(fbits)"},
|
|
{"inst": "vcvt.f32.s32 Vd, Vn, #fbits" , "t32": "1110|11111|Vd'|imm:6|Vd|11100|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecFBitsASIMD(fbits)"},
|
|
{"inst": "vcvt.s32.f32 Dd, Dn, #fbits" , "t32": "1110|11111|Vd'|imm:6|Vd|11110|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecFBitsASIMD(fbits)"},
|
|
{"inst": "vcvt.s32.f32 Vd, Vn, #fbits" , "t32": "1110|11111|Vd'|imm:6|Vd|11110|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecFBitsASIMD(fbits)"},
|
|
{"inst": "vcvt.f32.u32 Dd, Dn, #fbits" , "t32": "1111|11111|Vd'|imm:6|Vd|11100|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecFBitsASIMD(fbits)"},
|
|
{"inst": "vcvt.f32.u32 Vd, Vn, #fbits" , "t32": "1111|11111|Vd'|imm:6|Vd|11100|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecFBitsASIMD(fbits)"},
|
|
{"inst": "vcvt.u32.f32 Dd, Dn, #fbits" , "t32": "1111|11111|Vd'|imm:6|Vd|11110|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecFBitsASIMD(fbits)"},
|
|
{"inst": "vcvt.u32.f32 Vd, Vn, #fbits" , "t32": "1111|11111|Vd'|imm:6|Vd|11110|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecFBitsASIMD(fbits)"},
|
|
{"inst": "vcvta.s32.f32 Sd, Sn" , "t32": "1111|11101|'Vd|11|11|00|Vd|10101|1|'Vn|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vcvta.s32.f64 Sd, Dn" , "t32": "1111|11101|'Vd|11|11|00|Vd|10111|1|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vcvta.u32.f32 Sd, Sn" , "t32": "1111|11101|'Vd|11|11|00|Vd|10100|1|'Vn|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vcvta.u32.f64 Sd, Dn" , "t32": "1111|11101|'Vd|11|11|00|Vd|10110|1|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vcvtm.s32.f32 Dd, Dn" , "t32": "1111|11111|Vd'|11|10|11|Vd|00110|0|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vcvtm.s32.f32 Vd, Vn" , "t32": "1111|11111|Vd'|11|10|11|Vd|00110|1|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vcvtm.u32.f32 Dd, Dn" , "t32": "1111|11111|Vd'|11|10|11|Vd|00111|0|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vcvtm.u32.f32 Vd, Vn" , "t32": "1111|11111|Vd'|11|10|11|Vd|00111|1|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vcvtm.s32.f32 Sd, Sn" , "t32": "1111|11101|'Vd|11|11|11|Vd|10101|1|'Vn|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vcvtm.s32.f64 Sd, Dn" , "t32": "1111|11101|'Vd|11|11|11|Vd|10111|1|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vcvtm.u32.f32 Sd, Sn" , "t32": "1111|11101|'Vd|11|11|11|Vd|10100|1|'Vn|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vcvtm.u32.f64 Sd, Dn" , "t32": "1111|11101|'Vd|11|11|11|Vd|10110|1|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vcvtn.s32.f32 Dd, Dn" , "t32": "1111|11111|Vd'|11|10|11|Vd|00010|0|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vcvtn.s32.f32 Vd, Vn" , "t32": "1111|11111|Vd'|11|10|11|Vd|00010|1|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vcvtn.u32.f32 Dd, Dn" , "t32": "1111|11111|Vd'|11|10|11|Vd|00011|0|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vcvtn.u32.f32 Vd, Vn" , "t32": "1111|11111|Vd'|11|10|11|Vd|00011|1|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vcvtn.s32.f32 Sd, Sn" , "t32": "1111|11101|'Vd|11|11|01|Vd|10101|1|'Vn|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vcvtn.s32.f64 Sd, Dn" , "t32": "1111|11101|'Vd|11|11|01|Vd|10111|1|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vcvtn.u32.f32 Sd, Sn" , "t32": "1111|11101|'Vd|11|11|01|Vd|10100|1|'Vn|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vcvtn.u32.f64 Sd, Dn" , "t32": "1111|11101|'Vd|11|11|01|Vd|10110|1|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vcvtp.s32.f32 Dd, Dn" , "t32": "1111|11111|Vd'|11|10|11|Vd|00100|0|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vcvtp.s32.f32 Vd, Vn" , "t32": "1111|11111|Vd'|11|10|11|Vd|00100|1|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vcvtp.u32.f32 Dd, Dn" , "t32": "1111|11111|Vd'|11|10|11|Vd|00101|0|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vcvtp.u32.f32 Vd, Vn" , "t32": "1111|11111|Vd'|11|10|11|Vd|00101|1|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vcvtp.s32.f32 Sd, Sn" , "t32": "1111|11101|'Vd|11|11|10|Vd|10101|1|'Vn|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vcvtp.s32.f64 Sd, Dn" , "t32": "1111|11101|'Vd|11|11|10|Vd|10111|1|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vcvtp.u32.f32 Sd, Sn" , "t32": "1111|11101|'Vd|11|11|10|Vd|10100|1|'Vn|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vcvtp.u32.f64 Sd, Dn" , "t32": "1111|11101|'Vd|11|11|10|Vd|10110|1|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vdup.8 Dd, Rn!=PC" , "t32": "1110|11101|1|00|Vd|Rn|1011|Vd'|0|0|1|0000" , "ext": "ASIMD"},
|
|
{"inst": "vdup.8 Vd, Rn!=PC" , "t32": "1110|11101|1|10|Vd|Rn|1011|Vd'|0|0|1|0000" , "ext": "ASIMD"},
|
|
{"inst": "vdup.16 Dd, Rn!=PC" , "t32": "1110|11101|0|00|Vd|Rn|1011|Vd'|0|1|1|0000" , "ext": "ASIMD"},
|
|
{"inst": "vdup.16 Vd, Rn!=PC" , "t32": "1110|11101|0|10|Vd|Rn|1011|Vd'|0|1|1|0000" , "ext": "ASIMD"},
|
|
{"inst": "vdup.32 Dd, Rn!=PC" , "t32": "1110|11101|0|00|Vd|Rn|1011|Vd'|0|0|1|0000" , "ext": "ASIMD"},
|
|
{"inst": "vdup.32 Vd, Rn!=PC" , "t32": "1110|11101|0|10|Vd|Rn|1011|Vd'|0|0|1|0000" , "ext": "ASIMD"},
|
|
{"inst": "vdup.8 Dd, Dn[#i]" , "t32": "1111|11111|Vd'|11|i:3|1|Vd|1100|0|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vdup.8 Vd, Dn[#i]" , "t32": "1111|11111|Vd'|11|i:3|1|Vd|1100|0|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vdup.16 Dd, Dn[#i]" , "t32": "1111|11111|Vd'|11|i:2|10|Vd|1100|0|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vdup.16 Vd, Dn[#i]" , "t32": "1111|11111|Vd'|11|i:2|10|Vd|1100|0|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vdup.32 Dd, Dn[#i]" , "t32": "1111|11111|Vd'|11|i:1|100|Vd|1100|0|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vdup.32 Vd, Dn[#i]" , "t32": "1111|11111|Vd'|11|i:1|100|Vd|1100|0|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "veor.any Dd, Dn, Dm" , "t32": "1111|11110|Vd'|00|Vn|Vd|0001|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "veor.any Vd, Vn, Vm" , "t32": "1111|11110|Vd'|00|Vn|Vd|0001|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vext.8 Dd, Dn, Dm, #immZ<=07" , "t32": "1110|11111|Vd'|11|Vn|Vd|immZ:4|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vext.8 Vd, Vn, Vm, #immZ<=15" , "t32": "1110|11111|Vd'|11|Vn|Vd|immZ:4|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vfma.f16 Dx, Dn, Dm" , "t32": "1110|11110|Vx'|01|Vn|Vx|1100|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vfma.f16 Vx, Vn, Vm" , "t32": "1110|11110|Vx'|01|Vn|Vx|1100|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vfma.f32 Dx, Dn, Dm" , "t32": "1110|11110|Vx'|00|Vn|Vx|1100|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vfma.f32 Vx, Vn, Vm" , "t32": "1110|11110|Vx'|00|Vn|Vx|1100|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vfms.f16 Dx, Dn, Dm" , "t32": "1110|11110|Vx'|11|Vn|Vx|1100|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vfms.f16 Vx, Vn, Vm" , "t32": "1110|11110|Vx'|11|Vn|Vx|1100|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vfms.f32 Dx, Dn, Dm" , "t32": "1110|11110|Vx'|10|Vn|Vx|1100|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vfms.f32 Vx, Vn, Vm" , "t32": "1110|11110|Vx'|10|Vn|Vx|1100|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vhadd.x8-32 Dd, Dn, Dm" , "t32": "111U|11110|Vd'|sz|Vn|Vd|0000|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vhadd.x8-32 Vd, Vn, Vm" , "t32": "111U|11110|Vd'|sz|Vn|Vd|0000|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vhsub.x8-32 Dd, Dn, Dm" , "t32": "111U|11110|Vd'|sz|Vn|Vd|0010|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vhsub.x8-32 Vd, Vn, Vm" , "t32": "111U|11110|Vd'|sz|Vn|Vd|0010|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vins.f16 Sd, Sn" , "t32": "1111|11101|'Vd|11|0000|Vd|1010|11|'Vn|0|Vn" , "ext": "FP16"},
|
|
{"inst": "vld1.8-64 Dd, [Rn!=PC]" , "t32": "1111|10010|Vd'|10|Rn|Vd|0111|sz|0|align:1|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld1.8-64 Dd, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vd'|10|Rn|Vd|0111|sz|0|align:1|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld1.8-64 Dd, [Rn!=PC, #off==8]@" , "t32": "1111|10010|Vd'|10|Rn|Vd|0111|sz|0|align:1|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld1.8-64 2x{Dd<=30}+, [Rn!=PC]" , "t32": "1111|10010|Vd'|10|Rn|Vd|1010|sz|0|align:1|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld1.8-64 2x{Dd<=30}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vd'|10|Rn|Vd|1010|sz|0|align:1|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld1.8-64 2x{Dd<=30}+, [Rn!=PC, #off==16]@" , "t32": "1111|10010|Vd'|10|Rn|Vd|1010|sz|0|align:1|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld1.8-64 3x{Dd<=29}+, [Rn!=PC]" , "t32": "1111|10010|Vd'|10|Rn|Vd|0110|sz|0|align:1|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld1.8-64 3x{Dd<=29}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vd'|10|Rn|Vd|0110|sz|0|align:1|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld1.8-64 3x{Dd<=29}+, [Rn!=PC, #off==24]@" , "t32": "1111|10010|Vd'|10|Rn|Vd|0110|sz|0|align:1|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld1.8-64 4x{Dd<=28}+, [Rn!=PC]" , "t32": "1111|10010|Vd'|10|Rn|Vd|0010|sz|0|align:1|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld1.8-64 4x{Dd<=28}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vd'|10|Rn|Vd|0010|sz|0|align:1|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld1.8-64 4x{Dd<=28}+, [Rn!=PC, #off==32]@" , "t32": "1111|10010|Vd'|10|Rn|Vd|0010|sz|0|align:1|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld1.8 Dd[#i], [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|0000|i:3|align:1|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld1.8 Dd[#i], [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|0000|i:3|align:1|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld1.8 Dd[#i], [Rn!=PC, #off==1]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|0000|i:3|align:1|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld1.16 Dd[#i], [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|0100|i:2|0|align:1|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld1.16 Dd[#i], [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|0100|i:2|0|align:1|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld1.16 Dd[#i], [Rn!=PC, #off==2]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|0100|i:2|0|align:1|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld1.32 Dd[#i], [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|1000|i:1|0|align:2|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld1.32 Dd[#i], [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1000|i:1|0|align:2|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld1.32 Dd[#i], [Rn!=PC, #off==4]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1000|i:1|0|align:2|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld1r.8-32 Dd, [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|1100|sz|0|align:1|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld1r.8-32 Dd, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1100|sz|0|align:1|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld1r.8-32 Dd, [Rn!=PC, #off==1<<sz]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1100|sz|0|align:1|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld1r.8-32 2x{Dd<=30}+, [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|1100|sz|1|align:1|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld1r.8-32 2x{Dd<=30}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1100|sz|1|align:1|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld1r.8-32 2x{Dd<=30}+, [Rn!=PC, #off==1<<sz]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1100|sz|1|align:1|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld2.8-32 2x{Dd<=30}+, [Rn!=PC]" , "t32": "1111|10010|Vd'|10|Rn|Vd|1000|sz|align:2|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld2.8-32 2x{Dd<=30}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vd'|10|Rn|Vd|1000|sz|align:2|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld2.8-32 2x{Dd<=30}+, [Rn!=PC, #off==16]@" , "t32": "1111|10010|Vd'|10|Rn|Vd|1000|sz|align:2|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld2.8-32 2x{Dd<=29}++, [Rn!=PC]" , "t32": "1111|10010|Vd'|10|Rn|Vd|1001|sz|align:2|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld2.8-32 2x{Dd<=29}++, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vd'|10|Rn|Vd|1001|sz|align:2|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld2.8-32 2x{Dd<=29}++, [Rn!=PC, #off==16]@" , "t32": "1111|10010|Vd'|10|Rn|Vd|1001|sz|align:2|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld2.8-32 4x{Dd<=28}+, [Rn!=PC]" , "t32": "1111|10010|Vd'|10|Rn|Vd|0011|sz|align:2|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld2.8-32 4x{Dd<=28}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vd'|10|Rn|Vd|0011|sz|align:2|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld2.8-32 4x{Dd<=28}+, [Rn!=PC, #off==32]@" , "t32": "1111|10010|Vd'|10|Rn|Vd|0011|sz|align:2|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld2.8 2x{Dd<=30[#i]}+, [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|0001|i:3|align:1|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld2.8 2x{Dd<=30[#i]}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|0001|i:3|align:1|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld2.8 2x{Dd<=30[#i]}+, [Rn!=PC, #off==2]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|0001|i:3|align:1|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld2.16 2x{Dd<=30[#i]}+, [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|0101|i:2|0|align:1|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld2.16 2x{Dd<=30[#i]}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|0101|i:2|0|align:1|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld2.16 2x{Dd<=30[#i]}+, [Rn!=PC, #off==4]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|0101|i:2|0|align:1|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld2.16 2x{Dd<=29[#i]}++, [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|0101|i:2|1|align:1|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld2.16 2x{Dd<=29[#i]}++, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|0101|i:2|1|align:1|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld2.16 2x{Dd<=29[#i]}++, [Rn!=PC, #off==4]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|0101|i:2|1|align:1|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld2.32 2x{Dd<=30[#i]}+, [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|1001|i:1|0|0|align:1|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld2.32 2x{Dd<=30[#i]}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1001|i:1|0|0|align:1|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld2.32 2x{Dd<=30[#i]}+, [Rn!=PC, #off==8]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1001|i:1|0|0|align:1|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld2.32 2x{Dd<=29[#i]}++, [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|1001|i:1|1|0|align:1|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld2.32 2x{Dd<=29[#i]}++, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1001|i:1|1|0|align:1|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld2.32 2x{Dd<=29[#i]}++, [Rn!=PC, #off==8]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1001|i:1|1|0|align:1|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld2r.8-32 2x{Dd<=30}+, [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|1101|sz|0|align:1|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld2r.8-32 2x{Dd<=30}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1101|sz|0|align:1|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld2r.8-32 2x{Dd<=30}+, [Rn!=PC, #off==2<<sz]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1101|sz|0|align:1|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld2r.8-32 2x{Dd<=29}++, [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|1101|sz|1|align:1|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld2r.8-32 2x{Dd<=29}++, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1101|sz|1|align:1|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld2r.8-32 2x{Dd<=29}++, [Rn!=PC, #off==2<<sz]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1101|sz|1|align:1|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld3.8-32 3x{Dd<=29}+, [Rn!=PC]" , "t32": "1111|10010|Vd'|10|Rn|Vd|0100|sz|0|align:1|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld3.8-32 3x{Dd<=29}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vd'|10|Rn|Vd|0100|sz|0|align:1|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld3.8-32 3x{Dd<=29}+, [Rn!=PC, #off==24]@" , "t32": "1111|10010|Vd'|10|Rn|Vd|0100|sz|0|align:1|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld3.8-32 3x{Dd<=27}++, [Rn!=PC]" , "t32": "1111|10010|Vd'|10|Rn|Vd|0101|sz|1|align:1|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld3.8-32 3x{Dd<=27}++, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vd'|10|Rn|Vd|0101|sz|1|align:1|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld3.8-32 3x{Dd<=27}++, [Rn!=PC, #off==24]@" , "t32": "1111|10010|Vd'|10|Rn|Vd|0101|sz|1|align:1|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld3.8 3x{Dd<=29[#i]}+, [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|0010|i:3|0|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld3.8 3x{Dd<=29[#i]}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|0010|i:3|0|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld3.8 3x{Dd<=29[#i]}+, [Rn!=PC, #off==3]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|0010|i:3|0|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld3.16 3x{Dd<=29[#i]}+, [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|0110|i:2|00|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld3.16 3x{Dd<=29[#i]}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|0110|i:2|00|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld3.16 3x{Dd<=29[#i]}+, [Rn!=PC, #off==6]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|0110|i:2|00|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld3.16 3x{Dd<=27[#i]}++, [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|0110|i:2|10|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld3.16 3x{Dd<=27[#i]}++, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|0110|i:2|10|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld3.16 3x{Dd<=27[#i]}++, [Rn!=PC, #off==6]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|0110|i:2|10|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld3.32 3x{Dd<=29[#i]}+, [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|1010|i:1|000|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld3.32 3x{Dd<=29[#i]}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1010|i:1|000|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld3.32 3x{Dd<=29[#i]}+, [Rn!=PC, #off==12]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1010|i:1|000|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld3.32 3x{Dd<=27[#i]}++, [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|1010|i:1|100|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld3.32 3x{Dd<=27[#i]}++, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1010|i:1|100|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld3.32 3x{Dd<=27[#i]}++, [Rn!=PC, #off==12]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1010|i:1|100|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld3r.8-32 3x{Dd<=29}+, [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|1110|sz|0|0|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld3r.8-32 3x{Dd<=29}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1110|sz|0|0|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld3r.8-32 3x{Dd<=29}+, [Rn!=PC, #off==3<<sz]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1110|sz|0|0|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld3r.8-32 3x{Dd<=27}++, [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|1110|sz|1|0|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld3r.8-32 3x{Dd<=27}++, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1110|sz|1|0|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld3r.8-32 3x{Dd<=27}++, [Rn!=PC, #off==3<<sz]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1110|sz|1|0|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld4.8-32 4x{Dd<=29}+, [Rn!=PC]" , "t32": "1111|10010|Vd'|10|Rn|Vd|0000|sz|align:2|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld4.8-32 4x{Dd<=29}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vd'|10|Rn|Vd|0000|sz|align:2|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld4.8-32 4x{Dd<=29}+, [Rn!=PC, #off==32]@" , "t32": "1111|10010|Vd'|10|Rn|Vd|0000|sz|align:2|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld4.8-32 4x{Dd<=27}++, [Rn!=PC]" , "t32": "1111|10010|Vd'|10|Rn|Vd|0001|sz|align:2|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld4.8-32 4x{Dd<=27}++, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vd'|10|Rn|Vd|0001|sz|align:2|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld4.8-32 4x{Dd<=27}++, [Rn!=PC, #off==32]@" , "t32": "1111|10010|Vd'|10|Rn|Vd|0001|sz|align:2|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld4.8 4x{Dd<=29[#i]}+, [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|0011|i:3|align:1|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld4.8 4x{Dd<=29[#i]}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|0011|i:3|align:1|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld4.8 4x{Dd<=29[#i]}+, [Rn!=PC, #off==4]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|0011|i:3|align:1|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld4.16 4x{Dd<=29[#i]}+, [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|0111|i:2|0|align:1|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld4.16 4x{Dd<=29[#i]}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|0111|i:2|0|align:1|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld4.16 4x{Dd<=29[#i]}+, [Rn!=PC, #off==8]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|0111|i:2|0|align:1|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld4.16 4x{Dd<=27[#i]}++, [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|0111|i:2|1|align:1|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld4.16 4x{Dd<=27[#i]}++, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|0111|i:2|1|align:1|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld4.16 4x{Dd<=27[#i]}++, [Rn!=PC, #off==8]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|0111|i:2|1|align:1|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld4.32 4x{Dd<=29[#i]}+, [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|1011|i:1|0|align:2|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld4.32 4x{Dd<=29[#i]}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1011|i:1|0|align:2|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld4.32 4x{Dd<=29[#i]}+, [Rn!=PC, #off==16]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1011|i:1|0|align:2|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld4.32 4x{Dd<=27[#i]}++, [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|1011|i:1|1|align:2|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld4.32 4x{Dd<=27[#i]}++, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1011|i:1|1|align:2|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld4.32 4x{Dd<=27[#i]}++, [Rn!=PC, #off==16]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1011|i:1|1|align:2|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld4r.8-32 4x{Dd<=28}+, [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|1111|sz|0|align:1|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld4r.8-32 4x{Dd<=28}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1111|sz|0|align:1|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld4r.8-32 4x{Dd<=28}+, [Rn!=PC, #off==4<<sz]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1111|sz|0|align:1|1101" , "ext": "ASIMD"},
|
|
{"inst": "vld4r.8-32 4x{Dd<=25}++, [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|1111|sz|1|align:1|1111" , "ext": "ASIMD"},
|
|
{"inst": "vld4r.8-32 4x{Dd<=25}++, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1111|sz|1|align:1|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vld4r.8-32 4x{Dd<=25}++, [Rn!=PC, #off==4<<sz]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1111|sz|1|align:1|1101" , "ext": "ASIMD"},
|
|
{"inst": "vldmdb.32 [Rn!=PC]!, SdList" , "t32": "1110|11010|immVd[0]|11|Rn|immVd[4:1]|1010|immCount:8" , "ext": "ASIMD", "it": "any", "imm": "VecSListImm(SdList)"},
|
|
{"inst": "vldmdb.64 [Rn!=PC]!, DdList" , "t32": "1110|11010|immVd[4]|11|Rn|immVd[3:0]|1011|immCount:8" , "ext": "ASIMD", "it": "any", "imm": "VecDListImm(SdList)"},
|
|
{"inst": "vldmia.32 [Rn!=PC]{!}, SdList" , "t32": "1110|11001|immVd[0]|W1|Rn|immVd[4:1]|1010|immCount:8" , "ext": "ASIMD", "it": "any", "imm": "VecSListImm(SdList)"},
|
|
{"inst": "vldmia.64 [Rn!=PC]{!}, DdList" , "t32": "1110|11001|immVd[4]|W1|Rn|immVd[3:0]|1011|immCount:8" , "ext": "ASIMD", "it": "any", "imm": "VecDListImm(SdList)"},
|
|
{"inst": "vmax.f16 Dd, Dn, Dm" , "t32": "1110|11110|Vd'|01|Vn|Vd|1111|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD FP16", "it": "out"},
|
|
{"inst": "vmax.f16 Vd, Vn, Vm" , "t32": "1110|11110|Vd'|01|Vn|Vd|1111|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD FP16", "it": "out"},
|
|
{"inst": "vmax.f32 Dd, Dn, Dm" , "t32": "1110|11110|Vd'|00|Vn|Vd|1111|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "it": "out"},
|
|
{"inst": "vmax.f32 Vd, Vn, Vm" , "t32": "1110|11110|Vd'|00|Vn|Vd|1111|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD", "it": "out"},
|
|
{"inst": "vmax.x8-32 Dd, Dn, Dm" , "t32": "111U|11110|Vd'|sz|Vn|Vd|0110|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vmax.x8-32 Vd, Vn, Vm" , "t32": "111U|11110|Vd'|sz|Vn|Vd|0110|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vmaxnm.f16 Sd, Sn, Sm" , "t32": "1111|11101|'Vd|00|Vn|Vd|10|01|'Vn|0|'Vm|0|Vm" , "ext": "ARMv8+ FP16", "it": "out"},
|
|
{"inst": "vmaxnm.f32 Sd, Sn, Sm" , "t32": "1111|11101|'Vd|00|Vn|Vd|10|10|'Vn|0|'Vm|0|Vm" , "ext": "ARMv8+", "it": "out"},
|
|
{"inst": "vmaxnm.f64 Dd, Dn, Dm" , "t32": "1111|11101|Vd'|00|Vn|Vd|10|11|Vn'|0|Vm'|0|Vm" , "ext": "ARMv8+", "it": "out"},
|
|
{"inst": "vmaxnm.f16 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|01|Vn|Vd|1111|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD FP16", "it": "out"},
|
|
{"inst": "vmaxnm.f16 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|01|Vn|Vd|1111|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD FP16", "it": "out"},
|
|
{"inst": "vmaxnm.f32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|00|Vn|Vd|1111|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD", "it": "out"},
|
|
{"inst": "vmaxnm.f32 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|00|Vn|Vd|1111|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD", "it": "out"},
|
|
{"inst": "vmin.f16 Dd, Dn, Dm" , "t32": "1110|11110|Vd'|11|Vn|Vd|1111|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD FP16", "it": "out"},
|
|
{"inst": "vmin.f16 Vd, Vn, Vm" , "t32": "1110|11110|Vd'|11|Vn|Vd|1111|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD FP16", "it": "out"},
|
|
{"inst": "vmin.f32 Dd, Dn, Dm" , "t32": "1110|11110|Vd'|10|Vn|Vd|1111|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "it": "out"},
|
|
{"inst": "vmin.f32 Vd, Vn, Vm" , "t32": "1110|11110|Vd'|10|Vn|Vd|1111|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD", "it": "out"},
|
|
{"inst": "vmin.x8-32 Dd, Dn, Dm" , "t32": "111U|11110|Vd'|sz|Vn|Vd|0110|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vmin.x8-32 Vd, Vn, Vm" , "t32": "111U|11110|Vd'|sz|Vn|Vd|0110|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vminnm.f16 Sd, Sn, Sm" , "t32": "1111|11101|'Vd|00|Vn|Vd|10|01|'Vn|1|'Vm|0|Vm" , "ext": "ARMv8+ FP16", "it": "out"},
|
|
{"inst": "vminnm.f32 Sd, Sn, Sm" , "t32": "1111|11101|'Vd|00|Vn|Vd|10|10|'Vn|1|'Vm|0|Vm" , "ext": "ARMv8+", "it": "out"},
|
|
{"inst": "vminnm.f64 Dd, Dn, Dm" , "t32": "1111|11101|Vd'|00|Vn|Vd|10|11|Vn'|1|Vm'|0|Vm" , "ext": "ARMv8+", "it": "out"},
|
|
{"inst": "vminnm.f16 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|11|Vn|Vd|1111|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD FP16", "it": "out"},
|
|
{"inst": "vminnm.f16 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|11|Vn|Vd|1111|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD FP16", "it": "out"},
|
|
{"inst": "vminnm.f32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|10|Vn|Vd|1111|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD", "it": "out"},
|
|
{"inst": "vminnm.f32 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|10|Vn|Vd|1111|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD", "it": "out"},
|
|
{"inst": "vmla.f16 Dx, Dn, Dm" , "t32": "1110|11110|Vx'|01|Vn|Vx|1101|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vmla.f16 Vx, Vn, Vm" , "t32": "1110|11110|Vx'|01|Vn|Vx|1101|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vmla.f32 Dx, Dn, Dm" , "t32": "1110|11110|Vx'|00|Vn|Vx|1101|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vmla.f32 Vx, Vn, Vm" , "t32": "1110|11110|Vx'|00|Vn|Vx|1101|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vmla.x8-32 Dx, Dn, Dm" , "t32": "1110|11110|Vx'|sz|Vn|Vx|1001|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vmla.x8-32 Vx, Vn, Vm" , "t32": "1110|11110|Vx'|sz|Vn|Vx|1001|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vmla.f16 Dx, Dn, Dm<=07[#i]" , "t32": "1110|11111|Vx'|01|Vn|Vx|0001|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "FP16"},
|
|
{"inst": "vmla.f16 Vx, Vn, Dm<=07[#i]" , "t32": "1111|11111|Vx'|01|Vn|Vx|0001|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "FP16"},
|
|
{"inst": "vmla.f32 Dx, Dn, Dm<=15[#i]" , "t32": "1110|11111|Vx'|10|Vn|Vx|0001|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vmla.f32 Vx, Vn, Dm<=15[#i]" , "t32": "1111|11111|Vx'|10|Vn|Vx|0001|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vmla.x16 Dx, Dn, Dm<=07[#i]" , "t32": "1110|11111|Vx'|01|Vn|Vx|0000|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD"},
|
|
{"inst": "vmla.x16 Vx, Vn, Dm<=07[#i]" , "t32": "1111|11111|Vx'|01|Vn|Vx|0000|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD"},
|
|
{"inst": "vmla.x32 Dx, Dn, Dm<=15[#i]" , "t32": "1110|11111|Vx'|10|Vn|Vx|0000|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vmla.x32 Vx, Vn, Dm<=15[#i]" , "t32": "1111|11111|Vx'|10|Vn|Vx|0000|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vmlal.x8-32 Vx, Dn, Dm" , "t32": "111U|11111|Vx'|sz|Vn|Vx|1000|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "widen"},
|
|
{"inst": "vmlal.x16 Vx, Dn, Dm<=07[#i]" , "t32": "111U|11111|Vx'|01|Vn|Vx|0010|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD", "vecOp": "widen"},
|
|
{"inst": "vmlal.x32 Vx, Dn, Dm<=15[#i]" , "t32": "111U|11111|Vx'|10|Vn|Vx|0010|Vn'|1|i:1|0|Vm" , "ext": "ASIMD", "vecOp": "widen"},
|
|
{"inst": "vmls.f16 Dx, Dn, Dm" , "t32": "1110|11110|Vx'|11|Vn|Vx|1101|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vmls.f16 Vx, Vn, Vm" , "t32": "1110|11110|Vx'|11|Vn|Vx|1101|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vmls.f32 Dx, Dn, Dm" , "t32": "1110|11110|Vx'|10|Vn|Vx|1101|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vmls.f32 Vx, Vn, Vm" , "t32": "1110|11110|Vx'|10|Vn|Vx|1101|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vmls.x8-32 Dx, Dn, Dm" , "t32": "1111|11110|Vx'|sz|Vn|Vx|1001|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vmls.x8-32 Vx, Vn, Vm" , "t32": "1111|11110|Vx'|sz|Vn|Vx|1001|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vmls.f16 Dx, Dn, Dm<=07[#i]" , "t32": "1110|11111|Vx'|01|Vn|Vx|0101|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD"},
|
|
{"inst": "vmls.f16 Vx, Vn, Dm<=07[#i]" , "t32": "1111|11111|Vx'|01|Vn|Vx|0101|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD"},
|
|
{"inst": "vmls.f32 Dx, Dn, Dm<=15[#i]" , "t32": "1110|11111|Vx'|10|Vn|Vx|0101|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vmls.f32 Vx, Vn, Dm<=15[#i]" , "t32": "1111|11111|Vx'|10|Vn|Vx|0101|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vmls.x16 Dx, Dn, Dm<=07[#i]" , "t32": "1110|11111|Vx'|01|Vn|Vx|0100|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD"},
|
|
{"inst": "vmls.x16 Vx, Vn, Dm<=07[#i]" , "t32": "1111|11111|Vx'|01|Vn|Vx|0100|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD"},
|
|
{"inst": "vmls.x32 Dx, Dn, Dm<=15[#i]" , "t32": "1110|11111|Vx'|10|Vn|Vx|0100|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vmls.x32 Vx, Vn, Dm<=15[#i]" , "t32": "1111|11111|Vx'|10|Vn|Vx|0100|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vmlsl.x8-32 Vx, Dn, Dm" , "t32": "111U|11111|Vx'|sz|Vn|Vx|1010|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "widen"},
|
|
{"inst": "vmlsl.x16 Vx, Dn, Dm<=07[#i]" , "t32": "111U|11111|Vx'|01|Vn|Vx|0110|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD", "vecOp": "widen"},
|
|
{"inst": "vmlsl.x32 Vx, Dn, Dm<=15[#i]" , "t32": "111U|11111|Vx'|10|Vn|Vx|0110|Vn'|1|i:1|0|Vm" , "ext": "ASIMD", "vecOp": "widen"},
|
|
{"inst": "vmov Rd!=PC, Sn" , "t32": "1110|11100|0|01|Vn|Rd|1010|'Vn|00|1|0000" , "ext": "ASIMD"},
|
|
{"inst": "vmov Sd, Rn!=PC" , "t32": "1110|11100|0|00|Vd|Rn|1010|'Vd|00|1|0000" , "ext": "ASIMD"},
|
|
{"inst": "vmov Rd!=PC, Rd2!=PC, Ss!=31, Ss2+" , "t32": "1110|11000|1|01|Rd2|Rd|101|000|'Vs|1|Vs" , "ext": "ASIMD"},
|
|
{"inst": "vmov Sd!=31, Sd2+, Rs!=PC, Rs2!=PC" , "t32": "1110|11000|1|00|Rs2|Rs|101|000|'Vd|1|Vd" , "ext": "ASIMD"},
|
|
{"inst": "vmov Rd!=PC, Rd2!=PC, Ds" , "t32": "1110|11000|1|01|Rd2|Rd|1011|0|0|Vs'|1|Vs" , "ext": "ASIMD"},
|
|
{"inst": "vmov Dd, Rs!=PC, Rs2!=PC" , "t32": "1110|11000|1|00|Rs2|Rs|1011|0|0|Vd'|1|Vd" , "ext": "ASIMD"},
|
|
{"inst": "vmov.x8 Dd[#i], Rn!=PC" , "t32": "1110|11100|1|i:1|0|Vd|Rn|1011|Vd'|i:2|1|0000" , "ext": "ASIMD"},
|
|
{"inst": "vmov.x16 Dd[#i], Rn!=PC" , "t32": "1110|11100|0|i:1|0|Vd|Rn|1011|Vd'|i:1|110000" , "ext": "ASIMD"},
|
|
{"inst": "vmov.x32 Dd[#i], Rn!=PC" , "t32": "1110|11100|0|i:1|0|Vd|Rn|1011|Vd'|001|0000" , "ext": "ASIMD"},
|
|
{"inst": "vmov.x8 Rd!=PC, Dn[#i]" , "t32": "1110|1110U|1|i:1|1|Vn|Rd|1011|Vn'|i:2|1|0000" , "ext": "ASIMD"},
|
|
{"inst": "vmov.x16 Rd!=PC, Dn[#i]" , "t32": "1110|1110U|0|i:1|1|Vn|Rd|1011|Vn'|i:1|110000" , "ext": "ASIMD"},
|
|
{"inst": "vmov.x32 Rd!=PC, Dn[#i]" , "t32": "1110|11100|0|i:1|1|Vn|Rd|1011|Vn'|001|0000" , "ext": "ASIMD"},
|
|
{"inst": "vmov.any Dd, Dn" , "t32": "1110|11110|Vd'|10|Vn[3:0]|Vd|0001|Vn[4]|0|Vn[4]|1|Vn[3:0]", "ext": "ASIMD", "aliasOf": "vorr"},
|
|
{"inst": "vmov.any Vd, Vn" , "t32": "1110|11110|Vd'|10|Vn[3:0]|Vd|0001|Vn[4]|1|Vn[4]|1|Vn[3:0]", "ext": "ASIMD", "aliasOf": "vorr"},
|
|
{"inst": "vmov.x8-64 Dd, #immV" , "t32": "111|imm:1|11111|Vd'|000|imm:3|Vd|cmode:4|00|op|1|imm:4" , "ext": "ASIMD", "imm": "VecMovImm(sz, 0, immV)"},
|
|
{"inst": "vmov.x8-64 Vd, #immV" , "t32": "111|imm:1|11111|Vd'|000|imm:3|Vd|cmode:4|01|op|1|imm:4" , "ext": "ASIMD", "imm": "VecMovImm(sz, 0, immV)"},
|
|
{"inst": "vmovl.x8 Vd, Dn" , "t32": "111U|11111|Vd'|00|1000|Vd|1010|0|0|Vn'|1|Vn" , "ext": "ASIMD", "vecOp": "widen"},
|
|
{"inst": "vmovl.x16 Vd, Dn" , "t32": "111U|11111|Vd'|01|0000|Vd|1010|0|0|Vn'|1|Vn" , "ext": "ASIMD", "vecOp": "widen"},
|
|
{"inst": "vmovl.x32 Vd, Dn" , "t32": "111U|11111|Vd'|10|0000|Vd|1010|0|0|Vn'|1|Vn" , "ext": "ASIMD", "vecOp": "widen"},
|
|
{"inst": "vmovn.x16-64 Dd, Vn" , "t32": "1111|11111|Vd'|11|szM1:2|10|Vd|0010|00|Vn'|0|Vn" , "ext": "ASIMD", "vecOp": "narrow"},
|
|
{"inst": "vmul.f16 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|01|Vn|Vd|1101|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vmul.f16 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|01|Vn|Vd|1101|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vmul.f32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|00|Vn|Vd|1101|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vmul.f32 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|00|Vn|Vd|1101|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vmul.x8-32|p8 Dd, Dn, Dm" , "t32": "111P|11110|Vd'|sz|Vn|Vd|1001|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vmul.x8-32|p8 Vd, Vn, Vm" , "t32": "111P|11110|Vd'|sz|Vn|Vd|1001|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vmul.f32 Dd, Dn, Dm<=15[#i]" , "t32": "1110|11111|Vd'|10|Vn|Vd|1001|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vmul.f32 Vd, Vn, Dm<=15[#i]" , "t32": "1111|11111|Vd'|10|Vn|Vd|1001|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vmul.x16 Dd, Dn, Dm<=07[#i]" , "t32": "1110|11111|Vd'|01|Vn|Vd|1000|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD"},
|
|
{"inst": "vmul.x16 Vd, Vn, Dm<=07[#i]" , "t32": "1111|11111|Vd'|01|Vn|Vd|1000|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD"},
|
|
{"inst": "vmul.x32 Dd, Dn, Dm<=15[#i]" , "t32": "1110|11111|Vd'|10|Vn|Vd|1000|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vmul.x32 Vd, Vn, Dm<=15[#i]" , "t32": "1111|11111|Vd'|10|Vn|Vd|1000|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vmull.x8-32|p8 Vd, Dn, Dm" , "t32": "111U|11111|Vd'|sz|Vn|Vd|11P0|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "widen"},
|
|
{"inst": "vmull.p64 Vd, Dn, Dm" , "t32": "1110|11111|Vd'|10|Vn|Vd|11P0|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "widen"},
|
|
{"inst": "vmull.x16 Vd, Dn, Dm<=07[#i]" , "t32": "111U|11111|Vd'|01|Vn|Vd|1010|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD", "vecOp": "widen"},
|
|
{"inst": "vmull.x32 Vd, Dn, Dm<=15[#i]" , "t32": "111U|11111|Vd'|10|Vn|Vd|1010|Vn'|1|i:1|0|Vm" , "ext": "ASIMD", "vecOp": "widen"},
|
|
{"inst": "vmvn.any Dd, #immV" , "t32": "111|imm:1|11111|Vd'|000|imm:3|Vd|cmode:4|00|op|1|imm:4" , "ext": "ASIMD", "imm": "VecMovImm(sz, 1, immV)"},
|
|
{"inst": "vmvn.any Vd, #immV" , "t32": "111|imm:1|11111|Vd'|000|imm:3|Vd|cmode:4|01|op|1|imm:4" , "ext": "ASIMD", "imm": "VecMovImm(sz, 1, immV)"},
|
|
{"inst": "vmvn.any Dd, Dn" , "t32": "1111|11111|Vd'|11|0000|Vd|0101|10|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vmvn.any Vd, Vn" , "t32": "1111|11111|Vd'|11|0000|Vd|0101|11|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vneg.f16 Dd, Dn" , "t32": "1111|11111|Vd'|11|sz|01|Vd|0111|10|Vn'|0|Vn" , "ext": "ASIMD FP16", "it": "out"},
|
|
{"inst": "vneg.f16 Vd, Vn" , "t32": "1111|11111|Vd'|11|sz|01|Vd|0111|11|Vn'|0|Vn" , "ext": "ASIMD FP16", "it": "out"},
|
|
{"inst": "vneg.f32 Dd, Dn" , "t32": "1111|11111|Vd'|11|sz|01|Vd|0111|10|Vn'|0|Vn" , "ext": "ASIMD", "it": "out"},
|
|
{"inst": "vneg.f32 Vd, Vn" , "t32": "1111|11111|Vd'|11|sz|01|Vd|0111|11|Vn'|0|Vn" , "ext": "ASIMD", "it": "out"},
|
|
{"inst": "vneg.s8-32 Dd, Dn" , "t32": "1111|11111|Vd'|11|sz|01|Vd|0011|10|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vneg.s8-32 Vd, Vn" , "t32": "1111|11111|Vd'|11|sz|01|Vd|0011|11|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vorn.x16-64 Dx, #immV" , "t32": "111|imm:1|11111|Vx'|000|imm:3|Vx|cmode:4|0001|imm:4" , "ext": "ASIMD", "imm": "VecBicOrrImm(sz, 1, immV)", "pseudoOf": "vorr"},
|
|
{"inst": "vorn.x16-64 Vx, #immV" , "t32": "111|imm:1|11111|Vx'|000|imm:3|Vx|cmode:4|0101|imm:4" , "ext": "ASIMD", "imm": "VecBicOrrImm(sz, 1, immV)", "pseudoOf": "vorr"},
|
|
{"inst": "vorn.any Dd, Dn, Dm" , "t32": "1110|11110|Vd'|11|Vn|Vd|0001|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vorn.any Vd, Vn, Vm" , "t32": "1110|11110|Vd'|11|Vn|Vd|0001|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vorr.x16-64 Dx, #immV" , "t32": "111|imm:1|11111|Vx'|000|imm:3|Vx|cmode:4|0001|imm:4" , "ext": "ASIMD", "imm": "VecBicOrrImm(sz, 0, immV)"},
|
|
{"inst": "vorr.x16-64 Vx, #immV" , "t32": "111|imm:1|11111|Vx'|000|imm:3|Vx|cmode:4|0101|imm:4" , "ext": "ASIMD", "imm": "VecBicOrrImm(sz, 0, immV)"},
|
|
{"inst": "vorr.any Dd, Dn, Dm" , "t32": "1110|11110|Vd'|10|Vn|Vd|0001|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vorr.any Vd, Vn, Vm" , "t32": "1110|11110|Vd'|10|Vn|Vd|0001|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vpadal.x8-32 Dx, Dn" , "t32": "1111|11111|Vx'|11|sz|00|Vx|0110|U|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vpadal.x8-32 Vx, Vn" , "t32": "1111|11111|Vx'|11|sz|00|Vx|0110|U|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vpadd.f16 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|01|Vn|Vd|1101|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD FP16", "it": "out"},
|
|
{"inst": "vpadd.f32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|00|Vn|Vd|1101|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "it": "out"},
|
|
{"inst": "vpaddl.x8-32 Dd, Dn" , "t32": "1111|11111|Vd'|11|sz|00|Vd|0010|U|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vpaddl.x8-32 Vd, Vn" , "t32": "1111|11111|Vd'|11|sz|00|Vd|0010|U|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vpmax.f16 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|01|Vn|Vd|1111|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD FP16", "it": "out"},
|
|
{"inst": "vpmax.f32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|00|Vn|Vd|1111|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "it": "out"},
|
|
{"inst": "vpmax.x8-32 Dd, Dn, Dm" , "t32": "111U|11110|Vd'|sz|Vn|Vd|1010|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vpmin.f16 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|11|Vn|Vd|1111|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD FP16", "it": "out"},
|
|
{"inst": "vpmin.f32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|10|Vn|Vd|1111|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "it": "out"},
|
|
{"inst": "vpmin.x8-32 Dd, Dn, Dm" , "t32": "111U|11110|Vd'|sz|Vn|Vd|1010|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vpop.32 SdList" , "t32": "1110|11001|immVd[0]|11|1101|immVd[4:1]|1010|immCount:8" , "ext": "ASIMD", "it": "any", "imm": "VecSListImm(SdList)"},
|
|
{"inst": "vpop.64 DdList" , "t32": "1110|11001|immVd[4]|11|1101|immVd[3:0]|1011|immCount:8" , "ext": "ASIMD", "it": "any", "imm": "VecDListImm(SdList)"},
|
|
{"inst": "vpush.32 SdList" , "t32": "1110|11010|immVd[0]|10|1101|immVd[4:1]|1010|immCount:8" , "ext": "ASIMD", "it": "any", "imm": "VecSListImm(SdList)"},
|
|
{"inst": "vpush.64 DdList" , "t32": "1110|11010|immVd[4]|10|1101|immVd[3:0]|1011|immCount:8" , "ext": "ASIMD", "it": "any", "imm": "VecDListImm(SdList)"},
|
|
{"inst": "vqabs.s8-32 Dd, Dn" , "t32": "1111|11111|Vd'|11|sz|00|Vd|0111|0|0|Vn'|0|Vn" , "ext": "ASIMD", "fpcsr": "Q=X"},
|
|
{"inst": "vqabs.s8-32 Vd, Vn" , "t32": "1111|11111|Vd'|11|sz|00|Vd|0111|0|1|Vn'|0|Vn" , "ext": "ASIMD", "fpcsr": "Q=X"},
|
|
{"inst": "vqadd.x8-64 Dd, Dn, Dm" , "t32": "111U|11110|Vd'|sz|Vn|Vd|0000|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"},
|
|
{"inst": "vqadd.x8-64 Vd, Vn, Vm" , "t32": "111U|11110|Vd'|sz|Vn|Vd|0000|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"},
|
|
{"inst": "vqdmlal.s16-32 Vx, Dn, Dm" , "t32": "1110|11111|Vx'|sz|Vn|Vx|1001|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "widen"},
|
|
{"inst": "vqdmlal.s16 Vx, Dn, Dm<=07[#i]" , "t32": "1110|11111|Vx'|01|Vn|Vx|0011|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "widen"},
|
|
{"inst": "vqdmlal.s32 Vx, Dn, Dm<=15[#i]" , "t32": "1110|11111|Vx'|10|Vn|Vx|0011|Vn'|1|i:1|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "widen"},
|
|
{"inst": "vqdmlsl.s16-32 Vx, Dn, Dm" , "t32": "1110|11111|Vx'|sz|Vn|Vx|1011|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "widen"},
|
|
{"inst": "vqdmlsl.s16 Vx, Dn, Dm<=07[#i]" , "t32": "1110|11111|Vx'|01|Vn|Vx|0111|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "widen"},
|
|
{"inst": "vqdmlsl.s32 Vx, Dn, Dm<=15[#i]" , "t32": "1110|11111|Vx'|10|Vn|Vx|0111|Vn'|1|i:1|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "widen"},
|
|
{"inst": "vqdmulh.s16-32 Dd, Dn, Dm" , "t32": "1110|11110|Vd'|sz|Vn|Vd|1011|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"},
|
|
{"inst": "vqdmulh.s16-32 Vd, Vn, Vm" , "t32": "1110|11110|Vd'|sz|Vn|Vd|1011|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"},
|
|
{"inst": "vqdmulh.s16 Dd, Dn, Dm<=07[#i]" , "t32": "1110|11111|Vd'|01|Vn|Vd|1100|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD", "fpcsr": "Q=X"},
|
|
{"inst": "vqdmulh.s16 Vd, Vn, Dm<=07[#i]" , "t32": "1111|11111|Vd'|01|Vn|Vd|1100|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD", "fpcsr": "Q=X"},
|
|
{"inst": "vqdmulh.s32 Dd, Dn, Dm<=15[#i]" , "t32": "1110|11111|Vd'|10|Vn|Vd|1100|Vn'|1|i:1|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"},
|
|
{"inst": "vqdmulh.s32 Vd, Vn, Dm<=15[#i]" , "t32": "1111|11111|Vd'|10|Vn|Vd|1100|Vn'|1|i:1|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"},
|
|
{"inst": "vqdmull.s16-32 Vd, Dn, Dm" , "t32": "1110|11111|Vd'|sz|Vn|Vd|1101|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "widen"},
|
|
{"inst": "vqdmull.s16 Vd, Dn, Dm<=07[#i]" , "t32": "1110|11111|Vd'|01|Vn|Vd|1011|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "widen"},
|
|
{"inst": "vqdmull.s32 Vd, Dn, Dm<=15[#i]" , "t32": "1110|11111|Vd'|10|Vn|Vd|1011|Vn'|1|i:1|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "widen"},
|
|
{"inst": "vqmovn.x16-64 Dd, Vn" , "t32": "1111|11111|Vd'|11|szM1:2|10|Vd|0010|1|U|Vn'|0|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "narrow"},
|
|
{"inst": "vqmovun.s16-64 Dd, Vn" , "t32": "1111|11111|Vd'|11|szM1:2|10|Vd|0010|0|1|Vn'|0|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "narrow"},
|
|
{"inst": "vqneg.s8-32 Dd, Dn" , "t32": "1111|11111|Vd'|11|sz|00|Vd|0111|1|0|Vn'|0|Vn" , "ext": "ASIMD", "fpcsr": "Q=X"},
|
|
{"inst": "vqneg.s8-32 Vd, Vn" , "t32": "1111|11111|Vd'|11|sz|00|Vd|0111|1|1|Vn'|0|Vn" , "ext": "ASIMD", "fpcsr": "Q=X"},
|
|
{"inst": "vqrdmulh.s16-32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|sz|Vn|Vd|1011|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"},
|
|
{"inst": "vqrdmulh.s16-32 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|sz|Vn|Vd|1011|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"},
|
|
{"inst": "vqrdmulh.s16 Dd, Dn, Dm<=07[#i]" , "t32": "1110|11111|Vd'|01|Vn|Vd|1101|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD", "fpcsr": "Q=X"},
|
|
{"inst": "vqrdmulh.s16 Vd, Vn, Dm<=07[#i]" , "t32": "1111|11111|Vd'|01|Vn|Vd|1101|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD", "fpcsr": "Q=X"},
|
|
{"inst": "vqrdmulh.s32 Dd, Dn, Dm<=15[#i]" , "t32": "1110|11111|Vd'|10|Vn|Vd|1101|Vn'|1|i:1|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"},
|
|
{"inst": "vqrdmulh.s32 Vd, Vn, Dm<=15[#i]" , "t32": "1111|11111|Vd'|10|Vn|Vd|1101|Vn'|1|i:1|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"},
|
|
{"inst": "vqrshl.x8-64 Dd, Dn, Dm" , "t32": "111U|11110|Vd'|sz|Vm|Vd|0101|Vm'|0|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X"},
|
|
{"inst": "vqrshl.x8-64 Vd, Vn, Vm" , "t32": "111U|11110|Vd'|sz|Vm|Vd|0101|Vm'|1|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X"},
|
|
{"inst": "vqrshrn.x16-64 Dd, Vn, #zero" , "t32": "1111|11111|Vd'|11|szM1:2|10|Vd|0010|1U|Vn'|0|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "narrow"},
|
|
{"inst": "vqrshrn.x16-64 Dd, Vn, #n" , "t32": "111U|11111|Vd'|imm:6|Vd|1001|01|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "imm": "VecShiftNarrowImm(sz, n)", "vecOp": "narrow"},
|
|
{"inst": "vqrshrun.s16-64 Dd, Vn, #zero" , "t32": "1111|11111|Vd'|11|szM1:2|10|Vd|0010|01|Vn'|0|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "narrow"},
|
|
{"inst": "vqrshrun.s16-64 Dd, Vn, #n" , "t32": "1111|11111|Vd'|imm:6|Vd|1000|01|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "imm": "VecShiftNarrowImm(sz, n)", "vecOp": "narrow"},
|
|
{"inst": "vqshl.x8-64 Dd, Dn, Dm" , "t32": "111U|11110|Vd'|sz|Vm|Vd|0100|Vm'|0|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X"},
|
|
{"inst": "vqshl.x8-64 Vd, Vn, Vm" , "t32": "111U|11110|Vd'|sz|Vm|Vd|0100|Vm'|1|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X"},
|
|
{"inst": "vqshl.x8-64 Dd, Dn, #n" , "t32": "111U|11111|Vd'|imm[5:0]|Vd|0111|imm[6]|0|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "imm": "VecShiftPImm(sz, n)"},
|
|
{"inst": "vqshl.x8-64 Vd, Vn, #n" , "t32": "111U|11111|Vd'|imm[5:0]|Vd|0111|imm[6]|1|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "imm": "VecShiftPImm(sz, n)"},
|
|
{"inst": "vqshlu.s8-64 Dd, Dn, #n" , "t32": "1111|11111|Vd'|imm[5:0]|Vd|0110|imm[6]|0|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "imm": "VecShiftPImm(sz, n)"},
|
|
{"inst": "vqshlu.s8-64 Vd, Vn, #n" , "t32": "1111|11111|Vd'|imm[5:0]|Vd|0110|imm[6]|1|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "imm": "VecShiftPImm(sz, n)"},
|
|
{"inst": "vqshrn.x16-64 Dd, Vn, #zero" , "t32": "1111|11111|Vd'|11|szM1:2|10|Vd|0010|1U|Vn'|0|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "narrow"},
|
|
{"inst": "vqshrn.x16-64 Dd, Vn, #n" , "t32": "111U|11111|Vd'|imm:6|Vd|1001|0|0|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "imm": "VecShiftNarrowImm(sz, n)", "vecOp": "narrow"},
|
|
{"inst": "vqshrun.s16-64 Dd, Vn, #zero" , "t32": "1111|11111|Vd'|11|szM1:2|10|Vd|0010|01|Vn'|0|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "narrow"},
|
|
{"inst": "vqshrun.s16-64 Dd, Vn, #n" , "t32": "1111|11111|Vd'|imm:6|Vd|1000|0|0|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "imm": "VecShiftNarrowImm(sz, n)", "vecOp": "narrow"},
|
|
{"inst": "vqsub.x8-64 Dd, Dn, Dm" , "t32": "111U|11110|Vd'|sz|Vn|Vd|0010|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"},
|
|
{"inst": "vqsub.x8-64 Vd, Vn, Vm" , "t32": "111U|11110|Vd'|sz|Vn|Vd|0010|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"},
|
|
{"inst": "vraddhn.x16-64 Dd, Vn, Vm" , "t32": "1111|11111|Vd'|szM1:2|Vn|Vd|0100|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "narrow"},
|
|
{"inst": "vrecpe.f16 Dd, Dn" , "t32": "1111|11111|Vd'|11|01|11|Vd|0101|0|0|Vn'|0|Vn" , "ext": "ASIMD FP16"},
|
|
{"inst": "vrecpe.f16 Vd, Vn" , "t32": "1111|11111|Vd'|11|01|11|Vd|0101|0|1|Vn'|0|Vn" , "ext": "ASIMD FP16"},
|
|
{"inst": "vrecpe.f32 Dd, Dn" , "t32": "1111|11111|Vd'|11|10|11|Vd|0101|0|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vrecpe.f32 Vd, Vn" , "t32": "1111|11111|Vd'|11|10|11|Vd|0101|0|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vrecpe.u32 Dd, Dn" , "t32": "1111|11111|Vd'|11|10|11|Vd|0100|0|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vrecpe.u32 Vd, Vn" , "t32": "1111|11111|Vd'|11|10|11|Vd|0100|0|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vrecps.f16 Dd, Dn, Dm" , "t32": "1110|11110|Vd'|01|Vn|Vd|1111|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vrecps.f16 Vd, Vn, Vm" , "t32": "1110|11110|Vd'|01|Vn|Vd|1111|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vrecps.f32 Dd, Dn, Dm" , "t32": "1110|11110|Vd'|00|Vn|Vd|1111|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vrecps.f32 Vd, Vn, Vm" , "t32": "1110|11110|Vd'|00|Vn|Vd|1111|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vrev16.x8 Dd, Dn" , "t32": "1111|11111|Vd'|11|00|00|Vd|0001|0|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vrev16.x8 Vd, Vn" , "t32": "1111|11111|Vd'|11|00|00|Vd|0001|0|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vrev32.x8-16 Dd, Dn" , "t32": "1111|11111|Vd'|11|sz|00|Vd|0000|1|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vrev32.x8-16 Vd, Vn" , "t32": "1111|11111|Vd'|11|sz|00|Vd|0000|1|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vrev64.x8-32 Dd, Dn" , "t32": "1111|11111|Vd'|11|sz|00|Vd|0000|0|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vrev64.x8-32 Vd, Vn" , "t32": "1111|11111|Vd'|11|sz|00|Vd|0000|0|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vrhadd.x8-32 Dd, Dn, Dm" , "t32": "111U|11110|Vd'|sz|Vn|Vd|0001|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vrhadd.x8-32 Vd, Vn, Vm" , "t32": "111U|11110|Vd'|sz|Vn|Vd|0001|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vrinta.f16 Sd, Sn" , "t32": "1111|11101|'Vd|11|10|00|Vd|10|01|01|'Vn|0|Vn" , "ext": "ARMv8+ FP16", "it": "out"},
|
|
{"inst": "vrinta.f32 Sd, Sn" , "t32": "1111|11101|'Vd|11|10|00|Vd|10|10|01|'Vn|0|Vn" , "ext": "ARMv8+", "it": "out"},
|
|
{"inst": "vrinta.f64 Dd, Dn" , "t32": "1111|11101|Vd'|11|10|00|Vd|10|11|01|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vrinta.f16 Dd, Dn" , "t32": "1111|11111|Vd'|11|01|10|Vd|01|01|00|Vn'|0|Vn" , "ext": "ARMv8+ FP16", "it": "out"},
|
|
{"inst": "vrinta.f16 Vd, Vn" , "t32": "1111|11111|Vd'|11|01|10|Vd|01|01|01|Vn'|0|Vn" , "ext": "ARMv8+ FP16"},
|
|
{"inst": "vrinta.f32 Dd, Dn" , "t32": "1111|11111|Vd'|11|10|10|Vd|01|01|00|Vn'|0|Vn" , "ext": "ARMv8+", "it": "out"},
|
|
{"inst": "vrinta.f32 Vd, Vn" , "t32": "1111|11111|Vd'|11|10|10|Vd|01|01|01|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vrintm.f16 Sd, Sn" , "t32": "1111|11101|'Vd|11|10|11|Vd|10|01|01|'Vn|0|Vn" , "ext": "ARMv8+ FP16", "it": "out"},
|
|
{"inst": "vrintm.f32 Sd, Sn" , "t32": "1111|11101|'Vd|11|10|11|Vd|10|10|01|'Vn|0|Vn" , "ext": "ARMv8+", "it": "out"},
|
|
{"inst": "vrintm.f64 Dd, Dn" , "t32": "1111|11101|Vd'|11|10|11|Vd|10|11|01|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vrintm.f16 Dd, Dn" , "t32": "1111|11111|Vd'|11|01|10|Vd|01|10|10|Vn'|0|Vn" , "ext": "ARMv8+ FP16", "it": "out"},
|
|
{"inst": "vrintm.f16 Vd, Vn" , "t32": "1111|11111|Vd'|11|01|10|Vd|01|10|11|Vn'|0|Vn" , "ext": "ARMv8+ FP16", "it": "out"},
|
|
{"inst": "vrintm.f32 Dd, Dn" , "t32": "1111|11111|Vd'|11|10|10|Vd|01|10|10|Vn'|0|Vn" , "ext": "ARMv8+", "it": "out"},
|
|
{"inst": "vrintm.f32 Vd, Vn" , "t32": "1111|11111|Vd'|11|10|10|Vd|01|10|11|Vn'|0|Vn" , "ext": "ARMv8+", "it": "out"},
|
|
{"inst": "vrintn.f16 Sd, Sn" , "t32": "1111|11101|'Vd|11|10|01|Vd|10|01|01|'Vn|0|Vn" , "ext": "ARMv8+ FP16", "it": "out"},
|
|
{"inst": "vrintn.f32 Sd, Sn" , "t32": "1111|11101|'Vd|11|10|01|Vd|10|10|01|'Vn|0|Vn" , "ext": "ARMv8+", "it": "out"},
|
|
{"inst": "vrintn.f64 Dd, Dn" , "t32": "1111|11101|Vd'|11|10|01|Vd|10|11|01|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vrintn.f16 Dd, Dn" , "t32": "1111|11111|Vd'|11|01|10|Vd|01|00|00|Vn'|0|Vn" , "ext": "ARMv8+ FP16", "it": "out"},
|
|
{"inst": "vrintn.f16 Vd, Vn" , "t32": "1111|11111|Vd'|11|01|10|Vd|01|00|01|Vn'|0|Vn" , "ext": "ARMv8+ FP16", "it": "out"},
|
|
{"inst": "vrintn.f32 Dd, Dn" , "t32": "1111|11111|Vd'|11|10|10|Vd|01|00|00|Vn'|0|Vn" , "ext": "ARMv8+", "it": "out"},
|
|
{"inst": "vrintn.f32 Vd, Vn" , "t32": "1111|11111|Vd'|11|10|10|Vd|01|00|01|Vn'|0|Vn" , "ext": "ARMv8+", "it": "out"},
|
|
{"inst": "vrintp.f16 Sd, Sn" , "t32": "1111|11101|'Vd|11|10|10|Vd|10|01|01|'Vn|0|Vn" , "ext": "ARMv8+ FP16", "it": "out"},
|
|
{"inst": "vrintp.f32 Sd, Sn" , "t32": "1111|11101|'Vd|11|10|10|Vd|10|10|01|'Vn|0|Vn" , "ext": "ARMv8+", "it": "out"},
|
|
{"inst": "vrintp.f64 Dd, Dn" , "t32": "1111|11101|Vd'|11|10|10|Vd|10|11|01|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vrintp.f16 Dd, Dn" , "t32": "1111|11111|Vd'|11|01|10|Vd|01|11|10|Vn'|0|Vn" , "ext": "ARMv8+ FP16", "it": "out"},
|
|
{"inst": "vrintp.f16 Vd, Vn" , "t32": "1111|11111|Vd'|11|01|10|Vd|01|11|11|Vn'|0|Vn" , "ext": "ARMv8+ FP16", "it": "out"},
|
|
{"inst": "vrintp.f32 Dd, Dn" , "t32": "1111|11111|Vd'|11|10|10|Vd|01|11|10|Vn'|0|Vn" , "ext": "ARMv8+", "it": "out"},
|
|
{"inst": "vrintp.f32 Vd, Vn" , "t32": "1111|11111|Vd'|11|10|10|Vd|01|11|11|Vn'|0|Vn" , "ext": "ARMv8+", "it": "out"},
|
|
{"inst": "vrintr.f16 Sd, Sn" , "t32": "1110|11101|'Vd|11|01|10|Vd|10|01|01|'Vn|0|Vn" , "ext": "ARMv8+ FP16", "it": "out"},
|
|
{"inst": "vrintr.f32 Sd, Sn" , "t32": "1110|11101|'Vd|11|01|10|Vd|10|10|01|'Vn|0|Vn" , "ext": "ARMv8+", "it": "out"},
|
|
{"inst": "vrintr.f64 Dd, Dn" , "t32": "1110|11101|Vd'|11|01|10|Vd|10|11|01|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vrintx.f16 Sd, Sn" , "t32": "1110|11101|'Vd|11|01|11|Vd|10|01|01|'Vn|0|Vn" , "ext": "ARMv8+ FP16", "it": "out"},
|
|
{"inst": "vrintx.f32 Sd, Sn" , "t32": "1110|11101|'Vd|11|01|11|Vd|10|10|01|'Vn|0|Vn" , "ext": "ARMv8+", "it": "out"},
|
|
{"inst": "vrintx.f64 Dd, Dn" , "t32": "1110|11101|Vd'|11|01|11|Vd|10|11|01|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vrintx.f16 Dd, Dn" , "t32": "1111|11111|Vd'|11|01|10|Vd|01|00|10|Vn'|0|Vn" , "ext": "ARMv8+ FP16", "it": "out"},
|
|
{"inst": "vrintx.f16 Vd, Vn" , "t32": "1111|11111|Vd'|11|01|10|Vd|01|00|11|Vn'|0|Vn" , "ext": "ARMv8+ FP16", "it": "out"},
|
|
{"inst": "vrintx.f32 Dd, Dn" , "t32": "1111|11111|Vd'|11|10|10|Vd|01|00|10|Vn'|0|Vn" , "ext": "ARMv8+", "it": "out"},
|
|
{"inst": "vrintx.f32 Vd, Vn" , "t32": "1111|11111|Vd'|11|10|10|Vd|01|00|11|Vn'|0|Vn" , "ext": "ARMv8+", "it": "out"},
|
|
{"inst": "vrintz.f16 Sd, Sn" , "t32": "1110|11101|'Vd|11|01|10|Vd|10|01|11|'Vn|0|Vn" , "ext": "ARMv8+ FP16"},
|
|
{"inst": "vrintz.f32 Sd, Sn" , "t32": "1110|11101|'Vd|11|01|10|Vd|10|10|11|'Vn|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vrintz.f64 Dd, Dn" , "t32": "1110|11101|Vd'|11|01|10|Vd|10|11|11|Vn'|0|Vn" , "ext": "ARMv8+"},
|
|
{"inst": "vrintz.f16 Dd, Dn" , "t32": "1111|11111|Vd'|11|01|10|Vd|01|01|10|Vn'|0|Vn" , "ext": "ARMv8+ FP16", "it": "out"},
|
|
{"inst": "vrintz.f16 Vd, Vn" , "t32": "1111|11111|Vd'|11|01|10|Vd|01|01|11|Vn'|0|Vn" , "ext": "ARMv8+ FP16", "it": "out"},
|
|
{"inst": "vrintz.f32 Dd, Dn" , "t32": "1111|11111|Vd'|11|10|10|Vd|01|01|10|Vn'|0|Vn" , "ext": "ARMv8+", "it": "out"},
|
|
{"inst": "vrintz.f32 Vd, Vn" , "t32": "1111|11111|Vd'|11|10|10|Vd|01|01|11|Vn'|0|Vn" , "ext": "ARMv8+", "it": "out"},
|
|
{"inst": "vrshl.x8-64 Dd, Dn, Dm" , "t32": "111U|11110|Vd'|sz|Vm|Vd|0101|Vm'|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vrshl.x8-64 Vd, Vn, Vm" , "t32": "111U|11110|Vd'|sz|Vm|Vd|0101|Vm'|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vrshr.x8-32 Dd, Dn, #zero" , "t32": "1110|11110|Vd'|10|Vd|Vd|0001|Vn'|0|Vn'|1|Vn" , "ext": "ASIMD", "pseudoOf": "vorr"},
|
|
{"inst": "vrshr.x8-32 Vd, Vn, #zero" , "t32": "1110|11110|Vd'|10|Vd|Vd|0001|Vn'|1|Vn'|1|Vn" , "ext": "ASIMD", "pseudoOf": "vorr"},
|
|
{"inst": "vrshr.x8-32 Dd, Dn, #n" , "t32": "111U|11111|Vd'|imm:6|Vd|0010|0|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNImm(sz, n)"},
|
|
{"inst": "vrshr.x8-32 Vd, Vn, #n" , "t32": "111U|11111|Vd'|imm:6|Vd|0010|0|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNImm(sz, n)"},
|
|
{"inst": "vrshrn.x16-64 Dd, Vn, #zero" , "t32": "1111|11111|Vd'|11|sz|10|Vd|0010|00|Vn'|1|Vn" , "ext": "ASIMD", "vecOp": "narrow", "pseudoOf": "vmovn"},
|
|
{"inst": "vrshrn.x16-64 Dd, Vn, #n" , "t32": "1110|11111|Vd'|imm:6|Vd|1000|0|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNarrowImm(sz, n)", "vecOp": "narrow"},
|
|
{"inst": "vrsqrte.f16 Dd, Dn" , "t32": "1111|11111|Vd'|11|01|11|Vd|01|01|10|Vn'|0|Vn" , "ext": "ASIMD FP16", "it": "out"},
|
|
{"inst": "vrsqrte.f16 Vd, Vn" , "t32": "1111|11111|Vd'|11|01|11|Vd|01|01|11|Vn'|0|Vn" , "ext": "ASIMD FP16", "it": "out"},
|
|
{"inst": "vrsqrte.f32 Dd, Dn" , "t32": "1111|11111|Vd'|11|10|11|Vd|01|01|10|Vn'|0|Vn" , "ext": "ASIMD", "it": "out"},
|
|
{"inst": "vrsqrte.f32 Vd, Vn" , "t32": "1111|11111|Vd'|11|10|11|Vd|01|01|11|Vn'|0|Vn" , "ext": "ASIMD", "it": "out"},
|
|
{"inst": "vrsqrte.u32 Dd, Dn" , "t32": "1111|11111|Vd'|11|10|11|Vd|01|00|10|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vrsqrte.u32 Vd, Vn" , "t32": "1111|11111|Vd'|11|10|11|Vd|01|00|11|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vrsqrts.f16 Dd, Dn, Dm" , "t32": "1110|11110|Vd'|11|Vn|Vd|1111|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD FP16", "it": "out"},
|
|
{"inst": "vrsqrts.f16 Vd, Vn, Vm" , "t32": "1110|11110|Vd'|11|Vn|Vd|1111|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD FP16", "it": "out"},
|
|
{"inst": "vrsqrts.f32 Dd, Dn, Dm" , "t32": "1110|11110|Vd'|10|Vn|Vd|1111|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD", "it": "out"},
|
|
{"inst": "vrsqrts.f32 Vd, Vn, Vm" , "t32": "1110|11110|Vd'|10|Vn|Vd|1111|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD", "it": "out"},
|
|
{"inst": "vrsra.x8-64 Dx, Dn, #n" , "t32": "111U|11111|Vx'|imm[5:0]|Vx|0011|imm[6]|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNImm(sz, n)"},
|
|
{"inst": "vrsra.x8-64 Vx, Vn, #n" , "t32": "111U|11111|Vx'|imm[5:0]|Vx|0011|imm[6]|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNImm(sz, n)"},
|
|
{"inst": "vrsubhn.x16-64 Dd, Vn, Vm" , "t32": "1111|11111|Vd'|szM1:2|Vn|Vd|0110|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "narrow"},
|
|
{"inst": "vseleq.f16 Sd, Sn, Sm" , "t32": "1111|11100|'Vd|00|Vn|Vd|10|01|'Vn|0|'Vm|0|Vm" , "ext": "ARMv8+ FP16", "it": "out"},
|
|
{"inst": "vseleq.f32 Sd, Sn, Sm" , "t32": "1111|11100|'Vd|00|Vn|Vd|10|10|'Vn|0|'Vm|0|Vm" , "ext": "ARMv8+", "it": "out"},
|
|
{"inst": "vseleq.f64 Dd, Dn, Dm" , "t32": "1111|11100|Vd'|00|Vn|Vd|10|11|Vn'|0|Vm'|0|Vm" , "ext": "ARMv8+", "it": "out"},
|
|
{"inst": "vselge.f16 Sd, Sn, Sm" , "t32": "1111|11100|'Vd|10|Vn|Vd|10|01|'Vn|0|'Vm|0|Vm" , "ext": "ARMv8+ FP16", "it": "out"},
|
|
{"inst": "vselge.f32 Sd, Sn, Sm" , "t32": "1111|11100|'Vd|10|Vn|Vd|10|10|'Vn|0|'Vm|0|Vm" , "ext": "ARMv8+", "it": "out"},
|
|
{"inst": "vselge.f64 Dd, Dn, Dm" , "t32": "1111|11100|Vd'|10|Vn|Vd|10|11|Vn'|0|Vm'|0|Vm" , "ext": "ARMv8+", "it": "out"},
|
|
{"inst": "vselgt.f16 Sd, Sn, Sm" , "t32": "1111|11100|'Vd|11|Vn|Vd|10|01|'Vn|0|'Vm|0|Vm" , "ext": "ARMv8+ FP16", "it": "out"},
|
|
{"inst": "vselgt.f32 Sd, Sn, Sm" , "t32": "1111|11100|'Vd|11|Vn|Vd|10|10|'Vn|0|'Vm|0|Vm" , "ext": "ARMv8+", "it": "out"},
|
|
{"inst": "vselgt.f64 Dd, Dn, Dm" , "t32": "1111|11100|Vd'|11|Vn|Vd|10|11|Vn'|0|Vm'|0|Vm" , "ext": "ARMv8+", "it": "out"},
|
|
{"inst": "vselvs.f16 Sd, Sn, Sm" , "t32": "1111|11100|'Vd|01|Vn|Vd|10|01|'Vn|0|'Vm|0|Vm" , "ext": "ARMv8+ FP16", "it": "out"},
|
|
{"inst": "vselvs.f32 Sd, Sn, Sm" , "t32": "1111|11100|'Vd|01|Vn|Vd|10|10|'Vn|0|'Vm|0|Vm" , "ext": "ARMv8+", "it": "out"},
|
|
{"inst": "vselvs.f64 Dd, Dn, Dm" , "t32": "1111|11100|Vd'|01|Vn|Vd|10|11|Vn'|0|Vm'|0|Vm" , "ext": "ARMv8+", "it": "out"},
|
|
{"inst": "vshl.x8-64 Dd, Dn, Dm" , "t32": "111U|11110|Vd'|sz|Vm|Vd|0100|Vm'|0|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vshl.x8-64 Vd, Vn, Vm" , "t32": "111U|11110|Vd'|sz|Vm|Vd|0100|Vm'|1|Vn'|0|Vn" , "ext": "ASIMD"},
|
|
{"inst": "vshl.x8-64 Dd, Dn, #n" , "t32": "1110|11111|Vd'|imm[5:0]|Vd|0101|imm[6]|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftPImm(sz, n)"},
|
|
{"inst": "vshl.x8-64 Vd, Vn, #n" , "t32": "1110|11111|Vd'|imm[5:0]|Vd|0101|imm[6]|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftPImm(sz, n)"},
|
|
{"inst": "vshll.x8-32 Vd, Dn, #n" , "t32": "111U|11111|Vd'|imm[5:0]|Vd|1010|0|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftPImm(sz, n)", "vecOp": "widen"},
|
|
{"inst": "vshr.x8-64 Dd, Dn, #zero" , "t32": "1110|11110|Vd'|10|Vn|Vd|0001|Vn'|0|Vn'|1|Vn" , "ext": "ASIMD", "pseudoOf": "vorr"},
|
|
{"inst": "vshr.x8-64 Vd, Vn, #zero" , "t32": "1110|11110|Vd'|10|Vn|Vd|0001|Vn'|1|Vn'|1|Vn" , "ext": "ASIMD", "pseudoOf": "vorr"},
|
|
{"inst": "vshr.x8-64 Dd, Dn, #n" , "t32": "111U|11111|Vd'|imm[5:0]|Vd|0000|imm[6]|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNImm(sz, n)"},
|
|
{"inst": "vshr.x8-64 Vd, Vn, #n" , "t32": "111U|11111|Vd'|imm[5:0]|Vd|0000|imm[6]|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNImm(sz, n)"},
|
|
{"inst": "vshrn.x16-64 Dd, Vn, #zero" , "t32": "1111|11111|Vd'|11|sz|10|Vd|0010|00|Vn'|0|Vn" , "ext": "ASIMD", "vecOp": "narrow"},
|
|
{"inst": "vshrn.x16-64 Dd, Vn, #n" , "t32": "1110|11111|Vd'|imm:6|Vd|1000|00|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNarrowImm(sz, n)", "vecOp": "narrow"},
|
|
{"inst": "vsli.x8-64 Dx, Dn, #n" , "t32": "1111|11111|Vx'|imm[5:0]|Vx|0101|imm[6]|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftPImm(sz, n)"},
|
|
{"inst": "vsli.x8-64 Vx, Vn, #n" , "t32": "1111|11111|Vx'|imm[5:0]|Vx|0101|imm[6]|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftPImm(sz, n)"},
|
|
{"inst": "vsra.x8-64 Dx, Dn, #n" , "t32": "111U|11111|Vx'|imm[5:0]|Vx|0001|imm[6]|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNImm(sz, n)"},
|
|
{"inst": "vsra.x8-64 Vx, Vn, #n" , "t32": "111U|11111|Vx'|imm[5:0]|Vx|0001|imm[6]|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNImm(sz, n)"},
|
|
{"inst": "vsri.x8-64 Dx, Dn, #n" , "t32": "1111|11111|Vx'|imm[5:0]|Vx|0100|imm[6]|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNImm(sz, n)"},
|
|
{"inst": "vsri.x8-64 Vx, Vn, #n" , "t32": "1111|11111|Vx'|imm[5:0]|Vx|0100|imm[6]|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNImm(sz, n)"},
|
|
{"inst": "vst1.8-64 Ds, [Rn!=PC]" , "t32": "1111|10010|Vs'|00|Rn|Vs|0111|sz|0|align:1|1111" , "ext": "ASIMD"},
|
|
{"inst": "vst1.8-64 Ds, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|0111|sz|0|align:1|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vst1.8-64 Ds, [Rn!=PC, #off==8]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|0111|sz|0|align:1|1101" , "ext": "ASIMD"},
|
|
{"inst": "vst1.8-64 2x{Ds<=30}+, [Rn!=PC]" , "t32": "1111|10010|Vs'|00|Rn|Vs|1010|sz|0|align:1|1111" , "ext": "ASIMD"},
|
|
{"inst": "vst1.8-64 2x{Ds<=30}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|1010|sz|0|align:1|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vst1.8-64 2x{Ds<=30}+, [Rn!=PC, #off==16]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|1010|sz|0|align:1|1101" , "ext": "ASIMD"},
|
|
{"inst": "vst1.8-64 3x{Ds<=29}+, [Rn!=PC]" , "t32": "1111|10010|Vs'|00|Rn|Vs|0110|sz|0|align:1|1111" , "ext": "ASIMD"},
|
|
{"inst": "vst1.8-64 3x{Ds<=29}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|0110|sz|0|align:1|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vst1.8-64 3x{Ds<=29}+, [Rn!=PC, #off==24]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|0110|sz|0|align:1|1101" , "ext": "ASIMD"},
|
|
{"inst": "vst1.8-64 4x{Ds<=28}+, [Rn!=PC]" , "t32": "1111|10010|Vs'|00|Rn|Vs|0010|sz|0|align:1|1111" , "ext": "ASIMD"},
|
|
{"inst": "vst1.8-64 4x{Ds<=28}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|0010|sz|0|align:1|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vst1.8-64 4x{Ds<=28}+, [Rn!=PC, #off==32]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|0010|sz|0|align:1|1101" , "ext": "ASIMD"},
|
|
{"inst": "vst2.8-32 2x{Ds<=30}+, [Rn!=PC]" , "t32": "1111|10010|Vs'|00|Rn|Vs|1000|sz|align:2|1111" , "ext": "ASIMD"},
|
|
{"inst": "vst2.8-32 2x{Ds<=30}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|1000|sz|align:2|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vst2.8-32 2x{Ds<=30}+, [Rn!=PC, #off==16]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|1000|sz|align:2|1101" , "ext": "ASIMD"},
|
|
{"inst": "vst2.8-32 2x{Ds<=29}++, [Rn!=PC]" , "t32": "1111|10010|Vs'|00|Rn|Vs|1001|sz|align:2|1111" , "ext": "ASIMD"},
|
|
{"inst": "vst2.8-32 2x{Ds<=29}++, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|1001|sz|align:2|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vst2.8-32 2x{Ds<=29}++, [Rn!=PC, #off==16]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|1001|sz|align:2|1101" , "ext": "ASIMD"},
|
|
{"inst": "vst2.8-32 4x{Ds<=28}+, [Rn!=PC]" , "t32": "1111|10010|Vs'|00|Rn|Vs|0011|sz|align:2|1111" , "ext": "ASIMD"},
|
|
{"inst": "vst2.8-32 4x{Ds<=28}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|0011|sz|align:2|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vst2.8-32 4x{Ds<=28}+, [Rn!=PC, #off==32]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|0011|sz|align:2|1101" , "ext": "ASIMD"},
|
|
{"inst": "vst3.8-32 3x{Ds<=29}+, [Rn!=PC]" , "t32": "1111|10010|Vs'|00|Rn|Vs|0100|sz|0|align:1|1111" , "ext": "ASIMD"},
|
|
{"inst": "vst3.8-32 3x{Ds<=29}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|0100|sz|0|align:1|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vst3.8-32 3x{Ds<=29}+, [Rn!=PC, #off==24]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|0100|sz|0|align:1|1101" , "ext": "ASIMD"},
|
|
{"inst": "vst3.8-32 3x{Ds<=27}++, [Rn!=PC]" , "t32": "1111|10010|Vs'|00|Rn|Vs|0101|sz|1|align:1|1111" , "ext": "ASIMD"},
|
|
{"inst": "vst3.8-32 3x{Ds<=27}++, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|0101|sz|1|align:1|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vst3.8-32 3x{Ds<=27}++, [Rn!=PC, #off==24]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|0101|sz|1|align:1|1101" , "ext": "ASIMD"},
|
|
{"inst": "vst4.8-32 4x{Ds<=29}+, [Rn!=PC]" , "t32": "1111|10010|Vs'|00|Rn|Vs|0000|sz|align:2|1111" , "ext": "ASIMD"},
|
|
{"inst": "vst4.8-32 4x{Ds<=29}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|0000|sz|align:2|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vst4.8-32 4x{Ds<=29}+, [Rn!=PC, #off==32]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|0000|sz|align:2|1101" , "ext": "ASIMD"},
|
|
{"inst": "vst4.8-32 4x{Ds<=27}++, [Rn!=PC]" , "t32": "1111|10010|Vs'|00|Rn|Vs|0001|sz|align:2|1111" , "ext": "ASIMD"},
|
|
{"inst": "vst4.8-32 4x{Ds<=27}++, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|0001|sz|align:2|Rm" , "ext": "ASIMD"},
|
|
{"inst": "vst4.8-32 4x{Ds<=27}++, [Rn!=PC, #off==32]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|0001|sz|align:2|1101" , "ext": "ASIMD"},
|
|
{"inst": "vstmdb.32 [Rn!=PC]!, SdList" , "t32": "1110|11010|immVd[0]|10|Rn|immVd[4:1]|1010|immCount:8" , "ext": "ASIMD", "it": "any", "imm": "VecSListImm(SdList)"},
|
|
{"inst": "vstmdb.64 [Rn!=PC]!, DdList" , "t32": "1110|11010|immVd[4]|10|Rn|immVd[3:0]|1011|immCount:8" , "ext": "ASIMD", "it": "any", "imm": "VecDListImm(SdList)"},
|
|
{"inst": "vstmia.32 [Rn!=PC]{!}, SdList" , "t32": "1110|11001|immVd[0]|W0|Rn|immVd[4:1]|1010|immCount:8" , "ext": "ASIMD", "it": "any", "imm": "VecSListImm(SdList)"},
|
|
{"inst": "vstmia.64 [Rn!=PC]{!}, DdList" , "t32": "1110|11001|immVd[4]|W0|Rn|immVd[3:0]|1011|immCount:8" , "ext": "ASIMD", "it": "any", "imm": "VecDListImm(SdList)"},
|
|
{"inst": "vsub.f16 Dd, Dn, Dm" , "t32": "1110|11110|Vd'|11|Vn|Vd|11|01|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vsub.f16 Vd, Vn, Vm" , "t32": "1110|11110|Vd'|11|Vn|Vd|11|01|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD FP16"},
|
|
{"inst": "vsub.f32 Dd, Dn, Dm" , "t32": "1110|11110|Vd'|10|Vn|Vd|11|01|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vsub.f32 Vd, Vn, Vm" , "t32": "1110|11110|Vd'|10|Vn|Vd|11|01|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vsub.x8-64 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|sz|Vn|Vd|10|00|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vsub.x8-64 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|sz|Vn|Vd|10|00|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vsubhn.x16-64 Dd, Vn, Vm" , "t32": "1110|11111|Vd'|szM1:2|Vn|Vd|0110|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "narrow"},
|
|
{"inst": "vsubl.x8-32 Vd, Dn, Dm" , "t32": "111U|11111|Vd'|sz|Vn|Vd|0010|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "widen"},
|
|
{"inst": "vsubw.x8-32 Vd, Vn, Dm" , "t32": "111U|11111|Vd'|sz|Vn|Vd|0011|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "widen"},
|
|
{"inst": "vswp.any Dx, Dx2!=Dx" , "t32": "1111|11111|Vx'|11|00|10|Vx|0000|0|0|Vx2'|0|Vx2" , "ext": "ASIMD"},
|
|
{"inst": "vswp.any Vx, Vx2!=Vx" , "t32": "1111|11111|Vx'|11|00|10|Vx|0000|0|1|Vx2'|0|Vx2" , "ext": "ASIMD"},
|
|
{"inst": "vtbl.x8 Dd, Dn, Dm" , "t32": "1111|11111|Vd'|11|Vn|Vd|10|00|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vtbl.x8 Dd, Dn, Dn2+, Dm" , "t32": "1111|11111|Vd'|11|Vn|Vd|10|01|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vtbl.x8 Dd, Dn, Dn2+, Dn3+, Dm" , "t32": "1111|11111|Vd'|11|Vn|Vd|10|10|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vtbl.x8 Dd, Dn, Dn2+, Dn3+, Dn4+, Dm" , "t32": "1111|11111|Vd'|11|Vn|Vd|10|11|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vtbx.x8 Dd, Dn, Dm" , "t32": "1111|11111|Vd'|11|Vn|Vd|10|00|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vtbx.x8 Dd, Dn, Dn2+, Dm" , "t32": "1111|11111|Vd'|11|Vn|Vd|10|01|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vtbx.x8 Dd, Dn, Dn2+, Dn3+, Dm" , "t32": "1111|11111|Vd'|11|Vn|Vd|10|10|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vtbx.x8 Dd, Dn, Dn2+, Dn3+, Dn4+, Dm" , "t32": "1111|11111|Vd'|11|Vn|Vd|10|11|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vtrn.x8-32 Dx, Dx2" , "t32": "1111|11111|Vx'|11|sz|10|Vx|0000|1|0|Vx2'|0|Vx2" , "ext": "ASIMD"},
|
|
{"inst": "vtrn.x8-32 Vx, Vx2" , "t32": "1111|11111|Vx'|11|sz|10|Vx|0000|1|1|Vx2'|0|Vx2" , "ext": "ASIMD"},
|
|
{"inst": "vtst.x8-32 Dd, Dn, Dm" , "t32": "1110|11110|Vd'|sz|Vn|Vd|1000|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vtst.x8-32 Vd, Vn, Vm" , "t32": "1110|11110|Vd'|sz|Vn|Vd|1000|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
|
|
{"inst": "vuzp.x8-16 Dx, Dx2" , "t32": "1111|11111|Vx'|11|sz|10|Vx|0001|0|0|Vx2'|0|Vx2" , "ext": "ASIMD"},
|
|
{"inst": "vuzp.x32 Dx, Dx2" , "t32": "1111|11111|Vx'|11|sz|10|Vx|0000|1|0|Vx2'|0|Vx2" , "ext": "ASIMD", "aliasOf": "vtrn"},
|
|
{"inst": "vuzp.x8-32 Vx, Vx2" , "t32": "1111|11111|Vx'|11|sz|10|Vx|0001|0|1|Vx2'|0|Vx2" , "ext": "ASIMD"},
|
|
{"inst": "vzip.x8-16 Dx, Dx2" , "t32": "1111|11111|Vx'|11|sz|10|Vx|0001|1|0|Vx2'|0|Vx2" , "ext": "ASIMD"},
|
|
{"inst": "vzip.x32 Dx, Dx2" , "t32": "1111|11111|Vx'|11|sz|10|Vx|0000|1|0|Vx2'|0|Vx2" , "ext": "ASIMD", "aliasOf": "vtrn"},
|
|
{"inst": "vzip.x8-32 Vx, Vx2" , "t32": "1111|11111|Vx'|11|sz|10|Vx|0001|1|1|Vx2'|0|Vx2" , "ext": "ASIMD"}
|
|
]},
|
|
|
|
{"category": "ASIMD CRYPTO_HASH", "ext": "AES", "data": [
|
|
{"inst": "aesd.x8 Vx, Vm" , "a32": "1111|00111|Vx'|11|00|00|Vx|0|0110|1|Vm'|0|Vm"},
|
|
{"inst": "aese.x8 Vx, Vm" , "a32": "1111|00111|Vx'|11|00|00|Vx|0|0110|0|Vm'|0|Vm"},
|
|
{"inst": "aesimc.x8 Vd, Vm" , "a32": "1111|00111|Vd'|11|00|00|Vd|0|0111|1|Vm'|0|Vm"},
|
|
{"inst": "aesmc.x8 Vd, Vm" , "a32": "1111|00111|Vd'|11|00|00|Vd|0|0111|0|Vm'|0|Vm"}
|
|
]},
|
|
|
|
{"category": "ASIMD CRYPTO_HASH", "ext": "AES", "data": [
|
|
{"inst": "aesd.x8 Vx, Vm" , "t32": "1111|11111|Vx'|11|00|00|Vx|0|0110|1|Vm'|0|Vm" , "it": "out"},
|
|
{"inst": "aese.x8 Vx, Vm" , "t32": "1111|11111|Vx'|11|00|00|Vx|0|0110|0|Vm'|0|Vm" , "it": "out"},
|
|
{"inst": "aesimc.x8 Vd, Vm" , "t32": "1111|11111|Vd'|11|00|00|Vd|0|0111|1|Vm'|0|Vm" , "it": "out"},
|
|
{"inst": "aesmc.x8 Vd, Vm" , "t32": "1111|11111|Vd'|11|00|00|Vd|0|0111|0|Vm'|0|Vm" , "it": "out"}
|
|
]},
|
|
|
|
{"category": "ASIMD", "ext": "BF16", "data": [
|
|
{"inst": "vmmla.bf16 Vd, Vn, Vm" , "a32": "1111|11000|Vd'|00|Vn|Vd|1100|Vn'|1|Vm'|0|Vm"},
|
|
{"inst": "vcvtb.bf16.f32 Sd, Dn" , "a32": "cond|11101|'Vd|11|00|11|Vd|10010|1|'Vn|0|Vn"},
|
|
{"inst": "vcvtt.bf16.f32 Sd, Dn" , "a32": "cond|11101|'Vd|11|00|11|Vd|10011|1|'Vn|0|Vn"},
|
|
{"inst": "vdot.bf16 Dd, Dn, Dm" , "a32": "1111|11000|Vd'|00|Vn|Vd|1101|Vn'|0|Vm'|0|Vm"},
|
|
{"inst": "vdot.bf16 Vd, Vn, Vm" , "a32": "1111|11000|Vd'|00|Vn|Vd|1101|Vn'|1|Vm'|0|Vm"},
|
|
{"inst": "vdot.bf16 Dd, Dn, Dm<=15[#i]" , "a32": "1111|11100|Vd'|00|Vn|Vd|1101|Vn'|0|i:1|0|Vm"},
|
|
{"inst": "vdot.bf16 Vd, Vn, Dm<=15[#i]" , "a32": "1111|11100|Vd'|00|Vn|Vd|1101|Vn'|1|i:1|0|Vm"},
|
|
{"inst": "vfmab.bf16 Vd, Vn, Vm" , "a32": "1111|11000|Vd'|11|Vn|Vd|1000|Vn'|0|Vm'|1|Vm"},
|
|
{"inst": "vfmab.bf16 Vd, Vn, Dm<=07[#i]" , "a32": "1111|11100|Vd'|11|Vn|Vd|1000|Vn'|0|i:1|1|i:1|Vm[2:0]"},
|
|
{"inst": "vfmat.bf16 Vd, Vn, Vm" , "a32": "1111|11000|Vd'|11|Vn|Vd|1000|Vn'|1|Vm'|1|Vm"},
|
|
{"inst": "vfmat.bf16 Vd, Vn, Dm<=07[#i]" , "a32": "1111|11100|Vd'|11|Vn|Vd|1000|Vn'|1|i:1|1|i:1|Vm[2:0]"}
|
|
]},
|
|
|
|
{"category": "ASIMD", "ext": "BF16", "data": [
|
|
{"inst": "vmmla.bf16 Vd, Vn, Vm" , "t32": "1111|11000|Vd'|00|Vn|Vd|1100|Vn'|1|Vm'|0|Vm" , "it": "out"},
|
|
{"inst": "vcvtb.bf16.f32 Sd, Dn" , "t32": "1110|11101|'Vd|11|00|11|Vd|10010|1|'Vn|0|Vn" , "it": "any"},
|
|
{"inst": "vcvtt.bf16.f32 Sd, Dn" , "t32": "1110|11101|'Vd|11|00|11|Vd|10011|1|'Vn|0|Vn" , "it": "any"},
|
|
{"inst": "vdot.bf16 Dd, Dn, Dm" , "t32": "1110|11000|Vd'|00|Vn|Vd|1101|Vn'|0|Vm'|0|Vm" , "it": "out"},
|
|
{"inst": "vdot.bf16 Vd, Vn, Vm" , "t32": "1110|11000|Vd'|00|Vn|Vd|1101|Vn'|1|Vm'|0|Vm" , "it": "out"},
|
|
{"inst": "vdot.bf16 Dd, Dn, Dm<=15[#i]" , "t32": "1110|11100|Vd'|00|Vn|Vd|1101|Vn'|0|i:1|0|Vm" , "it": "out"},
|
|
{"inst": "vdot.bf16 Vd, Vn, Dm<=15[#i]" , "t32": "1110|11100|Vd'|00|Vn|Vd|1101|Vn'|1|i:1|0|Vm" , "it": "out"},
|
|
{"inst": "vfmab.bf16 Vd, Vn, Vm" , "t32": "1111|11000|Vd'|11|Vn|Vd|1000|Vn'|0|Vm'|1|Vm" , "it": "out"},
|
|
{"inst": "vfmab.bf16 Vd, Vn, Dm<=07[#i]" , "t32": "1111|11100|Vd'|11|Vn|Vd|1000|Vn'|0|i:1|1|i:1|Vm[2:0]" , "it": "out"},
|
|
{"inst": "vfmat.bf16 Vd, Vn, Vm" , "t32": "1111|11000|Vd'|11|Vn|Vd|1000|Vn'|1|Vm'|1|Vm" , "it": "out"},
|
|
{"inst": "vfmat.bf16 Vd, Vn, Dm<=07[#i]" , "t32": "1111|11100|Vd'|11|Vn|Vd|1000|Vn'|1|i:1|1|i:1|Vm[2:0]" , "it": "out"}
|
|
]},
|
|
|
|
{"category": "ASIMD", "ext": "DOTPROD", "data": [
|
|
{"inst": "vsdot.s8 Dd, Dn, Dm" , "a32": "1111|11000|Vd'|10|Vn|Vd|1101|Vn'|0|Vm'|0|Vm"},
|
|
{"inst": "vsdot.s8 Vd, Vn, Vm" , "a32": "1111|11000|Vd'|10|Vn|Vd|1101|Vn'|1|Vm'|0|Vm"},
|
|
{"inst": "vsdot.s8 Dd, Dn, Dm<=15[#i]" , "a32": "1111|11100|Vd'|10|Vn|Vd|1101|Vn'|0|i:1|0|Vm"},
|
|
{"inst": "vsdot.s8 Vd, Vn, Dm<=15[#i]" , "a32": "1111|11100|Vd'|10|Vn|Vd|1101|Vn'|1|i:1|0|Vm"},
|
|
{"inst": "vudot.u8 Dd, Dn, Dm" , "a32": "1111|11000|Vd'|10|Vn|Vd|1101|Vn'|0|Vm'|1|Vm"},
|
|
{"inst": "vudot.u8 Vd, Vn, Vm" , "a32": "1111|11000|Vd'|10|Vn|Vd|1101|Vn'|1|Vm'|1|Vm"},
|
|
{"inst": "vudot.u8 Dd, Dn, Dm<=15[#i]" , "a32": "1111|11100|Vd'|10|Vn|Vd|1101|Vn'|0|i:1|1|Vm"},
|
|
{"inst": "vudot.u8 Vd, Vn, Dm<=15[#i]" , "a32": "1111|11100|Vd'|10|Vn|Vd|1101|Vn'|1|i:1|1|Vm"}
|
|
]},
|
|
|
|
{"category": "ASIMD", "ext": "DOTPROD", "data": [
|
|
{"inst": "vsdot.s8 Dd, Dn, Dm" , "t32": "1111|11000|Vd'|10|Vn|Vd|1101|Vn'|0|Vm'|0|Vm" , "it": "out"},
|
|
{"inst": "vsdot.s8 Vd, Vn, Vm" , "t32": "1111|11000|Vd'|10|Vn|Vd|1101|Vn'|1|Vm'|0|Vm" , "it": "out"},
|
|
{"inst": "vsdot.s8 Dd, Dn, Dm<=15[#i]" , "t32": "1111|11100|Vd'|10|Vn|Vd|1101|Vn'|0|i:1|0|Vm" , "it": "out"},
|
|
{"inst": "vsdot.s8 Vd, Vn, Dm<=15[#i]" , "t32": "1111|11100|Vd'|10|Vn|Vd|1101|Vn'|1|i:1|0|Vm" , "it": "out"},
|
|
{"inst": "vudot.u8 Dd, Dn, Dm" , "t32": "1111|11000|Vd'|10|Vn|Vd|1101|Vn'|0|Vm'|1|Vm" , "it": "out"},
|
|
{"inst": "vudot.u8 Vd, Vn, Vm" , "t32": "1111|11000|Vd'|10|Vn|Vd|1101|Vn'|1|Vm'|1|Vm" , "it": "out"},
|
|
{"inst": "vudot.u8 Dd, Dn, Dm<=15[#i]" , "t32": "1111|11100|Vd'|10|Vn|Vd|1101|Vn'|0|i:1|1|Vm" , "it": "out"},
|
|
{"inst": "vudot.u8 Vd, Vn, Dm<=15[#i]" , "t32": "1111|11100|Vd'|10|Vn|Vd|1101|Vn'|1|i:1|1|Vm" , "it": "out"}
|
|
]},
|
|
|
|
{"category": "ASIMD", "ext": "FCMA", "data": [
|
|
{"inst": "vcadd.f32 Dd, Dn, Dm, #rot1" , "a32": "1111|110|imm:1|1|Vd'|01|Vn|Vd|1000|Vn'|0|Vm'|0|Vm" , "imm": "VecRot1Imm(rot1)"},
|
|
{"inst": "vcadd.f32 Vd, Vn, Vm, #rot1" , "a32": "1111|110|imm:1|1|Vd'|01|Vn|Vd|1000|Vn'|1|Vm'|0|Vm" , "imm": "VecRot1Imm(rot1)"},
|
|
{"inst": "vcmla.f32 Dx, Dn, Dm, #rot2" , "a32": "1111|110|imm:2|Vx'|11|Vn|Vx|1000|Vn'|0|Vm'|0|Vm" , "imm": "VecRot2Imm(rot2)"},
|
|
{"inst": "vcmla.f32 Vx, Vn, Vm, #rot2" , "a32": "1111|110|imm:2|Vx'|11|Vn|Vx|1000|Vn'|1|Vm'|0|Vm" , "imm": "VecRot2Imm(rot2)"},
|
|
{"inst": "vcmla.f32 Dx, Dn, Dm[#i], #rot2" , "a32": "1111|1110|1|Vx'|imm:2|Vn|Vx|1000|Vn'|0|Vm'|0|Vm" , "imm": "VecRot2Imm(rot2)"},
|
|
{"inst": "vcmla.f32 Vx, Vn, Dm[#i], #rot2" , "a32": "1111|1110|1|Vx'|imm:2|Vn|Vx|1000|Vn'|1|Vm'|0|Vm" , "imm": "VecRot2Imm(rot2)"}
|
|
]},
|
|
|
|
{"category": "ASIMD", "ext": "FCMA", "data": [
|
|
{"inst": "vcadd.f32 Dd, Dn, Dm, #rot1" , "t32": "1111|110|imm:1|1|Vd'|01|Vn|Vd|1000|Vn'|0|Vm'|0|Vm" , "it": "out", "imm": "VecRot1Imm(rot1)"},
|
|
{"inst": "vcadd.f32 Vd, Vn, Vm, #rot1" , "t32": "1111|110|imm:1|1|Vd'|01|Vn|Vd|1000|Vn'|1|Vm'|0|Vm" , "it": "out", "imm": "VecRot1Imm(rot1)"},
|
|
{"inst": "vcmla.f32 Vx, Vn, Vm, #rot2" , "t32": "1111|110|imm:2|Vx'|11|Vn|Vx|1000|Vn'|1|Vm'|0|Vm" , "it": "out", "imm": "VecRot2Imm(rot2)"},
|
|
{"inst": "vcmla.f32 Vx, Vn, Vm, #rot2" , "t32": "1111|110|imm:2|Vx'|11|Vn|Vx|1000|Vn'|1|Vm'|0|Vm" , "it": "out", "imm": "VecRot2Imm(rot2)"},
|
|
{"inst": "vcmla.f32 Dx, Dn, Dm[#i], #rot2" , "t32": "1111|1110|1|Vx'|imm:2|Vn|Vx|1000|Vn'|0|Vm'|0|Vm" , "it": "out", "imm": "VecRot2Imm(rot2)"},
|
|
{"inst": "vcmla.f32 Vx, Vn, Dm[#i], #rot2" , "t32": "1111|1110|1|Vx'|imm:2|Vn|Vx|1000|Vn'|1|Vm'|0|Vm" , "it": "out", "imm": "VecRot2Imm(rot2)"}
|
|
]},
|
|
|
|
{"category": "ASIMD", "ext": "FCMA FP16", "data": [
|
|
{"inst": "vcadd.f16 Dd, Dn, Dm, #rot1" , "a32": "1111|110|imm:1|1|Vd'|00|Vn|Vd|1000|Vn'|0|Vm'|0|Vm" , "imm": "VecRot1Imm(rot1)"},
|
|
{"inst": "vcadd.f16 Vd, Vn, Vm, #rot1" , "a32": "1111|110|imm:1|1|Vd'|00|Vn|Vd|1000|Vn'|1|Vm'|0|Vm" , "imm": "VecRot1Imm(rot1)"},
|
|
{"inst": "vcmla.f16 Dx, Dn, Dm, #rot2" , "a32": "1111|110|imm:2|Vx'|10|Vn|Vx|1000|Vn'|0|Vm'|0|Vm" , "imm": "VecRot2Imm(rot2)"},
|
|
{"inst": "vcmla.f16 Vx, Vn, Vm, #rot2" , "a32": "1111|110|imm:2|Vx'|10|Vn|Vx|1000|Vn'|1|Vm'|0|Vm" , "imm": "VecRot2Imm(rot2)"},
|
|
{"inst": "vcmla.f16 Dx, Dn, Dm<=15[#i], #rot2" , "a32": "1111|1110|0|Vx'|imm:2|Vn|Vx|1000|Vn'|0|i:1|0|Vm" , "imm": "VecRot2Imm(rot2)"},
|
|
{"inst": "vcmla.f16 Vx, Vn, Dm<=15[#i], #rot2" , "a32": "1111|1110|0|Vx'|imm:2|Vn|Vx|1000|Vn'|1|i:1|0|Vm" , "imm": "VecRot2Imm(rot2)"}
|
|
]},
|
|
|
|
{"category": "ASIMD", "ext": "FCMA FP16", "data": [
|
|
{"inst": "vcadd.f16 Dd, Dn, Dm, #rot1" , "t32": "1111|110|imm:1|1|Vd'|00|Vn|Vd|1000|Vn'|0|Vm'|0|Vm" , "it": "out", "imm": "VecRot1Imm(rot1)"},
|
|
{"inst": "vcadd.f16 Vd, Vn, Vm, #rot1" , "t32": "1111|110|imm:1|1|Vd'|00|Vn|Vd|1000|Vn'|1|Vm'|0|Vm" , "it": "out", "imm": "VecRot1Imm(rot1)"},
|
|
{"inst": "vcmla.f16 Dx, Dn, Dm, #rot2" , "t32": "1111|110|imm:2|Vx'|10|Vn|Vx|1000|Vn'|0|Vm'|0|Vm" , "it": "out", "imm": "VecRot2Imm(rot2)"},
|
|
{"inst": "vcmla.f16 Dx, Dn, Dm, #rot2" , "t32": "1111|110|imm:2|Vx'|10|Vn|Vx|1000|Vn'|0|Vm'|0|Vm" , "it": "out", "imm": "VecRot2Imm(rot2)"},
|
|
{"inst": "vcmla.f16 Dx, Dn, Dm<=15[#i], #rot2" , "t32": "1111|1110|0|Vx'|imm:2|Vn|Vx|1000|Vn'|0|i:1|0|Vm" , "it": "out", "imm": "VecRot2Imm(rot2)"},
|
|
{"inst": "vcmla.f16 Vx, Vn, Dm<=15[#i], #rot2" , "t32": "1111|1110|0|Vx'|imm:2|Vn|Vx|1000|Vn'|1|i:1|0|Vm" , "it": "out", "imm": "VecRot2Imm(rot2)"}
|
|
]},
|
|
|
|
{"category": "ASIMD", "ext": "FHM", "data": [
|
|
{"inst": "vfmal.f16 Dx, Sn, Sm" , "a32": "1111|11000|Vx'|10|Vn|Vx|1000|'Vn|0|'Vm|1|Vm"},
|
|
{"inst": "vfmal.f16 Vx, Dn, Dm" , "a32": "1111|11000|Vx'|10|Vn|Vx|1000|Vn'|1|Vm'|1|Vm"},
|
|
{"inst": "vfmal.f16 Dx, Sn, Sm<=15[#i]" , "a32": "1111|11100|Vx'|00|Vn|Vx|1000|'Vn|0|Vm[0]|1|i:1|Vm[3:1]"},
|
|
{"inst": "vfmal.f16 Vx, Dn, Dm<=15[#i]" , "a32": "1111|11100|Vx'|00|Vn|Vx|1000|Vn'|1|i:1|1|i:1|Vm:3"},
|
|
{"inst": "vfmsl.f16 Dx, Sn, Sm" , "a32": "1111|11001|Vx'|10|Vn|Vx|1000|'Vn|0|'Vm|1|Vm"},
|
|
{"inst": "vfmsl.f16 Vx, Dn, Dm" , "a32": "1111|11001|Vx'|10|Vn|Vx|1000|Vn'|1|Vm'|1|Vm"},
|
|
{"inst": "vfmsl.f16 Dx, Sn, Sm<=15[#i]" , "a32": "1111|11100|Vx'|01|Vn|Vx|1000|'Vn|0|Vm[0]|1|i:1|Vm[3:1]"},
|
|
{"inst": "vfmsl.f16 Vx, Dn, Dm<=07[#i]" , "a32": "1111|11100|Vx'|01|Vn|Vx|1000|Vn'|1|i:1|1|i:1|Vm:3"}
|
|
]},
|
|
|
|
{"category": "ASIMD", "ext": "FHM", "data": [
|
|
{"inst": "vfmal.f16 Dx, Sn, Sm" , "t32": "1111|11000|Vx'|10|Vn|Vx|1000|'Vn|0|'Vm|1|Vm" , "it": "out"},
|
|
{"inst": "vfmal.f16 Vx, Dn, Dm" , "t32": "1111|11000|Vx'|10|Vn|Vx|1000|Vn'|1|Vm'|1|Vm" , "it": "out"},
|
|
{"inst": "vfmal.f16 Dx, Sn, Sm<=15[#i]" , "t32": "1111|11100|Vx'|00|Vn|Vx|1000|'Vn|0|Vm[0]|1|i:1|Vm[3:1]" , "it": "out"},
|
|
{"inst": "vfmal.f16 Vx, Dn, Dm<=15[#i]" , "t32": "1111|11100|Vx'|00|Vn|Vx|1000|Vn'|1|i:1|1|i:1|Vm:3" , "it": "out"},
|
|
{"inst": "vfmsl.f16 Dx, Sn, Sm" , "t32": "1111|11001|Vx'|10|Vn|Vx|1000|'Vn|0|'Vm|1|Vm" , "it": "out"},
|
|
{"inst": "vfmsl.f16 Vx, Dn, Dm" , "t32": "1111|11001|Vx'|10|Vn|Vx|1000|Vn'|1|Vm'|1|Vm" , "it": "out"},
|
|
{"inst": "vfmsl.f16 Dx, Sn, Sm<=15[#i]" , "t32": "1111|11100|Vx'|01|Vn|Vx|1000|'Vn|0|Vm[0]|1|i:1|Vm[3:1]" , "it": "out"},
|
|
{"inst": "vfmsl.f16 Vx, Dn, Dm<=07[#i]" , "t32": "1111|11100|Vx'|01|Vn|Vx|1000|Vn'|1|i:1|1|i:1|Vm:3" , "it": "out"}
|
|
]},
|
|
|
|
{"category": "ASIMD", "ext": "FP16CONV", "data": [
|
|
{"inst": "vcvt.f16.f32 Dd, Vn" , "a32": "1111|00111|Vd'|11|01|10|Vd|01100|0|Vn'|0|Vn"},
|
|
{"inst": "vcvt.f32.f16 Vd, Dn" , "a32": "1111|00111|Vd'|11|01|10|Vd|01110|0|Vn'|0|Vn"},
|
|
{"inst": "vcvt.f16.s16 Dd, Dn, #fbits" , "a32": "1111|00101|Vd'|imm:6|Vd|11000|0|Vn'|1|Vn" , "imm": "VecFBitsASIMD(fbits)"},
|
|
{"inst": "vcvt.f16.s16 Vd, Vn, #fbits" , "a32": "1111|00101|Vd'|imm:6|Vd|11000|1|Vn'|1|Vn" , "imm": "VecFBitsASIMD(fbits)"},
|
|
{"inst": "vcvt.s16.f16 Dd, Dn, #fbits" , "a32": "1111|00101|Vd'|imm:6|Vd|11010|0|Vn'|1|Vn" , "imm": "VecFBitsASIMD(fbits)"},
|
|
{"inst": "vcvt.s16.f16 Vd, Vn, #fbits" , "a32": "1111|00101|Vd'|imm:6|Vd|11010|1|Vn'|1|Vn" , "imm": "VecFBitsASIMD(fbits)"},
|
|
{"inst": "vcvt.f16.u16 Dd, Dn, #fbits" , "a32": "1111|00111|Vd'|imm:6|Vd|11000|0|Vn'|1|Vn" , "imm": "VecFBitsASIMD(fbits)"},
|
|
{"inst": "vcvt.f16.u16 Vd, Vn, #fbits" , "a32": "1111|00111|Vd'|imm:6|Vd|11000|1|Vn'|1|Vn" , "imm": "VecFBitsASIMD(fbits)"},
|
|
{"inst": "vcvt.u16.f16 Dd, Dn, #fbits" , "a32": "1111|00111|Vd'|imm:6|Vd|11010|0|Vn'|1|Vn" , "imm": "VecFBitsASIMD(fbits)"},
|
|
{"inst": "vcvt.u16.f16 Vd, Vn, #fbits" , "a32": "1111|00111|Vd'|imm:6|Vd|11010|1|Vn'|1|Vn" , "imm": "VecFBitsASIMD(fbits)"},
|
|
{"inst": "vcvta.s32.f16 Sd, Sn" , "a32": "1111|11101|'Vd|11|11|00|Vd|10011|1|'Vn|0|Vn"},
|
|
{"inst": "vcvta.u32.f16 Sd, Sn" , "a32": "1111|11101|'Vd|11|11|00|Vd|10010|1|'Vn|0|Vn"},
|
|
{"inst": "vcvtb.f32.f16 Sd, Sn" , "a32": "cond|11101|'Vd|11|00|10|Vd|10100|1|'Vn|0|Vn"},
|
|
{"inst": "vcvtb.f16.f32 Sd, Sn" , "a32": "cond|11101|'Vd|11|00|11|Vd|10100|1|'Vn|0|Vn"},
|
|
{"inst": "vcvtb.f64.f16 Dd, Sn" , "a32": "cond|11101|Vd'|11|00|10|Vd|10110|1|'Vn|0|Vn"},
|
|
{"inst": "vcvtb.f16.f64 Sd, Dn" , "a32": "cond|11101|'Vd|11|00|11|Vd|10110|1|Vn'|0|Vn"},
|
|
{"inst": "vcvtm.s16.f16 Dd, Dn" , "a32": "1111|00111|Vd'|11|01|11|Vd|00110|0|Vn'|0|Vn"},
|
|
{"inst": "vcvtm.s16.f16 Vd, Vn" , "a32": "1111|00111|Vd'|11|01|11|Vd|00110|1|Vn'|0|Vn"},
|
|
{"inst": "vcvtm.u16.f16 Dd, Dn" , "a32": "1111|00111|Vd'|11|01|11|Vd|00111|0|Vn'|0|Vn"},
|
|
{"inst": "vcvtm.u16.f16 Vd, Vn" , "a32": "1111|00111|Vd'|11|01|11|Vd|00111|1|Vn'|0|Vn"},
|
|
{"inst": "vcvtm.s32.f16 Sd, Sn" , "a32": "1111|11101|'Vd|11|11|11|Vd|10011|1|'Vn|0|Vn"},
|
|
{"inst": "vcvtm.u32.f16 Sd, Sn" , "a32": "1111|11101|'Vd|11|11|11|Vd|10010|1|'Vn|0|Vn"},
|
|
{"inst": "vcvtn.s16.f16 Dd, Dn" , "a32": "1111|00111|Vd'|11|01|11|Vd|00010|0|Vn'|0|Vn"},
|
|
{"inst": "vcvtn.s16.f16 Vd, Vn" , "a32": "1111|00111|Vd'|11|01|11|Vd|00010|1|Vn'|0|Vn"},
|
|
{"inst": "vcvtn.u16.f16 Dd, Dn" , "a32": "1111|00111|Vd'|11|01|11|Vd|00011|0|Vn'|0|Vn"},
|
|
{"inst": "vcvtn.u16.f16 Vd, Vn" , "a32": "1111|00111|Vd'|11|01|11|Vd|00011|1|Vn'|0|Vn"},
|
|
{"inst": "vcvtn.s32.f16 Sd, Sn" , "a32": "1111|11101|'Vd|11|11|01|Vd|10011|1|'Vn|0|Vn"},
|
|
{"inst": "vcvtn.u32.f16 Sd, Sn" , "a32": "1111|11101|'Vd|11|11|01|Vd|10010|1|'Vn|0|Vn"},
|
|
{"inst": "vcvtp.s16.f16 Dd, Dn" , "a32": "1111|00111|Vd'|11|01|11|Vd|00100|0|Vn'|0|Vn"},
|
|
{"inst": "vcvtp.s16.f16 Vd, Vn" , "a32": "1111|00111|Vd'|11|01|11|Vd|00100|1|Vn'|0|Vn"},
|
|
{"inst": "vcvtp.u16.f16 Dd, Dn" , "a32": "1111|00111|Vd'|11|01|11|Vd|00101|0|Vn'|0|Vn"},
|
|
{"inst": "vcvtp.u16.f16 Vd, Vn" , "a32": "1111|00111|Vd'|11|01|11|Vd|00101|1|Vn'|0|Vn"},
|
|
{"inst": "vcvtp.s32.f16 Sd, Sn" , "a32": "1111|11101|'Vd|11|11|10|Vd|10011|1|'Vn|0|Vn"},
|
|
{"inst": "vcvtp.u32.f16 Sd, Sn" , "a32": "1111|11101|'Vd|11|11|10|Vd|10010|1|'Vn|0|Vn"},
|
|
{"inst": "vcvtr.s32.f16 Sd, Sn" , "a32": "1110|11101|'Vd|11|11|01|Vd|10010|1|'Vn|0|Vn"},
|
|
{"inst": "vcvtr.u32.f16 Sd, Sn" , "a32": "1110|11101|'Vd|11|11|00|Vd|10010|1|'Vn|0|Vn"},
|
|
{"inst": "vcvtt.f32.f16 Sd, Sn" , "a32": "cond|11101|'Vd|11|00|10|Vd|10101|1|'Vn|0|Vn"},
|
|
{"inst": "vcvtt.f16.f32 Sd, Sn" , "a32": "cond|11101|'Vd|11|00|11|Vd|10101|1|'Vn|0|Vn"},
|
|
{"inst": "vcvtt.f64.f16 Dd, Sn" , "a32": "cond|11101|Vd'|11|00|10|Vd|10111|1|'Vn|0|Vn"},
|
|
{"inst": "vcvtt.f16.f64 Sd, Dn" , "a32": "cond|11101|'Vd|11|00|11|Vd|10111|1|Vn'|0|Vn"}
|
|
]},
|
|
|
|
{"category": "ASIMD", "ext": "FP16CONV", "data": [
|
|
{"inst": "vcvt.f16.f32 Dd, Vn" , "t32": "1111|11111|Vd'|11|01|10|Vd|01100|0|Vn'|0|Vn" , "it": "out"},
|
|
{"inst": "vcvt.f32.f16 Vd, Dn" , "t32": "1111|11111|Vd'|11|01|10|Vd|01110|0|Vn'|0|Vn" , "it": "out"},
|
|
{"inst": "vcvt.f16.s16 Dd, Dn, #fbits" , "t32": "1110|11111|Vd'|imm:6|Vd|11000|0|Vn'|1|Vn" , "it": "out", "imm": "VecFBitsASIMD(fbits)"},
|
|
{"inst": "vcvt.f16.s16 Vd, Vn, #fbits" , "t32": "1110|11111|Vd'|imm:6|Vd|11000|1|Vn'|1|Vn" , "it": "out", "imm": "VecFBitsASIMD(fbits)"},
|
|
{"inst": "vcvt.s16.f16 Dd, Dn, #fbits" , "t32": "1110|11111|Vd'|imm:6|Vd|11010|0|Vn'|1|Vn" , "it": "out", "imm": "VecFBitsASIMD(fbits)"},
|
|
{"inst": "vcvt.s16.f16 Vd, Vn, #fbits" , "t32": "1110|11111|Vd'|imm:6|Vd|11010|1|Vn'|1|Vn" , "it": "out", "imm": "VecFBitsASIMD(fbits)"},
|
|
{"inst": "vcvt.f16.u16 Dd, Dn, #fbits" , "t32": "1111|11111|Vd'|imm:6|Vd|11000|0|Vn'|1|Vn" , "it": "out", "imm": "VecFBitsASIMD(fbits)"},
|
|
{"inst": "vcvt.f16.u16 Vd, Vn, #fbits" , "t32": "1111|11111|Vd'|imm:6|Vd|11000|1|Vn'|1|Vn" , "it": "out", "imm": "VecFBitsASIMD(fbits)"},
|
|
{"inst": "vcvt.u16.f16 Dd, Dn, #fbits" , "t32": "1111|11111|Vd'|imm:6|Vd|11010|0|Vn'|1|Vn" , "it": "out", "imm": "VecFBitsASIMD(fbits)"},
|
|
{"inst": "vcvt.u16.f16 Vd, Vn, #fbits" , "t32": "1111|11111|Vd'|imm:6|Vd|11010|1|Vn'|1|Vn" , "it": "out", "imm": "VecFBitsASIMD(fbits)"},
|
|
{"inst": "vcvta.s32.f16 Sd, Sn" , "t32": "1111|11101|'Vd|11|11|00|Vd|10011|1|'Vn|0|Vn" , "it": "out"},
|
|
{"inst": "vcvta.u32.f16 Sd, Sn" , "t32": "1111|11101|'Vd|11|11|00|Vd|10010|1|'Vn|0|Vn" , "it": "out"},
|
|
{"inst": "vcvtb.f32.f16 Sd, Sn" , "t32": "1110|11101|'Vd|11|00|10|Vd|10100|1|'Vn|0|Vn" , "it": "any"},
|
|
{"inst": "vcvtb.f16.f32 Sd, Sn" , "t32": "1110|11101|'Vd|11|00|11|Vd|10100|1|'Vn|0|Vn" , "it": "any"},
|
|
{"inst": "vcvtb.f64.f16 Dd, Sn" , "t32": "1110|11101|Vd'|11|00|10|Vd|10110|1|'Vn|0|Vn" , "it": "any"},
|
|
{"inst": "vcvtb.f16.f64 Sd, Dn" , "t32": "1110|11101|'Vd|11|00|11|Vd|10110|1|Vn'|0|Vn" , "it": "any"},
|
|
{"inst": "vcvtm.s16.f16 Dd, Dn" , "t32": "1111|11111|Vd'|11|01|11|Vd|00110|0|Vn'|0|Vn" , "it": "out"},
|
|
{"inst": "vcvtm.s16.f16 Vd, Vn" , "t32": "1111|11111|Vd'|11|01|11|Vd|00110|1|Vn'|0|Vn" , "it": "out"},
|
|
{"inst": "vcvtm.u16.f16 Dd, Dn" , "t32": "1111|11111|Vd'|11|01|11|Vd|00111|0|Vn'|0|Vn" , "it": "out"},
|
|
{"inst": "vcvtm.u16.f16 Vd, Vn" , "t32": "1111|11111|Vd'|11|01|11|Vd|00111|1|Vn'|0|Vn" , "it": "out"},
|
|
{"inst": "vcvtm.s32.f16 Sd, Sn" , "t32": "1111|11101|'Vd|11|11|11|Vd|10011|1|'Vn|0|Vn" , "it": "out"},
|
|
{"inst": "vcvtm.u32.f16 Sd, Sn" , "t32": "1111|11101|'Vd|11|11|11|Vd|10010|1|'Vn|0|Vn" , "it": "out"},
|
|
{"inst": "vcvtn.s16.f16 Dd, Dn" , "t32": "1111|11111|Vd'|11|01|11|Vd|00010|0|Vn'|0|Vn" , "it": "out"},
|
|
{"inst": "vcvtn.s16.f16 Vd, Vn" , "t32": "1111|11111|Vd'|11|01|11|Vd|00010|1|Vn'|0|Vn" , "it": "out"},
|
|
{"inst": "vcvtn.u16.f16 Dd, Dn" , "t32": "1111|11111|Vd'|11|01|11|Vd|00011|0|Vn'|0|Vn" , "it": "out"},
|
|
{"inst": "vcvtn.u16.f16 Vd, Vn" , "t32": "1111|11111|Vd'|11|01|11|Vd|00011|1|Vn'|0|Vn" , "it": "out"},
|
|
{"inst": "vcvtn.s32.f16 Sd, Sn" , "t32": "1111|11101|'Vd|11|11|01|Vd|10011|1|'Vn|0|Vn" , "it": "out"},
|
|
{"inst": "vcvtn.u32.f16 Sd, Sn" , "t32": "1111|11101|'Vd|11|11|01|Vd|10010|1|'Vn|0|Vn" , "it": "out"},
|
|
{"inst": "vcvtp.s16.f16 Dd, Dn" , "t32": "1111|11111|Vd'|11|01|11|Vd|00100|0|Vn'|0|Vn" , "it": "out"},
|
|
{"inst": "vcvtp.s16.f16 Vd, Vn" , "t32": "1111|11111|Vd'|11|01|11|Vd|00100|1|Vn'|0|Vn" , "it": "out"},
|
|
{"inst": "vcvtp.u16.f16 Dd, Dn" , "t32": "1111|11111|Vd'|11|01|11|Vd|00101|0|Vn'|0|Vn" , "it": "out"},
|
|
{"inst": "vcvtp.u16.f16 Vd, Vn" , "t32": "1111|11111|Vd'|11|01|11|Vd|00101|1|Vn'|0|Vn" , "it": "out"},
|
|
{"inst": "vcvtp.s32.f16 Sd, Sn" , "t32": "1111|11101|'Vd|11|11|10|Vd|10011|1|'Vn|0|Vn" , "it": "out"},
|
|
{"inst": "vcvtp.u32.f16 Sd, Sn" , "t32": "1111|11101|'Vd|11|11|10|Vd|10010|1|'Vn|0|Vn" , "it": "out"},
|
|
{"inst": "vcvtr.s32.f16 Sd, Sn" , "t32": "1110|11101|'Vd|11|11|01|Vd|10010|1|'Vn|0|Vn" , "it": "out"},
|
|
{"inst": "vcvtr.u32.f16 Sd, Sn" , "t32": "1110|11101|'Vd|11|11|00|Vd|10010|1|'Vn|0|Vn" , "it": "out"},
|
|
{"inst": "vcvtt.f32.f16 Sd, Sn" , "t32": "1110|11101|'Vd|11|00|10|Vd|10101|1|'Vn|0|Vn" , "it": "any"},
|
|
{"inst": "vcvtt.f16.f32 Sd, Sn" , "t32": "1110|11101|'Vd|11|00|11|Vd|10101|1|'Vn|0|Vn" , "it": "any"},
|
|
{"inst": "vcvtt.f64.f16 Dd, Sn" , "t32": "1110|11101|Vd'|11|00|10|Vd|10111|1|'Vn|0|Vn" , "it": "any"},
|
|
{"inst": "vcvtt.f16.f64 Sd, Dn" , "t32": "1110|11101|'Vd|11|00|11|Vd|10111|1|Vn'|0|Vn" , "it": "any"}
|
|
]},
|
|
|
|
{"category": "ASIMD", "ext": "I8MM", "data": [
|
|
{"inst": "vsmmla.s8 Vd, Vn, Vm" , "a32": "1111|11000|Vd'|10|Vn|Vd|1100|Vn'|1|Vm'|0|Vm"},
|
|
{"inst": "vsudot.u8 Dd, Dn, Dm<=15[#i]" , "a32": "1111|11101|Vd'|00|Vn|Vd|1101|Vn'|0|i:1|1|Vm"},
|
|
{"inst": "vsudot.u8 Vd, Vn, Dm<=15[#i]" , "a32": "1111|11101|Vd'|00|Vn|Vd|1101|Vn'|1|i:1|1|Vm"},
|
|
{"inst": "vummla.u8 Vd, Vn, Vm" , "a32": "1111|11000|Vd'|10|Vn|Vd|1100|Vn'|1|Vm'|1|Vm"},
|
|
{"inst": "vusdot.s8 Dd, Dn, Dm" , "a32": "1111|11001|Vd'|10|Vn|Vd|1101|Vn'|0|Vm'|0|Vm"},
|
|
{"inst": "vusdot.s8 Vd, Vn, Vm" , "a32": "1111|11001|Vd'|10|Vn|Vd|1101|Vn'|1|Vm'|0|Vm"},
|
|
{"inst": "vusdot.s8 Dd, Dn, Dm<=15[#i]" , "a32": "1111|11101|Vd'|00|Vn|Vd|1101|Vn'|0|i:1|0|Vm"},
|
|
{"inst": "vusdot.s8 Vd, Vn, Dm<=15[#i]" , "a32": "1111|11101|Vd'|00|Vn|Vd|1101|Vn'|1|i:1|0|Vm"},
|
|
{"inst": "vusmmla.s8 Vd, Vn, Vm" , "a32": "1111|11001|Vd'|10|Vn|Vd|1100|Vn'|1|Vm'|0|Vm"}
|
|
]},
|
|
|
|
{"category": "ASIMD", "ext": "I8MM", "data": [
|
|
{"inst": "vsmmla.s8 Vd, Vn, Vm" , "t32": "1111|11000|Vd'|10|Vn|Vd|1100|Vn'|1|Vm'|0|Vm" , "it": "out"},
|
|
{"inst": "vsudot.u8 Dd, Dn, Dm<=15[#i]" , "t32": "1111|11101|Vd'|00|Vn|Vd|1101|Vn'|0|i:1|1|Vm" , "it": "out"},
|
|
{"inst": "vsudot.u8 Vd, Vn, Dm<=15[#i]" , "t32": "1111|11101|Vd'|00|Vn|Vd|1101|Vn'|1|i:1|1|Vm" , "it": "out"},
|
|
{"inst": "vummla.u8 Vd, Vn, Vm" , "t32": "1111|11000|Vd'|10|Vn|Vd|1100|Vn'|1|Vm'|1|Vm" , "it": "out"},
|
|
{"inst": "vusdot.s8 Dd, Dn, Dm" , "t32": "1111|11001|Vd'|10|Vn|Vd|1101|Vn'|0|Vm'|0|Vm" , "it": "out"},
|
|
{"inst": "vusdot.s8 Vd, Vn, Vm" , "t32": "1111|11001|Vd'|10|Vn|Vd|1101|Vn'|1|Vm'|0|Vm" , "it": "out"},
|
|
{"inst": "vusdot.s8 Dd, Dn, Dm<=15[#i]" , "t32": "1111|11101|Vd'|00|Vn|Vd|1101|Vn'|0|i:1|0|Vm" , "it": "out"},
|
|
{"inst": "vusdot.s8 Vd, Vn, Dm<=15[#i]" , "t32": "1111|11101|Vd'|00|Vn|Vd|1101|Vn'|1|i:1|0|Vm" , "it": "out"},
|
|
{"inst": "vusmmla.s8 Vd, Vn, Vm" , "t32": "1111|11001|Vd'|10|Vn|Vd|1100|Vn'|1|Vm'|0|Vm" , "it": "out"}
|
|
]},
|
|
|
|
{"category": "ASIMD", "ext": "JSCVT", "data": [
|
|
{"inst": "vjcvt.s32.f64 Sd, Dn" , "a32": "1110|11101|'Vd|11|1001|Vd|1011|11|Vn'|0|Vn"}
|
|
]},
|
|
|
|
{"category": "ASIMD", "ext": "JSCVT", "data": [
|
|
{"inst": "vjcvt.s32.f64 Sd, Dn" , "t32": "1110|11101|'Vd|11|1001|Vd|1011|11|Vn'|0|Vn" , "it": "out"}
|
|
]},
|
|
|
|
{"category": "ASIMD", "ext": "RDM", "data": [
|
|
{"inst": "vqrdmlah.s16-32 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|sz|Vn|Vd|1011|Vn'|0|Vm'|1|Vm"},
|
|
{"inst": "vqrdmlah.s16-32 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|sz|Vn|Vd|1011|Vn'|1|Vm'|1|Vm"},
|
|
{"inst": "vqrdmlah.s16 Dd, Dn, Dm<=07[#i]" , "a32": "1111|00101|Vd'|sz|Vn|Vd|1110|Vn'|1|i:1|0|i:1|Vm:3"},
|
|
{"inst": "vqrdmlah.s16 Vd, Vn, Dm<=07[#i]" , "a32": "1111|00111|Vd'|sz|Vn|Vd|1110|Vn'|1|i:1|0|i:1|Vm:3"},
|
|
{"inst": "vqrdmlah.s32 Dd, Dn, Dm<=15[#i]" , "a32": "1111|00101|Vd'|sz|Vn|Vd|1110|Vn'|1|i:1|0|Vm"},
|
|
{"inst": "vqrdmlah.s32 Vd, Vn, Dm<=15[#i]" , "a32": "1111|00111|Vd'|sz|Vn|Vd|1110|Vn'|1|i:1|0|Vm"},
|
|
{"inst": "vqrdmlsh.s16-32 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|sz|Vn|Vd|1100|Vn'|0|Vm'|1|Vm"},
|
|
{"inst": "vqrdmlsh.s16-32 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|sz|Vn|Vd|1100|Vn'|1|Vm'|1|Vm"},
|
|
{"inst": "vqrdmlsh.s16 Dd, Dn, Dm<=07[#i]" , "a32": "1111|00101|Vd'|sz|Vn|Vd|1111|Vn'|1|i:1|0|i:1|Vm:3"},
|
|
{"inst": "vqrdmlsh.s16 Vd, Vn, Dm<=07[#i]" , "a32": "1111|00111|Vd'|sz|Vn|Vd|1111|Vn'|1|i:1|0|i:1|Vm:3"},
|
|
{"inst": "vqrdmlsh.s32 Dd, Dn, Dm<=15[#i]" , "a32": "1111|00101|Vd'|sz|Vn|Vd|1111|Vn'|1|i:1|0|Vm"},
|
|
{"inst": "vqrdmlsh.s32 Vd, Vn, Dm<=15[#i]" , "a32": "1111|00111|Vd'|sz|Vn|Vd|1111|Vn'|1|i:1|0|Vm"}
|
|
]},
|
|
|
|
{"category": "ASIMD", "ext": "RDM", "data": [
|
|
{"inst": "vqrdmlah.s16-32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|sz|Vn|Vd|1011|Vn'|0|Vm'|1|Vm" , "it": "out"},
|
|
{"inst": "vqrdmlah.s16-32 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|sz|Vn|Vd|1011|Vn'|1|Vm'|1|Vm" , "it": "out"},
|
|
{"inst": "vqrdmlah.s16 Dd, Dn, Dm<=07[#i]" , "t32": "1110|11111|Vd'|sz|Vn|Vd|1110|Vn'|1|i:1|0|i:1|Vm:3" , "it": "out"},
|
|
{"inst": "vqrdmlah.s16 Vd, Vn, Dm<=07[#i]" , "t32": "1111|11111|Vd'|sz|Vn|Vd|1110|Vn'|1|i:1|0|i:1|Vm:3" , "it": "out"},
|
|
{"inst": "vqrdmlah.s32 Dd, Dn, Dm<=15[#i]" , "t32": "1110|11111|Vd'|sz|Vn|Vd|1110|Vn'|1|i:1|0|Vm" , "it": "out"},
|
|
{"inst": "vqrdmlah.s32 Vd, Vn, Dm<=15[#i]" , "t32": "1111|11111|Vd'|sz|Vn|Vd|1110|Vn'|1|i:1|0|Vm" , "it": "out"},
|
|
{"inst": "vqrdmlsh.s16-32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|sz|Vn|Vd|1100|Vn'|0|Vm'|1|Vm" , "it": "out"},
|
|
{"inst": "vqrdmlsh.s16-32 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|sz|Vn|Vd|1100|Vn'|1|Vm'|1|Vm" , "it": "out"},
|
|
{"inst": "vqrdmlsh.s16 Dd, Dn, Dm<=07[#i]" , "t32": "1110|11111|Vd'|sz|Vn|Vd|1111|Vn'|1|i:1|0|i:1|Vm:3" , "it": "out"},
|
|
{"inst": "vqrdmlsh.s16 Vd, Vn, Dm<=07[#i]" , "t32": "1111|11111|Vd'|sz|Vn|Vd|1111|Vn'|1|i:1|0|i:1|Vm:3" , "it": "out"},
|
|
{"inst": "vqrdmlsh.s32 Dd, Dn, Dm<=15[#i]" , "t32": "1110|11111|Vd'|sz|Vn|Vd|1111|Vn'|1|i:1|0|Vm" , "it": "out"},
|
|
{"inst": "vqrdmlsh.s32 Vd, Vn, Dm<=15[#i]" , "t32": "1111|11111|Vd'|sz|Vn|Vd|1111|Vn'|1|i:1|0|Vm" , "it": "out"}
|
|
]},
|
|
|
|
{"category": "ASIMD CRYPTO_HASH", "ext": "SHA1", "data": [
|
|
{"inst": "sha1c.32 Vx, Vn, Vm" , "a32": "1111|00100|Vx'|00|Vn|Vx|1100|Vn'|1|Vm'|0|Vm"},
|
|
{"inst": "sha1h.32 Vd, Vn" , "a32": "1111|00111|Vd'|11|1001|Vd|0|0101|1|Vn'|0|Vn"},
|
|
{"inst": "sha1m.32 Vx, Vn, Vm" , "a32": "1111|00100|Vx'|10|Vn|Vx|1100|Vn'|1|Vm'|0|Vm"},
|
|
{"inst": "sha1p.32 Vx, Vn, Vm" , "a32": "1111|00100|Vx'|01|Vn|Vx|1100|Vn'|1|Vm'|0|Vm"},
|
|
{"inst": "sha1su0.32 Vx, Vn, Vm" , "a32": "1111|00100|Vx'|11|Vn|Vx|1100|Vn'|1|Vm'|0|Vm"},
|
|
{"inst": "sha1su1.32 Vx, Vn" , "a32": "1111|00111|Vx'|11|1010|Vx|0|0111|0|Vn'|0|Vn"}
|
|
]},
|
|
|
|
{"category": "ASIMD CRYPTO_HASH", "ext": "SHA1", "data": [
|
|
{"inst": "sha1c.32 Vx, Vn, Vm" , "t32": "1110|11110|Vx'|00|Vn|Vx|1100|Vn'|1|Vm'|0|Vm" , "it": "out"},
|
|
{"inst": "sha1h.32 Vd, Vn" , "t32": "1111|11111|Vd'|11|1001|Vd|0|0101|1|Vn'|0|Vn" , "it": "out"},
|
|
{"inst": "sha1m.32 Vx, Vn, Vm" , "t32": "1110|11110|Vx'|10|Vn|Vx|1100|Vn'|1|Vm'|0|Vm" , "it": "out"},
|
|
{"inst": "sha1p.32 Vx, Vn, Vm" , "t32": "1110|11110|Vx'|01|Vn|Vx|1100|Vn'|1|Vm'|0|Vm" , "it": "out"},
|
|
{"inst": "sha1su0.32 Vx, Vn, Vm" , "t32": "1110|11110|Vx'|11|Vn|Vx|1100|Vn'|1|Vm'|0|Vm" , "it": "out"},
|
|
{"inst": "sha1su1.32 Vx, Vn" , "t32": "1111|11111|Vx'|11|1010|Vx|0|0111|0|Vn'|0|Vn" , "it": "out"}
|
|
]},
|
|
|
|
{"category": "ASIMD CRYPTO_HASH", "ext": "SHA256", "data": [
|
|
{"inst": "sha256h.32 Vx, Vn, Vm" , "a32": "1111|00110|Vx'|00|Vn|Vx|1100|Vn'|1|Vm'|0|Vm"},
|
|
{"inst": "sha256h2.32 Vx, Vn, Vm" , "a32": "1111|00110|Vx'|01|Vn|Vx|1100|Vn'|1|Vm'|0|Vm"},
|
|
{"inst": "sha256su0.32 Vx, Vn" , "a32": "1111|00111|Vx'|11|1010|Vx|0|0111|1|Vn'|0|Vn"},
|
|
{"inst": "sha256su1.32 Vx, Vn, Vm" , "a32": "1111|00110|Vx'|10|Vn|Vx|1100|Vn'|1|Vm'|0|Vm"}
|
|
]},
|
|
|
|
{"category": "ASIMD CRYPTO_HASH", "ext": "SHA256", "data": [
|
|
{"inst": "sha256h.32 Vx, Vn, Vm" , "t32": "1111|11110|Vx'|00|Vn|Vx|1100|Vn'|1|Vm'|0|Vm" , "it": "out"},
|
|
{"inst": "sha256h2.32 Vx, Vn, Vm" , "t32": "1111|11110|Vx'|01|Vn|Vx|1100|Vn'|1|Vm'|0|Vm" , "it": "out"},
|
|
{"inst": "sha256su0.32 Vx, Vn" , "t32": "1111|11111|Vx'|11|1010|Vx|0|0111|1|Vn'|0|Vn" , "it": "out"},
|
|
{"inst": "sha256su1.32 Vx, Vn, Vm" , "t32": "1111|11110|Vx'|10|Vn|Vx|1100|Vn'|1|Vm'|0|Vm" , "it": "out"}
|
|
]}
|
|
]
|
|
}
|