3744 lines
475 KiB
JSON
3744 lines
475 KiB
JSON
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{
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"registers": {
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"r": {"kind": "gp" , "any": "r", "names": ["r0-31"]},
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"b": {"kind": "vec", "any": "b", "names": ["b0-31"]},
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"h": {"kind": "vec", "any": "h", "names": ["h0-31"]},
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"s": {"kind": "vec", "any": "s", "names": ["s0-31"]},
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"d": {"kind": "vec", "any": "d", "names": ["d0-31"]},
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"v": {"kind": "vec", "any": "v", "names": ["v0-31"]}
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},
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"instructions": [
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{"category": "GP", "data": [
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{"inst": "adc Wd, Wn, Wm" , "op": "00011010|000|Rm|000000|Rn|Rd" , "io": "C=R"},
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{"inst": "adc Xd, Xn, Xm" , "op": "10011010|000|Rm|000000|Rn|Rd" , "io": "C=R"},
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{"inst": "adcs Wd, Wn, Wm" , "op": "00111010|000|Rm|000000|Rn|Rd" , "io": "N=W Z=W C=X V=W"},
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{"inst": "adcs Xd, Xn, Xm" , "op": "10111010|000|Rm|000000|Rn|Rd" , "io": "N=W Z=W C=X V=W"},
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{"inst": "add Wd, Wn, Wm, {lsl|lsr|asr #n}" , "op": "00001011|sop:2|0|Rm|n:6|Rn|Rd"},
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{"inst": "add Xd, Xn, Xm, {lsl|lsr|asr #n}" , "op": "10001011|sop:2|0|Rm|n:6|Rn|Rd"},
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{"inst": "add Wd|WSP, Wn|WSP, Wm, {extend #n}" , "op": "00001011|001|Rm|option:3|n:3|Rn|Rd"},
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{"inst": "add Xd|SP, Xn|SP, Rm, {extend #n}" , "op": "10001011|001|Rm|option:3|n:3|Rn|Rd"},
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{"inst": "add Wd|WSP, Wn|WSP, #immZ, {lsl #n=0|12}" , "op": "00010001|0|n:1|immZ:12|Rn|Rd"},
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{"inst": "add Xd|SP, Xn|SP, #immZ, {lsl #n=0|12}" , "op": "10010001|0|n:1|immZ:12|Rn|Rd"},
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{"inst": "adds Wd, Wn, Wm, {lsl|lsr|asr #n}" , "op": "00101011|sop:2|0|Rm|n:6|Rn|Rd" , "io": "N=W Z=W C=W V=W"},
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{"inst": "adds Xd, Xn, Xm, {lsl|lsr|asr #n}" , "op": "10101011|sop:2|0|Rm|n:6|Rn|Rd" , "io": "N=W Z=W C=W V=W"},
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{"inst": "adds Wd, Wn|WSP, Wm, {extend #n}" , "op": "00101011|001|Rm|option:3|n:3|Rn|Rd" , "io": "N=W Z=W C=W V=W"},
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{"inst": "adds Xd, Xn|SP, Rm, {extend #n}" , "op": "10101011|001|Rm|option:3|n:3|Rn|Rd" , "io": "N=W Z=W C=W V=W"},
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{"inst": "adds Wd|WSP, Wn|WSP, #immZ, {lsl #n=0|12}" , "op": "00110001|0|n:1|immZ:12|Rn|Rd" , "io": "N=W Z=W C=W V=W"},
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{"inst": "adds Xd|SP, Xn|SP, #immZ, {lsl #n=0|12}" , "op": "10110001|0|n:1|immZ:12|Rn|Rd" , "io": "N=W Z=W C=W V=W"},
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{"inst": "adr Xd, #relS" , "op": "0|relS[1:0]|10000|relS[20:2]|Rd"},
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{"inst": "adrp Xd, #relS" , "op": "1|relS[1:0]|10000|relS[20:2]|Rd"},
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{"inst": "and Wd|WSP, Wn, Wm, {sop #n}" , "op": "00001010|sop|0|Rm|n:6|Rn|Rd" , "imm": "ShiftImm(n, x)"},
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{"inst": "and Xd|SP, Xn, Xm, {sop #n}" , "op": "10001010|sop|0|Rm|n:6|Rn|Rd" , "imm": "ShiftImm(n, x)"},
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{"inst": "and Wd|WSP, Wn, #imm" , "op": "00010010|0|imm:13|Rn|Rd" , "imm": "LogicalImm(imm, 0)"},
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{"inst": "and Xd|SP, Xn, #imm" , "op": "10010010|0|imm:13|Rn|Rd" , "imm": "LogicalImm(imm, 1)"},
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{"inst": "ands Wd|WSP, Wn, Wm, {sop #n}" , "op": "01101010|sop|0|Rm|n:6|Rn|Rd" , "io": "N=W Z=W C=W V=W", "imm": "ShiftImm(n, x)"},
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{"inst": "ands Xd|SP, Xn, Xm, {sop #n}" , "op": "11101010|sop|0|Rm|n:6|Rn|Rd" , "io": "N=W Z=W C=W V=W", "imm": "ShiftImm(n, x)"},
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{"inst": "ands Wd|WSP, Wn, #imm" , "op": "01110010|0|imm:13|Rn|Rd" , "io": "N=W Z=W C=W V=W", "imm": "LogicalImm(imm, 0)"},
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{"inst": "ands Xd|SP, Xn, #imm" , "op": "11110010|0|imm:13|Rn|Rd" , "io": "N=W Z=W C=W V=W", "imm": "LogicalImm(imm, 1)"},
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{"inst": "asr|asrv Wd, Wn, Wm" , "op": "00011010|110|Rm|001010|Rn|Rd"},
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{"inst": "asr|asrv Xd, Xn, Xm" , "op": "10011010|110|Rm|001010|Rn|Rd"},
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{"inst": "asr Wd, Wn, #n" , "op": "00010011|00|immr:6|011111|Rn|Rd"},
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{"inst": "asr Xd, Xn, #n" , "op": "10010011|01|immr:6|111111|Rn|Rd"},
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{"inst": "at #at_op, Xt" , "op": "11010101|00001|op1:3|0111|CRm|op2:3|Rt" , "imm": "ImmAt(at_op)"},
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{"inst": "b #relS*4" , "op": "000101|relS:26" , "control": "jump"},
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{"inst": "b.<cond> #relS*4" , "op": "01010100|relS:19|0|cond" , "control": "branch", "io": "N=R Z=R C=R V=R"},
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{"inst": "bfc Wd, #lsb, #width" , "op": "00110011|00|immr:6|imms:6|11111|Rd"},
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{"inst": "bfc Xd, #lsb, #width" , "op": "10110011|01|immr:6|imms:6|11111|Rd"},
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{"inst": "bfi Wd, Wn, #lsb, #width" , "op": "00110011|00|immr:6|imms:6|Rn|Rd"},
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{"inst": "bfi Xd, Xn, #lsb, #width" , "op": "10110011|01|immr:6|imms:6|Rn|Rd"},
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{"inst": "bfm Wd, Wn, #immr, #imms" , "op": "00110011|00|immr:6|imms:6|Rn|Rd" , "imm": "ImmBFM(immr, imms)"},
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{"inst": "bfm Xd, Xn, #immr, #imms" , "op": "10110011|01|immr:6|imms:6|Rn|Rd" , "imm": "ImmBFM(immr, imms)"},
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{"inst": "bfxil Wd, Wn, #lsb, #width" , "op": "00110011|00|immr:6|imms:6|Rn|Rd"},
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{"inst": "bfxil Xd, Xn, #lsb, #width" , "op": "10110011|01|immr:6|imms:6|Rn|Rd"},
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{"inst": "bic Wd, Wn, Wm, {sop #n}" , "op": "00001010|sop:2|1|Rm|n:6|Rn|Rd"},
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{"inst": "bic Xd, Xn, Xm, {sop #n}" , "op": "10001010|sop:2|1|Rm|n:6|Rn|Rd"},
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{"inst": "bics Wd, Wn, Wm, {sop #n}" , "op": "01101010|sop:2|1|Rm|n:6|Rn|Rd" , "io": "N=W Z=W C=W V=W"},
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{"inst": "bics Xd, Xn, Xm, {sop #n}" , "op": "11101010|sop:2|1|Rm|n:6|Rn|Rd" , "io": "N=W Z=W C=W V=W"},
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{"inst": "bl #relS*4" , "op": "100101|relS:26" , "control": "call"},
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{"inst": "blr Xn" , "op": "11010110|001|11111000000|Rn|00000" , "control": "call"},
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{"inst": "br Xn" , "op": "11010110|000|11111000000|Rn|00000" , "control": "jump"},
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{"inst": "brk #imm" , "op": "11010100|001|imm:16|00000"},
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{"inst": "cbnz Wn, #relS*4" , "op": "00110101|relS:19|Rn" , "control": "branch"},
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{"inst": "cbnz Xn, #relS*4" , "op": "10110101|relS:19|Rn" , "control": "branch"},
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{"inst": "cbz Wn, #relS*4" , "op": "00110101|relS:19|Rn" , "control": "branch"},
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{"inst": "cbz Xn, #relS*4" , "op": "10110101|relS:19|Rn" , "control": "branch"},
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{"inst": "ccmn Wn, Wm, #nzcv, #cond" , "op": "00111010|010|Rm|cond|00|Rn|0|nzcv" , "io": "N=W Z=W C=W V=W"},
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{"inst": "ccmn Xn, Xm, #nzcv, #cond" , "op": "10111010|010|Rm|cond|00|Rn|0|nzcv" , "io": "N=W Z=W C=W V=W"},
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{"inst": "ccmn Wn, #imm, #nzcv, #cond" , "op": "00111010|010|imm:5|cond|10|Rn|0|nzcv" , "io": "N=W Z=W C=W V=W"},
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{"inst": "ccmn Xn, #imm, #nzcv, #cond" , "op": "10111010|010|imm:5|cond|10|Rn|0|nzcv" , "io": "N=W Z=W C=W V=W"},
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{"inst": "ccmp Wn, Wm, #nzcv, #cond" , "op": "01111010|010|Rm|cond|00|Rn|0|nzcv" , "io": "N=W Z=W C=W V=W"},
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{"inst": "ccmp Xn, Xm, #nzcv, #cond" , "op": "11111010|010|Rm|cond|00|Rn|0|nzcv" , "io": "N=W Z=W C=W V=W"},
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{"inst": "ccmp Wn, #imm, #nzcv, #cond" , "op": "01111010|010|imm:5|cond|10|Rn|0|nzcv" , "io": "N=W Z=W C=W V=W"},
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{"inst": "ccmp Xn, #imm, #nzcv, #cond" , "op": "11111010|010|imm:5|cond|10|Rn|0|nzcv" , "io": "N=W Z=W C=W V=W"},
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{"inst": "cinc Wd, Wn, #cond" , "op": "00011010|100|Rn|cond|01|Rn|Rd" , "io": "N=R Z=R C=R V=R"},
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{"inst": "cinc Xd, Xn, #cond" , "op": "10011010|100|Rn|cond|01|Rn|Rd" , "io": "N=R Z=R C=R V=R"},
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{"inst": "cinv Wd, Wn, #cond" , "op": "01011010|100|Rn|cond|00|Rn|Rd" , "io": "N=R Z=R C=R V=R"},
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{"inst": "cinv Xd, Xn, #cond" , "op": "11011010|100|Rn|cond|00|Rn|Rd" , "io": "N=R Z=R C=R V=R"},
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{"inst": "clrex {#imm=15}" , "op": "11010101|000|00011|0011|CRm|010|11111" , "CRm": "imm"},
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{"inst": "cls Wd, Wn" , "op": "01011010|110|00000000101|Rn|Rd"},
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{"inst": "cls Xd, Xn" , "op": "11011010|110|00000000101|Rn|Rd"},
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{"inst": "clz Wd, Wn" , "op": "01011010|110|00000000100|Rn|Rd"},
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{"inst": "clz Xd, Xn" , "op": "11011010|110|00000000100|Rn|Rd"},
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{"inst": "cmn Wn|WSP, #imm, {lsl #n=0|12}" , "op": "00110001|0|n:1|imm:12|Rn|11111" , "io": "N=W Z=W C=W V=W"},
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{"inst": "cmn Xn|SP, #imm, {lsl #n=0|12}" , "op": "10110001|0|n:1|imm:12|Rn|11111" , "io": "N=W Z=W C=W V=W"},
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{"inst": "cmn Wn|WSP, Wm, {extend #n}" , "op": "00101011|001|Rm|option:3|n:3|Rn|11111" , "io": "N=W Z=W C=W V=W"},
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{"inst": "cmn Xn|SP, Rm, {extend #n}" , "op": "10101011|001|Rm|option:3|n:3|Rn|11111" , "io": "N=W Z=W C=W V=W"},
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{"inst": "cmn Wn, Wm, {lsl|lsr|asr #n}" , "op": "00101011|sop:2|0|Rm|n:6|Rn|11111" , "io": "N=W Z=W C=W V=W"},
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{"inst": "cmn Xn, Xm, {lsl|lsr|asr #n}" , "op": "10101011|sop:2|0|Rm|n:6|Rn|11111" , "io": "N=W Z=W C=W V=W"},
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{"inst": "cmp Wn, Wm, {lsl|lsr|asr #n}" , "op": "01101011|sop:2|0|Rm|n:6|Rn|11111" , "io": "N=W Z=W C=W V=W"},
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{"inst": "cmp Xn, Xm, {lsl|lsr|asr #n}" , "op": "11101011|sop:2|0|Rm|n:6|Rn|11111" , "io": "N=W Z=W C=W V=W"},
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{"inst": "cmp Wn|WSP, Wm, {extend #n}" , "op": "01101011|001|Rm|option:3|n:3|Rn|11111" , "io": "N=W Z=W C=W V=W"},
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{"inst": "cmp Xn|SP, Rm, {extend #n}" , "op": "11101011|001|Rm|option:3|n:3|Rn|11111" , "io": "N=W Z=W C=W V=W"},
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{"inst": "cmp Wn|WSP, #imm, {lsl #n=0|12}" , "op": "01110001|0|n:1|imm:12|Rn|11111" , "io": "N=W Z=W C=W V=W"},
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{"inst": "cmp Xn|SP, #imm, {lsl #n=0|12}" , "op": "11110001|0|n:1|imm:12|Rn|11111" , "io": "N=W Z=W C=W V=W"},
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{"inst": "cneg Wd, Wn, #cond" , "op": "01011010|100|Rn|cond|01|Rn|Rd" , "io": "N=R Z=R C=R V=R"},
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{"inst": "cneg Xd, Xn, #cond" , "op": "11011010|100|Rn|cond|01|Rn|Rd" , "io": "N=R Z=R C=R V=R"},
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{"inst": "csdb" , "op": "11010101|00|000|011|0010|0010|100|11111"},
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{"inst": "csel Wd, Wn, Wm, #cond" , "op": "00011010|100|Rm|cond|00|Rn|Rd" , "io": "N=R Z=R C=R V=R"},
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{"inst": "csel Xd, Xn, Xm, #cond" , "op": "10011010|100|Rm|cond|00|Rn|Rd" , "io": "N=R Z=R C=R V=R"},
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{"inst": "cset Wd, #cond" , "op": "00011010|100|11111|cond|01|11111|Rd" , "io": "N=R Z=R C=R V=R"},
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{"inst": "cset Xd, #cond" , "op": "10011010|100|11111|cond|01|11111|Rd" , "io": "N=R Z=R C=R V=R"},
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{"inst": "csetm Wd, #cond" , "op": "01011010|100|11111|cond|00|11111|Rd" , "io": "N=R Z=R C=R V=R"},
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{"inst": "csetm Xd, #cond" , "op": "11011010|100|11111|cond|00|11111|Rd" , "io": "N=R Z=R C=R V=R"},
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{"inst": "csinc Wd, Wn, Wm, #cond" , "op": "00011010|100|Rm|cond|01|Rn|Rd" , "io": "N=R Z=R C=R V=R"},
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{"inst": "csinc Xd, Xn, Xm, #cond" , "op": "10011010|100|Rm|cond|01|Rn|Rd" , "io": "N=R Z=R C=R V=R"},
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{"inst": "csinv Wd, Wn, Wm, #cond" , "op": "01011010|100|Rm|cond|00|Rn|Rd" , "io": "N=R Z=R C=R V=R"},
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{"inst": "csinv Xd, Xn, Xm, #cond" , "op": "11011010|100|Rm|cond|00|Rn|Rd" , "io": "N=R Z=R C=R V=R"},
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{"inst": "csneg Wd, Wn, Wm, #cond" , "op": "01011010|100|Rm|cond|01|Rn|Rd" , "io": "N=R Z=R C=R V=R"},
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{"inst": "csneg Xd, Xn, Xm, #cond" , "op": "11011010|100|Rm|cond|01|Rn|Rd" , "io": "N=R Z=R C=R V=R"},
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{"inst": "dc #dc_op, Xt" , "op": "11010101|000|01|op1:3|0111|CRm|op2:3|Rt" , "imm": "ImmDC(dc_op)"},
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{"inst": "dcps1 {#imm}" , "op": "11010100|101|imm:16|00001"},
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{"inst": "dcps2 {#imm}" , "op": "11010100|101|imm:16|00010"},
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{"inst": "dcps3 {#imm}" , "op": "11010100|101|imm:16|00011"},
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{"inst": "dmb #barrier_op" , "op": "11010101|000|00|011|0011|CRm|101|11111" , "imm": "ImmDataBarrier(barrier_op)"},
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{"inst": "drps" , "op": "11010110|101|11111|00000|01111|1|00000"},
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{"inst": "dsb #barrier_op" , "op": "11010101|000|00|011|0011|CRm|101|11111" , "imm": "ImmDataBarrier(barrier_op)", "ext": "XS"},
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{"inst": "eon Wd, Wn, Wm, {sop #n}" , "op": "01001010|sop:2|1|Rm|n:6|Rn|Rd"},
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{"inst": "eon Xd, Xn, Xm, {sop #n}" , "op": "11001010|sop:2|1|Rm|n:6|Rn|Rd"},
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{"inst": "eor Wd, Wn, Wm, {sop #n}" , "op": "01001010|sop:2|0|Rm|n:6|Rn|Rd"},
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{"inst": "eor Xd, Xn, Xm, {sop #n}" , "op": "11001010|sop:2|0|Rm|n:6|Rn|Rd"},
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{"inst": "eor Wd|WSP, Wn, #imm" , "op": "01010010|0|imm:13|Rn|Rd" , "imm": "LogicalImm(imm, 0)"},
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{"inst": "eor Xd|SP, Xn, #imm" , "op": "11010010|0|imm:13|Rn|Rd" , "imm": "LogicalImm(imm, 1)"},
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{"inst": "eret" , "op": "11010110|100|11111|0000|00|11111|00000"},
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{"inst": "extr Wd, Wn, Wm, #imm" , "op": "00010011|100|Rm|0|imm:5|Rn|Rd"},
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{"inst": "extr Xd, Xn, Xm, #imm" , "op": "10010011|110|Rm|imm:6|Rn|Rd"},
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{"inst": "hint #imm" , "op": "11010101|000|00|011|0010|imm:7|11111"},
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{"inst": "hlt #imm" , "op": "11010100|010|imm:16|00000"},
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{"inst": "hvc #imm" , "op": "11010100|000|imm:16|00010"},
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{"inst": "ic #ic_op" , "op": "11010101|000|01|op1:3|0111|CRm|op2:3|11111" , "imm": "ImmIC(ic_op)"},
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{"inst": "ic #ic_op, Xt" , "op": "11010101|000|01|op1:3|0111|CRm|op2:3|Rt" , "imm": "ImmIC(ic_op)"},
|
||
|
|
{"inst": "isb {#isb_op=15}" , "op": "11010101|000|00|011|0011|CRm|110|11111" , "imm": "ImmISB(isb_op)"},
|
||
|
|
{"inst": "ldar Wd, [Xn|SP]" , "op": "10001000|110|11111|1|11111|Rn|Rd"},
|
||
|
|
{"inst": "ldar Xd, [Xn|SP]" , "op": "11001000|110|11111|1|11111|Rn|Rd"},
|
||
|
|
{"inst": "ldarb Wd, [Xn|SP]" , "op": "00001000|110|11111|1|11111|Rn|Rd"},
|
||
|
|
{"inst": "ldarh Wd, [Xn|SP]" , "op": "01001000|110|11111|1|11111|Rn|Rd"},
|
||
|
|
{"inst": "ldaxp Wd, Wd2, [Xn|SP]" , "op": "10001000|011|11111|1|Rd2|Rn|Rd"},
|
||
|
|
{"inst": "ldaxp Xd, Xd2, [Xn|SP]" , "op": "11001000|011|11111|1|Rd2|Rn|Rd"},
|
||
|
|
{"inst": "ldaxr Wd, [Xn|SP]" , "op": "10001000|010|11111|1|11111|Rn|Rd"},
|
||
|
|
{"inst": "ldaxr Xd, [Xn|SP]" , "op": "11001000|010|11111|1|11111|Rn|Rd"},
|
||
|
|
{"inst": "ldaxrb Wd, [Xn|SP]" , "op": "00001000|010|11111|1|11111|Rn|Rd"},
|
||
|
|
{"inst": "ldaxrh Xd, [Xn|SP]" , "op": "01001000|010|11111|1|11111|Rn|Rd"},
|
||
|
|
{"inst": "ldnp Wd, Wd2, [Xn|SP, #soff*4]" , "op": "00101000|01|soff:7|Rd2|Rn|Rd"},
|
||
|
|
{"inst": "ldnp Xd, Xd2, [Xn|SP, #soff*8]" , "op": "10101000|01|soff:7|Rd2|Rn|Rd"},
|
||
|
|
{"inst": "ldp Wd, Wd2, [Xn|SP, #soff*4]{@}{!}" , "op": "0010100|!post|W|1|soff:7|Rd2|Rn|Rd"},
|
||
|
|
{"inst": "ldp Xd, Xd2, [Xn|SP, #soff*8]{@}{!}" , "op": "1010100|!post|W|1|soff:7|Rd2|Rn|Rd"},
|
||
|
|
{"inst": "ldpsw Xd, Xd2, [Xn|SP, #soff*4]{@}{!}" , "op": "0110100|!post|W|1|soff:7|Rd2|Rn|Rd"},
|
||
|
|
{"inst": "ldr Wd, [Xn|SP, #zoff*4]" , "op": "10111001|01|zoff:12|Rn|Rd"},
|
||
|
|
{"inst": "ldr Xd, [Xn|SP, #zoff*8]" , "op": "11111001|01|zoff:12|Rn|Rd"},
|
||
|
|
{"inst": "ldr Wd, [Xn|SP, #soff*4]@" , "op": "10111000|010|soff:9|01|Rn|Rd"},
|
||
|
|
{"inst": "ldr Xd, [Xn|SP, #soff*8]@" , "op": "11111000|010|soff:9|01|Rn|Rd"},
|
||
|
|
{"inst": "ldr Wd, [Xn|SP, #soff*4]!" , "op": "10111000|010|soff:9|11|Rn|Rd"},
|
||
|
|
{"inst": "ldr Xd, [Xn|SP, #soff*8]!" , "op": "11111000|010|soff:9|11|Rn|Rd"},
|
||
|
|
{"inst": "ldr Wd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "10111000|011|Rm|option:3|s:1|10|Rn|Rd" , "imm": "ImmLDR(iop, n)"},
|
||
|
|
{"inst": "ldr Xd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "11111000|011|Rm|option:3|s:1|10|Rn|Rd" , "imm": "ImmLDR(iop, n)"},
|
||
|
|
{"inst": "ldr Wd, [PC, #soff*4]" , "op": "00011000|soff:19|Rd"},
|
||
|
|
{"inst": "ldr Xd, [PC, #soff*4]" , "op": "01011000|soff:19|Rd"},
|
||
|
|
{"inst": "ldrb Wd, [Xn|SP, #zoff]" , "op": "00111001|01|zoff:12|Rn|Rd"},
|
||
|
|
{"inst": "ldrb Wd, [Xn|SP, #soff]@" , "op": "00111000|010|soff:9|01|Rn|Rd"},
|
||
|
|
{"inst": "ldrb Wd, [Xn|SP, #soff]!" , "op": "00111000|010|soff:9|11|Rn|Rd"},
|
||
|
|
{"inst": "ldrb Wd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "00111000|011|Rm|option:3|s:1|10|Rn|Rd" , "imm": "ImmLDRB(iop, n)"},
|
||
|
|
{"inst": "ldrh Wd, [Xn|SP, #zoff*2]" , "op": "01111001|01|zoff:12|Rn|Rd"},
|
||
|
|
{"inst": "ldrh Wd, [Xn|SP, #soff*2]@" , "op": "01111000|010|soff:9|01|Rn|Rd"},
|
||
|
|
{"inst": "ldrh Wd, [Xn|SP, #soff*2]!" , "op": "01111000|010|soff:9|11|Rn|Rd"},
|
||
|
|
{"inst": "ldrh Wd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "01111000|011|Rm|option:3|s:1|10|Rn|Rd" , "imm": "ImmLDRH(iop, n)"},
|
||
|
|
{"inst": "ldrsb Wd, [Xn|SP, #zoff]" , "op": "00111001|11|zoff:12|Rn|Rd"},
|
||
|
|
{"inst": "ldrsb Xd, [Xn|SP, #zoff]" , "op": "00111001|10|zoff:12|Rn|Rd"},
|
||
|
|
{"inst": "ldrsb Wd, [Xn|SP, #soff]@" , "op": "00111000|110|soff:9|01|Rn|Rd"},
|
||
|
|
{"inst": "ldrsb Xd, [Xn|SP, #soff]@" , "op": "00111000|100|soff:9|01|Rn|Rd"},
|
||
|
|
{"inst": "ldrsb Wd, [Xn|SP, #soff]!" , "op": "00111000|110|soff:9|11|Rn|Rd"},
|
||
|
|
{"inst": "ldrsb Xd, [Xn|SP, #soff]!" , "op": "00111000|100|soff:9|11|Rn|Rd"},
|
||
|
|
{"inst": "ldrsb Wd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "00111000|111|Rm|option:3|s:1|10|Rn|Rd" , "imm": "ImmLDRB(iop, n)"},
|
||
|
|
{"inst": "ldrsb Xd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "00111000|101|Rm|option:3|s:1|10|Rn|Rd" , "imm": "ImmLDRB(iop, n)"},
|
||
|
|
{"inst": "ldrsh Wd, [Xn|SP, #zoff*2]" , "op": "01111001|11|zoff:12|Rn|Rd"},
|
||
|
|
{"inst": "ldrsh Xd, [Xn|SP, #zoff*2]" , "op": "01111001|10|zoff:12|Rn|Rd"},
|
||
|
|
{"inst": "ldrsh Wd, [Xn|SP, #soff*2]@" , "op": "01111000|110|soff:9|01|Rn|Rd"},
|
||
|
|
{"inst": "ldrsh Xd, [Xn|SP, #soff*2]@" , "op": "01111000|100|soff:9|01|Rn|Rd"},
|
||
|
|
{"inst": "ldrsh Wd, [Xn|SP, #soff*2]!" , "op": "01111000|110|soff:9|11|Rn|Rd"},
|
||
|
|
{"inst": "ldrsh Xd, [Xn|SP, #soff*2]!" , "op": "01111000|100|soff:9|11|Rn|Rd"},
|
||
|
|
{"inst": "ldrsh Wd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "01111000|111|Rm|option:3|s:1|10|Rn|Rd" , "imm": "ImmLDRH(iop, n)"},
|
||
|
|
{"inst": "ldrsh Xd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "01111000|101|Rm|option:3|s:1|10|Rn|Rd" , "imm": "ImmLDRH(iop, n)"},
|
||
|
|
{"inst": "ldrsw Xd, [Xn|SP, #zoff*4]" , "op": "10111001|10|zoff:12|Rn|Rd"},
|
||
|
|
{"inst": "ldrsw Xd, [Xn|SP, #soff*4]@" , "op": "10111000|100|soff:9|01|Rn|Rd"},
|
||
|
|
{"inst": "ldrsw Xd, [Xn|SP, #soff*4]!" , "op": "10111000|100|soff:9|11|Rn|Rd"},
|
||
|
|
{"inst": "ldrsw Xd, [PC, #soff*4]" , "op": "10011000|soff:19|Rd"},
|
||
|
|
{"inst": "ldrsw Xd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "10111000|101|Rm|option:3|s:1|10|Rn|Rd" , "imm": "ImmLDRW(iop, n)"},
|
||
|
|
{"inst": "ldtr Wd, [Xn|SP, #soff]" , "op": "10111000|010|soff:9|10|Rn|Rd"},
|
||
|
|
{"inst": "ldtr Xd, [Xn|SP, #soff]" , "op": "11111000|010|soff:9|10|Rn|Rd"},
|
||
|
|
{"inst": "ldtrb Wd, [Xn|SP, #soff]" , "op": "00111000|010|soff:9|10|Rn|Rd"},
|
||
|
|
{"inst": "ldtrh Wd, [Xn|SP, #soff]" , "op": "01111000|010|soff:9|10|Rn|Rd"},
|
||
|
|
{"inst": "ldtrsb Wd, [Xn|SP, #soff]" , "op": "00111000|100|soff:9|10|Rn|Rd"},
|
||
|
|
{"inst": "ldtrsb Xd, [Xn|SP, #soff]" , "op": "00111000|110|soff:9|10|Rn|Rd"},
|
||
|
|
{"inst": "ldtrsh Wd, [Xn|SP, #soff]" , "op": "01111000|100|soff:9|10|Rn|Rd"},
|
||
|
|
{"inst": "ldtrsh Xd, [Xn|SP, #soff]" , "op": "01111000|110|soff:9|10|Rn|Rd"},
|
||
|
|
{"inst": "ldtrsw Xd, [Xn|SP, #soff]" , "op": "10111000|100|soff:9|10|Rn|Rd"},
|
||
|
|
{"inst": "ldur Wd, [Xn|SP, #soff]" , "op": "10111000|010|soff:9|00|Rn|Rd"},
|
||
|
|
{"inst": "ldur Xd, [Xn|SP, #soff]" , "op": "11111000|010|soff:9|00|Rn|Rd"},
|
||
|
|
{"inst": "ldurb Wd, [Xn|SP, #soff]" , "op": "00111000|010|soff:9|00|Rn|Rd"},
|
||
|
|
{"inst": "ldurh Wd, [Xn|SP, #soff]" , "op": "01111000|010|soff:9|00|Rn|Rd"},
|
||
|
|
{"inst": "ldursb Wd, [Xn|SP, #soff]" , "op": "00111000|100|soff:9|00|Rn|Rd"},
|
||
|
|
{"inst": "ldursb Xd, [Xn|SP, #soff]" , "op": "00111000|110|soff:9|00|Rn|Rd"},
|
||
|
|
{"inst": "ldursh Wd, [Xn|SP, #soff]" , "op": "01111000|100|soff:9|00|Rn|Rd"},
|
||
|
|
{"inst": "ldursh Xd, [Xn|SP, #soff]" , "op": "01111000|110|soff:9|00|Rn|Rd"},
|
||
|
|
{"inst": "ldursw Xd, [Xn|SP, #soff]" , "op": "10111000|100|soff:9|00|Rn|Rd"},
|
||
|
|
{"inst": "ldxp Wd, Wd2, [Xn|SP, #soff*4]" , "op": "10001000|011|11111|0|Rd2|Rn|Rd"},
|
||
|
|
{"inst": "ldxp Xd, Xd2, [Xn|SP, #soff*8]" , "op": "11001000|011|11111|0|Rd2|Rn|Rd"},
|
||
|
|
{"inst": "ldxr Wd, [Xn|SP]" , "op": "10001000|010|11111|0|11111|Rn|Rd"},
|
||
|
|
{"inst": "ldxr Xd, [Xn|SP]" , "op": "11001000|010|11111|0|11111|Rn|Rd"},
|
||
|
|
{"inst": "ldxrb Wd, [Xn|SP]" , "op": "00001000|010|11111|0|11111|Rn|Rd"},
|
||
|
|
{"inst": "ldxrh Wd, [Xn|SP]" , "op": "01001000|010|11111|0|11111|Rn|Rd"},
|
||
|
|
{"inst": "lsl|lslv Wd, Wn, Wm" , "op": "00011010|110|Rm|001000|Rn|Rd"},
|
||
|
|
{"inst": "lsl|lslv Xd, Xn, Xm" , "op": "10011010|110|Rm|001000|Rn|Rd"},
|
||
|
|
{"inst": "lsl Wd, Wn, #n" , "op": "01010011|00|immr:6|imms:6|Rn|Rd"},
|
||
|
|
{"inst": "lsl Xd, Xn, #n" , "op": "11010011|01|immr:6|imms:6|Rn|Rd"},
|
||
|
|
{"inst": "lsr|lsrv Wd, Wn, Wm" , "op": "00011010|110|Rm|001001|Rn|Rd"},
|
||
|
|
{"inst": "lsr|lsrv Xd, Xn, Xm" , "op": "10011010|110|Rm|001001|Rn|Rd"},
|
||
|
|
{"inst": "lsr Wd, Wn, #n" , "op": "01010011|00|immr:6|011111|Rn|Rd"},
|
||
|
|
{"inst": "lsr Xd, Xn, #n" , "op": "11010011|01|immr:6|111111|Rn|Rd"},
|
||
|
|
{"inst": "madd Wd, Wn, Wm, Wa" , "op": "00011011|000|Rm|0|Ra|Rn|Rd"},
|
||
|
|
{"inst": "madd Xd, Xn, Xm, Xa" , "op": "10011011|000|Rm|0|Ra|Rn|Rd"},
|
||
|
|
{"inst": "mneg Wd, Wn, Wm" , "op": "00011011|000|Rm|1|11111|Rn|Rd"},
|
||
|
|
{"inst": "mneg Xd, Xn, Xm" , "op": "10011011|000|Rm|1|11111|Rn|Rd"},
|
||
|
|
{"inst": "mov Wd, Wm" , "op": "00101010|000|Rm|0|00000|11111|Rd"},
|
||
|
|
{"inst": "mov Xd, Xm" , "op": "10101010|000|Rm|0|00000|11111|Rd"},
|
||
|
|
{"inst": "mov Wd|WSP, Wn|WSP" , "op": "00010001|000|00000|0|00000|Rn|Rd"},
|
||
|
|
{"inst": "mov Xd|SP, Xn|SP" , "op": "10010001|000|00000|0|00000|Rn|Rd"},
|
||
|
|
{"inst": "mov Wd, #imm" , "op": "01010010|1|hw:2|imm:16|Rd" , "imm": "ImmWide(imm, 0, 0)"},
|
||
|
|
{"inst": "mov Xd, #imm" , "op": "11010010|1|hw:2|imm:16|Rd" , "imm": "ImmWide(imm, 0, 1)"},
|
||
|
|
{"inst": "mov Wd, #imm" , "op": "00010010|1|hw:2|imm:16|Rd" , "imm": "ImmWideInv(imm, 0, 0)"},
|
||
|
|
{"inst": "mov Xd, #imm" , "op": "10010010|1|hw:2|imm:16|Rd" , "imm": "ImmWideInv(imm, 0, 1)"},
|
||
|
|
{"inst": "mov Wd|WSP, #log_imm" , "op": "00110010|00|immr:6|imms:6|11111|Rd" , "imm": "ImmLogical(log_imm, 0)"},
|
||
|
|
{"inst": "mov Xd|SP, #log_imm" , "op": "10110010|01|immr:6|imms:6|11111|Rd" , "imm": "ImmLogical(log_imm, 1)"},
|
||
|
|
{"inst": "movk Wd, #imm, {lsl #n}" , "op": "01110010|1|hw:2|imm:16|Rd" , "imm": "ImmWide(imm, n, 0)"},
|
||
|
|
{"inst": "movk Xd, #imm, {lsl #n}" , "op": "11110010|1|hw:2|imm:16|Rd" , "imm": "ImmWide(imm, n, 1)"},
|
||
|
|
{"inst": "movn Wd, #imm, {lsl #n}" , "op": "00010010|1|hw:2|imm:16|Rd" , "imm": "ImmWideInv(imm, n, 0)"},
|
||
|
|
{"inst": "movn Xd, #imm, {lsl #n}" , "op": "10010010|1|hw:2|imm:16|Rd" , "imm": "ImmWideInv(imm, n, 1)"},
|
||
|
|
{"inst": "movz Wd, #imm, {lsl #n}" , "op": "01010010|1|hw:2|imm:16|Rd" , "imm": "ImmWide(imm, n, 0)"},
|
||
|
|
{"inst": "movz Xd, #imm, {lsl #n}" , "op": "11010010|1|hw:2|imm:16|Rd" , "imm": "ImmWide(imm, n, 1)"},
|
||
|
|
{"inst": "mrs Xd, #sysreg" , "op": "11010101|001|1|sysreg:15|Rd"},
|
||
|
|
{"inst": "msr #sysreg, Xs" , "op": "11010101|000|1|sysreg:15|Rs"},
|
||
|
|
{"inst": "msr #pstatefield, #imm" , "op": "11010101|000|00|op1:3|0100|imm:4|op2:3|11111" , "imm": "ImmMSR(pstatefield)"},
|
||
|
|
{"inst": "msub Wd, Wn, Wm, Wa" , "op": "00011011|000|Rm|1|Ra|Rn|Rd"},
|
||
|
|
{"inst": "msub Xd, Xn, Xm, Xa" , "op": "10011011|000|Rm|1|Ra|Rn|Rd"},
|
||
|
|
{"inst": "mul Wd, Wn, Wm" , "op": "00011011|000|Rm|0|11111|Rn|Rd"},
|
||
|
|
{"inst": "mul Xd, Xn, Xm" , "op": "10011011|000|Rm|0|11111|Rn|Rd"},
|
||
|
|
{"inst": "mvn Wd, Wn, {sop #n}" , "op": "X0101010|sop|1|Rn|n:6|Rn|Rd"},
|
||
|
|
{"inst": "mvn Xd, Xn, {sop #n}" , "op": "X0101010|sop|1|Rn|n:6|Rn|Rd"},
|
||
|
|
{"inst": "neg Wd, Wm, {lsl|lsr|asr #n}" , "op": "01001011|sop:2|0|Rm|n:6|11111|Rd"},
|
||
|
|
{"inst": "neg Xd, Xm, {lsl|lsr|asr #n}" , "op": "11001011|sop:2|0|Rm|n:6|11111|Rd"},
|
||
|
|
{"inst": "negs Wd, Wm, {lsl|lsr|asr #n}" , "op": "01101011|sop:2|0|Rm|n:6|11111|Rd" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "negs Xd, Xm, {lsl|lsr|asr #n}" , "op": "11101011|sop:2|0|Rm|n:6|11111|Rd" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "ngc Wd, Wm" , "op": "01011010|000|Rm|0|00000|11111|Rd" , "io": "C=R"},
|
||
|
|
{"inst": "ngc Xd, Xm" , "op": "11011010|000|Rm|0|00000|11111|Rd" , "io": "C=R"},
|
||
|
|
{"inst": "ngcs Wd, Wm" , "op": "01111010|000|Rm|0|00000|11111|Rd" , "io": "N=W Z=W C=X V=W"},
|
||
|
|
{"inst": "ngcs Xd, Xm" , "op": "11111010|000|Rm|0|00000|11111|Rd" , "io": "N=W Z=W C=X V=W"},
|
||
|
|
{"inst": "nop" , "op": "11010101|00|000011|0010|0000|000|11111"},
|
||
|
|
{"inst": "orn Wd, Wn, Wm, {sop #n}" , "op": "00101010|sop:2|1|Rm|n:6|Rn|Rd"},
|
||
|
|
{"inst": "orn Xd, Xn, Xm, {sop #n}" , "op": "10101010|sop:2|1|Rm|n:6|Rn|Rd"},
|
||
|
|
{"inst": "orr Wd, Wn, Wm, {sop #n}" , "op": "00101010|sop:2|0|Rm|n:6|Rn|Rd"},
|
||
|
|
{"inst": "orr Xd, Xn, Xm, {sop #n}" , "op": "10101010|sop:2|0|Rm|n:6|Rn|Rd"},
|
||
|
|
{"inst": "orr Wd|WSP, Wn, #log_imm" , "op": "00110010|0|imm:13|Rn|Rd" , "imm": "ImmLogical(log_imm, 0)"},
|
||
|
|
{"inst": "orr Xd|SP, Xn, #log_imm" , "op": "10110010|0|imm:13|Rn|Rd" , "imm": "ImmLogical(log_imm, 1)"},
|
||
|
|
{"inst": "prfm #prf_op, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n*8}]" , "op": "11111000|101|Rm|option:3|n:1|10|Rn|prf_op:5" , "imm": "ImmPRF(prf_op)"},
|
||
|
|
{"inst": "prfm #prf_op, [Xn|SP, #zoff]" , "op": "11111001|10|zoff:12|Rn|prf_op:5" , "imm": "ImmPRF(prf_op)"},
|
||
|
|
{"inst": "prfm #prf_op, [PC, #soff*4]" , "op": "11011000|soff:19|prf_op:5" , "imm": "ImmPRF(prf_op)"},
|
||
|
|
{"inst": "prfum #prf_op, [Xn|SP, #soff]" , "op": "11111000|100|soff:9|00|Rn|prf_op:5" , "imm": "ImmPRF(prf_op)"},
|
||
|
|
{"inst": "pssbb" , "op": "11010101|000|00011|0011|0100|100|11111"},
|
||
|
|
{"inst": "rbit Wd, Wn" , "op": "01011010|110|00000|0|00000|Rn|Rd"},
|
||
|
|
{"inst": "rbit Xd, Xn" , "op": "11011010|110|00000|0|00000|Rn|Rd"},
|
||
|
|
{"inst": "ret Xn" , "op": "11010100|010|11111|0|00000|Rn|00000" , "control": "return"},
|
||
|
|
{"inst": "rev Wd, Wn" , "op": "01011010|110|00000|0|00010|Rn|Rd"},
|
||
|
|
{"inst": "rev|rev64 Xd, Xn" , "op": "11011010|110|00000|0|00011|Rn|Rd"},
|
||
|
|
{"inst": "rev16 Wd, Wn" , "op": "01011010|110|00000|0|00001|Rn|Rd"},
|
||
|
|
{"inst": "rev16 Xd, Xn" , "op": "11011010|110|00000|0|00001|Rn|Rd"},
|
||
|
|
{"inst": "rev32 Xd, Xn" , "op": "11011010|110|00000|0|00010|Rn|Rd"},
|
||
|
|
{"inst": "ror|rorv Wd, Wn, Wm" , "op": "00011010|110|Rm|0|01011|Rn|Rd"},
|
||
|
|
{"inst": "ror|rorv Xd, Xn, Xm" , "op": "10011010|110|Rm|0|01011|Rn|Rd"},
|
||
|
|
{"inst": "ror Wd, Wn, #n" , "op": "00010011|100|Rn|n:6|Rn|Rd"},
|
||
|
|
{"inst": "ror Xd, Xn, #n" , "op": "10010011|111|Rn|n:6|Rn|Rd"},
|
||
|
|
{"inst": "sbc Wd, Wn, Wm" , "op": "01011010|000|Rm|0|00000|Rn|Rd" , "io": "C=R"},
|
||
|
|
{"inst": "sbc Xd, Xn, Xm" , "op": "11011010|000|Rm|0|00000|Rn|Rd" , "io": "C=R"},
|
||
|
|
{"inst": "sbcs Wd, Wn, Wm" , "op": "01111010|000|Rm|0|00000|Rn|Rd" , "io": "N=W Z=W C=X V=W"},
|
||
|
|
{"inst": "sbcs Xd, Xn, Xm" , "op": "11111010|000|Rm|0|00000|Rn|Rd" , "io": "N=W Z=W C=X V=W"},
|
||
|
|
{"inst": "sbfiz Wd, Wn, #lsb, #width" , "op": "00010011|00|immr:6|imms:6|Rn|Rd" , "imm": "ImmBFIZ(lsb, width, 0)"},
|
||
|
|
{"inst": "sbfiz Xd, Xn, #lsb, #width" , "op": "10010011|01|immr:6|imms:6|Rn|Rd" , "imm": "ImmBFIZ(lsb, width, 1)"},
|
||
|
|
{"inst": "sbfm Wd, Wn, #immr, #imms" , "op": "00010011|00|immr:6|imms:6|Rn|Rd" , "imm": "ImmBFM(immr, imms, 0)"},
|
||
|
|
{"inst": "sbfm Xd, Xn, #immr, #imms" , "op": "10010011|01|immr:6|imms:6|Rn|Rd" , "imm": "ImmBFM(immr, imms, 1)"},
|
||
|
|
{"inst": "sbfx Wd, Wn, #lsb, #width" , "op": "00010011|00|immr:6|imms:6|Rn|Rd" , "imm": "ImmBFX(lsb, width, 0)"},
|
||
|
|
{"inst": "sbfx Xd, Xn, #lsb, #width" , "op": "10010011|01|immr:6|imms:6|Rn|Rd" , "imm": "ImmBFX(lsb, width, 1)"},
|
||
|
|
{"inst": "sdiv Wd, Wn, Wm" , "op": "00011010|110|Rm|0|00011|Rn|Rd"},
|
||
|
|
{"inst": "sdiv Xd, Xn, Xm" , "op": "10011010|110|Rm|0|00011|Rn|Rd"},
|
||
|
|
{"inst": "sev" , "op": "11010101|000|00011|0010|0000|100|11111"},
|
||
|
|
{"inst": "sevl" , "op": "11010101|000|00011|0010|0000|101|11111"},
|
||
|
|
{"inst": "smaddl Xd, Wn, Wm, Xa" , "op": "10011011|001|Rm|0|Ra|Rn|Rd"},
|
||
|
|
{"inst": "smc #zimm" , "op": "11010100|000|zimm:16|00011"},
|
||
|
|
{"inst": "smnegl Xd, Wn, Wm" , "op": "10011011|001|Rm|1|11111|Rn|Rd"},
|
||
|
|
{"inst": "smsubl Xd, Wn, Wm, Xa" , "op": "10011011|001|Rm|1|Ra|Rn|Rd"},
|
||
|
|
{"inst": "smulh Xd, Xn, Xm" , "op": "10011011|010|Rm|0|11111|Rn|Rd"},
|
||
|
|
{"inst": "smull Xd, Wn, Wm" , "op": "10011011|001|Rm|0|11111|Rn|Rd"},
|
||
|
|
{"inst": "ssbb" , "op": "11010101|000|00011|0011|0000|100|11111"},
|
||
|
|
{"inst": "stlr Ws, [Xn|SP]" , "op": "10001000|100|11111|1|11111|Rn|Rs"},
|
||
|
|
{"inst": "stlr Xs, [Xn|SP]" , "op": "11001000|100|11111|1|11111|Rn|Rs"},
|
||
|
|
{"inst": "stlrb Ws, [Xn|SP]" , "op": "00001000|100|11111|1|11111|Rn|Rs"},
|
||
|
|
{"inst": "stlrh Ws, [Xn|SP]" , "op": "01001000|100|11111|1|11111|Rn|Rs"},
|
||
|
|
{"inst": "stlxp Wd, Ws, Ws2, [Xn|SP]" , "op": "10001000|001|Rd|1|Rs2|Rn|Rs"},
|
||
|
|
{"inst": "stlxp Wd, Xs, Xs2, [Xn|SP]" , "op": "11001000|001|Rd|1|Rs2|Rn|Rs"},
|
||
|
|
{"inst": "stlxr Wd, Ws, [Xn|SP]" , "op": "10001000|000|Rd|1|11111|Rn|Rs"},
|
||
|
|
{"inst": "stlxr Wd, Xs, [Xn|SP]" , "op": "11001000|000|Rd|1|11111|Rn|Rs"},
|
||
|
|
{"inst": "stlxrb Wd, Ws, [Xn|SP]" , "op": "00001000|000|Rd|1|11111|Rn|Rs"},
|
||
|
|
{"inst": "stlxrh Wd, Xs, [Xn|SP]" , "op": "01001000|000|Rd|1|11111|Rn|Rs"},
|
||
|
|
{"inst": "stnp Ws, Ws2, [Xn|SP, #simm*4]" , "op": "00101000|00|simm:7|Rs2|Rn|Rs"},
|
||
|
|
{"inst": "stnp Xs, Xs2, [Xn|SP, #simm*8]" , "op": "10101000|00|simm:7|Rs2|Rn|Rs"},
|
||
|
|
{"inst": "stp Ws, Ws2, [Xn|SP, #simm*4]{@}{!}" , "op": "0010100|!post|W|0|simm:7|Rs2|Rn|Rs"},
|
||
|
|
{"inst": "stp Xs, Xs2, [Xn|SP, #simm*8]{@}{!}" , "op": "1010100|!post|W|0|simm:7|Rs2|Rn|Rs"},
|
||
|
|
{"inst": "str Ws, [Xn|SP, #zoff*4]" , "op": "10111001|00|zoff:12|Rn|Rs"},
|
||
|
|
{"inst": "str Xs, [Xn|SP, #zoff*8]" , "op": "11111001|00|zoff:12|Rn|Rs"},
|
||
|
|
{"inst": "str Ws, [Xn|SP, #soff*4]@" , "op": "10111000|000|soff:9|01|Rn|Rs"},
|
||
|
|
{"inst": "str Xs, [Xn|SP, #soff*8]@" , "op": "11111000|000|soff:9|01|Rn|Rs"},
|
||
|
|
{"inst": "str Ws, [Xn|SP, #soff*4]!" , "op": "10111000|000|soff:9|11|Rn|Rs"},
|
||
|
|
{"inst": "str Xs, [Xn|SP, #soff*8]!" , "op": "11111000|000|soff:9|11|Rn|Rs"},
|
||
|
|
{"inst": "str Ws, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "10111000|001|Rm|option:3|s:1|10|Rn|Rs" , "imm": "ImmLDR_STR(iop, n)"},
|
||
|
|
{"inst": "str Xs, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "11111000|001|Rm|option:3|s:1|10|Rn|Rs" , "imm": "ImmLDR_STR(iop, n)"},
|
||
|
|
{"inst": "strb Ws, [Xn|SP, #zoff]" , "op": "00111001|00|zoff:12|Rn|Rs"},
|
||
|
|
{"inst": "strb Ws, [Xn|SP, #soff]@" , "op": "00111000|000|soff:9|01|Rn|Rs"},
|
||
|
|
{"inst": "strb Ws, [Xn|SP, #soff]!" , "op": "00111000|000|soff:9|11|Rn|Rs"},
|
||
|
|
{"inst": "strb Ws, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "00111000|001|Rm|option:3|s:1|10|Rn|Rs" , "imm": "ImmLDRB_STRB(iop, n)"},
|
||
|
|
{"inst": "strh Ws, [Xn|SP, #zoff*2]" , "op": "01111001|00|zoff:12|Rn|Rs"},
|
||
|
|
{"inst": "strh Ws, [Xn|SP, #soff*2]@" , "op": "01111000|000|soff:9|01|Rn|Rs"},
|
||
|
|
{"inst": "strh Ws, [Xn|SP, #soff*2]!" , "op": "01111000|000|soff:9|11|Rn|Rs"},
|
||
|
|
{"inst": "strh Ws, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "01111000|001|Rm|option:3|s:1|10|Rn|Rs" , "imm": "ImmLDRH_STRH(iop, n)"},
|
||
|
|
{"inst": "sttr Ws, [Xn|SP, #soff]" , "op": "10111000|000|soff:9|10|Rn|Rs"},
|
||
|
|
{"inst": "sttr Xs, [Xn|SP, #soff]" , "op": "11111000|000|soff:9|10|Rn|Rs"},
|
||
|
|
{"inst": "sttrb Ws, [Xn|SP, #soff]" , "op": "00111000|000|soff:9|10|Rn|Rs"},
|
||
|
|
{"inst": "sttrh Ws, [Xn|SP, #soff]" , "op": "01111000|000|soff:9|10|Rn|Rs"},
|
||
|
|
{"inst": "stur Ws, [Xn|SP, #soff]" , "op": "10111000|000|soff:9|00|Rn|Rs"},
|
||
|
|
{"inst": "stur Xs, [Xn|SP, #soff]" , "op": "11111000|000|soff:9|00|Rn|Rs"},
|
||
|
|
{"inst": "sturb Ws, [Xn|SP, #soff]" , "op": "00111000|000|soff:9|00|Rn|Rs"},
|
||
|
|
{"inst": "sturh Ws, [Xn|SP, #soff]" , "op": "01111000|000|soff:9|00|Rn|Rs"},
|
||
|
|
{"inst": "stxp Wd, Ws, Ws2, [Xn|SP]" , "op": "10001000|001|Rd|0|Rs2|Rn|Rs"},
|
||
|
|
{"inst": "stxp Wd, Xs, Xs2, [Xn|SP]" , "op": "11001000|001|Rd|0|Rs2|Rn|Rs"},
|
||
|
|
{"inst": "stxr Wd, Ws, [Xn|SP]" , "op": "10001000|000|Rd|0|11111|Rn|Rs"},
|
||
|
|
{"inst": "stxr Wd, Xs, [Xn|SP]" , "op": "11001000|000|Rd|0|11111|Rn|Rs"},
|
||
|
|
{"inst": "stxrb Wd, Ws, [Xn|SP]" , "op": "00001000|000|Rd|0|11111|Rn|Rs"},
|
||
|
|
{"inst": "stxrh Wd, Xs, [Xn|SP]" , "op": "01001000|000|Rd|0|11111|Rn|Rs"},
|
||
|
|
{"inst": "sub Wd, Wn, Wm, {lsl|lsr|asr #n}" , "op": "01001011|sop:2|0|Rm|n:6|Rn|Rd"},
|
||
|
|
{"inst": "sub Xd, Xn, Xm, {lsl|lsr|asr #n}" , "op": "11001011|sop:2|0|Rm|n:6|Rn|Rd"},
|
||
|
|
{"inst": "sub Wd|WSP, Wn|WSP, Wm, {extend #n}" , "op": "01001011|00|1|Rm|option:3|n:3|Rn|Rd"},
|
||
|
|
{"inst": "sub Xd|SP, Xn|SP, Rm, {extend #n}" , "op": "11001011|00|1|Rm|option:3|n:3|Rn|Rd"},
|
||
|
|
{"inst": "sub Wd|WSP, Wn|WSP, #immZ, {lsl #n=0|12}" , "op": "01010001|0|n:1|immZ:12|Rn|Rd"},
|
||
|
|
{"inst": "sub Xd|SP, Xn|SP, #immZ, {lsl #n=0|12}" , "op": "11010001|0|n:1|immZ:12|Rn|Rd"},
|
||
|
|
{"inst": "subs Wd, Wn, Wm, {lsl|lsr|asr #n}" , "op": "01101011|sop:2|0|Rm|n:6|Rn|Rd" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "subs Xd, Xn, Xm, {lsl|lsr|asr #n}" , "op": "11101011|sop:2|0|Rm|n:6|Rn|Rd" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "subs Wd, Wn|WSP, Wm, {extend #n}" , "op": "01101011|00|1|Rm|option:3|n:3|Rn|Rd" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "subs Xd, Xn|SP, Rm, {extend #n}" , "op": "11101011|00|1|Rm|option:3|n:3|Rn|Rd" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "subs Wd|WSP, Wn|WSP, #immZ, {lsl #n=0|12}" , "op": "01110001|0|n:1|immZ:12|Rn|Rd" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "subs Xd|SP, Xn|SP, #immZ, {lsl #n=0|12}" , "op": "11110001|0|n:1|immZ:12|Rn|Rd" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "svc #zimm" , "op": "11010100|000|zimm:16|00001"},
|
||
|
|
{"inst": "sxtb Wd, Wn" , "op": "00010011|000|00000|0|00111|Rn|Rd"},
|
||
|
|
{"inst": "sxtb Xd, Wn" , "op": "10010011|010|00000|0|00111|Rn|Rd"},
|
||
|
|
{"inst": "sxth Wd, Wn" , "op": "00010011|000|00000|0|01111|Rn|Rd"},
|
||
|
|
{"inst": "sxth Xd, Wn" , "op": "10010011|010|00000|0|01111|Rn|Rd"},
|
||
|
|
{"inst": "sxtw Xd, Wn" , "op": "10010011|010|00000|0|11111|Rn|Rd"},
|
||
|
|
{"inst": "sys #op1, #Cn, #Cm, #op2" , "op": "11010101|000|01|op1:3|CRn|CRm|op2:3|11111"},
|
||
|
|
{"inst": "sys #op1, #Cn, #Cm, #op2, Xt" , "op": "11010101|000|01|op1:3|CRn|CRm|op2:3|Rt"},
|
||
|
|
{"inst": "sysl Xd, #op1, #Cn, #Cm, #op2" , "op": "11010101|001|01|op1:3|CRn|CRm|op2:3|Rd"},
|
||
|
|
{"inst": "tbnz Wt, #imm, #relS*4" , "op": "00110111|imm:5|relS:14|Rt"},
|
||
|
|
{"inst": "tbnz Xt, #imm, #relS*4" , "op": "imm:1|0110111|imm:5|relS:14|Rt"},
|
||
|
|
{"inst": "tbz Wt, #imm, #relS*4" , "op": "00110110|imm:5|relS:14|Rt"},
|
||
|
|
{"inst": "tbz Xt, #imm, #relS*4" , "op": "imm:1|0110110|imm:5|relS:14|Rt"},
|
||
|
|
{"inst": "tlbi #tlbi_op" , "op": "11010101|00|001|op1:3|1000|CRm|op2:3|11111" , "imm": "ImmTLBI(tlbi_op)"},
|
||
|
|
{"inst": "tlbi #tlbi_op, Xt" , "op": "11010101|00|001|op1:3|1000|CRm|op2:3|Rt" , "imm": "ImmTLBI(tlbi_op)"},
|
||
|
|
{"inst": "tst Wn, Wm, {sop #n}" , "op": "01101010|sop:2|0|Rm|n:6|Rn|11111" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "tst Xn, Xm, {sop #n}" , "op": "11101010|sop:2|0|Rm|n:6|Rn|11111" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "tst Wn, #imm" , "op": "01110010|0|imm:13|Rn|11111" , "io": "N=W Z=W C=W V=W", "imm": "LogicalImm(imm, 0)"},
|
||
|
|
{"inst": "tst Xn, #imm" , "op": "11110010|0|imm:13|Rn|11111" , "io": "N=W Z=W C=W V=W", "imm": "LogicalImm(imm, 1)"},
|
||
|
|
{"inst": "ubfiz Wd, Wn, #lsb, #width" , "op": "01010011|00|immr:6|imms:6|Rn|Rd" , "imm": "ImmBFIZ(lsb, width, 0)"},
|
||
|
|
{"inst": "ubfiz Xd, Xn, #lsb, #width" , "op": "11010011|01|immr:6|imms:6|Rn|Rd" , "imm": "ImmBFIZ(lsb, width, 1)"},
|
||
|
|
{"inst": "ubfm Wd, Wn, #immr, #imms" , "op": "01010011|00|immr:6|imms:6|Rn|Rd" , "imm": "ImmBFM(immr, imms, 0)"},
|
||
|
|
{"inst": "ubfm Xd, Xn, #immr, #imms" , "op": "11010011|01|immr:6|imms:6|Rn|Rd" , "imm": "ImmBFM(immr, imms, 1)"},
|
||
|
|
{"inst": "ubfx Wd, Wn, #lsb, #width" , "op": "01010011|00|immr:6|imms:6|Rn|Rd" , "imm": "ImmBFX(lsb, width, 0)"},
|
||
|
|
{"inst": "ubfx Xd, Xn, #lsb, #width" , "op": "11010011|01|immr:6|imms:6|Rn|Rd" , "imm": "ImmBFX(lsb, width, 1)"},
|
||
|
|
{"inst": "udf #imm" , "op": "00000000|000|00000|imm:16"},
|
||
|
|
{"inst": "udiv Wd, Wn, Wm" , "op": "00011010|110|Rm|0|00010|Rn|Rd"},
|
||
|
|
{"inst": "udiv Xd, Xn, Xm" , "op": "10011010|110|Rm|0|00010|Rn|Rd"},
|
||
|
|
{"inst": "umaddl Xd, Wn, Wm, Xa" , "op": "10011011|101|Rm|0|Ra|Rn|Rd"},
|
||
|
|
{"inst": "umnegl Xd, Wn, Wm" , "op": "10011011|101|Rm|1|11111|Rn|Rd"},
|
||
|
|
{"inst": "umsubl Xd, Wn, Wm, Xa" , "op": "10011011|101|Rm|1|Ra|Rn|Rd"},
|
||
|
|
{"inst": "umulh Xd, Xn, Xm" , "op": "10011011|110|Rm|0|11111|Rn|Rd"},
|
||
|
|
{"inst": "umull Xd, Wn, Wm" , "op": "10011011|101|Rm|0|11111|Rn|Rd"},
|
||
|
|
{"inst": "uxtb Wd, Wn" , "op": "01010011|000|00000|0|00111|Rn|Rd"},
|
||
|
|
{"inst": "uxth Wd, Wn" , "op": "01010011|000|00000|0|01111|Rn|Rd"},
|
||
|
|
{"inst": "wfe" , "op": "11010101|000|00011|0010|0000|010|11111"},
|
||
|
|
{"inst": "wfi" , "op": "11010101|000|00011|0010|0000|011|11111"},
|
||
|
|
{"inst": "yield" , "op": "11010101|000|00011|0010|0000|001|11111"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "GP GP_EXT", "ext": "BRBE", "data": [
|
||
|
|
{"inst": "brb #brb_op" , "op": "11010101|000|01001|0111|0010|op2:3|11111" , "imm": "ImmBRB(beb_op)"},
|
||
|
|
{"inst": "brb #brb_op, Xt" , "op": "11010101|000|01001|0111|0010|op2:3|Rt" , "imm": "ImmBRB(beb_op)"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "GP GP_EXT", "ext": "BTI", "data": [
|
||
|
|
{"inst": "bti {#targets}" , "op": "11010101|000|00011|0010|0100|op2:3|11111" , "imm": "ImmBTI(targets)"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "GP GP_EXT", "ext": "CHK", "data": [
|
||
|
|
{"inst": "chkfeat" , "op": "11010101|000|00011|0010|0101|000|11111"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "GP GP_EXT", "ext": "CLRBHB", "data": [
|
||
|
|
{"inst": "clrbhb" , "op": "11010101|000|00011|0010|0010|110|11111"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "GP GP_EXT CRYPTO_HASH", "ext": "CRC32", "data": [
|
||
|
|
{"inst": "crc32b Wd, Wn, Wm" , "op": "00011010|110|Rm|0|10000|Rn|Rd"},
|
||
|
|
{"inst": "crc32h Wd, Wn, Wm" , "op": "00011010|110|Rm|0|10001|Rn|Rd"},
|
||
|
|
{"inst": "crc32w Wd, Wn, Wm" , "op": "00011010|110|Rm|0|10010|Rn|Rd"},
|
||
|
|
{"inst": "crc32x Xd, Xn, Xm" , "op": "10011010|110|Rm|0|10011|Rn|Rd"},
|
||
|
|
|
||
|
|
{"inst": "crc32cb Wd, Wn, Wm" , "op": "00011010|110|Rm|0|10100|Rn|Rd"},
|
||
|
|
{"inst": "crc32ch Wd, Wn, Wm" , "op": "00011010|110|Rm|0|10101|Rn|Rd"},
|
||
|
|
{"inst": "crc32cw Wd, Wn, Wm" , "op": "00011010|110|Rm|0|10110|Rn|Rd"},
|
||
|
|
{"inst": "crc32cx Xd, Xn, Xm" , "op": "10011010|110|Rm|0|10111|Rn|Rd"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "GP GP_EXT", "ext": "CSSC", "data": [
|
||
|
|
{"inst": "abs Wd, Wn" , "op": "01011010|110|00000|0|01000|Rn|Rd"},
|
||
|
|
{"inst": "abs Xd, Xn" , "op": "11011010|110|00000|0|01000|Rn|Rd"},
|
||
|
|
{"inst": "cnt Wd, Wn" , "op": "01011010|110|00000|0|00111|Rn|Rd"},
|
||
|
|
{"inst": "cnt Xd, Xn" , "op": "11011010|110|00000|0|00111|Rn|Rd"},
|
||
|
|
{"inst": "ctz Wd, Wn" , "op": "01011010|110|00000|0|00110|Rn|Rd"},
|
||
|
|
{"inst": "ctz Xd, Xn" , "op": "11011010|110|00000|0|00110|Rn|Rd"},
|
||
|
|
{"inst": "smax Wd, Wn, Wm" , "op": "00011010|110|Rm|0|11000|Rn|Rd"},
|
||
|
|
{"inst": "smax Xd, Xn, Xm" , "op": "10011010|110|Rm|0|11000|Rn|Rd"},
|
||
|
|
{"inst": "smax Wd, Wn, #simm" , "op": "00010001|110|000|simm:8|Rn|Rd"},
|
||
|
|
{"inst": "smax Xd, Xn, #simm" , "op": "10010001|110|000|simm:8|Rn|Rd"},
|
||
|
|
{"inst": "smin Wd, Wn, Wm" , "op": "00011010|110|Rm|0|11010|Rn|Rd"},
|
||
|
|
{"inst": "smin Xd, Xn, Xm" , "op": "10011010|110|Rm|0|11010|Rn|Rd"},
|
||
|
|
{"inst": "smin Wd, Wn, #simm" , "op": "00010001|110|010|simm:8|Rn|Rd"},
|
||
|
|
{"inst": "smin Xd, Xn, #simm" , "op": "10010001|110|010|simm:8|Rn|Rd"},
|
||
|
|
{"inst": "umax Wd, Wn, Wm" , "op": "00011010|110|Rm|0|11001|Rn|Rd"},
|
||
|
|
{"inst": "umax Xd, Xn, Xm" , "op": "10011010|110|Rm|0|11001|Rn|Rd"},
|
||
|
|
{"inst": "umax Wd, Wn, #simm" , "op": "00010001|110|001|simm:8|Rn|Rd"},
|
||
|
|
{"inst": "umax Xd, Xn, #simm" , "op": "10010001|110|001|simm:8|Rn|Rd"},
|
||
|
|
{"inst": "umin Wd, Wn, Wm" , "op": "00011010|110|Rm|0|11011|Rn|Rd"},
|
||
|
|
{"inst": "umin Xd, Xn, Xm" , "op": "10011010|110|Rm|0|11011|Rn|Rd"},
|
||
|
|
{"inst": "umin Wd, Wn, #simm" , "op": "00010001|110|011|simm:8|Rn|Rd"},
|
||
|
|
{"inst": "umin Xd, Xn, #simm" , "op": "10010001|110|011|simm:8|Rn|Rd"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "GP GP_EXT", "ext": "D128", "data": [
|
||
|
|
{"inst": "tlbip #tlbip_op, 2x{Xt}+" , "op": "11010101|010|01|op1:3|CRn|CRm|op2:3|Rt" , "imm": "ImmTLBIP(tlbip_op)"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "GP GP_EXT", "ext": "DGH", "data": [
|
||
|
|
{"inst": "dgh" , "op": "11010101|000|00|011|0010|0000|110|11111"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "GP GP_EXT", "ext": "FLAGM", "data": [
|
||
|
|
{"inst": "cfinv" , "op": "11010101|000|00000|0100|0000|000|11111" , "io": "C=X"},
|
||
|
|
{"inst": "rmif Xn, #shift, #mask" , "op": "10111010|000|shift:6|00001|Rn|0|mask:4" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "setf16 Wn" , "op": "00111010|000|00000|0|10010|Rn|01101" , "io": "N=W Z=W V=W"},
|
||
|
|
{"inst": "setf8 Wn" , "op": "00111010|000|00000|0|00010|Rn|01101" , "io": "N=W Z=W V=W"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "GP GP_EXT", "ext": "FLAGM2", "data": [
|
||
|
|
{"inst": "axflag" , "op": "11010101|000|00000|0100|0000|010|11111" , "io": "N=X Z=X C=X V=X"},
|
||
|
|
{"inst": "xaflag" , "op": "11010101|000|00000|0100|0000|001|11111" , "io": "N=X Z=X C=X V=X"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "GP GP_EXT", "ext": "GCS", "data": [
|
||
|
|
{"inst": "gcsb #dsync" , "op": "11010101|000|00011|0010|0010|011|11111"},
|
||
|
|
{"inst": "gcspopcx" , "op": "11010101|000|01000|0111|0111|101|11111"},
|
||
|
|
{"inst": "gcspopcx Xt" , "op": "11010101|000|01000|0111|0111|101|Rt"},
|
||
|
|
{"inst": "gcspopm Xt" , "op": "11010101|001|01011|0111|0111|001|Rt"},
|
||
|
|
{"inst": "gcspopx" , "op": "11010101|000|01000|0111|0111|110|11111"},
|
||
|
|
{"inst": "gcspopx Xt" , "op": "11010101|000|01000|0111|0111|110|Rt"},
|
||
|
|
{"inst": "gcspushm Xt" , "op": "11010101|000|01011|0111|0111|000|Rt"},
|
||
|
|
{"inst": "gcspushx" , "op": "11010101|000|01000|0111|0111|100|11111"},
|
||
|
|
{"inst": "gcspushx Xt" , "op": "11010101|000|01000|0111|0111|100|Rt"},
|
||
|
|
{"inst": "gcsss1 Xt" , "op": "11010101|000|01011|0111|0111|010|Rt"},
|
||
|
|
{"inst": "gcsss2 Xt" , "op": "11010101|001|01011|0111|0111|011|Rt"},
|
||
|
|
{"inst": "gcsstr Xs, [Xn|SP]" , "op": "11011001|000|11111|0|00011|Rn|Rs"},
|
||
|
|
{"inst": "gcssttr Xs, [Xn|SP]" , "op": "11011001|000|11111|0|00111|Rn|Rs"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "GP GP_EXT", "ext": "HBC", "data": [
|
||
|
|
{"inst": "bc.<cond> #relS*4" , "op": "01010100|relS:19|1|cond" , "control": "branch", "io": "N=R Z=R C=R V=R"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "GP GP_EXT", "ext": "ITE", "data": [
|
||
|
|
{"inst": "trcit Xt" , "op": "11010101|000|01011|0111|0010|111|Rt"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "GP GP_EXT", "ext": "LOR", "data": [
|
||
|
|
{"inst": "ldlar Wd, [Xn|SP]" , "op": "10001000|110|11111|0|11111|Rn|Rd"},
|
||
|
|
{"inst": "ldlar Xd, [Xn|SP]" , "op": "11001000|110|11111|0|11111|Rn|Rd"},
|
||
|
|
{"inst": "ldlarb Wd, [Xn|SP]" , "op": "00001000|110|11111|0|11111|Rn|Rd"},
|
||
|
|
{"inst": "ldlarh Wd, [Xn|SP]" , "op": "01001000|110|11111|0|11111|Rn|Rd"},
|
||
|
|
{"inst": "stllr Ws, [Xn|SP]" , "op": "10001000|100|11111|0|11111|Rn|Rs"},
|
||
|
|
{"inst": "stllr Xs, [Xn|SP]" , "op": "11001000|100|11111|0|11111|Rn|Rs"},
|
||
|
|
{"inst": "stllrb Ws, [Xn|SP]" , "op": "00001000|100|11111|0|11111|Rn|Rs"},
|
||
|
|
{"inst": "stllrh Ws, [Xn|SP]" , "op": "01001000|100|11111|0|11111|Rn|Rs"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "GP GP_EXT", "ext": "LRCPC", "data": [
|
||
|
|
{"inst": "ldapr Wd, [Xn|SP]" , "op": "10111000|101|11111|1|10000|Rn|Rd"},
|
||
|
|
{"inst": "ldapr Xd, [Xn|SP]" , "op": "11111000|101|11111|1|10000|Rn|Rd"},
|
||
|
|
{"inst": "ldaprb Wd, [Xn|SP]" , "op": "00111000|101|11111|1|10000|Rn|Rd"},
|
||
|
|
{"inst": "ldaprh Wd, [Xn|SP]" , "op": "01111000|101|11111|1|10000|Rn|Rd"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "GP GP_EXT", "ext": "LRCPC2", "data": [
|
||
|
|
{"inst": "ldapur Wd, [Xn|SP, #soff]" , "op": "10011001|010|soff:9|00|Rn|Rd"},
|
||
|
|
{"inst": "ldapur Xd, [Xn|SP, #soff]" , "op": "11011001|010|soff:9|00|Rn|Rd"},
|
||
|
|
{"inst": "ldapurb Wd, [Xn|SP, #soff]" , "op": "00011001|010|soff:9|00|Rn|Rd"},
|
||
|
|
{"inst": "ldapurh Wd, [Xn|SP, #soff]" , "op": "01011001|010|soff:9|00|Rn|Rd"},
|
||
|
|
|
||
|
|
{"inst": "ldapursb Wd, [Xn|SP, #soff]" , "op": "00011001|110|soff:9|00|Rn|Rd"},
|
||
|
|
{"inst": "ldapursb Xd, [Xn|SP, #soff]" , "op": "00011001|100|soff:9|00|Rn|Rd"},
|
||
|
|
{"inst": "ldapursh Wd, [Xn|SP, #soff]" , "op": "01011001|110|soff:9|00|Rn|Rd"},
|
||
|
|
{"inst": "ldapursh Xd, [Xn|SP, #soff]" , "op": "01011001|100|soff:9|00|Rn|Rd"},
|
||
|
|
{"inst": "ldapursw Xd, [Xn|SP, #soff]" , "op": "10011001|100|soff:9|00|Rn|Rd"},
|
||
|
|
|
||
|
|
{"inst": "stlur Ws, [Xn|SP, #soff]" , "op": "10011001|000|soff:9|00|Rn|Rs"},
|
||
|
|
{"inst": "stlur Xs, [Xn|SP, #soff]" , "op": "11011001|000|soff:9|00|Rn|Rs"},
|
||
|
|
{"inst": "stlurb Ws, [Xn|SP, #soff]" , "op": "00011001|000|soff:9|00|Rn|Rs"},
|
||
|
|
{"inst": "stlurh Ws, [Xn|SP, #soff]" , "op": "01011001|000|soff:9|00|Rn|Rs"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "GP GP_EXT", "ext": "LRCPC3", "data": [
|
||
|
|
{"inst": "ldiapp Wd, Wd2, [Xn|SP]" , "op": "10011001|010|Rd2|0|00110|Rn|Rd"},
|
||
|
|
{"inst": "ldiapp Wd, Wd2, [Xn|SP, #8]@" , "op": "10011001|010|Rd2|0|00010|Rn|Rd"},
|
||
|
|
{"inst": "ldiapp Xd, Xd2, [Xn|SP]" , "op": "11011001|010|Rd2|0|00110|Rn|Rd"},
|
||
|
|
{"inst": "ldiapp Xd, Xd2, [Xn|SP, #16]@" , "op": "11011001|010|Rd2|0|00010|Rn|Rd"},
|
||
|
|
{"inst": "stilp Ws, Ws2, [Xn|SP]" , "op": "10011001|000|Rs2|0|00110|Rn|Rs"},
|
||
|
|
{"inst": "stilp Ws, Ws2, [Xn|SP, #8]@" , "op": "10011001|000|Rs2|0|00010|Rn|Rs"},
|
||
|
|
{"inst": "stilp Xs, Xs2, [Xn|SP]" , "op": "11011001|000|Rs2|0|00110|Rn|Rs"},
|
||
|
|
{"inst": "stilp Xs, Xs2, [Xn|SP, #16]@" , "op": "11011001|000|Rs2|0|00010|Rn|Rs"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "GP GP_EXT", "ext": "LS64", "data": [
|
||
|
|
{"inst": "ld64b 8x{Xd}+, [Xn|SP]" , "op": "11111000|001|11111|1|10100|Rn|Rd"},
|
||
|
|
{"inst": "st64b 8x{Xs}+, [Xn|SP]" , "op": "11111000|001|11111|1|00100|Rn|Rs"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "GP GP_EXT", "ext": "LS64_ACCDATA", "data": [
|
||
|
|
{"inst": "st64bv0 Rd, 8x{Xs}+, [Xn|SP]" , "op": "11111000|001|Rd|1|01000|Rn|Rs"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "GP GP_EXT", "ext": "LS64_V", "data": [
|
||
|
|
{"inst": "st64bv Rd, 8x{Xs}+, [Xn|SP]" , "op": "11111000|001|Rd|1|01100|Rn|Rs"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "GP GP_EXT", "ext": "LSE", "data": [
|
||
|
|
{"inst": "cas Ws, Wd, [Xn|SP]" , "op": "10001000|001|Rs|0|11111|Rn|Rd"},
|
||
|
|
{"inst": "casa Ws, Wd, [Xn|SP]" , "op": "10001000|011|Rs|0|11111|Rn|Rd"},
|
||
|
|
{"inst": "casal Ws, Wd, [Xn|SP]" , "op": "10001000|011|Rs|1|11111|Rn|Rd"},
|
||
|
|
{"inst": "casl Ws, Wd, [Xn|SP]" , "op": "10001000|001|Rs|1|11111|Rn|Rd"},
|
||
|
|
{"inst": "cas Xs, Xd, [Xn|SP]" , "op": "11001000|001|Rs|0|11111|Rn|Rd"},
|
||
|
|
{"inst": "casa Xs, Xd, [Xn|SP]" , "op": "11001000|011|Rs|0|11111|Rn|Rd"},
|
||
|
|
{"inst": "casal Xs, Xd, [Xn|SP]" , "op": "11001000|011|Rs|1|11111|Rn|Rd"},
|
||
|
|
{"inst": "casl Xs, Xd, [Xn|SP]" , "op": "11001000|001|Rs|1|11111|Rn|Rd"},
|
||
|
|
{"inst": "casab Ws, Wd, [Xn|SP]" , "op": "00001000|111|Rs|0|11111|Rn|Rd"},
|
||
|
|
{"inst": "casalb Ws, Wd, [Xn|SP]" , "op": "00001000|111|Rs|1|11111|Rn|Rd"},
|
||
|
|
{"inst": "casb Ws, Wd, [Xn|SP]" , "op": "00001000|101|Rs|0|11111|Rn|Rd"},
|
||
|
|
{"inst": "caslb Ws, Wd, [Xn|SP]" , "op": "00001000|101|Rs|1|11111|Rn|Rd"},
|
||
|
|
{"inst": "casah Ws, Wd, [Xn|SP]" , "op": "01001000|111|Rs|0|11111|Rn|Rd"},
|
||
|
|
{"inst": "casalh Ws, Wd, [Xn|SP]" , "op": "01001000|111|Rs|1|11111|Rn|Rd"},
|
||
|
|
{"inst": "cash Ws, Wd, [Xn|SP]" , "op": "01001000|101|Rs|0|11111|Rn|Rd"},
|
||
|
|
{"inst": "caslh Ws, Wd, [Xn|SP]" , "op": "01001000|101|Rs|1|11111|Rn|Rd"},
|
||
|
|
{"inst": "casp 2x{Ws}+, 2x{Wd}+, [Xn|SP]" , "op": "00001000|001|Rs|0|11111|Rn|Rd"},
|
||
|
|
{"inst": "caspa 2x{Ws}+, 2x{Wd}+, [Xn|SP]" , "op": "00001000|011|Rs|0|11111|Rn|Rd"},
|
||
|
|
{"inst": "caspal 2x{Ws}+, 2x{Wd}+, [Xn|SP]" , "op": "00001000|011|Rs|1|11111|Rn|Rd"},
|
||
|
|
{"inst": "caspl 2x{Ws}+, 2x{Wd}+, [Xn|SP]" , "op": "00001000|001|Rs|1|11111|Rn|Rd"},
|
||
|
|
{"inst": "casp 2x{Xs}+, 2x{Xd}+, [Xn|SP]" , "op": "01001000|001|Rs|0|11111|Rn|Rd"},
|
||
|
|
{"inst": "caspa 2x{Xs}+, 2x{Xd}+, [Xn|SP]" , "op": "01001000|011|Rs|0|11111|Rn|Rd"},
|
||
|
|
{"inst": "caspal 2x{Xs}+, 2x{Xd}+, [Xn|SP]" , "op": "01001000|011|Rs|1|11111|Rn|Rd"},
|
||
|
|
{"inst": "caspl 2x{Xs}+, 2x{Xd}+, [Xn|SP]" , "op": "01001000|001|Rs|1|11111|Rn|Rd"},
|
||
|
|
{"inst": "ldadd Ws, Wd, [Xn|SP]" , "op": "10111000|001|Rs|0|00000|Rn|Rd"},
|
||
|
|
{"inst": "ldadda Ws, Wd, [Xn|SP]" , "op": "10111000|101|Rs|0|00000|Rn|Rd"},
|
||
|
|
{"inst": "ldaddal Ws, Wd, [Xn|SP]" , "op": "10111000|111|Rs|0|00000|Rn|Rd"},
|
||
|
|
{"inst": "ldaddl Ws, Wd, [Xn|SP]" , "op": "10111000|011|Rs|0|00000|Rn|Rd"},
|
||
|
|
{"inst": "ldadd Xs, Xd, [Xn|SP]" , "op": "11111000|001|Rs|0|00000|Rn|Rd"},
|
||
|
|
{"inst": "ldadda Xs, Xd, [Xn|SP]" , "op": "11111000|101|Rs|0|00000|Rn|Rd"},
|
||
|
|
{"inst": "ldaddal Xs, Xd, [Xn|SP]" , "op": "11111000|111|Rs|0|00000|Rn|Rd"},
|
||
|
|
{"inst": "ldaddl Xs, Xd, [Xn|SP]" , "op": "11111000|011|Rs|0|00000|Rn|Rd"},
|
||
|
|
{"inst": "ldaddb Ws, Wd, [Xn|SP]" , "op": "00111000|001|Rs|0|00000|Rn|Rd"},
|
||
|
|
{"inst": "ldaddab Ws, Wd, [Xn|SP]" , "op": "00111000|101|Rs|0|00000|Rn|Rd"},
|
||
|
|
{"inst": "ldaddalb Ws, Wd, [Xn|SP]" , "op": "00111000|111|Rs|0|00000|Rn|Rd"},
|
||
|
|
{"inst": "ldaddlb Ws, Wd, [Xn|SP]" , "op": "00111000|011|Rs|0|00000|Rn|Rd"},
|
||
|
|
{"inst": "ldaddh Ws, Wd, [Xn|SP]" , "op": "01111000|001|Rs|0|00000|Rn|Rd"},
|
||
|
|
{"inst": "ldaddah Ws, Wd, [Xn|SP]" , "op": "01111000|101|Rs|0|00000|Rn|Rd"},
|
||
|
|
{"inst": "ldaddalh Ws, Wd, [Xn|SP]" , "op": "01111000|111|Rs|0|00000|Rn|Rd"},
|
||
|
|
{"inst": "ldaddlh Ws, Wd, [Xn|SP]" , "op": "01111000|011|Rs|0|00000|Rn|Rd"},
|
||
|
|
{"inst": "ldclr Ws, Wd, [Xn|SP]" , "op": "10111000|001|Rs|0|00100|Rn|Rd"},
|
||
|
|
{"inst": "ldclra Ws, Wd, [Xn|SP]" , "op": "10111000|101|Rs|0|00100|Rn|Rd"},
|
||
|
|
{"inst": "ldclral Ws, Wd, [Xn|SP]" , "op": "10111000|111|Rs|0|00100|Rn|Rd"},
|
||
|
|
{"inst": "ldclrl Ws, Wd, [Xn|SP]" , "op": "10111000|011|Rs|0|00100|Rn|Rd"},
|
||
|
|
{"inst": "ldclr Xs, Xd, [Xn|SP]" , "op": "11111000|001|Rs|0|00100|Rn|Rd"},
|
||
|
|
{"inst": "ldclra Xs, Xd, [Xn|SP]" , "op": "11111000|101|Rs|0|00100|Rn|Rd"},
|
||
|
|
{"inst": "ldclral Xs, Xd, [Xn|SP]" , "op": "11111000|111|Rs|0|00100|Rn|Rd"},
|
||
|
|
{"inst": "ldclrl Xs, Xd, [Xn|SP]" , "op": "11111000|011|Rs|0|00100|Rn|Rd"},
|
||
|
|
{"inst": "ldclrb Ws, Wd, [Xn|SP]" , "op": "00111000|001|Rs|0|00100|Rn|Rd"},
|
||
|
|
{"inst": "ldclrab Ws, Wd, [Xn|SP]" , "op": "00111000|101|Rs|0|00100|Rn|Rd"},
|
||
|
|
{"inst": "ldclralb Ws, Wd, [Xn|SP]" , "op": "00111000|111|Rs|0|00100|Rn|Rd"},
|
||
|
|
{"inst": "ldclrlb Ws, Wd, [Xn|SP]" , "op": "00111000|011|Rs|0|00100|Rn|Rd"},
|
||
|
|
{"inst": "ldclrh Ws, Wd, [Xn|SP]" , "op": "01111000|001|Rs|0|00100|Rn|Rd"},
|
||
|
|
{"inst": "ldclrah Ws, Wd, [Xn|SP]" , "op": "01111000|101|Rs|0|00100|Rn|Rd"},
|
||
|
|
{"inst": "ldclralh Ws, Wd, [Xn|SP]" , "op": "01111000|111|Rs|0|00100|Rn|Rd"},
|
||
|
|
{"inst": "ldclrlh Ws, Wd, [Xn|SP]" , "op": "01111000|011|Rs|0|00100|Rn|Rd"},
|
||
|
|
{"inst": "ldeor Ws, Wd, [Xn|SP]" , "op": "10111000|001|Rs|0|01000|Rn|Rd"},
|
||
|
|
{"inst": "ldeora Ws, Wd, [Xn|SP]" , "op": "10111000|101|Rs|0|01000|Rn|Rd"},
|
||
|
|
{"inst": "ldeoral Ws, Wd, [Xn|SP]" , "op": "10111000|111|Rs|0|01000|Rn|Rd"},
|
||
|
|
{"inst": "ldeorl Ws, Wd, [Xn|SP]" , "op": "10111000|011|Rs|0|01000|Rn|Rd"},
|
||
|
|
{"inst": "ldeor Xs, Xd, [Xn|SP]" , "op": "11111000|001|Rs|0|01000|Rn|Rd"},
|
||
|
|
{"inst": "ldeora Xs, Xd, [Xn|SP]" , "op": "11111000|101|Rs|0|01000|Rn|Rd"},
|
||
|
|
{"inst": "ldeoral Xs, Xd, [Xn|SP]" , "op": "11111000|111|Rs|0|01000|Rn|Rd"},
|
||
|
|
{"inst": "ldeorl Xs, Xd, [Xn|SP]" , "op": "11111000|011|Rs|0|01000|Rn|Rd"},
|
||
|
|
{"inst": "ldeorb Ws, Wd, [Xn|SP]" , "op": "00111000|001|Rs|0|01000|Rn|Rd"},
|
||
|
|
{"inst": "ldeorab Ws, Wd, [Xn|SP]" , "op": "00111000|101|Rs|0|01000|Rn|Rd"},
|
||
|
|
{"inst": "ldeoralb Ws, Wd, [Xn|SP]" , "op": "00111000|111|Rs|0|01000|Rn|Rd"},
|
||
|
|
{"inst": "ldeorlb Ws, Wd, [Xn|SP]" , "op": "00111000|011|Rs|0|01000|Rn|Rd"},
|
||
|
|
{"inst": "ldeorh Ws, Wd, [Xn|SP]" , "op": "01111000|001|Rs|0|01000|Rn|Rd"},
|
||
|
|
{"inst": "ldeorah Ws, Wd, [Xn|SP]" , "op": "01111000|101|Rs|0|01000|Rn|Rd"},
|
||
|
|
{"inst": "ldeoralh Ws, Wd, [Xn|SP]" , "op": "01111000|111|Rs|0|01000|Rn|Rd"},
|
||
|
|
{"inst": "ldeorlh Ws, Wd, [Xn|SP]" , "op": "01111000|011|Rs|0|01000|Rn|Rd"},
|
||
|
|
{"inst": "ldset Ws, Wd, [Xn|SP]" , "op": "10111000|001|Rs|0|01100|Rn|Rd"},
|
||
|
|
{"inst": "ldseta Ws, Wd, [Xn|SP]" , "op": "10111000|101|Rs|0|01100|Rn|Rd"},
|
||
|
|
{"inst": "ldsetal Ws, Wd, [Xn|SP]" , "op": "10111000|111|Rs|0|01100|Rn|Rd"},
|
||
|
|
{"inst": "ldsetl Ws, Wd, [Xn|SP]" , "op": "10111000|011|Rs|0|01100|Rn|Rd"},
|
||
|
|
{"inst": "ldset Xs, Wd, [Xn|SP]" , "op": "11111000|001|Rs|0|01100|Rn|Rd"},
|
||
|
|
{"inst": "ldseta Xs, Wd, [Xn|SP]" , "op": "11111000|101|Rs|0|01100|Rn|Rd"},
|
||
|
|
{"inst": "ldsetal Xs, Wd, [Xn|SP]" , "op": "11111000|111|Rs|0|01100|Rn|Rd"},
|
||
|
|
{"inst": "ldsetl Xs, Wd, [Xn|SP]" , "op": "11111000|011|Rs|0|01100|Rn|Rd"},
|
||
|
|
{"inst": "ldsetb Ws, Wd, [Xn|SP]" , "op": "00111000|001|Rs|0|01100|Rn|Rd"},
|
||
|
|
{"inst": "ldsetab Ws, Wd, [Xn|SP]" , "op": "00111000|101|Rs|0|01100|Rn|Rd"},
|
||
|
|
{"inst": "ldsetalb Ws, Wd, [Xn|SP]" , "op": "00111000|111|Rs|0|01100|Rn|Rd"},
|
||
|
|
{"inst": "ldsetlb Ws, Wd, [Xn|SP]" , "op": "00111000|011|Rs|0|01100|Rn|Rd"},
|
||
|
|
{"inst": "ldseth Ws, Wd, [Xn|SP]" , "op": "01111000|001|Rs|0|01100|Rn|Rd"},
|
||
|
|
{"inst": "ldsetah Ws, Wd, [Xn|SP]" , "op": "01111000|101|Rs|0|01100|Rn|Rd"},
|
||
|
|
{"inst": "ldsetalh Ws, Wd, [Xn|SP]" , "op": "01111000|111|Rs|0|01100|Rn|Rd"},
|
||
|
|
{"inst": "ldsetlh Ws, Wd, [Xn|SP]" , "op": "01111000|011|Rs|0|01100|Rn|Rd"},
|
||
|
|
{"inst": "ldsmax Ws, Wd, [Xn|SP]" , "op": "10111000|001|Rs|0|10000|Rn|Rd"},
|
||
|
|
{"inst": "ldsmaxa Ws, Wd, [Xn|SP]" , "op": "10111000|101|Rs|0|10000|Rn|Rd"},
|
||
|
|
{"inst": "ldsmaxal Ws, Wd, [Xn|SP]" , "op": "10111000|111|Rs|0|10000|Rn|Rd"},
|
||
|
|
{"inst": "ldsmaxl Ws, Wd, [Xn|SP]" , "op": "10111000|011|Rs|0|10000|Rn|Rd"},
|
||
|
|
{"inst": "ldsmax Xs, Xd, [Xn|SP]" , "op": "11111000|001|Rs|0|10000|Rn|Rd"},
|
||
|
|
{"inst": "ldsmaxa Xs, Xd, [Xn|SP]" , "op": "11111000|101|Rs|0|10000|Rn|Rd"},
|
||
|
|
{"inst": "ldsmaxal Xs, Xd, [Xn|SP]" , "op": "11111000|111|Rs|0|10000|Rn|Rd"},
|
||
|
|
{"inst": "ldsmaxl Xs, Xd, [Xn|SP]" , "op": "11111000|011|Rs|0|10000|Rn|Rd"},
|
||
|
|
{"inst": "ldsmaxb Ws, Wd, [Xn|SP]" , "op": "00111000|001|Rs|0|10000|Rn|Rd"},
|
||
|
|
{"inst": "ldsmaxab Ws, Wd, [Xn|SP]" , "op": "00111000|101|Rs|0|10000|Rn|Rd"},
|
||
|
|
{"inst": "ldsmaxalb Ws, Wd, [Xn|SP]" , "op": "00111000|111|Rs|0|10000|Rn|Rd"},
|
||
|
|
{"inst": "ldsmaxlb Ws, Wd, [Xn|SP]" , "op": "00111000|011|Rs|0|10000|Rn|Rd"},
|
||
|
|
{"inst": "ldsmaxh Ws, Wd, [Xn|SP]" , "op": "01111000|001|Rs|0|10000|Rn|Rd"},
|
||
|
|
{"inst": "ldsmaxah Ws, Wd, [Xn|SP]" , "op": "01111000|101|Rs|0|10000|Rn|Rd"},
|
||
|
|
{"inst": "ldsmaxalh Ws, Wd, [Xn|SP]" , "op": "01111000|111|Rs|0|10000|Rn|Rd"},
|
||
|
|
{"inst": "ldsmaxlh Ws, Wd, [Xn|SP]" , "op": "01111000|011|Rs|0|10000|Rn|Rd"},
|
||
|
|
{"inst": "ldsmin Ws, Wd, [Xn|SP]" , "op": "10111000|001|Rs|0|10100|Rn|Rd"},
|
||
|
|
{"inst": "ldsmina Ws, Wd, [Xn|SP]" , "op": "10111000|101|Rs|0|10100|Rn|Rd"},
|
||
|
|
{"inst": "ldsminal Ws, Wd, [Xn|SP]" , "op": "10111000|111|Rs|0|10100|Rn|Rd"},
|
||
|
|
{"inst": "ldsminl Ws, Wd, [Xn|SP]" , "op": "10111000|011|Rs|0|10100|Rn|Rd"},
|
||
|
|
{"inst": "ldsmin Xs, Xd, [Xn|SP]" , "op": "11111000|001|Rs|0|10100|Rn|Rd"},
|
||
|
|
{"inst": "ldsmina Xs, Xd, [Xn|SP]" , "op": "11111000|101|Rs|0|10100|Rn|Rd"},
|
||
|
|
{"inst": "ldsminal Xs, Xd, [Xn|SP]" , "op": "11111000|111|Rs|0|10100|Rn|Rd"},
|
||
|
|
{"inst": "ldsminl Xs, Xd, [Xn|SP]" , "op": "11111000|011|Rs|0|10100|Rn|Rd"},
|
||
|
|
{"inst": "ldsminb Ws, Wd, [Xn|SP]" , "op": "00111000|001|Rs|0|10100|Rn|Rd"},
|
||
|
|
{"inst": "ldsminab Ws, Wd, [Xn|SP]" , "op": "00111000|101|Rs|0|10100|Rn|Rd"},
|
||
|
|
{"inst": "ldsminalb Ws, Wd, [Xn|SP]" , "op": "00111000|111|Rs|0|10100|Rn|Rd"},
|
||
|
|
{"inst": "ldsminlb Ws, Wd, [Xn|SP]" , "op": "00111000|011|Rs|0|10100|Rn|Rd"},
|
||
|
|
{"inst": "ldsminh Ws, Wd, [Xn|SP]" , "op": "01111000|001|Rs|0|10100|Rn|Rd"},
|
||
|
|
{"inst": "ldsminah Ws, Wd, [Xn|SP]" , "op": "01111000|101|Rs|0|10100|Rn|Rd"},
|
||
|
|
{"inst": "ldsminalh Ws, Wd, [Xn|SP]" , "op": "01111000|111|Rs|0|10100|Rn|Rd"},
|
||
|
|
{"inst": "ldsminlh Ws, Wd, [Xn|SP]" , "op": "01111000|011|Rs|0|10100|Rn|Rd"},
|
||
|
|
{"inst": "ldumax Ws, Wd, [Xn|SP]" , "op": "10111000|001|Rs|0|11000|Rn|Rd"},
|
||
|
|
{"inst": "ldumaxa Ws, Wd, [Xn|SP]" , "op": "10111000|101|Rs|0|11000|Rn|Rd"},
|
||
|
|
{"inst": "ldumaxal Ws, Wd, [Xn|SP]" , "op": "10111000|111|Rs|0|11000|Rn|Rd"},
|
||
|
|
{"inst": "ldumaxl Ws, Wd, [Xn|SP]" , "op": "10111000|011|Rs|0|11000|Rn|Rd"},
|
||
|
|
{"inst": "ldumax Xs, Xd, [Xn|SP]" , "op": "11111000|001|Rs|0|11000|Rn|Rd"},
|
||
|
|
{"inst": "ldumaxa Xs, Xd, [Xn|SP]" , "op": "11111000|101|Rs|0|11000|Rn|Rd"},
|
||
|
|
{"inst": "ldumaxal Xs, Xd, [Xn|SP]" , "op": "11111000|111|Rs|0|11000|Rn|Rd"},
|
||
|
|
{"inst": "ldumaxl Xs, Xd, [Xn|SP]" , "op": "11111000|011|Rs|0|11000|Rn|Rd"},
|
||
|
|
{"inst": "ldumaxb Ws, Wd, [Xn|SP]" , "op": "00111000|001|Rs|0|11000|Rn|Rd"},
|
||
|
|
{"inst": "ldumaxab Ws, Wd, [Xn|SP]" , "op": "00111000|101|Rs|0|11000|Rn|Rd"},
|
||
|
|
{"inst": "ldumaxalb Ws, Wd, [Xn|SP]" , "op": "00111000|111|Rs|0|11000|Rn|Rd"},
|
||
|
|
{"inst": "ldumaxlb Ws, Wd, [Xn|SP]" , "op": "00111000|011|Rs|0|11000|Rn|Rd"},
|
||
|
|
{"inst": "ldumaxh Ws, Wd, [Xn|SP]" , "op": "01111000|001|Rs|0|11000|Rn|Rd"},
|
||
|
|
{"inst": "ldumaxah Ws, Wd, [Xn|SP]" , "op": "01111000|101|Rs|0|11000|Rn|Rd"},
|
||
|
|
{"inst": "ldumaxalh Ws, Wd, [Xn|SP]" , "op": "01111000|111|Rs|0|11000|Rn|Rd"},
|
||
|
|
{"inst": "ldumaxlh Ws, Wd, [Xn|SP]" , "op": "01111000|011|Rs|0|11000|Rn|Rd"},
|
||
|
|
{"inst": "ldumin Ws, Wd, [Xn|SP]" , "op": "10111000|001|Rs|0|11100|Rn|Rd"},
|
||
|
|
{"inst": "ldumina Ws, Wd, [Xn|SP]" , "op": "10111000|101|Rs|0|11100|Rn|Rd"},
|
||
|
|
{"inst": "lduminal Ws, Wd, [Xn|SP]" , "op": "10111000|111|Rs|0|11100|Rn|Rd"},
|
||
|
|
{"inst": "lduminl Ws, Wd, [Xn|SP]" , "op": "10111000|011|Rs|0|11100|Rn|Rd"},
|
||
|
|
{"inst": "ldumin Xs, Xd, [Xn|SP]" , "op": "11111000|001|Rs|0|11100|Rn|Rd"},
|
||
|
|
{"inst": "ldumina Xs, Xd, [Xn|SP]" , "op": "11111000|101|Rs|0|11100|Rn|Rd"},
|
||
|
|
{"inst": "lduminal Xs, Xd, [Xn|SP]" , "op": "11111000|111|Rs|0|11100|Rn|Rd"},
|
||
|
|
{"inst": "lduminl Xs, Xd, [Xn|SP]" , "op": "11111000|011|Rs|0|11100|Rn|Rd"},
|
||
|
|
{"inst": "lduminb Ws, Wd, [Xn|SP]" , "op": "00111000|001|Rs|0|11100|Rn|Rd"},
|
||
|
|
{"inst": "lduminab Ws, Wd, [Xn|SP]" , "op": "00111000|101|Rs|0|11100|Rn|Rd"},
|
||
|
|
{"inst": "lduminalb Ws, Wd, [Xn|SP]" , "op": "00111000|111|Rs|0|11100|Rn|Rd"},
|
||
|
|
{"inst": "lduminlb Ws, Wd, [Xn|SP]" , "op": "00111000|011|Rs|0|11100|Rn|Rd"},
|
||
|
|
{"inst": "lduminh Ws, Wd, [Xn|SP]" , "op": "01111000|001|Rs|0|11100|Rn|Rd"},
|
||
|
|
{"inst": "lduminah Ws, Wd, [Xn|SP]" , "op": "01111000|101|Rs|0|11100|Rn|Rd"},
|
||
|
|
{"inst": "lduminalh Ws, Wd, [Xn|SP]" , "op": "01111000|111|Rs|0|11100|Rn|Rd"},
|
||
|
|
{"inst": "lduminlh Ws, Wd, [Xn|SP]" , "op": "01111000|011|Rs|0|11100|Rn|Rd"},
|
||
|
|
{"inst": "stadd Ws, [Xn|SP]" , "op": "10111000|001|Rs|0|00000|Rn|11111"},
|
||
|
|
{"inst": "stadda Ws, [Xn|SP]" , "op": "10111000|101|Rs|0|00000|Rn|11111"},
|
||
|
|
{"inst": "staddal Ws, [Xn|SP]" , "op": "10111000|111|Rs|0|00000|Rn|11111"},
|
||
|
|
{"inst": "staddl Ws, [Xn|SP]" , "op": "10111000|011|Rs|0|00000|Rn|11111"},
|
||
|
|
{"inst": "stadd Xs, [Xn|SP]" , "op": "11111000|001|Rs|0|00000|Rn|11111"},
|
||
|
|
{"inst": "stadda Xs, [Xn|SP]" , "op": "11111000|101|Rs|0|00000|Rn|11111"},
|
||
|
|
{"inst": "staddal Xs, [Xn|SP]" , "op": "11111000|111|Rs|0|00000|Rn|11111"},
|
||
|
|
{"inst": "staddl Xs, [Xn|SP]" , "op": "11111000|011|Rs|0|00000|Rn|11111"},
|
||
|
|
{"inst": "staddb Ws, [Xn|SP]" , "op": "00111000|001|Rs|0|00000|Rn|11111"},
|
||
|
|
{"inst": "staddab Ws, [Xn|SP]" , "op": "00111000|101|Rs|0|00000|Rn|11111"},
|
||
|
|
{"inst": "staddalb Ws, [Xn|SP]" , "op": "00111000|111|Rs|0|00000|Rn|11111"},
|
||
|
|
{"inst": "staddlb Ws, [Xn|SP]" , "op": "00111000|011|Rs|0|00000|Rn|11111"},
|
||
|
|
{"inst": "staddh Ws, [Xn|SP]" , "op": "01111000|001|Rs|0|00000|Rn|11111"},
|
||
|
|
{"inst": "staddah Ws, [Xn|SP]" , "op": "01111000|101|Rs|0|00000|Rn|11111"},
|
||
|
|
{"inst": "staddalh Ws, [Xn|SP]" , "op": "01111000|111|Rs|0|00000|Rn|11111"},
|
||
|
|
{"inst": "staddlh Ws, [Xn|SP]" , "op": "01111000|011|Rs|0|00000|Rn|11111"},
|
||
|
|
{"inst": "stclr Ws, [Xn|SP]" , "op": "10111000|001|Rs|0|00100|Rn|11111"},
|
||
|
|
{"inst": "stclra Ws, [Xn|SP]" , "op": "10111000|101|Rs|0|00100|Rn|11111"},
|
||
|
|
{"inst": "stclral Ws, [Xn|SP]" , "op": "10111000|111|Rs|0|00100|Rn|11111"},
|
||
|
|
{"inst": "stclrl Ws, [Xn|SP]" , "op": "10111000|011|Rs|0|00100|Rn|11111"},
|
||
|
|
{"inst": "stclr Xs, [Xn|SP]" , "op": "11111000|001|Rs|0|00100|Rn|11111"},
|
||
|
|
{"inst": "stclra Xs, [Xn|SP]" , "op": "11111000|101|Rs|0|00100|Rn|11111"},
|
||
|
|
{"inst": "stclral Xs, [Xn|SP]" , "op": "11111000|111|Rs|0|00100|Rn|11111"},
|
||
|
|
{"inst": "stclrl Xs, [Xn|SP]" , "op": "11111000|011|Rs|0|00100|Rn|11111"},
|
||
|
|
{"inst": "stclrb Ws, [Xn|SP]" , "op": "00111000|001|Rs|0|00100|Rn|11111"},
|
||
|
|
{"inst": "stclrab Ws, [Xn|SP]" , "op": "00111000|101|Rs|0|00100|Rn|11111"},
|
||
|
|
{"inst": "stclralb Ws, [Xn|SP]" , "op": "00111000|111|Rs|0|00100|Rn|11111"},
|
||
|
|
{"inst": "stclrlb Ws, [Xn|SP]" , "op": "00111000|011|Rs|0|00100|Rn|11111"},
|
||
|
|
{"inst": "stclrh Ws, [Xn|SP]" , "op": "01111000|001|Rs|0|00100|Rn|11111"},
|
||
|
|
{"inst": "stclrah Ws, [Xn|SP]" , "op": "01111000|101|Rs|0|00100|Rn|11111"},
|
||
|
|
{"inst": "stclralh Ws, [Xn|SP]" , "op": "01111000|111|Rs|0|00100|Rn|11111"},
|
||
|
|
{"inst": "stclrlh Ws, [Xn|SP]" , "op": "01111000|011|Rs|0|00100|Rn|11111"},
|
||
|
|
{"inst": "steor Ws, [Xn|SP]" , "op": "10111000|001|Rs|0|01000|Rn|11111"},
|
||
|
|
{"inst": "steora Ws, [Xn|SP]" , "op": "10111000|101|Rs|0|01000|Rn|11111"},
|
||
|
|
{"inst": "steoral Ws, [Xn|SP]" , "op": "10111000|111|Rs|0|01000|Rn|11111"},
|
||
|
|
{"inst": "steorl Ws, [Xn|SP]" , "op": "10111000|011|Rs|0|01000|Rn|11111"},
|
||
|
|
{"inst": "steor Xs, [Xn|SP]" , "op": "11111000|001|Rs|0|01000|Rn|11111"},
|
||
|
|
{"inst": "steora Xs, [Xn|SP]" , "op": "11111000|101|Rs|0|01000|Rn|11111"},
|
||
|
|
{"inst": "steoral Xs, [Xn|SP]" , "op": "11111000|111|Rs|0|01000|Rn|11111"},
|
||
|
|
{"inst": "steorl Xs, [Xn|SP]" , "op": "11111000|011|Rs|0|01000|Rn|11111"},
|
||
|
|
{"inst": "steorb Ws, [Xn|SP]" , "op": "00111000|001|Rs|0|01000|Rn|11111"},
|
||
|
|
{"inst": "steorab Ws, [Xn|SP]" , "op": "00111000|101|Rs|0|01000|Rn|11111"},
|
||
|
|
{"inst": "steoralb Ws, [Xn|SP]" , "op": "00111000|111|Rs|0|01000|Rn|11111"},
|
||
|
|
{"inst": "steorlb Ws, [Xn|SP]" , "op": "00111000|011|Rs|0|01000|Rn|11111"},
|
||
|
|
{"inst": "steorh Ws, [Xn|SP]" , "op": "01111000|001|Rs|0|01000|Rn|11111"},
|
||
|
|
{"inst": "steorah Ws, [Xn|SP]" , "op": "01111000|101|Rs|0|01000|Rn|11111"},
|
||
|
|
{"inst": "steoralh Ws, [Xn|SP]" , "op": "01111000|111|Rs|0|01000|Rn|11111"},
|
||
|
|
{"inst": "steorlh Ws, [Xn|SP]" , "op": "01111000|011|Rs|0|01000|Rn|11111"},
|
||
|
|
{"inst": "stset Ws, [Xn|SP]" , "op": "10111000|001|Rs|0|01100|Rn|11111"},
|
||
|
|
{"inst": "stseta Ws, [Xn|SP]" , "op": "10111000|101|Rs|0|01100|Rn|11111"},
|
||
|
|
{"inst": "stsetal Ws, [Xn|SP]" , "op": "10111000|111|Rs|0|01100|Rn|11111"},
|
||
|
|
{"inst": "stsetl Ws, [Xn|SP]" , "op": "10111000|011|Rs|0|01100|Rn|11111"},
|
||
|
|
{"inst": "stset Xs, [Xn|SP]" , "op": "11111000|001|Rs|0|01100|Rn|11111"},
|
||
|
|
{"inst": "stseta Xs, [Xn|SP]" , "op": "11111000|101|Rs|0|01100|Rn|11111"},
|
||
|
|
{"inst": "stsetal Xs, [Xn|SP]" , "op": "11111000|111|Rs|0|01100|Rn|11111"},
|
||
|
|
{"inst": "stsetl Xs, [Xn|SP]" , "op": "11111000|011|Rs|0|01100|Rn|11111"},
|
||
|
|
{"inst": "stsetb Ws, [Xn|SP]" , "op": "00111000|001|Rs|0|01100|Rn|11111"},
|
||
|
|
{"inst": "stsetab Ws, [Xn|SP]" , "op": "00111000|101|Rs|0|01100|Rn|11111"},
|
||
|
|
{"inst": "stsetalb Ws, [Xn|SP]" , "op": "00111000|111|Rs|0|01100|Rn|11111"},
|
||
|
|
{"inst": "stsetlb Ws, [Xn|SP]" , "op": "00111000|011|Rs|0|01100|Rn|11111"},
|
||
|
|
{"inst": "stseth Ws, [Xn|SP]" , "op": "01111000|001|Rs|0|01100|Rn|11111"},
|
||
|
|
{"inst": "stsetah Ws, [Xn|SP]" , "op": "01111000|101|Rs|0|01100|Rn|11111"},
|
||
|
|
{"inst": "stsetalh Ws, [Xn|SP]" , "op": "01111000|111|Rs|0|01100|Rn|11111"},
|
||
|
|
{"inst": "stsetlh Ws, [Xn|SP]" , "op": "01111000|011|Rs|0|01100|Rn|11111"},
|
||
|
|
{"inst": "stsmax Ws, [Xn|SP]" , "op": "10111000|001|Rs|0|10000|Rn|11111"},
|
||
|
|
{"inst": "stsmaxa Ws, [Xn|SP]" , "op": "10111000|101|Rs|0|10000|Rn|11111"},
|
||
|
|
{"inst": "stsmaxal Ws, [Xn|SP]" , "op": "10111000|111|Rs|0|10000|Rn|11111"},
|
||
|
|
{"inst": "stsmaxl Ws, [Xn|SP]" , "op": "10111000|011|Rs|0|10000|Rn|11111"},
|
||
|
|
{"inst": "stsmax Xs, [Xn|SP]" , "op": "11111000|001|Rs|0|10000|Rn|11111"},
|
||
|
|
{"inst": "stsmaxa Xs, [Xn|SP]" , "op": "11111000|101|Rs|0|10000|Rn|11111"},
|
||
|
|
{"inst": "stsmaxal Xs, [Xn|SP]" , "op": "11111000|111|Rs|0|10000|Rn|11111"},
|
||
|
|
{"inst": "stsmaxl Xs, [Xn|SP]" , "op": "11111000|011|Rs|0|10000|Rn|11111"},
|
||
|
|
{"inst": "stsmaxb Ws, [Xn|SP]" , "op": "00111000|001|Rs|0|10000|Rn|11111"},
|
||
|
|
{"inst": "stsmaxab Ws, [Xn|SP]" , "op": "00111000|101|Rs|0|10000|Rn|11111"},
|
||
|
|
{"inst": "stsmaxalb Ws, [Xn|SP]" , "op": "00111000|111|Rs|0|10000|Rn|11111"},
|
||
|
|
{"inst": "stsmaxlb Ws, [Xn|SP]" , "op": "00111000|011|Rs|0|10000|Rn|11111"},
|
||
|
|
{"inst": "stsmaxh Ws, [Xn|SP]" , "op": "01111000|001|Rs|0|10000|Rn|11111"},
|
||
|
|
{"inst": "stsmaxah Ws, [Xn|SP]" , "op": "01111000|101|Rs|0|10000|Rn|11111"},
|
||
|
|
{"inst": "stsmaxalh Ws, [Xn|SP]" , "op": "01111000|111|Rs|0|10000|Rn|11111"},
|
||
|
|
{"inst": "stsmaxlh Ws, [Xn|SP]" , "op": "01111000|011|Rs|0|10000|Rn|11111"},
|
||
|
|
{"inst": "stsmin Ws, [Xn|SP]" , "op": "10111000|001|Rs|0|10100|Rn|11111"},
|
||
|
|
{"inst": "stsmina Ws, [Xn|SP]" , "op": "10111000|101|Rs|0|10100|Rn|11111"},
|
||
|
|
{"inst": "stsminal Ws, [Xn|SP]" , "op": "10111000|111|Rs|0|10100|Rn|11111"},
|
||
|
|
{"inst": "stsminl Ws, [Xn|SP]" , "op": "10111000|011|Rs|0|10100|Rn|11111"},
|
||
|
|
{"inst": "stsmin Xs, [Xn|SP]" , "op": "11111000|001|Rs|0|10100|Rn|11111"},
|
||
|
|
{"inst": "stsmina Xs, [Xn|SP]" , "op": "11111000|101|Rs|0|10100|Rn|11111"},
|
||
|
|
{"inst": "stsminal Xs, [Xn|SP]" , "op": "11111000|111|Rs|0|10100|Rn|11111"},
|
||
|
|
{"inst": "stsminl Xs, [Xn|SP]" , "op": "11111000|011|Rs|0|10100|Rn|11111"},
|
||
|
|
{"inst": "stsminb Ws, [Xn|SP]" , "op": "00111000|001|Rs|0|10100|Rn|11111"},
|
||
|
|
{"inst": "stsminab Ws, [Xn|SP]" , "op": "00111000|101|Rs|0|10100|Rn|11111"},
|
||
|
|
{"inst": "stsminalb Ws, [Xn|SP]" , "op": "00111000|111|Rs|0|10100|Rn|11111"},
|
||
|
|
{"inst": "stsminlb Ws, [Xn|SP]" , "op": "00111000|011|Rs|0|10100|Rn|11111"},
|
||
|
|
{"inst": "stsminh Ws, [Xn|SP]" , "op": "01111000|001|Rs|0|10100|Rn|11111"},
|
||
|
|
{"inst": "stsminah Ws, [Xn|SP]" , "op": "01111000|101|Rs|0|10100|Rn|11111"},
|
||
|
|
{"inst": "stsminalh Ws, [Xn|SP]" , "op": "01111000|111|Rs|0|10100|Rn|11111"},
|
||
|
|
{"inst": "stsminlh Ws, [Xn|SP]" , "op": "01111000|011|Rs|0|10100|Rn|11111"},
|
||
|
|
{"inst": "stumax Ws, [Xn|SP]" , "op": "10111000|001|Rs|0|11000|Rn|11111"},
|
||
|
|
{"inst": "stumaxa Ws, [Xn|SP]" , "op": "10111000|101|Rs|0|11000|Rn|11111"},
|
||
|
|
{"inst": "stumaxal Ws, [Xn|SP]" , "op": "10111000|111|Rs|0|11000|Rn|11111"},
|
||
|
|
{"inst": "stumaxl Ws, [Xn|SP]" , "op": "10111000|011|Rs|0|11000|Rn|11111"},
|
||
|
|
{"inst": "stumax Xs, [Xn|SP]" , "op": "11111000|001|Rs|0|11000|Rn|11111"},
|
||
|
|
{"inst": "stumaxa Xs, [Xn|SP]" , "op": "11111000|101|Rs|0|11000|Rn|11111"},
|
||
|
|
{"inst": "stumaxal Xs, [Xn|SP]" , "op": "11111000|111|Rs|0|11000|Rn|11111"},
|
||
|
|
{"inst": "stumaxl Xs, [Xn|SP]" , "op": "11111000|011|Rs|0|11000|Rn|11111"},
|
||
|
|
{"inst": "stumaxb Ws, [Xn|SP]" , "op": "00111000|001|Rs|0|11000|Rn|11111"},
|
||
|
|
{"inst": "stumaxab Ws, [Xn|SP]" , "op": "00111000|101|Rs|0|11000|Rn|11111"},
|
||
|
|
{"inst": "stumaxalb Ws, [Xn|SP]" , "op": "00111000|111|Rs|0|11000|Rn|11111"},
|
||
|
|
{"inst": "stumaxlb Ws, [Xn|SP]" , "op": "00111000|011|Rs|0|11000|Rn|11111"},
|
||
|
|
{"inst": "stumaxh Ws, [Xn|SP]" , "op": "01111000|001|Rs|0|11000|Rn|11111"},
|
||
|
|
{"inst": "stumaxah Ws, [Xn|SP]" , "op": "01111000|101|Rs|0|11000|Rn|11111"},
|
||
|
|
{"inst": "stumaxalh Ws, [Xn|SP]" , "op": "01111000|111|Rs|0|11000|Rn|11111"},
|
||
|
|
{"inst": "stumaxlh Ws, [Xn|SP]" , "op": "01111000|011|Rs|0|11000|Rn|11111"},
|
||
|
|
{"inst": "stumin Ws, [Xn|SP]" , "op": "10111000|001|Rs|0|11100|Rn|11111"},
|
||
|
|
{"inst": "stumina Ws, [Xn|SP]" , "op": "10111000|101|Rs|0|11100|Rn|11111"},
|
||
|
|
{"inst": "stuminal Ws, [Xn|SP]" , "op": "10111000|111|Rs|0|11100|Rn|11111"},
|
||
|
|
{"inst": "stuminl Ws, [Xn|SP]" , "op": "10111000|011|Rs|0|11100|Rn|11111"},
|
||
|
|
{"inst": "stumin Xs, [Xn|SP]" , "op": "11111000|001|Rs|0|11100|Rn|11111"},
|
||
|
|
{"inst": "stumina Xs, [Xn|SP]" , "op": "11111000|101|Rs|0|11100|Rn|11111"},
|
||
|
|
{"inst": "stuminal Xs, [Xn|SP]" , "op": "11111000|111|Rs|0|11100|Rn|11111"},
|
||
|
|
{"inst": "stuminl Xs, [Xn|SP]" , "op": "11111000|011|Rs|0|11100|Rn|11111"},
|
||
|
|
{"inst": "stuminb Ws, [Xn|SP]" , "op": "00111000|001|Rs|0|11100|Rn|11111"},
|
||
|
|
{"inst": "stuminab Ws, [Xn|SP]" , "op": "00111000|101|Rs|0|11100|Rn|11111"},
|
||
|
|
{"inst": "stuminalb Ws, [Xn|SP]" , "op": "00111000|111|Rs|0|11100|Rn|11111"},
|
||
|
|
{"inst": "stuminlb Ws, [Xn|SP]" , "op": "00111000|011|Rs|0|11100|Rn|11111"},
|
||
|
|
{"inst": "stuminh Ws, [Xn|SP]" , "op": "01111000|001|Rs|0|11100|Rn|11111"},
|
||
|
|
{"inst": "stuminah Ws, [Xn|SP]" , "op": "01111000|101|Rs|0|11100|Rn|11111"},
|
||
|
|
{"inst": "stuminalh Ws, [Xn|SP]" , "op": "01111000|111|Rs|0|11100|Rn|11111"},
|
||
|
|
{"inst": "stuminlh Ws, [Xn|SP]" , "op": "01111000|011|Rs|0|11100|Rn|11111"},
|
||
|
|
{"inst": "swp Ws, Wd, [Xn|SP]" , "op": "10111000|001|Rs|1|00000|Rn|Rd"},
|
||
|
|
{"inst": "swpa Ws, Wd, [Xn|SP]" , "op": "10111000|101|Rs|1|00000|Rn|Rd"},
|
||
|
|
{"inst": "swpal Ws, Wd, [Xn|SP]" , "op": "10111000|111|Rs|1|00000|Rn|Rd"},
|
||
|
|
{"inst": "swpl Ws, Wd, [Xn|SP]" , "op": "10111000|011|Rs|1|00000|Rn|Rd"},
|
||
|
|
{"inst": "swp Xs, Xd, [Xn|SP]" , "op": "11111000|001|Rs|1|00000|Rn|Rd"},
|
||
|
|
{"inst": "swpa Xs, Xd, [Xn|SP]" , "op": "11111000|101|Rs|1|00000|Rn|Rd"},
|
||
|
|
{"inst": "swpal Xs, Xd, [Xn|SP]" , "op": "11111000|111|Rs|1|00000|Rn|Rd"},
|
||
|
|
{"inst": "swpl Xs, Xd, [Xn|SP]" , "op": "11111000|011|Rs|1|00000|Rn|Rd"},
|
||
|
|
{"inst": "swpb Ws, Wd, [Xn|SP]" , "op": "00111000|001|Rs|1|00000|Rn|Rd"},
|
||
|
|
{"inst": "swpab Ws, Wd, [Xn|SP]" , "op": "00111000|101|Rs|1|00000|Rn|Rd"},
|
||
|
|
{"inst": "swpalb Ws, Wd, [Xn|SP]" , "op": "00111000|111|Rs|1|00000|Rn|Rd"},
|
||
|
|
{"inst": "swplb Ws, Wd, [Xn|SP]" , "op": "00111000|011|Rs|1|00000|Rn|Rd"},
|
||
|
|
{"inst": "swph Ws, Wd, [Xn|SP]" , "op": "01111000|001|Rs|1|00000|Rn|Rd"},
|
||
|
|
{"inst": "swpah Ws, Wd, [Xn|SP]" , "op": "01111000|101|Rs|1|00000|Rn|Rd"},
|
||
|
|
{"inst": "swpalh Ws, Wd, [Xn|SP]" , "op": "01111000|111|Rs|1|00000|Rn|Rd"},
|
||
|
|
{"inst": "swplh Ws, Wd, [Xn|SP]" , "op": "01111000|011|Rs|1|00000|Rn|Rd"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "GP GP_EXT", "ext": "MOPS", "data": [
|
||
|
|
{"inst": "cpyfe [Xd]!, [Xs]!, Xn!" , "op": "00011001|100|Rs|0|00001|Rn|Rd"},
|
||
|
|
{"inst": "cpyfm [Xd]!, [Xs]!, Xn!" , "op": "00011001|010|Rs|0|00001|Rn|Rd"},
|
||
|
|
{"inst": "cpyfp [Xd]!, [Xs]!, Xn!" , "op": "00011001|000|Rs|0|00001|Rn|Rd"},
|
||
|
|
{"inst": "cpyfen [Xd]!, [Xs]!, Xn!" , "op": "00011001|100|Rs|1|10001|Rn|Rd"},
|
||
|
|
{"inst": "cpyfmn [Xd]!, [Xs]!, Xn!" , "op": "00011001|010|Rs|1|10001|Rn|Rd"},
|
||
|
|
{"inst": "cpyfpn [Xd]!, [Xs]!, Xn!" , "op": "00011001|000|Rs|1|10001|Rn|Rd"},
|
||
|
|
{"inst": "cpyfern [Xd]!, [Xs]!, Xn!" , "op": "00011001|100|Rs|1|00001|Rn|Rd"},
|
||
|
|
{"inst": "cpyfmrn [Xd]!, [Xs]!, Xn!" , "op": "00011001|010|Rs|1|00001|Rn|Rd"},
|
||
|
|
{"inst": "cpyfprn [Xd]!, [Xs]!, Xn!" , "op": "00011001|000|Rs|1|00001|Rn|Rd"},
|
||
|
|
{"inst": "cpyfert [Xd]!, [Xs]!, Xn!" , "op": "00011001|100|Rs|0|01001|Rn|Rd"},
|
||
|
|
{"inst": "cpyfmrt [Xd]!, [Xs]!, Xn!" , "op": "00011001|010|Rs|0|01001|Rn|Rd"},
|
||
|
|
{"inst": "cpyfprt [Xd]!, [Xs]!, Xn!" , "op": "00011001|000|Rs|0|01001|Rn|Rd"},
|
||
|
|
{"inst": "cpyfert [Xd]!, [Xs]!, Xn!" , "op": "00011001|100|Rs|0|01001|Rn|Rd"},
|
||
|
|
{"inst": "cpyfmrt [Xd]!, [Xs]!, Xn!" , "op": "00011001|010|Rs|0|01001|Rn|Rd"},
|
||
|
|
{"inst": "cpyfprt [Xd]!, [Xs]!, Xn!" , "op": "00011001|000|Rs|0|01001|Rn|Rd"},
|
||
|
|
{"inst": "cpyfertn [Xd]!, [Xs]!, Xn!" , "op": "00011001|100|Rs|1|11001|Rn|Rd"},
|
||
|
|
{"inst": "cpyfmrtn [Xd]!, [Xs]!, Xn!" , "op": "00011001|010|Rs|1|11001|Rn|Rd"},
|
||
|
|
{"inst": "cpyfprtn [Xd]!, [Xs]!, Xn!" , "op": "00011001|000|Rs|1|11001|Rn|Rd"},
|
||
|
|
{"inst": "cpyfertrn [Xd]!, [Xs]!, Xn!" , "op": "00011001|100|Rs|1|01001|Rn|Rd"},
|
||
|
|
{"inst": "cpyfmrtrn [Xd]!, [Xs]!, Xn!" , "op": "00011001|010|Rs|1|01001|Rn|Rd"},
|
||
|
|
{"inst": "cpyfprtrn [Xd]!, [Xs]!, Xn!" , "op": "00011001|000|Rs|1|01001|Rn|Rd"},
|
||
|
|
{"inst": "cpyfertwn [Xd]!, [Xs]!, Xn!" , "op": "00011001|100|Rs|0|11001|Rn|Rd"},
|
||
|
|
{"inst": "cpyfmrtwn [Xd]!, [Xs]!, Xn!" , "op": "00011001|010|Rs|0|11001|Rn|Rd"},
|
||
|
|
{"inst": "cpyfprtwn [Xd]!, [Xs]!, Xn!" , "op": "00011001|000|Rs|0|11001|Rn|Rd"},
|
||
|
|
{"inst": "cpyfet [Xd]!, [Xs]!, Xn!" , "op": "00011001|100|Rs|0|01101|Rn|Rd"},
|
||
|
|
{"inst": "cpyfmt [Xd]!, [Xs]!, Xn!" , "op": "00011001|010|Rs|0|01101|Rn|Rd"},
|
||
|
|
{"inst": "cpyfpt [Xd]!, [Xs]!, Xn!" , "op": "00011001|000|Rs|0|01101|Rn|Rd"},
|
||
|
|
{"inst": "cpyfetn [Xd]!, [Xs]!, Xn!" , "op": "00011001|100|Rs|1|11101|Rn|Rd"},
|
||
|
|
{"inst": "cpyfmtn [Xd]!, [Xs]!, Xn!" , "op": "00011001|010|Rs|1|11101|Rn|Rd"},
|
||
|
|
{"inst": "cpyfptn [Xd]!, [Xs]!, Xn!" , "op": "00011001|000|Rs|1|11101|Rn|Rd"},
|
||
|
|
{"inst": "cpyfetrn [Xd]!, [Xs]!, Xn!" , "op": "00011001|100|Rs|1|01101|Rn|Rd"},
|
||
|
|
{"inst": "cpyfmtrn [Xd]!, [Xs]!, Xn!" , "op": "00011001|010|Rs|1|01101|Rn|Rd"},
|
||
|
|
{"inst": "cpyfptrn [Xd]!, [Xs]!, Xn!" , "op": "00011001|000|Rs|1|01101|Rn|Rd"},
|
||
|
|
{"inst": "cpyfetwn [Xd]!, [Xs]!, Xn!" , "op": "00011001|100|Rs|0|11101|Rn|Rd"},
|
||
|
|
{"inst": "cpyfmtwn [Xd]!, [Xs]!, Xn!" , "op": "00011001|010|Rs|0|11101|Rn|Rd"},
|
||
|
|
{"inst": "cpyfptwn [Xd]!, [Xs]!, Xn!" , "op": "00011001|000|Rs|0|11101|Rn|Rd"},
|
||
|
|
{"inst": "cpyfewn [Xd]!, [Xs]!, Xn!" , "op": "00011001|100|Rs|0|10001|Rn|Rd"},
|
||
|
|
{"inst": "cpyfmwn [Xd]!, [Xs]!, Xn!" , "op": "00011001|010|Rs|0|10001|Rn|Rd"},
|
||
|
|
{"inst": "cpyfpwn [Xd]!, [Xs]!, Xn!" , "op": "00011001|000|Rs|0|10001|Rn|Rd"},
|
||
|
|
{"inst": "cpyfewt [Xd]!, [Xs]!, Xn!" , "op": "00011001|100|Rs|0|00101|Rn|Rd"},
|
||
|
|
{"inst": "cpyfmwt [Xd]!, [Xs]!, Xn!" , "op": "00011001|010|Rs|0|00101|Rn|Rd"},
|
||
|
|
{"inst": "cpyfpwt [Xd]!, [Xs]!, Xn!" , "op": "00011001|000|Rs|0|00101|Rn|Rd"},
|
||
|
|
{"inst": "cpyfewtn [Xd]!, [Xs]!, Xn!" , "op": "00011001|100|Rs|1|10101|Rn|Rd"},
|
||
|
|
{"inst": "cpyfmwtn [Xd]!, [Xs]!, Xn!" , "op": "00011001|010|Rs|1|10101|Rn|Rd"},
|
||
|
|
{"inst": "cpyfpwtn [Xd]!, [Xs]!, Xn!" , "op": "00011001|000|Rs|1|10101|Rn|Rd"},
|
||
|
|
{"inst": "cpyfewtrn [Xd]!, [Xs]!, Xn!" , "op": "00011001|100|Rs|1|00101|Rn|Rd"},
|
||
|
|
{"inst": "cpyfmwtrn [Xd]!, [Xs]!, Xn!" , "op": "00011001|010|Rs|1|00101|Rn|Rd"},
|
||
|
|
{"inst": "cpyfpwtrn [Xd]!, [Xs]!, Xn!" , "op": "00011001|000|Rs|1|00101|Rn|Rd"},
|
||
|
|
{"inst": "cpyfewtwn [Xd]!, [Xs]!, Xn!" , "op": "00011001|100|Rs|0|10101|Rn|Rd"},
|
||
|
|
{"inst": "cpyfmwtwn [Xd]!, [Xs]!, Xn!" , "op": "00011001|010|Rs|0|10101|Rn|Rd"},
|
||
|
|
{"inst": "cpyfpwtwn [Xd]!, [Xs]!, Xn!" , "op": "00011001|000|Rs|0|10101|Rn|Rd"},
|
||
|
|
{"inst": "cpye [Xd]!, [Xs]!, Xn!" , "op": "00011101|100|Rs|0|00001|Rn|Rd"},
|
||
|
|
{"inst": "cpym [Xd]!, [Xs]!, Xn!" , "op": "00011101|010|Rs|0|00001|Rn|Rd"},
|
||
|
|
{"inst": "cpyp [Xd]!, [Xs]!, Xn!" , "op": "00011101|000|Rs|0|00001|Rn|Rd"},
|
||
|
|
{"inst": "cpyen [Xd]!, [Xs]!, Xn!" , "op": "00011101|100|Rs|1|10001|Rn|Rd"},
|
||
|
|
{"inst": "cpymn [Xd]!, [Xs]!, Xn!" , "op": "00011101|010|Rs|1|10001|Rn|Rd"},
|
||
|
|
{"inst": "cpypn [Xd]!, [Xs]!, Xn!" , "op": "00011101|000|Rs|1|10001|Rn|Rd"},
|
||
|
|
{"inst": "cpyern [Xd]!, [Xs]!, Xn!" , "op": "00011101|100|Rs|1|00001|Rn|Rd"},
|
||
|
|
{"inst": "cpymrn [Xd]!, [Xs]!, Xn!" , "op": "00011101|010|Rs|1|00001|Rn|Rd"},
|
||
|
|
{"inst": "cpyprn [Xd]!, [Xs]!, Xn!" , "op": "00011101|000|Rs|1|00001|Rn|Rd"},
|
||
|
|
{"inst": "cpyert [Xd]!, [Xs]!, Xn!" , "op": "00011101|100|Rs|0|01001|Rn|Rd"},
|
||
|
|
{"inst": "cpymrt [Xd]!, [Xs]!, Xn!" , "op": "00011101|010|Rs|0|01001|Rn|Rd"},
|
||
|
|
{"inst": "cpyprt [Xd]!, [Xs]!, Xn!" , "op": "00011101|000|Rs|0|01001|Rn|Rd"},
|
||
|
|
{"inst": "cpyertn [Xd]!, [Xs]!, Xn!" , "op": "00011101|100|Rs|1|11001|Rn|Rd"},
|
||
|
|
{"inst": "cpymrtn [Xd]!, [Xs]!, Xn!" , "op": "00011101|010|Rs|1|11001|Rn|Rd"},
|
||
|
|
{"inst": "cpyprtn [Xd]!, [Xs]!, Xn!" , "op": "00011101|000|Rs|1|11001|Rn|Rd"},
|
||
|
|
{"inst": "cpyertrn [Xd]!, [Xs]!, Xn!" , "op": "00011101|100|Rs|1|01001|Rn|Rd"},
|
||
|
|
{"inst": "cpymrtrn [Xd]!, [Xs]!, Xn!" , "op": "00011101|010|Rs|1|01001|Rn|Rd"},
|
||
|
|
{"inst": "cpyprtrn [Xd]!, [Xs]!, Xn!" , "op": "00011101|000|Rs|1|01001|Rn|Rd"},
|
||
|
|
{"inst": "cpyertwn [Xd]!, [Xs]!, Xn!" , "op": "00011101|100|Rs|0|11001|Rn|Rd"},
|
||
|
|
{"inst": "cpymrtwn [Xd]!, [Xs]!, Xn!" , "op": "00011101|010|Rs|0|11001|Rn|Rd"},
|
||
|
|
{"inst": "cpyprtwn [Xd]!, [Xs]!, Xn!" , "op": "00011101|000|Rs|0|11001|Rn|Rd"},
|
||
|
|
{"inst": "cpyet [Xd]!, [Xs]!, Xn!" , "op": "00011101|100|Rs|0|01101|Rn|Rd"},
|
||
|
|
{"inst": "cpymt [Xd]!, [Xs]!, Xn!" , "op": "00011101|010|Rs|0|01101|Rn|Rd"},
|
||
|
|
{"inst": "cpypt [Xd]!, [Xs]!, Xn!" , "op": "00011101|000|Rs|0|01101|Rn|Rd"},
|
||
|
|
{"inst": "cpyetn [Xd]!, [Xs]!, Xn!" , "op": "00011101|100|Rs|1|11101|Rn|Rd"},
|
||
|
|
{"inst": "cpymtn [Xd]!, [Xs]!, Xn!" , "op": "00011101|010|Rs|1|11101|Rn|Rd"},
|
||
|
|
{"inst": "cpyptn [Xd]!, [Xs]!, Xn!" , "op": "00011101|000|Rs|1|11101|Rn|Rd"},
|
||
|
|
{"inst": "cpyetrn [Xd]!, [Xs]!, Xn!" , "op": "00011101|100|Rs|1|01101|Rn|Rd"},
|
||
|
|
{"inst": "cpymtrn [Xd]!, [Xs]!, Xn!" , "op": "00011101|010|Rs|1|01101|Rn|Rd"},
|
||
|
|
{"inst": "cpyptrn [Xd]!, [Xs]!, Xn!" , "op": "00011101|000|Rs|1|01101|Rn|Rd"},
|
||
|
|
{"inst": "cpyetwn [Xd]!, [Xs]!, Xn!" , "op": "00011101|100|Rs|0|11101|Rn|Rd"},
|
||
|
|
{"inst": "cpymtwn [Xd]!, [Xs]!, Xn!" , "op": "00011101|010|Rs|0|11101|Rn|Rd"},
|
||
|
|
{"inst": "cpyptwn [Xd]!, [Xs]!, Xn!" , "op": "00011101|000|Rs|0|11101|Rn|Rd"},
|
||
|
|
{"inst": "cpyewn [Xd]!, [Xs]!, Xn!" , "op": "00011101|100|Rs|0|10001|Rn|Rd"},
|
||
|
|
{"inst": "cpymwn [Xd]!, [Xs]!, Xn!" , "op": "00011101|010|Rs|0|10001|Rn|Rd"},
|
||
|
|
{"inst": "cpypwn [Xd]!, [Xs]!, Xn!" , "op": "00011101|000|Rs|0|10001|Rn|Rd"},
|
||
|
|
{"inst": "cpyewt [Xd]!, [Xs]!, Xn!" , "op": "00011101|100|Rs|0|00101|Rn|Rd"},
|
||
|
|
{"inst": "cpymwt [Xd]!, [Xs]!, Xn!" , "op": "00011101|010|Rs|0|00101|Rn|Rd"},
|
||
|
|
{"inst": "cpypwt [Xd]!, [Xs]!, Xn!" , "op": "00011101|000|Rs|0|00101|Rn|Rd"},
|
||
|
|
{"inst": "cpyewtn [Xd]!, [Xs]!, Xn!" , "op": "00011101|100|Rs|1|10101|Rn|Rd"},
|
||
|
|
{"inst": "cpymwtn [Xd]!, [Xs]!, Xn!" , "op": "00011101|010|Rs|1|10101|Rn|Rd"},
|
||
|
|
{"inst": "cpypwtn [Xd]!, [Xs]!, Xn!" , "op": "00011101|000|Rs|1|10101|Rn|Rd"},
|
||
|
|
{"inst": "cpyewtrn [Xd]!, [Xs]!, Xn!" , "op": "00011101|100|Rs|1|00101|Rn|Rd"},
|
||
|
|
{"inst": "cpymwtrn [Xd]!, [Xs]!, Xn!" , "op": "00011101|010|Rs|1|00101|Rn|Rd"},
|
||
|
|
{"inst": "cpypwtrn [Xd]!, [Xs]!, Xn!" , "op": "00011101|000|Rs|1|00101|Rn|Rd"},
|
||
|
|
{"inst": "cpyewtwn [Xd]!, [Xs]!, Xn!" , "op": "00011101|100|Rs|0|10101|Rn|Rd"},
|
||
|
|
{"inst": "cpymwtwn [Xd]!, [Xs]!, Xn!" , "op": "00011101|010|Rs|0|10101|Rn|Rd"},
|
||
|
|
{"inst": "cpypwtwn [Xd]!, [Xs]!, Xn!" , "op": "00011101|000|Rs|0|10101|Rn|Rd"},
|
||
|
|
{"inst": "setge [Xd]!, Xn!, Xs" , "op": "00011101|110|Rs|1|00001|Rn|Rd"},
|
||
|
|
{"inst": "setgm [Xd]!, Xn!, Xs" , "op": "00011101|110|Rs|0|10001|Rn|Rd"},
|
||
|
|
{"inst": "setgp [Xd]!, Xn!, Xs" , "op": "00011101|110|Rs|0|00001|Rn|Rd"},
|
||
|
|
{"inst": "setgen [Xd]!, Xn!, Xs" , "op": "00011101|110|Rs|1|01001|Rn|Rd"},
|
||
|
|
{"inst": "setgmn [Xd]!, Xn!, Xs" , "op": "00011101|110|Rs|0|11001|Rn|Rd"},
|
||
|
|
{"inst": "setgpn [Xd]!, Xn!, Xs" , "op": "00011101|110|Rs|0|01001|Rn|Rd"},
|
||
|
|
{"inst": "setget [Xd]!, Xn!, Xs" , "op": "00011101|110|Rs|1|00101|Rn|Rd"},
|
||
|
|
{"inst": "setgmt [Xd]!, Xn!, Xs" , "op": "00011101|110|Rs|0|10101|Rn|Rd"},
|
||
|
|
{"inst": "setgpt [Xd]!, Xn!, Xs" , "op": "00011101|110|Rs|0|00101|Rn|Rd"},
|
||
|
|
{"inst": "setgetn [Xd]!, Xn!, Xs" , "op": "00011101|110|Rs|1|01101|Rn|Rd"},
|
||
|
|
{"inst": "setgmtn [Xd]!, Xn!, Xs" , "op": "00011101|110|Rs|0|11101|Rn|Rd"},
|
||
|
|
{"inst": "setgptn [Xd]!, Xn!, Xs" , "op": "00011101|110|Rs|0|01101|Rn|Rd"},
|
||
|
|
{"inst": "sete [Xd]!, Xn!, Xs" , "op": "00011001|110|Rs|1|00001|Rn|Rd"},
|
||
|
|
{"inst": "setm [Xd]!, Xn!, Xs" , "op": "00011001|110|Rs|0|10001|Rn|Rd"},
|
||
|
|
{"inst": "setp [Xd]!, Xn!, Xs" , "op": "00011001|110|Rs|0|00001|Rn|Rd"},
|
||
|
|
{"inst": "seten [Xd]!, Xn!, Xs" , "op": "00011001|110|Rs|1|01001|Rn|Rd"},
|
||
|
|
{"inst": "setmn [Xd]!, Xn!, Xs" , "op": "00011001|110|Rs|0|11001|Rn|Rd"},
|
||
|
|
{"inst": "setpn [Xd]!, Xn!, Xs" , "op": "00011001|110|Rs|0|01001|Rn|Rd"},
|
||
|
|
{"inst": "setet [Xd]!, Xn!, Xs" , "op": "00011001|110|Rs|1|00101|Rn|Rd"},
|
||
|
|
{"inst": "setmt [Xd]!, Xn!, Xs" , "op": "00011001|110|Rs|0|10101|Rn|Rd"},
|
||
|
|
{"inst": "setpt [Xd]!, Xn!, Xs" , "op": "00011001|110|Rs|0|00101|Rn|Rd"},
|
||
|
|
{"inst": "setetn [Xd]!, Xn!, Xs" , "op": "00011001|110|Rs|1|01101|Rn|Rd"},
|
||
|
|
{"inst": "setmtn [Xd]!, Xn!, Xs" , "op": "00011001|110|Rs|0|11101|Rn|Rd"},
|
||
|
|
{"inst": "setptn [Xd]!, Xn!, Xs" , "op": "00011001|110|Rs|0|01101|Rn|Rd"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "GP MTE", "ext": "MTE", "data": [
|
||
|
|
{"inst": "addg Xd|SP, Xn|SP, #imm1, #imm2" , "op": "10010001|10|imm1:6|00|imm2:4|Rn|Rd"},
|
||
|
|
{"inst": "cmpp Xn|SP, Xm|SP" , "op": "10111010|110|Rm|000000|Rn|11111"},
|
||
|
|
{"inst": "gmi Xd, Xn|SP, Xm" , "op": "10011010|110|Rm|000101|Rn|Rd"},
|
||
|
|
{"inst": "irg Xd, Xn|SP, Xm" , "op": "10011010|110|Rm|000100|Rn|Rd"},
|
||
|
|
{"inst": "ldg Xd, [Xn|SP, #soff*16]" , "op": "11011001|011|soff:9|00|Rn|Rd"},
|
||
|
|
{"inst": "st2g Xs|SP, [Xn|SP, #soff*16]{@}{!}" , "op": "11011001|101|soff:9|!post|W|Rn|Rs"},
|
||
|
|
{"inst": "stg Xs|SP, [Xn|SP, #soff*16]{@}{!}" , "op": "11011001|001|soff:9|!post|W|Rn|Rs"},
|
||
|
|
{"inst": "stgp Xs, Xs2, [Xn|SP, #soff*16]{@}{!}" , "op": "0110100|!post|W|0|soff:7|Rs2|Rn|Rs"},
|
||
|
|
{"inst": "stz2g Xs|SP, [Xn|SP, #soff*16]{@}{!}" , "op": "11011001|111|soff:9|!post|W|Rn|Rs"},
|
||
|
|
{"inst": "stzg Xs|SP, [Xn|SP, #soff*16]{@}{!}" , "op": "11011001|011|soff:9|!post|W|Rn|Rs"},
|
||
|
|
{"inst": "subg Xd|SP, Xn|SP, #imm1, #imm2" , "op": "11010001|10|imm1:6|00|imm2:4|Rn|Rd"},
|
||
|
|
{"inst": "subp Xd, Xn|SP, Xm|SP" , "op": "10011010|110|Rm|0|00000|Rn|Rd"},
|
||
|
|
{"inst": "subps Xd, Xn|SP, Xm|SP" , "op": "10011010|110|Rm|0|00000|Rn|Rd" , "io": "N=W Z=W C=W V=W"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "GP MTE", "ext": "MTE2", "data": [
|
||
|
|
{"inst": "ldgm Xd, [Xn|SP]" , "op": "11011001|111|00000|0|00000|Rn|Rd"},
|
||
|
|
{"inst": "stgm Xs, [Xn|SP]" , "op": "11011001|101|00000|0|00000|Rn|Rs"},
|
||
|
|
{"inst": "stzgm Xs, [Xn|SP]" , "op": "11011001|001|00000|0|00000|Rn|Rs"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "GP PAUTH", "ext": "PAUTH", "data": [
|
||
|
|
{"inst": "autda Xd, Xn|SP" , "op": "11011010|110|00001|000110|Rn|Rd"},
|
||
|
|
{"inst": "autdb Xd, Xn|SP" , "op": "11011010|110|00001|000111|Rn|Rd"},
|
||
|
|
{"inst": "autdza Xd" , "op": "11011010|110|00001|001110|11111|Rd"},
|
||
|
|
{"inst": "autdzb Xd" , "op": "11011010|110|00001|001111|11111|Rd"},
|
||
|
|
{"inst": "autia Xd, Xn|SP" , "op": "11011010|110|00001|000100|Rn|Rd"},
|
||
|
|
{"inst": "autia1716" , "op": "11010101|000|00011|0010|0001|100|11111"},
|
||
|
|
{"inst": "autiasp" , "op": "11010101|000|00011|0010|0011|101|11111"},
|
||
|
|
{"inst": "autiaz" , "op": "11010101|000|00011|0010|0011|100|11111"},
|
||
|
|
{"inst": "autib Xd, Xn|SP" , "op": "11011010|110|00001|000101|Rn|Rd"},
|
||
|
|
{"inst": "autib1716" , "op": "11010101|000|00011|0010|0001|110|11111"},
|
||
|
|
{"inst": "autibsp" , "op": "11010101|000|00011|0010|0011|111|11111"},
|
||
|
|
{"inst": "autibz" , "op": "11010101|000|00011|0010|0011|110|11111"},
|
||
|
|
{"inst": "autiza Xd" , "op": "11011010|110|00001|001100|11111|Rd"},
|
||
|
|
{"inst": "autizb Xd" , "op": "11011010|110|00001|001101|11111|Rd"},
|
||
|
|
{"inst": "blraa Xn, Xm|SP" , "op": "11010111|001|11111|0000|10|Rn|Rm" , "control": "call"},
|
||
|
|
{"inst": "blraaz Xn" , "op": "11010110|001|11111|0000|10|Rn|11111" , "control": "call"},
|
||
|
|
{"inst": "blrab Xn, Xm|SP" , "op": "11010111|001|11111|0000|11|Rn|Rm" , "control": "call"},
|
||
|
|
{"inst": "blrabz Xn" , "op": "11010110|001|11111|0000|11|Rn|11111" , "control": "call"},
|
||
|
|
{"inst": "braa Xn, Xm|SP" , "op": "11010111|000|11111|0000|10|Rn|Rm" , "control": "call"},
|
||
|
|
{"inst": "braaz Xn" , "op": "11010110|000|11111|0000|10|Rn|11111" , "control": "call"},
|
||
|
|
{"inst": "brab Xn, Xm|SP" , "op": "11010111|000|11111|0000|11|Rn|Rm" , "control": "call"},
|
||
|
|
{"inst": "brabz Xn" , "op": "11010110|000|11111|0000|11|Rn|11111" , "control": "call"},
|
||
|
|
{"inst": "eretaa" , "op": "11010110|100|11111|0000|10|11111|11111" , "control": "return"},
|
||
|
|
{"inst": "eretab" , "op": "11010110|100|11111|0000|11|11111|11111" , "control": "return"},
|
||
|
|
{"inst": "ldraa Xd, [Xn|SP, #soff]{!}" , "op": "11111000|0|soff:1|1|soff:9|W1|Rn|Rd"},
|
||
|
|
{"inst": "ldrab Xd, [Xn|SP, #soff]{!}" , "op": "11111000|1|soff:1|1|soff:9|W1|Rn|Rd"},
|
||
|
|
{"inst": "pacda Xd, Xn|SP" , "op": "11011010|110|00001|0|00010|Rn|Rd"},
|
||
|
|
{"inst": "pacdb Xd, Xn|SP" , "op": "11011010|110|00001|0|00011|Rn|Rd"},
|
||
|
|
{"inst": "pacdza Xd" , "op": "11011010|110|00001|0|01010|11111|Rd"},
|
||
|
|
{"inst": "pacdzb Xd" , "op": "11011010|110|00001|0|01011|11111|Rd"},
|
||
|
|
{"inst": "pacga Xd, Xn, Xm|SP" , "op": "10011010|110|Rm|0|01100|Rn|Rd"},
|
||
|
|
{"inst": "pacia Xd, Xn|SP" , "op": "11011010|110|00001|0|00000|Rn|Rd"},
|
||
|
|
{"inst": "pacia1716" , "op": "11010101|000|00011|0010|0001|000|11111"},
|
||
|
|
{"inst": "paciasp" , "op": "11010101|000|00011|0010|0011|001|11111"},
|
||
|
|
{"inst": "paciaz" , "op": "11010101|000|00011|0010|0011|000|11111"},
|
||
|
|
{"inst": "pacib Xd, Xn|SP" , "op": "11011010|110|00001|0|00001|Rn|Rd"},
|
||
|
|
{"inst": "pacib1716" , "op": "11010101|000|00011|0010|0001|010|11111"},
|
||
|
|
{"inst": "pacibsp" , "op": "11010101|000|00011|0010|0011|011|11111"},
|
||
|
|
{"inst": "pacibz" , "op": "11010101|000|00011|0010|0011|010|11111"},
|
||
|
|
{"inst": "paciza Xd" , "op": "11011010|110|00001|0|01000|11111|Rd"},
|
||
|
|
{"inst": "pacizb Xd" , "op": "11011010|110|00001|0|01001|11111|Rd"},
|
||
|
|
{"inst": "retaa" , "op": "11010110|010|11111|0|00010|11111|11111" , "control": "return"},
|
||
|
|
{"inst": "retab" , "op": "11010110|010|11111|0|00011|11111|11111" , "control": "return"},
|
||
|
|
{"inst": "xpacd Xd" , "op": "11011010|110|00001|0|10001|11111|Rd"},
|
||
|
|
{"inst": "xpaci Xd" , "op": "11011010|110|00001|0|10000|11111|Rd"},
|
||
|
|
{"inst": "xpaclri Xd" , "op": "11010101|000|00011|0|01000|00111|11111"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "GP GP_EXT", "ext": "RAS", "data": [
|
||
|
|
{"inst": "esb" , "op": "11010101|000|00011|0010|0010|000|11111"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "GP GP_EXT", "ext": "RPRFM", "data": [
|
||
|
|
{"inst": "rprfm #rprf_op, Xm, [Xn|SP]" , "op": "11111000|101|Rm|imm:1|1|imm:2|10|Rn|11|imm:3" , "imm": "ImmRPRF(rprf_op)"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "GP GP_EXT", "ext": "SB", "data": [
|
||
|
|
{"inst": "sb" , "op": "11010101|000|00011|0011|0000|111|11111"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "GP GP_EXT", "ext": "SPE", "data": [
|
||
|
|
{"inst": "psb #psb_tsb_op" , "op": "11010101|000|00011|0010|0010|001|11111" , "imm": "ImmPSB_TSB(psb_tsb_op)"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "GP GP_EXT", "ext": "SPECRES", "data": [
|
||
|
|
{"inst": "cfp #rctx, Xt" , "op": "11010101|000|01011|0111|0011|100|Rt" , "imm": "ImmRCTX(rctx)"},
|
||
|
|
{"inst": "cpp #rctx, Xt" , "op": "11010101|000|01011|0111|0011|111|Rt" , "imm": "ImmRCTX(rctx)"},
|
||
|
|
{"inst": "dvp #rctx, Xt" , "op": "11010101|000|01|011|0111|0011|101|Rt" , "imm": "ImmRCTX(rctx)"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "GP GP_EXT", "ext": "SPECRES2", "data": [
|
||
|
|
{"inst": "cosp #rctx, Xt" , "op": "11010101|000|01011|0111|0011|110|Rt" , "imm": "ImmRCTX(rctx)"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "GP GP_EXT", "ext": "SYSINSTR128", "data": [
|
||
|
|
{"inst": "sysp #op1, #CRn, #CRm, #op2, 2x{Xt}+" , "op": "11010101|010|01|op1:3|CRn|CRm|op2:3|Rt"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "GP GP_EXT", "ext": "SYSREG128", "data": [
|
||
|
|
{"inst": "mrrs 2x{Xd}+, #sysreg" , "op": "11010101|011|1|sysreg:15|Rd"},
|
||
|
|
{"inst": "msrr 2x{Xs}+, #sysreg" , "op": "11010101|010|1|sysreg:15|Rd"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "GP GP_EXT", "ext": "THE", "data": [
|
||
|
|
{"inst": "rcwcas Xs, Xt, [Xn|SP]" , "op": "00011001|001|Rs|0|00010|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "rcwcasa Xs, Xt, [Xn|SP]" , "op": "00011001|101|Rs|0|00010|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "rcwcasal Xs, Xt, [Xn|SP]" , "op": "00011001|111|Rs|0|00010|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "rcwcasl Xs, Xt, [Xn|SP]" , "op": "00011001|011|Rs|0|00010|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "rcwcasp 2x{Xs}+, 2x{Xt}+, [Xn|SP]" , "op": "00011001|001|Rs|0|00011|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"},
|
||
|
|
{"inst": "rcwcaspa 2x{Xs}+, 2x{Xt}+, [Xn|SP]" , "op": "00011001|101|Rs|0|00011|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"},
|
||
|
|
{"inst": "rcwcaspal 2x{Xs}+, 2x{Xt}+, [Xn|SP]" , "op": "00011001|111|Rs|0|00011|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"},
|
||
|
|
{"inst": "rcwcaspl 2x{Xs}+, 2x{Xt}+, [Xn|SP]" , "op": "00011001|011|Rs|0|00011|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"},
|
||
|
|
{"inst": "rcwclr Xs, Xt, [Xn|SP]" , "op": "00111000|001|Rs|1|00100|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "rcwclra Xs, Xt, [Xn|SP]" , "op": "00111000|101|Rs|1|00100|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "rcwclral Xs, Xt, [Xn|SP]" , "op": "00111000|111|Rs|1|00100|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "rcwclrl Xs, Xt, [Xn|SP]" , "op": "00111000|011|Rs|1|00100|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "rcwclrp Xt, Xt2, [Xn|SP]" , "op": "00011001|001|Rt2|1|00100|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"},
|
||
|
|
{"inst": "rcwclrpa Xt, Xt2, [Xn|SP]" , "op": "00011001|101|Rt2|1|00100|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"},
|
||
|
|
{"inst": "rcwclrpal Xt, Xt2, [Xn|SP]" , "op": "00011001|111|Rt2|1|00100|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"},
|
||
|
|
{"inst": "rcwclrpl Xt, Xt2, [Xn|SP]" , "op": "00011001|011|Rt2|1|00100|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"},
|
||
|
|
{"inst": "rcwscas Xs, Xt, [Xn|SP]" , "op": "01011001|001|Rs|0|00010|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "rcwscasa Xs, Xt, [Xn|SP]" , "op": "01011001|101|Rs|0|00010|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "rcwscasal Xs, Xt, [Xn|SP]" , "op": "01011001|111|Rs|0|00010|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "rcwscasl Xs, Xt, [Xn|SP]" , "op": "01011001|011|Rs|0|00010|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "rcwscasp 2x{Xs}+, 2x{Xt}+, [Xn|SP]" , "op": "01011001|001|Rs|0|00011|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"},
|
||
|
|
{"inst": "rcwscaspa 2x{Xs}+, 2x{Xt}+, [Xn|SP]" , "op": "01011001|101|Rs|0|00011|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"},
|
||
|
|
{"inst": "rcwscaspal 2x{Xs}+, 2x{Xt}+, [Xn|SP]" , "op": "01011001|111|Rs|0|00011|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"},
|
||
|
|
{"inst": "rcwscaspl 2x{Xs}+, 2x{Xt}+, [Xn|SP]" , "op": "01011001|011|Rs|0|00011|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"},
|
||
|
|
{"inst": "rcwsclr Xs, Xt, [Xn|SP]" , "op": "01111000|001|Rs|1|00100|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "rcwsclra Xs, Xt, [Xn|SP]" , "op": "01111000|101|Rs|1|00100|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "rcwsclral Xs, Xt, [Xn|SP]" , "op": "01111000|111|Rs|1|00100|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "rcwsclrl Xs, Xt, [Xn|SP]" , "op": "01111000|011|Rs|1|00100|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "rcwsclrp Xt, Xt2, [Xn|SP]" , "op": "01011001|001|Rt2|1|00100|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"},
|
||
|
|
{"inst": "rcwsclrpa Xt, Xt2, [Xn|SP]" , "op": "01011001|101|Rt2|1|00100|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"},
|
||
|
|
{"inst": "rcwsclrpal Xt, Xt2, [Xn|SP]" , "op": "01011001|111|Rt2|1|00100|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"},
|
||
|
|
{"inst": "rcwsclrpl Xt, Xt2, [Xn|SP]" , "op": "01011001|011|Rt2|1|00100|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"},
|
||
|
|
{"inst": "rcwset Xs, Xt, [Xn|SP]" , "op": "00111000|001|Rs|1|01100|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "rcwseta Xs, Xt, [Xn|SP]" , "op": "00111000|101|Rs|1|01100|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "rcwsetal Xs, Xt, [Xn|SP]" , "op": "00111000|111|Rs|1|01100|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "rcwsetl Xs, Xt, [Xn|SP]" , "op": "00111000|011|Rs|1|01100|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "rcwsetp Xt, Xt2, [Xn|SP]" , "op": "00011001|001|Rt2|1|01100|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"},
|
||
|
|
{"inst": "rcwsetpa Xt, Xt2, [Xn|SP]" , "op": "00011001|101|Rt2|1|01100|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"},
|
||
|
|
{"inst": "rcwsetpal Xt, Xt2, [Xn|SP]" , "op": "00011001|111|Rt2|1|01100|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"},
|
||
|
|
{"inst": "rcwsetpl Xt, Xt2, [Xn|SP]" , "op": "00011001|011|Rt2|1|01100|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"},
|
||
|
|
{"inst": "rcwsset Xs, Xt, [Xn|SP]" , "op": "01111000|001|Rs|1|01100|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "rcwsseta Xs, Xt, [Xn|SP]" , "op": "01111000|101|Rs|1|01100|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "rcwssetal Xs, Xt, [Xn|SP]" , "op": "01111000|111|Rs|1|01100|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "rcwssetl Xs, Xt, [Xn|SP]" , "op": "01111000|011|Rs|1|01100|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "rcwssetp Xt, Xt2, [Xn|SP]" , "op": "01011001|001|Rt2|1|01100|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"},
|
||
|
|
{"inst": "rcwssetpa Xt, Xt2, [Xn|SP]" , "op": "01011001|101|Rt2|1|01100|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"},
|
||
|
|
{"inst": "rcwssetpal Xt, Xt2, [Xn|SP]" , "op": "01011001|111|Rt2|1|01100|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"},
|
||
|
|
{"inst": "rcwssetpl Xt, Xt2, [Xn|SP]" , "op": "01011001|011|Rt2|1|01100|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"},
|
||
|
|
{"inst": "rcwsswp Xs, Xt, [Xn|SP]" , "op": "01111000|001|Rs|1|01000|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "rcwsswpa Xs, Xt, [Xn|SP]" , "op": "01111000|101|Rs|1|01000|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "rcwsswpal Xs, Xt, [Xn|SP]" , "op": "01111000|111|Rs|1|01000|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "rcwsswpl Xs, Xt, [Xn|SP]" , "op": "01111000|011|Rs|1|01000|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "rcwsswpp Xt, Xt2, [Xn|SP]" , "op": "01011001|001|Rt2|1|01000|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"},
|
||
|
|
{"inst": "rcwsswppa Xt, Xt2, [Xn|SP]" , "op": "01011001|101|Rt2|1|01000|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"},
|
||
|
|
{"inst": "rcwsswppal Xt, Xt2, [Xn|SP]" , "op": "01011001|111|Rt2|1|01000|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"},
|
||
|
|
{"inst": "rcwsswppl Xt, Xt2, [Xn|SP]" , "op": "01011001|011|Rt2|1|01000|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"},
|
||
|
|
{"inst": "rcwswp Xs, Xt, [Xn|SP]" , "op": "00111000|001|Rs|1|01000|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "rcwswpa Xs, Xt, [Xn|SP]" , "op": "00111000|101|Rs|1|01000|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "rcwswpal Xs, Xt, [Xn|SP]" , "op": "00111000|111|Rs|1|01000|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "rcwswpl Xs, Xt, [Xn|SP]" , "op": "00111000|011|Rs|1|01000|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "rcwswpp Xt, Xt2, [Xn|SP]" , "op": "00011001|001|Rt2|1|01000|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"},
|
||
|
|
{"inst": "rcwswppa Xt, Xt2, [Xn|SP]" , "op": "00011001|101|Rt2|1|01000|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"},
|
||
|
|
{"inst": "rcwswppal Xt, Xt2, [Xn|SP]" , "op": "00011001|111|Rt2|1|01000|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"},
|
||
|
|
{"inst": "rcwswppl Xt, Xt2, [Xn|SP]" , "op": "00011001|011|Rt2|1|01000|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "GP GP_EXT", "ext": "TME", "data": [
|
||
|
|
{"inst": "tcancel #imm" , "op": "11010100|011|imm:16|00000"},
|
||
|
|
{"inst": "tcommit" , "op": "11010101|000|00011|0011|0000|011|11111"},
|
||
|
|
{"inst": "tstart Xt" , "op": "11010101|001|00011|0011|0000|011|Rt"},
|
||
|
|
{"inst": "ttest Xd" , "op": "11010101|001|00011|0011|0001|011|Rd"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "GP GP_EXT", "ext": "TRF", "data": [
|
||
|
|
{"inst": "tsb #psb_tsb_op" , "op": "11010101|000|00011|0010|0010|010|11111" , "imm": "ImmPSB_TSB(psb_tsb_op)"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "GP GP_EXT", "ext": "WFXT", "data": [
|
||
|
|
{"inst": "wfet Xs" , "op": "11010101|000|00011|0001|0000|000|Rs"},
|
||
|
|
{"inst": "wfit Xs" , "op": "11010101|000|00011|0001|0000|001|Rs"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "ASIMD", "ext": "ASIMD", "data": [
|
||
|
|
{"inst": "abs Dd, Dn" , "op": "01011110|11|10000|01011|10|Vn|Vd"},
|
||
|
|
{"inst": "abs Vd.t, Vn.t" , "op": "00001110|sz|10000|01011|10|Vn|Vd" , "t": "8B 4H 2S"},
|
||
|
|
{"inst": "abs Vd.t, Vn.t" , "op": "01001110|sz|10000|01011|10|Vn|Vd" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "add Dd, Dn, Dm" , "op": "01011110|11|1|Vm|10000|1|Vn|Vd"},
|
||
|
|
{"inst": "add Vd.t, Vn.t, Vm.t" , "op": "00001110|sz|1|Vm|10000|1|Vn|Vd" , "t": "8B 4H 2S"},
|
||
|
|
{"inst": "add Vd.t, Vn.t, Vm.t" , "op": "01001110|sz|1|Vm|10000|1|Vn|Vd" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "addhn Vd.ta, Vn.tb, Vm.tb" , "op": "00001110|sz|1|Vm|01000|0|Vn|Vd" , "ta.tb": "8B.8H 4H.4S 2S.2D"},
|
||
|
|
{"inst": "addhn2 Vx.ta, Vn.tb, Vm.tb" , "op": "01001110|sz|1|Vm|01000|0|Vn|Vx" , "ta.tb": "16B.8H 8H.4S 4S.2D"},
|
||
|
|
{"inst": "addp Dd, Vn.2D" , "op": "01011110|sz|11000|11011|10|Vn|Vd"},
|
||
|
|
{"inst": "addp Vd.t, Vn.t, Vm.t" , "op": "00001110|sz|1|Vm|10111|1|Vn|Vd" , "t": "8B 4H 2S"},
|
||
|
|
{"inst": "addp Vd.t, Vn.t, Vm.t" , "op": "01001110|sz|1|Vm|10111|1|Vn|Vd" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "addv Bd, Vn.8B" , "op": "00001110|00|11000|11011|10|Vn|Vd"},
|
||
|
|
{"inst": "addv Bd, Vn.16B" , "op": "01001110|00|11000|11011|10|Vn|Vd"},
|
||
|
|
{"inst": "addv Hd, Vn.4H" , "op": "00001110|01|11000|11011|10|Vn|Vd"},
|
||
|
|
{"inst": "addv Hd, Vn.8H" , "op": "01001110|01|11000|11011|10|Vn|Vd"},
|
||
|
|
{"inst": "addv Sd, Vn.4S" , "op": "01001110|10|11000|11011|10|Vn|Vd"},
|
||
|
|
{"inst": "and Vd.8B, Vn.8B, Vm.8B" , "op": "00001110|00|1|Vm|00011|1|Vn|Vd"},
|
||
|
|
{"inst": "and Vd.16B, Vn.16B, Vm.16B" , "op": "01001110|00|1|Vm|00011|1|Vn|Vd"},
|
||
|
|
{"inst": "bic Vd.8B, Vn.8B, Vm.8B" , "op": "00001110|01|1|Vm|00011|1|Vn|Vd"},
|
||
|
|
{"inst": "bic Vd.16B, Vn.16B, Vm.16B" , "op": "01001110|01|1|Vm|00011|1|Vn|Vd"},
|
||
|
|
{"inst": "bic Vd.t, #imm, {lsl #n}" , "op": "00101111|00000|abc:3|cmode:4|01|defgh:5|Vd" , "t": "4H 2S", "imm": "ASimdLogicalImm(sz, 1, imm, lsl)"},
|
||
|
|
{"inst": "bic Vd.t, #imm, {lsl #n}" , "op": "01101111|00000|abc:3|cmode:4|01|defgh:5|Vd" , "t": "8H 4S", "imm": "ASimdLogicalImm(sz, 1, imm, lsl)"},
|
||
|
|
{"inst": "bif Dx.8B, Vn.8B, Vm.8B" , "op": "00101111|11|1|Vm|00011|1|Vn|Vx"},
|
||
|
|
{"inst": "bif Vx.16B, Vn.16B, Vm.16B" , "op": "01101111|11|1|Vm|00011|1|Vn|Vx"},
|
||
|
|
{"inst": "bit Dx.8B, Vn.8B, Vm.8B" , "op": "00101111|10|1|Vm|00011|1|Vn|Vx"},
|
||
|
|
{"inst": "bit Vx.16B, Vn.16B, Vm.16B" , "op": "01101111|10|1|Vm|00011|1|Vn|Vx"},
|
||
|
|
{"inst": "bsl Dx.8B, Vn.8B, Vm.8B" , "op": "00101111|01|1|Vm|00011|1|Vn|Vx"},
|
||
|
|
{"inst": "bsl Vx.16B, Vn.16B, Vm.16B" , "op": "01101111|01|1|Vm|00011|1|Vn|Vx"},
|
||
|
|
{"inst": "cls Vd.t, Vn.t" , "op": "00001110|sz|10000|00100|10|Vn|Vd" , "t": "8B 4H 2S"},
|
||
|
|
{"inst": "cls Vd.t, Vn.t" , "op": "01001110|sz|10000|00100|10|Vn|Vd" , "t": "16B 8H 4S"},
|
||
|
|
{"inst": "clz Vd.t, Vn.t" , "op": "00101110|sz|10000|00100|10|Vn|Vd" , "t": "8B 4H 2S"},
|
||
|
|
{"inst": "clz Vd.t, Vn.t" , "op": "01101110|sz|10000|00100|10|Vn|Vd" , "t": "16B 8H 4S"},
|
||
|
|
{"inst": "cmeq Dd, Dn, Dm" , "op": "01111110|11|1|Vm|10001|1|Vn|Vd"},
|
||
|
|
{"inst": "cmeq Dd, Dn, #0" , "op": "01011110|11|10000|01001|10|Vn|Vd"},
|
||
|
|
{"inst": "cmeq Vd.t, Vn.t, Vm.t" , "op": "00101110|sz|1|Vm|10001|1|Vn|Vd" , "t": "8B 4H 2S"},
|
||
|
|
{"inst": "cmeq Vd.t, Vn.t, #0" , "op": "00101110|sz|10000|01001|10|Vn|Vd" , "t": "8B 4H 2S"},
|
||
|
|
{"inst": "cmeq Vd.t, Vn.t, Vm.t" , "op": "01101110|sz|1|Vm|10001|1|Vn|Vd" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "cmeq Vd.t, Vn.t, #0" , "op": "01101110|sz|10000|01001|10|Vn|Vd" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "cmge Dd, Dn, Dm" , "op": "01011110|11|1|Vm|00111|1|Vn|Vd"},
|
||
|
|
{"inst": "cmge Dd, Dn, #0" , "op": "01111110|11|10000|01000|10|Vn|Vd"},
|
||
|
|
{"inst": "cmge Vd.t, Vn.t, Vm.t" , "op": "00001110|sz|1|Vm|00111|1|Vn|Vd" , "t": "8B 4H 2S"},
|
||
|
|
{"inst": "cmge Vd.t, Vn.t, #0" , "op": "00101110|sz|10000|01000|10|Vn|Vd" , "t": "8B 4H 2S"},
|
||
|
|
{"inst": "cmge Vd.t, Vn.t, Vm.t" , "op": "01001110|sz|1|Vm|00111|1|Vn|Vd" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "cmge Vd.t, Vn.t, #0" , "op": "01101110|sz|10000|01000|10|Vn|Vd" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "cmgt Dd, Dn, Dm" , "op": "01011110|11|1|Vm|00110|1|Vn|Vd"},
|
||
|
|
{"inst": "cmgt Dd, Dn, #0" , "op": "01011110|11|10000|01000|10|Vn|Vd"},
|
||
|
|
{"inst": "cmgt Vd.t, Vn.t, Vm.t" , "op": "00001110|sz|1|Vm|00110|1|Vn|Vd" , "t": "8B 4H 2S"},
|
||
|
|
{"inst": "cmgt Vd.t, Vn.t, #0" , "op": "00001110|sz|10000|01000|10|Vn|Vd" , "t": "8B 4H 2S"},
|
||
|
|
{"inst": "cmgt Vd.t, Vn.t, Vm.t" , "op": "01001110|sz|1|Vm|00110|1|Vn|Vd" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "cmgt Vd.t, Vn.t, #0" , "op": "01001110|sz|10000|01000|10|Vn|Vd" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "cmhi Dd, Dn, Dm" , "op": "01111110|11|1|Vm|00110|1|Vn|Vd"},
|
||
|
|
{"inst": "cmhi Vd.t, Vn.t, Vm.t" , "op": "00101110|sz|1|Vm|00110|1|Vn|Vd" , "t": "8B 4H 2S"},
|
||
|
|
{"inst": "cmhi Vd.t, Vn.t, Vm.t" , "op": "01101110|sz|1|Vm|00110|1|Vn|Vd" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "cmhs Dd, Dn, Dm" , "op": "01111110|11|1|Vm|00111|1|Vn|Vd"},
|
||
|
|
{"inst": "cmhs Vd.t, Vn.t, Vm.t" , "op": "00101110|sz|1|Vm|00111|1|Vn|Vd" , "t": "8B 4H 2S"},
|
||
|
|
{"inst": "cmhs Vd.t, Vn.t, Vm.t" , "op": "01101110|sz|1|Vm|00111|1|Vn|Vd" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "cmle Dd, Dn, #0" , "op": "01111110|11|10000|01001|10|Vn|Vd"},
|
||
|
|
{"inst": "cmle Vd.t, Vn.t, #0" , "op": "00101110|sz|10000|01001|10|Vn|Vd" , "t": "8B 4H 2S"},
|
||
|
|
{"inst": "cmle Vd.t, Vn.t, #0" , "op": "01101110|sz|10000|01001|10|Vn|Vd" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "cmlt Dd, Dn, #0" , "op": "01011110|11|10000|01010|10|Vn|Vd"},
|
||
|
|
{"inst": "cmlt Vd.t, Vn.t, #0" , "op": "00001110|sz|10000|01010|10|Vn|Vd" , "t": "8B 4H 2S"},
|
||
|
|
{"inst": "cmlt Vd.t, Vn.t, #0" , "op": "01001110|sz|10000|01010|10|Vn|Vd" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "cmtst Dd, Dn, Dm" , "op": "01011110|11|1|Vm|10001|1|Vn|Vd"},
|
||
|
|
{"inst": "cmtst Vd.t, Vn.t, Vm.t" , "op": "00001110|sz|1|Vm|10001|1|Vn|Vd" , "t": "8B 4H 2S"},
|
||
|
|
{"inst": "cmtst Vd.t, Vn.t, Vm.t" , "op": "01001110|sz|1|Vm|10001|1|Vn|Vd" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "cnt Vd.8B, Vn.8B" , "op": "00001110|sz|10000|00101|10|Vn|Vd"},
|
||
|
|
{"inst": "cnt Vd.16B, Vn.16B" , "op": "01001110|sz|10000|00101|10|Vn|Vd"},
|
||
|
|
{"inst": "dup|mov Bd, Vn.B[#idx]" , "op": "01011110|00|0|idx:4| 1|00000|1|Vn|Vd"},
|
||
|
|
{"inst": "dup|mov Hd, Vn.H[#idx]" , "op": "01011110|00|0|idx:3| 10|00000|1|Vn|Vd"},
|
||
|
|
{"inst": "dup|mov Sd, Vn.S[#idx]" , "op": "01011110|00|0|idx:2| 100|00000|1|Vn|Vd"},
|
||
|
|
{"inst": "dup|mov Dd, Vn.D[#idx]" , "op": "01011110|00|0|idx:1| 1000|00000|1|Vn|Vd"},
|
||
|
|
{"inst": "dup Vd.8B, Wn" , "op": "00001110|00|0|00001|00001|1|Rn|Vd"},
|
||
|
|
{"inst": "dup Vd.4H, Wn" , "op": "00001110|00|0|00010|00001|1|Rn|Vd"},
|
||
|
|
{"inst": "dup Vd.2S, Wn" , "op": "00001110|00|0|11011|00001|1|Rn|Vd"},
|
||
|
|
{"inst": "dup Vd.16B, Wn" , "op": "01001110|00|0|00001|00001|1|Rn|Vd"},
|
||
|
|
{"inst": "dup Vd.8H, Wn" , "op": "01001110|00|0|00010|00001|1|Rn|Vd"},
|
||
|
|
{"inst": "dup Vd.4S, Wn" , "op": "01001110|00|0|11011|00001|1|Rn|Vd"},
|
||
|
|
{"inst": "dup Vd.2D, Xn" , "op": "01001110|00|0|11011|00001|1|Rn|Vd"},
|
||
|
|
{"inst": "dup Vd.8B, Vn.B[#idx]" , "op": "00001110|00|0|idx:4| 1|00000|1|Vn|Vd"},
|
||
|
|
{"inst": "dup Vd.4H, Vn.H[#idx]" , "op": "00001110|00|0|idx:3| 10|00000|1|Vn|Vd"},
|
||
|
|
{"inst": "dup Vd.2S, Vn.S[#idx]" , "op": "00001110|00|0|idx:2| 100|00000|1|Vn|Vd"},
|
||
|
|
{"inst": "dup Vd.16B, Vn.B[#idx]" , "op": "01001110|00|0|idx:4| 1|00000|1|Vn|Vd"},
|
||
|
|
{"inst": "dup Vd.8H, Vn.H[#idx]" , "op": "01001110|00|0|idx:3| 10|00000|1|Vn|Vd"},
|
||
|
|
{"inst": "dup Vd.4S, Vn.S[#idx]" , "op": "01001110|00|0|idx:2| 100|00000|1|Vn|Vd"},
|
||
|
|
{"inst": "dup Vd.2D, Vn.D[#idx]" , "op": "01001110|00|0|idx:1| 1000|00000|1|Vn|Vd"},
|
||
|
|
{"inst": "eor Vd.8B, Vn.8B, Vm.8B" , "op": "00101110|00|1|Vm|00011|1|Vn|Vd"},
|
||
|
|
{"inst": "eor Vd.16B, Vn.16B, Vm.16B" , "op": "01101110|00|1|Vm|00011|1|Vn|Vd"},
|
||
|
|
{"inst": "ext Vd.8B, Vn.8B, Vm.8B, #idx" , "op": "00101110|00|0|Vm|00|idx:3|0|Vn|Vd"},
|
||
|
|
{"inst": "ext Vd.16B, Vn.16B, Vm.16B, #idx" , "op": "01101110|00|0|Vm|0|idx:4|0|Vn|Vd"},
|
||
|
|
{"inst": "fabd Sd, Sn, Sm" , "op": "01111110|10|1|Vm|11010|1|Vn|Vd"},
|
||
|
|
{"inst": "fabd Dd, Dn, Dm" , "op": "01111110|11|1|Vm|11010|1|Vn|Vd"},
|
||
|
|
{"inst": "fabd Vd.2S, Vn.2S, Vm.2S" , "op": "00101110|10|0|Vm|11010|1|Vn|Vd"},
|
||
|
|
{"inst": "fabd Vd.4S, Vn.4S, Vm.4S" , "op": "00101110|10|0|Vm|11010|1|Vn|Vd"},
|
||
|
|
{"inst": "fabd Vd.2D, Vn.2D, Vm.2D" , "op": "01101110|11|0|Vm|11010|1|Vn|Vd"},
|
||
|
|
{"inst": "fabs Sd, Sn" , "op": "00011110|00|10000|01100|00|Vn|Vd"},
|
||
|
|
{"inst": "fabs Dd, Dn" , "op": "00011110|01|10000|01100|00|Vn|Vd"},
|
||
|
|
{"inst": "fabs Vd.2S, Vn.2S" , "op": "00001110|10|10000|01111|10|Vn|Vd"},
|
||
|
|
{"inst": "fabs Vd.4S, Vn.4S" , "op": "01001110|10|10000|01111|10|Vn|Vd"},
|
||
|
|
{"inst": "fabs Vd.2D, Vn.2D" , "op": "01001110|11|10000|01111|10|Vn|Vd"},
|
||
|
|
{"inst": "facge Sd, Sn, Sm" , "op": "01111110|00|1|Vm|11101|1|Vn|Vd"},
|
||
|
|
{"inst": "facge Dd, Dn, Dm" , "op": "01111110|01|0|Vm|11101|1|Vn|Vd"},
|
||
|
|
{"inst": "facge Vd.2S, Vn.2S, Vm.2S" , "op": "00101110|00|1|Vm|11101|1|Vn|Vd"},
|
||
|
|
{"inst": "facge Vd.4S, Vn.4S, Vm.4S" , "op": "01101110|00|1|Vm|11101|1|Vn|Vd"},
|
||
|
|
{"inst": "facge Vd.2D, Vn.2D, Vm.2D" , "op": "01101110|01|1|Vm|11101|1|Vn|Vd"},
|
||
|
|
{"inst": "facgt Sd, Sn, Sm" , "op": "01111110|10|1|Vm|11101|1|Vn|Vd"},
|
||
|
|
{"inst": "facgt Dd, Dn, Dm" , "op": "01111110|11|0|Vm|11101|1|Vn|Vd"},
|
||
|
|
{"inst": "facgt Vd.2S, Vn.2S, Vm.2S" , "op": "00101110|10|1|Vm|11101|1|Vn|Vd"},
|
||
|
|
{"inst": "facgt Vd.4S, Vn.4S, Vm.4S" , "op": "01101110|10|1|Vm|11101|1|Vn|Vd"},
|
||
|
|
{"inst": "facgt Vd.2D, Vn.2D, Vm.2D" , "op": "01101110|11|1|Vm|11101|1|Vn|Vd"},
|
||
|
|
{"inst": "fadd Sd, Sn, Sm" , "op": "00011110|00|1|Vm|00101|0|Vn|Vd"},
|
||
|
|
{"inst": "fadd Dd, Dn, Dm" , "op": "00011110|01|1|Vm|00101|0|Vn|Vd"},
|
||
|
|
{"inst": "fadd Vd.2S, Vn.2S, Vm.2S" , "op": "00001110|00|1|Vm|11010|1|Vn|Vd"},
|
||
|
|
{"inst": "fadd Vd.4S, Vn.4S, Vm.4S" , "op": "01001110|00|1|Vm|11010|1|Vn|Vd"},
|
||
|
|
{"inst": "fadd Vd.2D, Vn.2D, Vm.2D" , "op": "01001110|01|1|Vm|11010|1|Vn|Vd"},
|
||
|
|
{"inst": "faddp Sd, Vn.2S" , "op": "01111110|00|11000|01101|10|Vn|Vd"},
|
||
|
|
{"inst": "faddp Dd, Vn.2D" , "op": "01111110|01|11000|01101|10|Vn|Vd"},
|
||
|
|
{"inst": "faddp Vd.2S, Vn.2S, Vm.2S" , "op": "00101110|00|1|Vm|11010|1|Vn|Vd"},
|
||
|
|
{"inst": "faddp Vd.4S, Vn.4S, Vm.4S" , "op": "01101110|00|1|Vm|11010|1|Vn|Vd"},
|
||
|
|
{"inst": "faddp Vd.2D, Vn.2D, Vm.2D" , "op": "01101110|01|1|Vm|11010|1|Vn|Vd"},
|
||
|
|
{"inst": "fccmp Sn, Sm, #nzcv, #cond" , "op": "00011110|00|1|Vm|cond|01|Vn|0|nzcv" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "fccmp Dn, Dm, #nzcv, #cond" , "op": "00011110|01|1|Vm|cond|01|Vn|0|nzcv" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "fccmpe Sn, Sm, #nzcv, #cond" , "op": "00011110|00|1|Vm|cond|01|Vn|1|nzcv" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "fccmpe Dn, Dm, #nzcv, #cond" , "op": "00011110|01|1|Vm|cond|01|Vn|1|nzcv" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "fcmeq Sd, Sn, Sm" , "op": "01011110|00|1|Vm|11100|1|Vn|Vd"},
|
||
|
|
{"inst": "fcmeq Sd, Sn, #0" , "op": "01011110|10|10000|01101|10|Vn|Vd"},
|
||
|
|
{"inst": "fcmeq Dd, Dn, Dm" , "op": "01011110|01|1|Vm|11100|1|Vn|Vd"},
|
||
|
|
{"inst": "fcmeq Dd, Dn, #0" , "op": "01011110|11|10000|01101|10|Vn|Vd"},
|
||
|
|
{"inst": "fcmeq Vd.2S, Vn.2S, Vm.2S" , "op": "00001110|00|1|Vm|11100|1|Vn|Vd"},
|
||
|
|
{"inst": "fcmeq Vd.2S, Vn.2S, #0" , "op": "00001110|10|10000|01101|10|Vn|Vd"},
|
||
|
|
{"inst": "fcmeq Vd.4S, Vn.4S, Vm.4S" , "op": "01001110|00|1|Vm|11100|1|Vn|Vd"},
|
||
|
|
{"inst": "fcmeq Vd.4S, Vn.4S, #0" , "op": "01001110|10|10000|01101|10|Vn|Vd"},
|
||
|
|
{"inst": "fcmeq Vd.2D, Vn.2D, Vm.2D" , "op": "01001110|01|1|Vm|11100|1|Vn|Vd"},
|
||
|
|
{"inst": "fcmeq Vd.2D, Vn.2D, #0" , "op": "01001110|11|10000|01101|10|Vn|Vd"},
|
||
|
|
{"inst": "fcmge Sd, Sn, Sm" , "op": "01111110|00|1|Vm|11100|1|Vn|Vd"},
|
||
|
|
{"inst": "fcmge Sd, Sn, #0" , "op": "01111110|10|10000|01100|10|Vn|Vd"},
|
||
|
|
{"inst": "fcmge Dd, Dn, Dm" , "op": "01111110|01|1|Vm|11100|1|Vn|Vd"},
|
||
|
|
{"inst": "fcmge Dd, Dn, #0" , "op": "01111110|11|10000|01100|10|Vn|Vd"},
|
||
|
|
{"inst": "fcmge Vd.2S, Vn.2S, Vm.2S" , "op": "00101110|00|1|Vm|11100|1|Vn|Vd"},
|
||
|
|
{"inst": "fcmge Vd.2S, Vn.2S, #0" , "op": "00101110|10|10000|01100|10|Vn|Vd"},
|
||
|
|
{"inst": "fcmge Vd.4S, Vn.4S, Vm.4S" , "op": "01101110|00|1|Vm|11100|1|Vn|Vd"},
|
||
|
|
{"inst": "fcmge Vd.4S, Vn.4S, #0" , "op": "01101110|10|10000|01100|10|Vn|Vd"},
|
||
|
|
{"inst": "fcmge Vd.2D, Vn.2D, Vm.2D" , "op": "01101110|01|1|Vm|11100|1|Vn|Vd"},
|
||
|
|
{"inst": "fcmge Vd.2D, Vn.2D, #0" , "op": "01101110|11|10000|01100|10|Vn|Vd"},
|
||
|
|
{"inst": "fcmgt Sd, Sn, Sm" , "op": "01111110|10|1|Vm|11100|1|Vn|Vd"},
|
||
|
|
{"inst": "fcmgt Sd, Sn, #0" , "op": "01011110|10|10000|01100|10|Vn|Vd"},
|
||
|
|
{"inst": "fcmgt Dd, Dn, Dm" , "op": "01111110|11|1|Vm|11100|1|Vn|Vd"},
|
||
|
|
{"inst": "fcmgt Dd, Dn, #0" , "op": "01011110|11|10000|01100|10|Vn|Vd"},
|
||
|
|
{"inst": "fcmgt Vd.2S, Vn.2S, Vm.2S" , "op": "00101110|10|1|Vm|11100|1|Vn|Vd"},
|
||
|
|
{"inst": "fcmgt Vd.2S, Vn.2S, #0" , "op": "00001110|10|10000|01100|10|Vn|Vd"},
|
||
|
|
{"inst": "fcmgt Vd.4S, Vn.4S, Vm.4S" , "op": "01101110|10|1|Vm|11100|1|Vn|Vd"},
|
||
|
|
{"inst": "fcmgt Vd.4S, Vn.4S, #0" , "op": "01001110|10|10000|01100|10|Vn|Vd"},
|
||
|
|
{"inst": "fcmgt Vd.2D, Vn.2D, Vm.2D" , "op": "01101110|11|1|Vm|11100|1|Vn|Vd"},
|
||
|
|
{"inst": "fcmgt Vd.2D, Vn.2D, #0" , "op": "01001110|11|10000|01100|10|Vn|Vd"},
|
||
|
|
{"inst": "fcmle Sd, Sn, #0" , "op": "01111110|10|10000|01101|10|Vn|Vd"},
|
||
|
|
{"inst": "fcmle Dd, Dn, #0" , "op": "01111110|11|10000|01101|10|Vn|Vd"},
|
||
|
|
{"inst": "fcmle Vd.2S, Vn.2S, #0" , "op": "00101110|10|10000|01101|10|Vn|Vd"},
|
||
|
|
{"inst": "fcmle Vd.4S, Vn.4S, #0" , "op": "01101110|10|10000|01101|10|Vn|Vd"},
|
||
|
|
{"inst": "fcmle Vd.2D, Vn.2D, #0" , "op": "01101110|11|10000|01101|10|Vn|Vd"},
|
||
|
|
{"inst": "fcmlt Sd, Sn, #0" , "op": "01011110|10|10000|01110|10|Vn|Vd"},
|
||
|
|
{"inst": "fcmlt Dd, Dn, #0" , "op": "01011110|11|10000|01110|10|Vn|Vd"},
|
||
|
|
{"inst": "fcmlt Vd.2S, Vn.2S, #0" , "op": "00001110|10|10000|01110|10|Vn|Vd"},
|
||
|
|
{"inst": "fcmlt Vd.4S, Vn.4S, #0" , "op": "01001110|10|10000|01110|10|Vn|Vd"},
|
||
|
|
{"inst": "fcmlt Vd.2D, Vn.2D, #0" , "op": "01001110|11|10000|01110|10|Vn|Vd"},
|
||
|
|
{"inst": "fcmp Sn, Sm" , "op": "00011110|00|1|Vm|00100|0|Vn|00000" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "fcmp Sn, #0" , "op": "00011110|00|1|00000|00100|0|Vn|01000" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "fcmp Dn, Dm" , "op": "00011110|01|1|Vm|00100|0|Vn|00000" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "fcmp Dn, #0" , "op": "00011110|01|1|00000|00100|0|Vn|01000" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "fcmpe Sn, Sm" , "op": "00011110|00|1|Vm|00100|0|Vn|10000" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "fcmpe Sn, #0" , "op": "00011110|00|1|00000|00100|0|Vn|11000" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "fcmpe Dn, Dm" , "op": "00011110|01|1|Vm|00100|0|Vn|10000" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "fcmpe Dn, #0" , "op": "00011110|01|1|00000|00100|0|Vn|11000" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "fcsel Sd, Sn, Sm, #cond" , "op": "00011110|00|1|Vm|cond|11|Vn|Vd" , "io": "N=R Z=R C=R V=R"},
|
||
|
|
{"inst": "fcsel Dd, Dn, Dm, #cond" , "op": "00011110|01|1|Vm|cond|11|Vn|Vd" , "io": "N=R Z=R C=R V=R"},
|
||
|
|
{"inst": "fcvt Sd, Hn" , "op": "00011110|11|10001|00100|00|Vn|Vd"},
|
||
|
|
{"inst": "fcvt Dd, Hn" , "op": "00011110|11|10001|01100|00|Vn|Vd"},
|
||
|
|
{"inst": "fcvt Hd, Sn" , "op": "00011110|00|10001|11100|00|Vn|Vd"},
|
||
|
|
{"inst": "fcvt Dd, Sn" , "op": "00011110|00|10001|01100|00|Vn|Vd"},
|
||
|
|
{"inst": "fcvt Hd, Dn" , "op": "00011110|01|10001|11100|00|Vn|Vd"},
|
||
|
|
{"inst": "fcvt Sd, Dn" , "op": "00011110|01|10001|00100|00|Vn|Vd"},
|
||
|
|
{"inst": "fcvtas Wd, Sn" , "op": "00011110|00|10010|00000|00|Vn|Rd"},
|
||
|
|
{"inst": "fcvtas Xd, Sn" , "op": "10011110|00|10010|00000|00|Vn|Rd"},
|
||
|
|
{"inst": "fcvtas Wd, Dn" , "op": "00011110|01|10010|00000|00|Vn|Rd"},
|
||
|
|
{"inst": "fcvtas Xd, Dn" , "op": "10011110|01|10010|00000|00|Vn|Rd"},
|
||
|
|
{"inst": "fcvtas Sd, Sn" , "op": "01011110|00|10000|11100|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtas Dd, Dn" , "op": "01011110|01|10000|11100|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtas Vd.2S, Vn.2S" , "op": "00001110|00|10000|11100|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtas Vd.4S, Vn.4S" , "op": "01001110|00|10000|11100|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtas Vd.2D, Vn.2D" , "op": "01001110|01|10000|11100|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtau Wd, Sn" , "op": "00011110|00|10010|10000|00|Vn|Rd"},
|
||
|
|
{"inst": "fcvtau Xd, Sn" , "op": "10011110|00|10010|10000|00|Vn|Rd"},
|
||
|
|
{"inst": "fcvtau Wd, Dn" , "op": "00011110|01|10010|10000|00|Vn|Rd"},
|
||
|
|
{"inst": "fcvtau Xd, Dn" , "op": "10011110|01|10010|10000|00|Vn|Rd"},
|
||
|
|
{"inst": "fcvtau Sd, Sn" , "op": "01111110|00|10000|11100|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtau Dd, Dn" , "op": "01111110|01|10000|11100|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtau Vd.2S, Vn.2S" , "op": "00101110|00|10000|11100|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtau Vd.4S, Vn.4S" , "op": "01101110|00|10000|11100|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtau Vd.2D, Vn.2D" , "op": "01101110|01|10000|11100|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtl Vd.4S, Vn.4H" , "op": "00001110|00|10000|10111|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtl2 Vd.4S, Vn.8H" , "op": "01001110|00|10000|10111|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtl Vd.2D, Vn.2S" , "op": "00001110|01|10000|10111|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtl2 Vd.2D, Vn.4S" , "op": "01001110|01|10000|10111|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtms Wd, Sn" , "op": "00011110|00|11000|00000|00|Vn|Rd"},
|
||
|
|
{"inst": "fcvtms Xd, Sn" , "op": "10011110|00|11000|00000|00|Vn|Rd"},
|
||
|
|
{"inst": "fcvtms Wd, Dn" , "op": "00011110|01|11000|00000|00|Vn|Rd"},
|
||
|
|
{"inst": "fcvtms Xd, Dn" , "op": "10011110|01|11000|00000|00|Vn|Rd"},
|
||
|
|
{"inst": "fcvtms Sd, Sn" , "op": "01011110|00|10000|11011|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtms Dd, Dn" , "op": "01011110|01|10000|11011|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtms Vd.2S, Vn.2S" , "op": "00001110|00|10000|11011|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtms Vd.4S, Vn.4S" , "op": "01001110|00|10000|11011|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtms Vd.2D, Vn.2D" , "op": "01001110|01|10000|11011|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtmu Wd, Sn" , "op": "00011110|00|11000|10000|00|Vn|Rd"},
|
||
|
|
{"inst": "fcvtmu Xd, Sn" , "op": "10011110|00|11000|10000|00|Vn|Rd"},
|
||
|
|
{"inst": "fcvtmu Wd, Dn" , "op": "00011110|01|11000|10000|00|Vn|Rd"},
|
||
|
|
{"inst": "fcvtmu Xd, Dn" , "op": "10011110|01|11000|10000|00|Vn|Rd"},
|
||
|
|
{"inst": "fcvtmu Sd, Sn" , "op": "01111110|00|10000|11011|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtmu Dd, Dn" , "op": "01111110|01|10000|11011|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtmu Vd.2S, Vn.2S" , "op": "00101110|00|10000|11011|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtmu Vd.4S, Vn.4S" , "op": "01101110|00|10000|11011|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtmu Vd.2D, Vn.2D" , "op": "01101110|01|10000|11011|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtn Vd.4S, Vn.4H" , "op": "00001110|00|10000|10110|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtn2 Vd.4S, Vn.8H" , "op": "01001110|00|10000|10110|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtn Vd.2D, Vn.2S" , "op": "00001110|01|10000|10110|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtn2 Vd.2D, Vn.4S" , "op": "01001110|01|10000|10110|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtns Wd, Sn" , "op": "00011110|00|10000|00000|00|Vn|Rd"},
|
||
|
|
{"inst": "fcvtns Xd, Sn" , "op": "10011110|00|10000|00000|00|Vn|Rd"},
|
||
|
|
{"inst": "fcvtns Wd, Dn" , "op": "00011110|01|10000|00000|00|Vn|Rd"},
|
||
|
|
{"inst": "fcvtns Xd, Dn" , "op": "10011110|01|10000|00000|00|Vn|Rd"},
|
||
|
|
{"inst": "fcvtns Sd, Sn" , "op": "01011110|00|10000|11010|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtns Dd, Dn" , "op": "01011110|01|10000|11010|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtns Vd.2S, Vn.2S" , "op": "00001110|00|10000|11010|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtns Vd.4S, Vn.4S" , "op": "01001110|00|10000|11010|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtns Vd.2D, Vn.2D" , "op": "01001110|01|10000|11010|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtnu Wd, Sn" , "op": "00011110|00|10000|10000|00|Vn|Rd"},
|
||
|
|
{"inst": "fcvtnu Xd, Sn" , "op": "10011110|00|10000|10000|00|Vn|Rd"},
|
||
|
|
{"inst": "fcvtnu Wd, Dn" , "op": "00011110|01|10000|10000|00|Vn|Rd"},
|
||
|
|
{"inst": "fcvtnu Xd, Dn" , "op": "10011110|01|10000|10000|00|Vn|Rd"},
|
||
|
|
{"inst": "fcvtnu Sd, Sn" , "op": "01111110|00|10000|11010|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtnu Dd, Dn" , "op": "01111110|01|10000|11010|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtnu Vd.2S, Vn.2S" , "op": "00101110|00|10000|11010|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtnu Vd.4S, Vn.4S" , "op": "01101110|00|10000|11010|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtnu Vd.2D, Vn.2D" , "op": "01101110|01|10000|11010|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtps Wd, Sn" , "op": "00011110|00|10100|00000|00|Vn|Rd"},
|
||
|
|
{"inst": "fcvtps Xd, Sn" , "op": "10011110|00|10100|00000|00|Vn|Rd"},
|
||
|
|
{"inst": "fcvtps Wd, Dn" , "op": "00011110|01|10100|00000|00|Vn|Rd"},
|
||
|
|
{"inst": "fcvtps Xd, Dn" , "op": "10011110|01|10100|00000|00|Vn|Rd"},
|
||
|
|
{"inst": "fcvtps Sd, Sn" , "op": "01011110|10|10000|11010|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtps Dd, Dn" , "op": "01011110|11|10000|11010|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtps Vd.2S, Vn.2S" , "op": "00001110|10|10000|11010|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtps Vd.4S, Vn.4S" , "op": "01001110|10|10000|11010|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtps Vd.2D, Vn.2D" , "op": "01001110|11|10000|11010|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtpu Wd, Sn" , "op": "00011110|00|10100|10000|00|Vn|Rd"},
|
||
|
|
{"inst": "fcvtpu Xd, Sn" , "op": "10011110|00|10100|10000|00|Vn|Rd"},
|
||
|
|
{"inst": "fcvtpu Wd, Dn" , "op": "00011110|01|10100|10000|00|Vn|Rd"},
|
||
|
|
{"inst": "fcvtpu Xd, Dn" , "op": "10011110|01|10100|10000|00|Vn|Rd"},
|
||
|
|
{"inst": "fcvtpu Sd, Sn" , "op": "01111110|10|10000|11010|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtpu Dd, Dn" , "op": "01111110|11|10000|11010|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtpu Vd.2S, Vn.2S" , "op": "00101110|10|10000|11010|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtpu Vd.4S, Vn.4S" , "op": "01101110|10|10000|11010|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtpu Vd.2D, Vn.2D" , "op": "01101110|11|10000|11010|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtx Sd, Dn" , "op": "01111110|01|10000|10110|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtx Vd.4S, Vn.4H" , "op": "00101110|00|10000|10110|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtx2 Vd.4S, Vn.8H" , "op": "01101110|00|10000|10110|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtx Vd.2D, Vn.2S" , "op": "00101110|01|10000|10110|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtx2 Vd.2D, Vn.4S" , "op": "01101110|01|10000|10110|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtzs Wd, Sn" , "op": "00011110|00|11100|00000|00|Vn|Rd"},
|
||
|
|
{"inst": "fcvtzs Xd, Sn" , "op": "10011110|00|11100|00000|00|Vn|Rd"},
|
||
|
|
{"inst": "fcvtzs Wd, Dn" , "op": "00011110|01|11100|00000|00|Vn|Rd"},
|
||
|
|
{"inst": "fcvtzs Xd, Dn" , "op": "10011110|01|11100|00000|00|Vn|Rd"},
|
||
|
|
{"inst": "fcvtzs Sd, Sn" , "op": "01011110|10|10000|11011|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtzs Dd, Dn" , "op": "01011110|11|10000|11011|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtzs Vd.2S, Vn.2S" , "op": "00001110|10|10000|11011|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtzs Vd.4S, Vn.4S" , "op": "01001110|10|10000|11011|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtzs Vd.2D, Vn.2D" , "op": "01001110|11|10000|11011|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtzs Wd, Sn, #fbits" , "op": "00011110|00|011000|scale:6|Vn|Vd" , "imm": "ASimdFBitsScaleImm(fbits, 32)"},
|
||
|
|
{"inst": "fcvtzs Xd, Sn, #fbits" , "op": "10011110|00|011000|scale:6|Vn|Vd" , "imm": "ASimdFBitsScaleImm(fbits, 64)"},
|
||
|
|
{"inst": "fcvtzs Wd, Dn, #fbits" , "op": "00011110|01|011000|scale:6|Vn|Vd" , "imm": "ASimdFBitsScaleImm(fbits, 32)"},
|
||
|
|
{"inst": "fcvtzs Xd, Dn, #fbits" , "op": "10011110|01|011000|scale:6|Vn|Vd" , "imm": "ASimdFBitsScaleImm(fbits, 64)"},
|
||
|
|
{"inst": "fcvtzs Sd, Sn, #fbits" , "op": "01011111|0|immh:4|immb:3|11111|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 32)"},
|
||
|
|
{"inst": "fcvtzs Dd, Dn, #fbits" , "op": "01011111|0|immh:4|immb:3|11111|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 64)"},
|
||
|
|
{"inst": "fcvtzs Vd.2S, Vn.2S, #fbits" , "op": "00001111|0|immh:4|immb:3|11111|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 32)"},
|
||
|
|
{"inst": "fcvtzs Vd.4S, Vn.4S, #fbits" , "op": "01001111|0|immh:4|immb:3|11111|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 32)"},
|
||
|
|
{"inst": "fcvtzs Vd.2D, Vn.2D, #fbits" , "op": "01001111|0|immh:4|immb:3|11111|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 64)"},
|
||
|
|
{"inst": "fcvtzu Wd, Sn" , "op": "00011110|00|11100|10000|00|Vn|Rd"},
|
||
|
|
{"inst": "fcvtzu Xd, Sn" , "op": "10011110|00|11100|10000|00|Vn|Rd"},
|
||
|
|
{"inst": "fcvtzu Wd, Dn" , "op": "00011110|01|11100|10000|00|Vn|Rd"},
|
||
|
|
{"inst": "fcvtzu Xd, Dn" , "op": "10011110|01|11100|10000|00|Vn|Rd"},
|
||
|
|
{"inst": "fcvtzu Sd, Sn" , "op": "01111110|10|10000|11011|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtzu Dd, Dn" , "op": "01111110|11|10000|11011|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtzu Vd.2S, Vn.2S" , "op": "00101110|10|10000|11011|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtzu Vd.4S, Vn.4S" , "op": "01101110|10|10000|11011|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtzu Vd.2D, Vn.2D" , "op": "01101110|11|10000|11011|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtzu Wd, Sn, #fbits" , "op": "00011110|00|011001|scale:6|Vn|Vd" , "imm": "ASimdFBitsScaleImm(fbits, 32)"},
|
||
|
|
{"inst": "fcvtzu Xd, Sn, #fbits" , "op": "10011110|00|011001|scale:6|Vn|Vd" , "imm": "ASimdFBitsScaleImm(fbits, 64)"},
|
||
|
|
{"inst": "fcvtzu Wd, Dn, #fbits" , "op": "00011110|01|011001|scale:6|Vn|Vd" , "imm": "ASimdFBitsScaleImm(fbits, 32)"},
|
||
|
|
{"inst": "fcvtzu Xd, Dn, #fbits" , "op": "10011110|01|011001|scale:6|Vn|Vd" , "imm": "ASimdFBitsScaleImm(fbits, 64)"},
|
||
|
|
{"inst": "fcvtzu Sd, Sn, #fbits" , "op": "01111111|0|immh:4|immb:3|11111|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 32)"},
|
||
|
|
{"inst": "fcvtzu Dd, Dn, #fbits" , "op": "01111111|0|immh:4|immb:3|11111|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 64)"},
|
||
|
|
{"inst": "fcvtzu Vd.2S, Vn.2S, #fbits" , "op": "00101111|0|immh:4|immb:3|11111|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 32)"},
|
||
|
|
{"inst": "fcvtzu Vd.4S, Vn.4S, #fbits" , "op": "01101111|0|immh:4|immb:3|11111|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 32)"},
|
||
|
|
{"inst": "fcvtzu Vd.2D, Vn.2D, #fbits" , "op": "01101111|0|immh:4|immb:3|11111|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 64)"},
|
||
|
|
{"inst": "fdiv Sd, Sn, Sm" , "op": "00011110|00|1|Vm|00011|0|Vn|Vd"},
|
||
|
|
{"inst": "fdiv Dd, Dn, Dm" , "op": "00011110|01|1|Vm|00011|0|Vn|Vd"},
|
||
|
|
{"inst": "fdiv Vd.2S, Vn.2S, Vm.2S" , "op": "00101110|00|1|Vm|11111|1|Vn|Vd"},
|
||
|
|
{"inst": "fdiv Vd.4S, Vn.4S, Vm.4S" , "op": "01101110|00|1|Vm|11111|1|Vn|Vd"},
|
||
|
|
{"inst": "fdiv Vd.2D, Vn.2D, Vm.2D" , "op": "01101110|01|1|Vm|11111|1|Vn|Vd"},
|
||
|
|
{"inst": "fmadd Sd, Sn, Sm, Sa" , "op": "00011111|00|0|Vm|0|Va|Vn|Vd"},
|
||
|
|
{"inst": "fmadd Dd, Dn, Dm, Da" , "op": "00011111|01|0|Vm|0|Va|Vn|Vd"},
|
||
|
|
{"inst": "fmax Sd, Sn, Sm" , "op": "00011110|00|1|Vm|01001|0|Vn|Vd"},
|
||
|
|
{"inst": "fmax Dd, Dn, Dm" , "op": "00011110|01|1|Vm|01001|0|Vn|Vd"},
|
||
|
|
{"inst": "fmax Vd.2S, Vn.2S, Vm.2S" , "op": "00001110|00|1|Vm|11110|1|Vn|Vd"},
|
||
|
|
{"inst": "fmax Vd.4S, Vn.4S, Vm.4S" , "op": "01001110|00|1|Vm|11110|1|Vn|Vd"},
|
||
|
|
{"inst": "fmax Vd.2D, Vn.2D, Vm.2D" , "op": "01001110|01|1|Vm|11110|1|Vn|Vd"},
|
||
|
|
{"inst": "fmaxnm Sd, Sn, Sm" , "op": "00011110|00|1|Vm|01101|0|Vn|Vd"},
|
||
|
|
{"inst": "fmaxnm Dd, Dn, Dm" , "op": "00011110|01|1|Vm|01101|0|Vn|Vd"},
|
||
|
|
{"inst": "fmaxnm Vd.2S, Vn.2S, Vm.2S" , "op": "00001110|00|1|Vm|11000|1|Vn|Vd"},
|
||
|
|
{"inst": "fmaxnm Vd.2D, Vn.2D, Vm.2D" , "op": "01001110|01|1|Vm|11000|1|Vn|Vd"},
|
||
|
|
{"inst": "fmaxnm Vd.4S, Vn.4S, Vm.4S" , "op": "01001110|00|1|Vm|11000|1|Vn|Vd"},
|
||
|
|
{"inst": "fmaxnmp Sd, Vn.2S" , "op": "01111110|00|11000|01100|10|Vn|Vd"},
|
||
|
|
{"inst": "fmaxnmp Dd, Vn.2D" , "op": "01111110|01|11000|01100|10|Vn|Vd"},
|
||
|
|
{"inst": "fmaxnmp Vd.2S, Vn.2S, Vm.2S" , "op": "00101110|00|1|Vm|11000|1|Vn|Vd"},
|
||
|
|
{"inst": "fmaxnmp Vd.4S, Vn.4S, Vm.4S" , "op": "01101110|00|1|Vm|11000|1|Vn|Vd"},
|
||
|
|
{"inst": "fmaxnmp Vd.2D, Vn.2D, Vm.2D" , "op": "01101110|01|1|Vm|11000|1|Vn|Vd"},
|
||
|
|
{"inst": "fmaxnmv Sd, Vn.4S" , "op": "01101110|00|11000|01100|10|Vn|Vd"},
|
||
|
|
{"inst": "fmaxp Sd, Vn.2S" , "op": "01111110|00|11000|01111|10|Vn|Vd"},
|
||
|
|
{"inst": "fmaxp Dd, Vn.2D" , "op": "01111110|01|11000|01111|10|Vn|Vd"},
|
||
|
|
{"inst": "fmaxp Vd.2S, Vn.2S, Vm.2S" , "op": "00101110|00|1|Vm|11110|1|Vn|Vd"},
|
||
|
|
{"inst": "fmaxp Vd.4S, Vn.4S, Vm.4S" , "op": "01101110|00|1|Vm|11110|1|Vn|Vd"},
|
||
|
|
{"inst": "fmaxp Vd.2D, Vn.2D, Vm.2D" , "op": "01101110|01|1|Vm|11110|1|Vn|Vd"},
|
||
|
|
{"inst": "fmaxv Sd, Vn.4S" , "op": "01101110|00|11000|01111|10|Vn|Vd"},
|
||
|
|
{"inst": "fmin Sd, Sn, Sm" , "op": "00011110|00|1|Vm|01011|0|Vn|Vd"},
|
||
|
|
{"inst": "fmin Dd, Dn, Dm" , "op": "00011110|01|1|Vm|01011|0|Vn|Vd"},
|
||
|
|
{"inst": "fmin Vd.2S, Vn.2S, Vm.2S" , "op": "00001110|10|1|Vm|11110|1|Vn|Vd"},
|
||
|
|
{"inst": "fmin Vd.4S, Vn.4S, Vm.4S" , "op": "01001110|10|1|Vm|11110|1|Vn|Vd"},
|
||
|
|
{"inst": "fmin Vd.2D, Vn.2D, Vm.2D" , "op": "01001110|11|1|Vm|11110|1|Vn|Vd"},
|
||
|
|
{"inst": "fminnm Sd, Sn, Sm" , "op": "00011110|00|1|Vm|01111|0|Vn|Vd"},
|
||
|
|
{"inst": "fminnm Dd, Dn, Dm" , "op": "00011110|01|1|Vm|01111|0|Vn|Vd"},
|
||
|
|
{"inst": "fminnm Vd.2S, Vn.2S, Vm.2S" , "op": "00001110|10|1|Vm|11000|1|Vn|Vd"},
|
||
|
|
{"inst": "fminnm Vd.2D, Vn.2D, Vm.2D" , "op": "01001110|11|1|Vm|11000|1|Vn|Vd"},
|
||
|
|
{"inst": "fminnm Vd.4S, Vn.4S, Vm.4S" , "op": "01001110|10|1|Vm|11000|1|Vn|Vd"},
|
||
|
|
{"inst": "fminnmp Sd, Vn.2S" , "op": "01111110|10|11000|01100|10|Vn|Vd"},
|
||
|
|
{"inst": "fminnmp Dd, Vn.2D" , "op": "01111110|11|11000|01100|10|Vn|Vd"},
|
||
|
|
{"inst": "fminnmp Vd.2S, Vn.2S, Vm.2S" , "op": "00101110|10|1|Vm|11000|1|Vn|Vd"},
|
||
|
|
{"inst": "fminnmp Vd.4S, Vn.4S, Vm.4S" , "op": "01101110|10|1|Vm|11000|1|Vn|Vd"},
|
||
|
|
{"inst": "fminnmp Vd.2D, Vn.2D, Vm.2D" , "op": "01101110|11|1|Vm|11000|1|Vn|Vd"},
|
||
|
|
{"inst": "fminnmv Sd, Vn.4S" , "op": "01101110|10|11000|01100|10|Vn|Vd"},
|
||
|
|
{"inst": "fminp Sd, Vn.2S" , "op": "01111110|10|11000|01111|10|Vn|Vd"},
|
||
|
|
{"inst": "fminp Dd, Vn.2D" , "op": "01111110|11|11000|01111|10|Vn|Vd"},
|
||
|
|
{"inst": "fminp Vd.2S, Vn.2S, Vm.2S" , "op": "00101110|10|1|Vm|11110|1|Vn|Vd"},
|
||
|
|
{"inst": "fminp Vd.4S, Vn.4S, Vm.4S" , "op": "01101110|10|1|Vm|11110|1|Vn|Vd"},
|
||
|
|
{"inst": "fminp Vd.2D, Vn.2D, Vm.2D" , "op": "01101110|11|1|Vm|11110|1|Vn|Vd"},
|
||
|
|
{"inst": "fminv Sd, Vn.4S" , "op": "01101110|10|11000|01111|10|Vn|Vd"},
|
||
|
|
{"inst": "fmla Sx, Sn, Vm.S[#idx]" , "op": "01011111|10|idx[0]|Vm|0001|idx[1]|0|Vn|Vx"},
|
||
|
|
{"inst": "fmla Dx, Dn, Vm.D[#idx]" , "op": "01011111|11|0|Vm|0001|idx[0]|0|Vn|Vx"},
|
||
|
|
{"inst": "fmla Vx.2S, Vn.2S, Vm.2S" , "op": "00001110|00|1|Vm|11001|1|Vn|Vx"},
|
||
|
|
{"inst": "fmla Vx.4S, Vn.4S, Vm.4S" , "op": "01001110|00|1|Vm|11001|1|Vn|Vx"},
|
||
|
|
{"inst": "fmla Vx.2D, Vn.2D, Vm.2D" , "op": "01001110|01|1|Vm|11001|1|Vn|Vx"},
|
||
|
|
{"inst": "fmla Vx.2S, Vn.2S, Vm.S[#idx]" , "op": "00001111|10|idx[0]|Vm|0001|idx[1]|0|Vn|Vx"},
|
||
|
|
{"inst": "fmla Vx.4S, Vn.4S, Vm.S[#idx]" , "op": "01001111|11|idx[0]|Vm|0001|idx[1]|0|Vn|Vx"},
|
||
|
|
{"inst": "fmla Vx.2D, Vn.2D, Vm.D[#idx]" , "op": "01001111|11|0|Vm|0001|idx[0]|0|Vn|Vx"},
|
||
|
|
{"inst": "fmls Sx, Sn, Vm.S[#idx]" , "op": "01011111|10|idx[0]|Vm|0101|idx[1]|0|Vn|Vx"},
|
||
|
|
{"inst": "fmls Dx, Dn, Vm.D[#idx]" , "op": "01011111|11|0|Vm|0101|idx[0]|0|Vn|Vx"},
|
||
|
|
{"inst": "fmls Vx.2S, Vn.2S, Vm.2S" , "op": "00001110|10|1|Vm|11001|1|Vn|Vx"},
|
||
|
|
{"inst": "fmls Vx.4S, Vn.4S, Vm.4S" , "op": "01001110|10|1|Vm|11001|1|Vn|Vx"},
|
||
|
|
{"inst": "fmls Vx.2D, Vn.2D, Vm.2D" , "op": "01001110|11|1|Vm|11001|1|Vn|Vx"},
|
||
|
|
{"inst": "fmls Vx.2S, Vn.2S, Vm.S[#idx]" , "op": "00001111|10|idx[0]|Vm|0101|idx[1]|0|Vn|Vx"},
|
||
|
|
{"inst": "fmls Vx.4S, Vn.4S, Vm.S[#idx]" , "op": "01001111|11|idx[0]|Vm|0101|idx[1]|0|Vn|Vx"},
|
||
|
|
{"inst": "fmls Vx.2D, Vn.2D, Vm.D[#idx]" , "op": "01001111|11|0|Vm|0101|idx[0]|0|Vn|Vx"},
|
||
|
|
{"inst": "fmov Wd, Sn" , "op": "00011110|00|10011|00000|00|Vn|Rd"},
|
||
|
|
{"inst": "fmov Xd, Dn" , "op": "10011110|01|10011|00000|00|Vn|Rd"},
|
||
|
|
{"inst": "fmov Xd, Vn.D[#1]" , "op": "10011110|10|10111|00000|00|Vn|Rd"},
|
||
|
|
{"inst": "fmov Sd, Wn" , "op": "00011110|00|10011|10000|00|Rn|Vd"},
|
||
|
|
{"inst": "fmov Sd, Sn" , "op": "00011110|00|10000|00100|00|Vn|Vd"},
|
||
|
|
{"inst": "fmov Sd, #fimm" , "op": "00011110|00|1|imm:8|100|00000|Vd" , "imm": "ASimdFMovImm(fimm)"},
|
||
|
|
{"inst": "fmov Dd, Xn" , "op": "10011110|01|10011|10000|00|Rn|Vd"},
|
||
|
|
{"inst": "fmov Dd, Dn" , "op": "00011110|01|10000|00100|00|Vn|Vd"},
|
||
|
|
{"inst": "fmov Dd, #fimm" , "op": "00011110|01|1|imm:8|100|00000|Vd" , "imm": "ASimdFMovImm(fimm)"},
|
||
|
|
{"inst": "fmov Vd.D[#1], Xn" , "op": "10011110|10|10111|10000|00|Rn|Vd"},
|
||
|
|
{"inst": "fmov Vd.2S, #fimm" , "op": "00001111|00|000|abc:3|111101|defgh:5|Vd" , "imm": "ASimdFMovImm(fimm)"},
|
||
|
|
{"inst": "fmov Vd.4S, #fimm" , "op": "01001111|00|000|abc:3|111101|defgh:5|Vd" , "imm": "ASimdFMovImm(fimm)"},
|
||
|
|
{"inst": "fmov Vd.2D, #fimm" , "op": "01101111|00|000|abc:3|111101|defgh:5|Vd" , "imm": "ASimdFMovImm(fimm)"},
|
||
|
|
{"inst": "fmsub Sd, Sn, Sm, Sa" , "op": "00011111|00|0|Vm|1|Va|Vn|Vd"},
|
||
|
|
{"inst": "fmsub Dd, Dn, Dm, Da" , "op": "00011111|01|0|Vm|1|Va|Vn|Vd"},
|
||
|
|
{"inst": "fmul Sd, Sn, Sm" , "op": "00011110|00|1|Vm|00001|0|Vn|Vd"},
|
||
|
|
{"inst": "fmul Dd, Dn, Dm" , "op": "00011110|01|1|Vm|00001|0|Vn|Vd"},
|
||
|
|
{"inst": "fmul Sd, Sn, Vm.S[#idx]" , "op": "01011111|10|idx[0]|Vm|1001|idx[1]|0|Vn|Vd"},
|
||
|
|
{"inst": "fmul Dd, Dn, Vm.D[#idx]" , "op": "01011111|11|0|Vm|1001|idx[0]|0|Vn|Vd"},
|
||
|
|
{"inst": "fmul Vd.2S, Vn.2S, Vm.2S" , "op": "00101110|00|1|Vm|11011|1|Vn|Vd"},
|
||
|
|
{"inst": "fmul Vd.4S, Vn.4S, Vm.4S" , "op": "01101110|00|1|Vm|11011|1|Vn|Vd"},
|
||
|
|
{"inst": "fmul Vd.2D, Vn.2D, Vm.2D" , "op": "01101110|01|1|Vm|11011|1|Vn|Vd"},
|
||
|
|
{"inst": "fmul Vd.2S, Vn.2S, Vm.S[#idx]" , "op": "00001111|10|idx[0]|Vm|1001|idx[1]|0|Vn|Vd"},
|
||
|
|
{"inst": "fmul Vd.4S, Vn.4S, Vm.S[#idx]" , "op": "01001111|11|idx[0]|Vm|1001|idx[1]|0|Vn|Vd"},
|
||
|
|
{"inst": "fmul Vd.2D, Vn.2D, Vm.D[#idx]" , "op": "01001111|11|0|Vm|1001|idx[0]|0|Vn|Vd"},
|
||
|
|
{"inst": "fmulx Sd, Sn, Sm" , "op": "01011110|00|1|Vm|11011|1|Vn|Vd"},
|
||
|
|
{"inst": "fmulx Dd, Dn, Dm" , "op": "01011110|01|1|Vm|11011|1|Vn|Vd"},
|
||
|
|
{"inst": "fmulx Sd, Sn, Vm.S[#idx]" , "op": "01111111|10|idx[0]|Vm|1001|idx[1]|0|Vn|Vd"},
|
||
|
|
{"inst": "fmulx Dd, Dn, Vm.D[#idx]" , "op": "01111111|11|0|Vm|1001|idx:1|0|Vn|Vd"},
|
||
|
|
{"inst": "fmulx Vd.2S, Vn.2S, Vm.2S" , "op": "00001110|00|1|Vm|11011|1|Vn|Vd"},
|
||
|
|
{"inst": "fmulx Vd.4S, Vn.4S, Vm.4S" , "op": "01001110|00|1|Vm|11011|1|Vn|Vd"},
|
||
|
|
{"inst": "fmulx Vd.2D, Vn.2D, Vm.2D" , "op": "01001110|01|1|Vm|11011|1|Vn|Vd"},
|
||
|
|
{"inst": "fmulx Vd.2S, Vn.2S, Vm.S[#idx]" , "op": "00101111|10|idx[0]|Vm|1001|idx[1]|0|Vn|Vd"},
|
||
|
|
{"inst": "fmulx Vd.4S, Vn.4S, Vm.S[#idx]" , "op": "01101111|10|idx[0]|Vm|1001|idx[1]|0|Vn|Vd"},
|
||
|
|
{"inst": "fmulx Vd.2D, Vn.2D, Vm.D[#idx]" , "op": "01101111|11|0|Vm|1001|idx:1|0|Vn|Vd"},
|
||
|
|
{"inst": "fneg Sd, Sn" , "op": "00011110|00|10000|10100|00|Vn|Vd"},
|
||
|
|
{"inst": "fneg Dd, Dn" , "op": "00011110|01|10000|10100|00|Vn|Vd"},
|
||
|
|
{"inst": "fneg Vd.2S, Vn.2S" , "op": "00101110|10|10000|01111|10|Vn|Vd"},
|
||
|
|
{"inst": "fneg Vd.4S, Vn.4S" , "op": "01101110|10|10000|01111|10|Vn|Vd"},
|
||
|
|
{"inst": "fneg Vd.2D, Vn.2D" , "op": "01101110|11|10000|01111|10|Vn|Vd"},
|
||
|
|
{"inst": "fnmadd Sd, Sn, Sm, Sa" , "op": "00011111|00|1|Vm|0|Va|Vn|Vd"},
|
||
|
|
{"inst": "fnmadd Dd, Dn, Dm, Da" , "op": "00011111|01|1|Vm|0|Va|Vn|Vd"},
|
||
|
|
{"inst": "fnmsub Sd, Sn, Sm, Sa" , "op": "00011111|00|1|Vm|1|Va|Vn|Vd"},
|
||
|
|
{"inst": "fnmsub Dd, Dn, Dm, Da" , "op": "00011111|01|1|Vm|1|Va|Vn|Vd"},
|
||
|
|
{"inst": "fnmul Sd, Sn, Sm" , "op": "00011110|00|1|Vm|10001|0|Vn|Vd"},
|
||
|
|
{"inst": "fnmul Dd, Dn, Dm" , "op": "00011110|01|1|Vm|10001|0|Vn|Vd"},
|
||
|
|
{"inst": "frecpe Sd, Sn" , "op": "01011110|10|10000|11101|10|Vn|Vd"},
|
||
|
|
{"inst": "frecpe Dd, Dn" , "op": "01011110|11|10000|11101|10|Vn|Vd"},
|
||
|
|
{"inst": "frecpe Vd.2S, Vn.2S" , "op": "00001110|10|10000|11101|10|Vn|Vd"},
|
||
|
|
{"inst": "frecpe Vd.4S, Vn.4S" , "op": "01001110|10|10000|11101|10|Vn|Vd"},
|
||
|
|
{"inst": "frecpe Vd.2D, Vn.2D" , "op": "01001110|11|10000|11101|10|Vn|Vd"},
|
||
|
|
{"inst": "frecps Sd, Sn, Sm" , "op": "01011110|00|1|Vm|11111|1|Vn|Vd"},
|
||
|
|
{"inst": "frecps Dd, Dn, Dm" , "op": "01011110|01|1|Vm|11111|1|Vn|Vd"},
|
||
|
|
{"inst": "frecps Vd.2S, Vn.2S, Vm.2S" , "op": "00001110|00|1|Vm|11111|1|Vn|Vd"},
|
||
|
|
{"inst": "frecps Vd.4S, Vn.4S, Vm.4S" , "op": "01001110|00|1|Vm|11111|1|Vn|Vd"},
|
||
|
|
{"inst": "frecps Vd.2D, Vn.2D, Vm.2D" , "op": "01001110|01|1|Vm|11111|1|Vn|Vd"},
|
||
|
|
{"inst": "frecpx Sd, Sn, Sm" , "op": "01011110|10|10000|11111|10|Vn|Vd"},
|
||
|
|
{"inst": "frecpx Dd, Dn, Dm" , "op": "01011110|11|10000|11111|10|Vn|Vd"},
|
||
|
|
{"inst": "frinta Sd, Sn" , "op": "00011110|00|10011|00100|00|Vn|Vd"},
|
||
|
|
{"inst": "frinta Dd, Dn" , "op": "00011110|01|10011|00100|00|Vn|Vd"},
|
||
|
|
{"inst": "frinta Vd.2S, Vn.2S" , "op": "00101110|00|10000|11000|10|Vn|Vd"},
|
||
|
|
{"inst": "frinta Vd.4S, Vn.4S" , "op": "01101110|00|10000|11000|10|Vn|Vd"},
|
||
|
|
{"inst": "frinta Vd.2D, Vn.2D" , "op": "01101110|01|10000|11000|10|Vn|Vd"},
|
||
|
|
{"inst": "frinti Sd, Sn" , "op": "00011110|00|10011|11100|00|Vn|Vd"},
|
||
|
|
{"inst": "frinti Dd, Dn" , "op": "00011110|01|10011|11100|00|Vn|Vd"},
|
||
|
|
{"inst": "frinti Vd.2S, Vn.2S" , "op": "00101110|10|10000|11001|10|Vn|Vd"},
|
||
|
|
{"inst": "frinti Vd.4S, Vn.4S" , "op": "01101110|10|10000|11001|10|Vn|Vd"},
|
||
|
|
{"inst": "frinti Vd.2D, Vn.2D" , "op": "01101110|11|10000|11001|10|Vn|Vd"},
|
||
|
|
{"inst": "frintm Sd, Sn" , "op": "00011110|00|10010|10100|00|Vn|Vd"},
|
||
|
|
{"inst": "frintm Dd, Dn" , "op": "00011110|01|10010|10100|00|Vn|Vd"},
|
||
|
|
{"inst": "frintm Vd.2S, Vn.2S" , "op": "00001110|00|10000|11001|10|Vn|Vd"},
|
||
|
|
{"inst": "frintm Vd.4S, Vn.4S" , "op": "01001110|00|10000|11001|10|Vn|Vd"},
|
||
|
|
{"inst": "frintm Vd.2D, Vn.2D" , "op": "01001110|01|10000|11001|10|Vn|Vd"},
|
||
|
|
{"inst": "frintn Sd, Sn" , "op": "00011110|00|10010|00100|00|Vn|Vd"},
|
||
|
|
{"inst": "frintn Dd, Dn" , "op": "00011110|01|10010|00100|00|Vn|Vd"},
|
||
|
|
{"inst": "frintn Vd.2S, Vn.2S" , "op": "00001110|00|10000|11000|10|Vn|Vd"},
|
||
|
|
{"inst": "frintn Vd.4S, Vn.4S" , "op": "01001110|00|10000|11000|10|Vn|Vd"},
|
||
|
|
{"inst": "frintn Vd.2D, Vn.2D" , "op": "01001110|01|10000|11000|10|Vn|Vd"},
|
||
|
|
{"inst": "frintp Sd, Sn" , "op": "00011110|00|10010|01100|00|Vn|Vd"},
|
||
|
|
{"inst": "frintp Dd, Dn" , "op": "00011110|01|10010|01100|00|Vn|Vd"},
|
||
|
|
{"inst": "frintp Vd.2S, Vn.2S" , "op": "00001110|10|10000|11000|10|Vn|Vd"},
|
||
|
|
{"inst": "frintp Vd.4S, Vn.4S" , "op": "01001110|10|10000|11000|10|Vn|Vd"},
|
||
|
|
{"inst": "frintp Vd.2D, Vn.2D" , "op": "01001110|11|10000|11000|10|Vn|Vd"},
|
||
|
|
{"inst": "frintx Sd, Sn" , "op": "00011110|00|10011|10100|00|Vn|Vd"},
|
||
|
|
{"inst": "frintx Dd, Dn" , "op": "00011110|01|10011|10100|00|Vn|Vd"},
|
||
|
|
{"inst": "frintx Vd.2S, Vn.2S" , "op": "00101110|00|10000|11001|10|Vn|Vd"},
|
||
|
|
{"inst": "frintx Vd.4S, Vn.4S" , "op": "01101110|00|10000|11001|10|Vn|Vd"},
|
||
|
|
{"inst": "frintx Vd.2D, Vn.2D" , "op": "01101110|01|10000|11001|10|Vn|Vd"},
|
||
|
|
{"inst": "frintz Sd, Sn" , "op": "00011110|00|10010|11100|00|Vn|Vd"},
|
||
|
|
{"inst": "frintz Dd, Dn" , "op": "00011110|01|10010|11100|00|Vn|Vd"},
|
||
|
|
{"inst": "frintz Vd.2S, Vn.2S" , "op": "00001110|10|10000|11001|10|Vn|Vd"},
|
||
|
|
{"inst": "frintz Vd.4S, Vn.4S" , "op": "01001110|10|10000|11001|10|Vn|Vd"},
|
||
|
|
{"inst": "frintz Vd.2D, Vn.2D" , "op": "01001110|11|10000|11001|10|Vn|Vd"},
|
||
|
|
{"inst": "frsqrte Sd, Sn" , "op": "01111110|10|10000|11101|10|Vn|Vd"},
|
||
|
|
{"inst": "frsqrte Dd, Dn" , "op": "01111110|11|10000|11101|10|Vn|Vd"},
|
||
|
|
{"inst": "frsqrte Vd.2S, Vn.2S" , "op": "00101110|10|10000|11101|10|Vn|Vd"},
|
||
|
|
{"inst": "frsqrte Vd.4S, Vn.4S" , "op": "01101110|10|10000|11101|10|Vn|Vd"},
|
||
|
|
{"inst": "frsqrte Vd.2D, Vn.2D" , "op": "01101110|11|10000|11101|10|Vn|Vd"},
|
||
|
|
{"inst": "frsqrts Sd, Sn, Sm" , "op": "01011110|10|1|Vm|11111|1|Vn|Vd"},
|
||
|
|
{"inst": "frsqrts Dd, Dn, Dm" , "op": "01011110|11|1|Vm|11111|1|Vn|Vd"},
|
||
|
|
{"inst": "frsqrts Vd.2S, Vn.2S, Vm.2S" , "op": "00001110|10|1|Vm|11111|1|Vn|Vd"},
|
||
|
|
{"inst": "frsqrts Vd.4S, Vn.4S, Vm.4S" , "op": "01001110|10|1|Vm|11111|1|Vn|Vd"},
|
||
|
|
{"inst": "frsqrts Vd.2D, Vn.2D, Vm.2D" , "op": "01001110|11|1|Vm|11111|1|Vn|Vd"},
|
||
|
|
{"inst": "fsqrt Sd, Sn" , "op": "00011110|10|10000|11100|00|Vn|Vd"},
|
||
|
|
{"inst": "fsqrt Dd, Dn" , "op": "00011110|11|10000|11100|00|Vn|Vd"},
|
||
|
|
{"inst": "fsqrt Vd.2S, Vn.2S" , "op": "00101110|10|10000|11111|10|Vn|Vd"},
|
||
|
|
{"inst": "fsqrt Vd.4S, Vn.4S" , "op": "01101110|10|10000|11111|10|Vn|Vd"},
|
||
|
|
{"inst": "fsqrt Vd.2D, Vn.2D" , "op": "01101110|11|10000|11111|10|Vn|Vd"},
|
||
|
|
{"inst": "fsub Sd, Sn, Sm" , "op": "00011110|00|1|Vm|00111|0|Vn|Vd"},
|
||
|
|
{"inst": "fsub Dd, Dn, Dm" , "op": "00011110|01|1|Vm|00111|0|Vn|Vd"},
|
||
|
|
{"inst": "fsub Vd.2S, Vn.2S, Vm.2S" , "op": "00001110|10|1|Vm|11010|1|Vn|Vd"},
|
||
|
|
{"inst": "fsub Vd.4S, Vn.4S, Vm.4S" , "op": "01001110|10|1|Vm|11010|1|Vn|Vd"},
|
||
|
|
{"inst": "fsub Vd.2D, Vn.2D, Vm.2D" , "op": "01001110|11|1|Vm|11010|1|Vn|Vd"},
|
||
|
|
{"inst": "ins|mov Vd.B[#idx], Wn" , "op": "01001110|00|0|idx:4|1 |00011|1|Rn|Vd"},
|
||
|
|
{"inst": "ins|mov Vd.H[#idx], Wn" , "op": "01001110|00|0|idx:3|10 |00011|1|Rn|Vd"},
|
||
|
|
{"inst": "ins|mov Vd.S[#idx], Wn" , "op": "01001110|00|0|idx:2|100 |00011|1|Rn|Vd"},
|
||
|
|
{"inst": "ins|mov Vd.D[#idx], Xn" , "op": "01001110|00|0|idx:1|1000|00011|1|Rn|Vd"},
|
||
|
|
{"inst": "ins|mov Vd.B[#idx1], Vn.B[#idx2]" , "op": "01101110|00|0|idx1:4|1 |0|idx2:4|1 |Rn|Vd"},
|
||
|
|
{"inst": "ins|mov Vd.H[#idx1], Vn.H[#idx2]" , "op": "01101110|00|0|idx1:3|10 |0|idx2:3|01 |Rn|Vd"},
|
||
|
|
{"inst": "ins|mov Vd.S[#idx1], Vn.S[#idx2]" , "op": "01101110|00|0|idx1:2|100 |0|idx2:2|001 |Rn|Vd"},
|
||
|
|
{"inst": "ins|mov Vd.D[#idx1], Vn.D[#idx2]" , "op": "01101110|00|0|idx1:1|1000|0|idx2:1|0001|Rn|Vd"},
|
||
|
|
{"inst": "ld1 Vx.B[#idx], [Xn|SP]" , "op": "0|idx:1|001101|010|00000|000|idx:3 |Rn|Vx"},
|
||
|
|
{"inst": "ld1 Vx.H[#idx], [Xn|SP]" , "op": "0|idx:1|001101|010|00000|010|idx:2| 0|Rn|Vx"},
|
||
|
|
{"inst": "ld1 Vx.S[#idx], [Xn|SP]" , "op": "0|idx:1|001101|010|00000|100|idx:1|00|Rn|Vx"},
|
||
|
|
{"inst": "ld1 Vx.D[#idx], [Xn|SP]" , "op": "0|idx:1|001101|010|00000|100| 001|Rn|Vx"},
|
||
|
|
{"inst": "ld1 Vx.B[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|110|Rm |000|idx:3 |Rn|Vx"},
|
||
|
|
{"inst": "ld1 Vx.H[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|110|Rm |010|idx:2| 0|Rn|Vx"},
|
||
|
|
{"inst": "ld1 Vx.S[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|110|Rm |100|idx:1|00|Rn|Vx"},
|
||
|
|
{"inst": "ld1 Vx.D[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|110|Rm |100| 001|Rn|Vx"},
|
||
|
|
{"inst": "ld1 Vx.B[#idx], [Xn|SP, #off=1]@" , "op": "0|idx:1|001101|110|11111|000|idx:3 |Rn|Vx"},
|
||
|
|
{"inst": "ld1 Vx.H[#idx], [Xn|SP, #off=2]@" , "op": "0|idx:1|001101|110|11111|010|idx:2| 0|Rn|Vx"},
|
||
|
|
{"inst": "ld1 Vx.S[#idx], [Xn|SP, #off=4]@" , "op": "0|idx:1|001101|110|11111|100|idx:1|00|Rn|Vx"},
|
||
|
|
{"inst": "ld1 Vx.D[#idx], [Xn|SP, #off=8]@" , "op": "0|idx:1|001101|110|11111|100| 001|Rn|Vx"},
|
||
|
|
{"inst": "ld1 1x{Vd.t}, [Xn|SP]" , "op": "00001100|010|00000|0111|sz|Rn|Vd" , "t": "8B 4H 2S 1D"},
|
||
|
|
{"inst": "ld1 1x{Vd.t}, [Xn|SP]" , "op": "01001100|010|00000|0111|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "ld1 2x{Vd.t}, [Xn|SP]" , "op": "00001100|010|00000|1010|sz|Rn|Vd" , "t": "8B 4H 2S 1D"},
|
||
|
|
{"inst": "ld1 2x{Vd.t}, [Xn|SP]" , "op": "01001100|010|00000|1010|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "ld1 3x{Vd.t}, [Xn|SP]" , "op": "00001100|010|00000|0110|sz|Rn|Vd" , "t": "8B 4H 2S 1D"},
|
||
|
|
{"inst": "ld1 3x{Vd.t}, [Xn|SP]" , "op": "01001100|010|00000|0110|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "ld1 4x{Vd.t}, [Xn|SP]" , "op": "00001100|010|00000|0010|sz|Rn|Vd" , "t": "8B 4H 2S 1D"},
|
||
|
|
{"inst": "ld1 4x{Vd.t}, [Xn|SP]" , "op": "01001100|010|00000|0010|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "ld1 1x{Vd.t}, [Xn|SP, Xm]@" , "op": "00001100|110|Rm |0111|sz|Rn|Vd" , "t": "8B 4H 2S 1D"},
|
||
|
|
{"inst": "ld1 1x{Vd.t}, [Xn|SP, Xm]@" , "op": "01001100|110|Rm |0111|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "ld1 2x{Vd.t}, [Xn|SP, Xm]@" , "op": "00001100|110|Rm |1010|sz|Rn|Vd" , "t": "8B 4H 2S 1D"},
|
||
|
|
{"inst": "ld1 2x{Vd.t}, [Xn|SP, Xm]@" , "op": "01001100|110|Rm |1010|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "ld1 3x{Vd.t}, [Xn|SP, Xm]@" , "op": "00001100|110|Rm |0110|sz|Rn|Vd" , "t": "8B 4H 2S 1D"},
|
||
|
|
{"inst": "ld1 3x{Vd.t}, [Xn|SP, Xm]@" , "op": "01001100|110|Rm |0110|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "ld1 4x{Vd.t}, [Xn|SP, Xm]@" , "op": "00001100|110|Rm |0010|sz|Rn|Vd" , "t": "8B 4H 2S 1D"},
|
||
|
|
{"inst": "ld1 4x{Vd.t}, [Xn|SP, Xm]@" , "op": "01001100|110|Rm |0010|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "ld1 1x{Vd.t}, [Xn|SP, #off==8]@" , "op": "00001100|110|11111|0111|sz|Rn|Vd" , "t": "8B 4H 2S 1D"},
|
||
|
|
{"inst": "ld1 1x{Vd.t}, [Xn|SP, #off==16]@" , "op": "01001100|110|11111|0111|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "ld1 2x{Vd.t}, [Xn|SP, #off==16]@" , "op": "00001100|110|11111|1010|sz|Rn|Vd" , "t": "8B 4H 2S 1D"},
|
||
|
|
{"inst": "ld1 2x{Vd.t}, [Xn|SP, #off==32]@" , "op": "01001100|110|11111|1010|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "ld1 3x{Vd.t}, [Xn|SP, #off==24]@" , "op": "00001100|110|11111|0110|sz|Rn|Vd" , "t": "8B 4H 2S 1D"},
|
||
|
|
{"inst": "ld1 3x{Vd.t}, [Xn|SP, #off==48]@" , "op": "01001100|110|11111|0110|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "ld1 4x{Vd.t}, [Xn|SP, #off==32]@" , "op": "00001100|110|11111|0010|sz|Rn|Vd" , "t": "8B 4H 2S 1D"},
|
||
|
|
{"inst": "ld1 4x{Vd.t}, [Xn|SP, #off==64]@" , "op": "01001100|110|11111|0010|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "ld1r 1x{Vd.t}, [Xn|SP]" , "op": "00001101|010|00000|1100|sz|Rn|Vd" , "t": "8B 4H 2S 1D"},
|
||
|
|
{"inst": "ld1r 1x{Vd.t}, [Xn|SP]" , "op": "01001101|010|00000|1100|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "ld1r 1x{Vd.t}, [Xn|SP, Xm]@" , "op": "00001101|110|Rm |1100|sz|Rn|Vd" , "t": "8B 4H 2S 1D"},
|
||
|
|
{"inst": "ld1r 1x{Vd.t}, [Xn|SP, Xm]@" , "op": "01001101|110|Rm |1100|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "ld1r 1x{Vd.t}, [Xn|SP, #off==1<<sz]@" , "op": "00001101|110|11111|1100|sz|Rn|Vd" , "t": "8B 4H 2S 1D"},
|
||
|
|
{"inst": "ld1r 1x{Vd.t}, [Xn|SP, #off==1<<sz]@" , "op": "01001101|110|11111|1100|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "ld2 2x{Vx.B}[#idx], [Xn|SP]" , "op": "0|idx:1|001101|011|00000|000|idx:3 |Rn|Vx"},
|
||
|
|
{"inst": "ld2 2x{Vx.H}[#idx], [Xn|SP]" , "op": "0|idx:1|001101|011|00000|010|idx:2| 0|Rn|Vx"},
|
||
|
|
{"inst": "ld2 2x{Vx.S}[#idx], [Xn|SP]" , "op": "0|idx:1|001101|011|00000|100|idx:1|00|Rn|Vx"},
|
||
|
|
{"inst": "ld2 2x{Vx.D}[#idx], [Xn|SP]" , "op": "0|idx:1|001101|011|00000|100| 001|Rn|Vx"},
|
||
|
|
{"inst": "ld2 2x{Vx.B}[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|111|Rm |000|idx:3 |Rn|Vx"},
|
||
|
|
{"inst": "ld2 2x{Vx.H}[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|111|Rm |010|idx:2| 0|Rn|Vx"},
|
||
|
|
{"inst": "ld2 2x{Vx.S}[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|111|Rm |100|idx:1|00|Rn|Vx"},
|
||
|
|
{"inst": "ld2 2x{Vx.D}[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|111|Rm |100| 001|Rn|Vx"},
|
||
|
|
{"inst": "ld2 2x{Vx.B}[#idx], [Xn|SP, #off=2]@" , "op": "0|idx:1|001101|111|11111|000|idx:3 |Rn|Vx"},
|
||
|
|
{"inst": "ld2 2x{Vx.H}[#idx], [Xn|SP, #off=4]@" , "op": "0|idx:1|001101|111|11111|010|idx:2| 0|Rn|Vx"},
|
||
|
|
{"inst": "ld2 2x{Vx.S}[#idx], [Xn|SP, #off=8]@" , "op": "0|idx:1|001101|111|11111|100|idx:1|00|Rn|Vx"},
|
||
|
|
{"inst": "ld2 2x{Vx.D}[#idx], [Xn|SP, #off=16]@" , "op": "0|idx:1|001101|111|11111|100| 001|Rn|Vx"},
|
||
|
|
{"inst": "ld2 2x{Vd.t}, [Xn|SP]" , "op": "00001100|010|00000|1000|sz|Rn|Vd" , "t": "8B 4H 2S"},
|
||
|
|
{"inst": "ld2 2x{Vd.t}, [Xn|SP]" , "op": "01001100|010|00000|1000|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "ld2 2x{Vd.t}, [Xn|SP, Xm]@" , "op": "00001100|110|Rm |1000|sz|Rn|Vd" , "t": "8B 4H 2S"},
|
||
|
|
{"inst": "ld2 2x{Vd.t}, [Xn|SP, Xm]@" , "op": "01001100|110|Rm |1000|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "ld2 2x{Vd.t}, [Xn|SP, #off==16]@" , "op": "00001100|110|11111|1000|sz|Rn|Vd" , "t": "8B 4H 2S"},
|
||
|
|
{"inst": "ld2 2x{Vd.t}, [Xn|SP, #off==32]@" , "op": "01001100|110|11111|1000|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "ld2r 2x{Vd.t}, [Xn|SP]" , "op": "00001101|011|00000|1100|sz|Rn|Vd" , "t": "8B 4H 2S 1D"},
|
||
|
|
{"inst": "ld2r 2x{Vd.t}, [Xn|SP]" , "op": "01001101|011|00000|1100|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "ld2r 2x{Vd.t}, [Xn|SP, Xm]@" , "op": "00001101|111|Rm |1100|sz|Rn|Vd" , "t": "8B 4H 2S 1D"},
|
||
|
|
{"inst": "ld2r 2x{Vd.t}, [Xn|SP, Xm]@" , "op": "01001101|111|Rm |1100|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "ld2r 2x{Vd.t}, [Xn|SP, #off==2<<sz]@" , "op": "00001101|111|11111|1100|sz|Rn|Vd" , "t": "8B 4H 2S 1D"},
|
||
|
|
{"inst": "ld2r 2x{Vd.t}, [Xn|SP, #off==2<<sz]@" , "op": "01001101|111|11111|1100|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "ld3 3x{Vx.B}[#idx], [Xn|SP]" , "op": "0|idx:1|001101|010|00000|001|idx:3 |Rn|Vx"},
|
||
|
|
{"inst": "ld3 3x{Vx.H}[#idx], [Xn|SP]" , "op": "0|idx:1|001101|010|00000|011|idx:2| 0|Rn|Vx"},
|
||
|
|
{"inst": "ld3 3x{Vx.S}[#idx], [Xn|SP]" , "op": "0|idx:1|001101|010|00000|101|idx:1|00|Rn|Vx"},
|
||
|
|
{"inst": "ld3 3x{Vx.D}[#idx], [Xn|SP]" , "op": "0|idx:1|001101|010|00000|101| 001|Rn|Vx"},
|
||
|
|
{"inst": "ld3 3x{Vx.B}[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|110|Rm |001|idx:3 |Rn|Vx"},
|
||
|
|
{"inst": "ld3 3x{Vx.H}[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|110|Rm |011|idx:2| 0|Rn|Vx"},
|
||
|
|
{"inst": "ld3 3x{Vx.S}[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|110|Rm |101|idx:1|00|Rn|Vx"},
|
||
|
|
{"inst": "ld3 3x{Vx.D}[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|110|Rm |101| 001|Rn|Vx"},
|
||
|
|
{"inst": "ld3 3x{Vx.B}[#idx], [Xn|SP, #off=3]@" , "op": "0|idx:1|001101|110|11111|001|idx:3 |Rn|Vx"},
|
||
|
|
{"inst": "ld3 3x{Vx.H}[#idx], [Xn|SP, #off=6]@" , "op": "0|idx:1|001101|110|11111|011|idx:2| 0|Rn|Vx"},
|
||
|
|
{"inst": "ld3 3x{Vx.S}[#idx], [Xn|SP, #off=12]@" , "op": "0|idx:1|001101|110|11111|101|idx:1|00|Rn|Vx"},
|
||
|
|
{"inst": "ld3 3x{Vx.D}[#idx], [Xn|SP, #off=24]@" , "op": "0|idx:1|001101|110|11111|101| 001|Rn|Vx"},
|
||
|
|
{"inst": "ld3 3x{Vd.t}, [Xn|SP]" , "op": "00001100|010|00000|0100|sz|Rn|Vd" , "t": "8B 4H 2S"},
|
||
|
|
{"inst": "ld3 3x{Vd.t}, [Xn|SP]" , "op": "01001100|010|00000|0100|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "ld3 3x{Vd.t}, [Xn|SP, Xm]@" , "op": "00001100|110|Rm |0100|sz|Rn|Vd" , "t": "8B 4H 2S"},
|
||
|
|
{"inst": "ld3 3x{Vd.t}, [Xn|SP, Xm]@" , "op": "01001100|110|Rm |0100|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "ld3 3x{Vd.t}, [Xn|SP, #off==16]@" , "op": "00001100|110|11111|0100|sz|Rn|Vd" , "t": "8B 4H 2S"},
|
||
|
|
{"inst": "ld3 3x{Vd.t}, [Xn|SP, #off==32]@" , "op": "01001100|110|11111|0100|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "ld3r 3x{Vd.t}, [Xn|SP]" , "op": "00001101|010|00000|1110|sz|Rn|Vd" , "t": "8B 4H 2S 1D"},
|
||
|
|
{"inst": "ld3r 3x{Vd.t}, [Xn|SP]" , "op": "01001101|010|00000|1110|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "ld3r 3x{Vd.t}, [Xn|SP, Xm]@" , "op": "00001101|110|Rm |1110|sz|Rn|Vd" , "t": "8B 4H 2S 1D"},
|
||
|
|
{"inst": "ld3r 3x{Vd.t}, [Xn|SP, Xm]@" , "op": "01001101|110|Rm |1110|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "ld3r 3x{Vd.t}, [Xn|SP, #off==3<<sz]@" , "op": "00001101|110|11111|1110|sz|Rn|Vd" , "t": "8B 4H 2S 1D"},
|
||
|
|
{"inst": "ld3r 3x{Vd.t}, [Xn|SP, #off==3<<sz]@" , "op": "01001101|110|11111|1110|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "ld4 4x{Vx.B}[#idx], [Xn|SP]" , "op": "0|idx:1|001101|011|00000|001|idx:3 |Rn|Vx"},
|
||
|
|
{"inst": "ld4 4x{Vx.H}[#idx], [Xn|SP]" , "op": "0|idx:1|001101|011|00000|011|idx:2| 0|Rn|Vx"},
|
||
|
|
{"inst": "ld4 4x{Vx.S}[#idx], [Xn|SP]" , "op": "0|idx:1|001101|011|00000|101|idx:1|00|Rn|Vx"},
|
||
|
|
{"inst": "ld4 4x{Vx.D}[#idx], [Xn|SP]" , "op": "0|idx:1|001101|011|00000|101| 001|Rn|Vx"},
|
||
|
|
{"inst": "ld4 4x{Vx.B}[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|110|Rm |001|idx:3 |Rn|Vx"},
|
||
|
|
{"inst": "ld4 4x{Vx.H}[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|110|Rm |011|idx:2| 0|Rn|Vx"},
|
||
|
|
{"inst": "ld4 4x{Vx.S}[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|110|Rm |101|idx:1|00|Rn|Vx"},
|
||
|
|
{"inst": "ld4 4x{Vx.D}[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|110|Rm |101| 001|Rn|Vx"},
|
||
|
|
{"inst": "ld4 4x{Vx.B}[#idx], [Xn|SP, #off=4]@" , "op": "0|idx:1|001101|110|11111|001|idx:3 |Rn|Vx"},
|
||
|
|
{"inst": "ld4 4x{Vx.H}[#idx], [Xn|SP, #off=8]@" , "op": "0|idx:1|001101|110|11111|011|idx:2| 0|Rn|Vx"},
|
||
|
|
{"inst": "ld4 4x{Vx.S}[#idx], [Xn|SP, #off=16]@" , "op": "0|idx:1|001101|110|11111|101|idx:1|00|Rn|Vx"},
|
||
|
|
{"inst": "ld4 4x{Vx.D}[#idx], [Xn|SP, #off=32]@" , "op": "0|idx:1|001101|110|11111|101| 001|Rn|Vx"},
|
||
|
|
{"inst": "ld4 4x{Vd.t}, [Xn|SP]" , "op": "00001100|010|00000|0000|sz|Rn|Vd" , "t": "8B 4H 2S"},
|
||
|
|
{"inst": "ld4 4x{Vd.t}, [Xn|SP]" , "op": "01001100|010|00000|0000|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "ld4 4x{Vd.t}, [Xn|SP, Xm]@" , "op": "00001100|110|Rm |0000|sz|Rn|Vd" , "t": "8B 4H 2S"},
|
||
|
|
{"inst": "ld4 4x{Vd.t}, [Xn|SP, Xm]@" , "op": "01001100|110|Rm |0000|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "ld4 4x{Vd.t}, [Xn|SP, #off==32]@" , "op": "00001100|110|11111|0000|sz|Rn|Vd" , "t": "8B 4H 2S"},
|
||
|
|
{"inst": "ld4 4x{Vd.t}, [Xn|SP, #off==64]@" , "op": "01001100|110|11111|0000|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "ld4r 4x{Vd.t}, [Xn|SP]" , "op": "00001101|011|00000|1110|sz|Rn|Vd" , "t": "8B 4H 2S 1D"},
|
||
|
|
{"inst": "ld4r 4x{Vd.t}, [Xn|SP]" , "op": "01001101|011|00000|1110|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "ld4r 4x{Vd.t}, [Xn|SP, Xm]@" , "op": "00001101|111|Rm |1110|sz|Rn|Vd" , "t": "8B 4H 2S 1D"},
|
||
|
|
{"inst": "ld4r 4x{Vd.t}, [Xn|SP, Xm]@" , "op": "01001101|111|Rm |1110|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "ld4r 4x{Vd.t}, [Xn|SP, #off==4<<sz]@" , "op": "00001101|111|11111|1110|sz|Rn|Vd" , "t": "8B 4H 2S 1D"},
|
||
|
|
{"inst": "ld4r 4x{Vd.t}, [Xn|SP, #off==4<<sz]@" , "op": "01001101|111|11111|1110|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "ldnp Sd, Sd2, [Xn|SP, #soff*4]" , "op": "00101100|01|soff:7|Vd2|Vn|Vd"},
|
||
|
|
{"inst": "ldnp Dd, Dd2, [Xn|SP, #soff*8]" , "op": "01101100|01|soff:7|Vd2|Vn|Vd"},
|
||
|
|
{"inst": "ldnp Qd, Qd2, [Xn|SP, #soff*16]" , "op": "10101100|01|soff:7|Vd2|Vn|Vd"},
|
||
|
|
{"inst": "ldp Sd, Sd2, [Xn|SP, #soff*4]{@}{!}" , "op": "0010110|!post|W|1|soff:7|Vd2|Vn|Vd"},
|
||
|
|
{"inst": "ldp Dd, Dd2, [Xn|SP, #soff*8]{@}{!}" , "op": "0110110|!post|W|1|soff:7|Vd2|Vn|Vd"},
|
||
|
|
{"inst": "ldp Qd, Qd2, [Xn|SP, #soff*16]{@}{!}" , "op": "1010110|!post|W|1|soff:7|Vd2|Vn|Vd"},
|
||
|
|
{"inst": "ldr Bd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "00111100|011|Rm|option:3|n:1|10|Rn|Vd"},
|
||
|
|
{"inst": "ldr Hd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "01111100|011|Rm|option:3|n:1|10|Rn|Vd"},
|
||
|
|
{"inst": "ldr Sd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n*2}]" , "op": "10111100|011|Rm|option:3|n:1|10|Rn|Vd"},
|
||
|
|
{"inst": "ldr Dd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n*3}]" , "op": "11111100|011|Rm|option:3|n:1|10|Rn|Vd"},
|
||
|
|
{"inst": "ldr Qd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n*4}]" , "op": "00111100|111|Rm|option:3|n:1|10|Rn|Vd"},
|
||
|
|
{"inst": "ldr Sd, [PC, #soff*4]" , "op": "00011100|soff:19|Vd"},
|
||
|
|
{"inst": "ldr Dd, [PC, #soff*4]" , "op": "01011100|soff:19|Vd"},
|
||
|
|
{"inst": "ldr Qd, [PC, #soff*4]" , "op": "10011100|soff:19|Vd"},
|
||
|
|
{"inst": "ldr Bd, [Xn|SP, #zoff]" , "op": "00111101|01|zoff:12|Rn|Vd"},
|
||
|
|
{"inst": "ldr Hd, [Xn|SP, #zoff*2]" , "op": "01111101|01|zoff:12|Rn|Vd"},
|
||
|
|
{"inst": "ldr Sd, [Xn|SP, #zoff*4]" , "op": "10111101|01|zoff:12|Rn|Vd"},
|
||
|
|
{"inst": "ldr Dd, [Xn|SP, #zoff*8]" , "op": "11111101|01|zoff:12|Rn|Vd"},
|
||
|
|
{"inst": "ldr Qd, [Xn|SP, #zoff*16]" , "op": "00111101|11|zoff:12|Rn|Vd"},
|
||
|
|
{"inst": "ldr Bd, [Xn|SP, #soff]!" , "op": "00111100|010|soff:9|11|Rn|Vd"},
|
||
|
|
{"inst": "ldr Hd, [Xn|SP, #soff*2]!" , "op": "01111100|010|soff:9|11|Rn|Vd"},
|
||
|
|
{"inst": "ldr Sd, [Xn|SP, #soff*4]!" , "op": "10111100|010|soff:9|11|Rn|Vd"},
|
||
|
|
{"inst": "ldr Dd, [Xn|SP, #soff*8]!" , "op": "11111100|010|soff:9|11|Rn|Vd"},
|
||
|
|
{"inst": "ldr Qd, [Xn|SP, #soff*16]!" , "op": "00111100|110|soff:9|11|Rn|Vd"},
|
||
|
|
{"inst": "ldr Bd, [Xn|SP, #soff]@" , "op": "00111100|010|soff:9|01|Rn|Vd"},
|
||
|
|
{"inst": "ldr Hd, [Xn|SP, #soff*2]@" , "op": "01111100|010|soff:9|01|Rn|Vd"},
|
||
|
|
{"inst": "ldr Sd, [Xn|SP, #soff*4]@" , "op": "10111100|010|soff:9|01|Rn|Vd"},
|
||
|
|
{"inst": "ldr Dd, [Xn|SP, #soff*8]@" , "op": "11111100|010|soff:9|01|Rn|Vd"},
|
||
|
|
{"inst": "ldr Qd, [Xn|SP, #soff*16]@" , "op": "00111100|110|soff:9|01|Rn|Vd"},
|
||
|
|
{"inst": "ldur Bd, [Xn|SP, #soff]" , "op": "00111100|010|soff:9|00|Rn|Vd"},
|
||
|
|
{"inst": "ldur Hd, [Xn|SP, #soff]" , "op": "01111100|010|soff:9|00|Rn|Vd"},
|
||
|
|
{"inst": "ldur Sd, [Xn|SP, #soff]" , "op": "10111100|010|soff:9|00|Rn|Vd"},
|
||
|
|
{"inst": "ldur Dd, [Xn|SP, #soff]" , "op": "11111100|010|soff:9|00|Rn|Vd"},
|
||
|
|
{"inst": "ldur Qd, [Xn|SP, #soff]" , "op": "00111100|110|soff:9|00|Rn|Vd"},
|
||
|
|
{"inst": "mla Vx.t, Vn.t, Vm.t" , "op": "00001110|sz|1|Vm|10010|1|Vn|Vx" , "t": "8B 4H 2S"},
|
||
|
|
{"inst": "mla Vx.t, Vn.t, Vm.t" , "op": "01001110|sz|1|Vm|10010|1|Vn|Vx" , "t": "16B 8H 4S"},
|
||
|
|
{"inst": "mla Vx.4H, Vn.4H, Vm.H[#idx]" , "op": "00101111|01|idx[1:0]|Vm:4|0000|idx[2]|0|Vn|Vx"},
|
||
|
|
{"inst": "mla Vx.8H, Vn.8H, Vm.H[#idx]" , "op": "01101111|01|idx[1:0]|Vm:4|0000|idx[2]|0|Vn|Vx"},
|
||
|
|
{"inst": "mla Vx.2S, Vn.2S, Vm.S[#idx]" , "op": "00101111|10|idx[0]|Vm|0000|idx[1]|0|Vn|Vx"},
|
||
|
|
{"inst": "mla Vx.4S, Vn.4S, Vm.S[#idx]" , "op": "01101111|10|idx[0]|Vm|0000|idx[1]|0|Vn|Vx"},
|
||
|
|
{"inst": "mls Vx.t, Vn.t, Vm.t" , "op": "00101110|sz|1|Vm|10010|1|Vn|Vx" , "t": "8B 4H 2S"},
|
||
|
|
{"inst": "mls Vx.t, Vn.t, Vm.t" , "op": "01101110|sz|1|Vm|10010|1|Vn|Vx" , "t": "16B 8H 4S"},
|
||
|
|
{"inst": "mls Vx.4H, Vn.4H, Vm.H[#idx]" , "op": "00101111|01|idx[1:0]|Vm:4|0100|idx[2]|0|Vn|Vx"},
|
||
|
|
{"inst": "mls Vx.8H, Vn.8H, Vm.H[#idx]" , "op": "01101111|01|idx[1:0]|Vm:4|0100|idx[2]|0|Vn|Vx"},
|
||
|
|
{"inst": "mls Vx.2S, Vn.2S, Vm.S[#idx]" , "op": "00101111|10|idx[0]|Vm|0100|idx[1]|0|Vn|Vx"},
|
||
|
|
{"inst": "mls Vx.4S, Vn.4S, Vm.S[#idx]" , "op": "01101111|10|idx[0]|Vm|0100|idx[1]|0|Vn|Vx"},
|
||
|
|
{"inst": "mov Vd.8B, Vn.8B" , "op": "00001110|10|1|Vn|00011|1|Vn|Vd"},
|
||
|
|
{"inst": "mov Vd.16B, Vn.16B" , "op": "01001110|10|1|Vn|00011|1|Vn|Vd"},
|
||
|
|
{"inst": "movi Dd, #imm, {lsl #n}" , "op": "00|op:1|01111|00|0|00|abc:3|cmode:4|01|defgh:5|Vd" , "imm": "ASimdMovPImm(0, imm, n)"},
|
||
|
|
{"inst": "movi Vd.t, #imm, {lsl #n}" , "op": "00|op:1|01111|00|0|00|abc:3|cmode:4|01|defgh:5|Vd" , "imm": "ASimdMovPImm(sz, imm, n)", "t": "8B 4H 2S"},
|
||
|
|
{"inst": "movi Vd.t, #imm, {lsl #n}" , "op": "01|op:1|01111|00|0|00|abc:3|cmode:4|01|defgh:5|Vd" , "imm": "ASimdMovPImm(sz, imm, n)", "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "mul Vd.t, Vn.t, Vm.t" , "op": "01001110|sz|1|Vm|10011|1|Vn|Vd" , "t": "16B 8H 4S"},
|
||
|
|
{"inst": "mul Vd.t, Vn.t, Vm.t" , "op": "00001110|sz|1|Vm|10011|1|Vn|Vd" , "t": "8B 4H 2S"},
|
||
|
|
{"inst": "mul Vd.4H, Vn.4H, Vm.H[#idx]" , "op": "00001111|01|idx[1:0]|Vm:4|1000|idx[2]|0|Vn|Vd"},
|
||
|
|
{"inst": "mul Vd.8H, Vn.8H, Vm.H[#idx]" , "op": "01001111|01|idx[1:0]|Vm:4|1000|idx[2]|0|Vn|Vd"},
|
||
|
|
{"inst": "mul Vd.2S, Vn.2S, Vm.S[#idx]" , "op": "00001111|10|idx[0]|Vm|1000|idx[1]|0|Vn|Vd"},
|
||
|
|
{"inst": "mul Vd.4S, Vn.4S, Vm.S[#idx]" , "op": "01001111|10|idx[0]|Vm|1000|idx[1]|0|Vn|Vd"},
|
||
|
|
{"inst": "mvni Dd, #imm, {lsl #n}" , "op": "00|op:1|01111|00|0|00|abc:3|cmode:4|01|defgh:5|Vd" , "imm": "ASimdMovNImm(0, imm, n)"},
|
||
|
|
{"inst": "mvni Vd.t, #imm, {lsl #n}" , "op": "00|op:1|01111|00|0|00|abc:3|cmode:4|01|defgh:5|Vd" , "imm": "ASimdMovNImm(sz, imm, n)", "t": "8B 4H 2S"},
|
||
|
|
{"inst": "mvni Vd.t, #imm, {lsl #n}" , "op": "01|op:1|01111|00|0|00|abc:3|cmode:4|01|defgh:5|Vd" , "imm": "ASimdMovNImm(sz, imm, n)", "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "neg Dd, Dn" , "op": "01111110|11|10000|01011|10|Vn|Vd"},
|
||
|
|
{"inst": "neg Vd.t, Vn.t" , "op": "00101110|sz|10000|01011|10|Vn|Vd" , "t": "8B 4H 2S"},
|
||
|
|
{"inst": "neg Vd.t, Vn.t" , "op": "01101110|sz|10000|01011|10|Vn|Vd" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "not|mvn Vd.8B, Vn.8B" , "op": "00101110|00|10000|00101|10|Vn|Vd"},
|
||
|
|
{"inst": "not|mvn Vd.16B, Vn.16B" , "op": "01101110|00|10000|00101|10|Vn|Vd"},
|
||
|
|
{"inst": "orn Vd.8B, Vn.8B, Vm.8B" , "op": "00001110|11|1|Vm|00011|1|Vn|Vd"},
|
||
|
|
{"inst": "orn Vd.16B, Vn.16B, Vm.16B" , "op": "01001110|11|1|Vm|00011|1|Vn|Vd"},
|
||
|
|
{"inst": "orr Vd.8B, Vn.8B, Vm.8B" , "op": "00001110|10|1|Vm|00011|1|Vn|Vd"},
|
||
|
|
{"inst": "orr Vd.16B, Vn.16B, Vm.16B" , "op": "01001110|10|1|Vm|00011|1|Vn|Vd"},
|
||
|
|
{"inst": "orr Vd.t, #imm, {lsl #n}" , "op": "00001111|00000|abc:3|cmode:4|01|defgh:5|Vd" , "t": "4H 2S", "imm": "ASimdLogicalImm(sz, 0, imm, n)"},
|
||
|
|
{"inst": "orr Vd.t, #imm, {lsl #n}" , "op": "01001111|00000|abc:3|cmode:4|01|defgh:5|Vd" , "t": "8H 4S", "imm": "ASimdLogicalImm(sz, 0, imm, n)"},
|
||
|
|
{"inst": "pmul Vd.8B, Vn.8B, Vm.8B" , "op": "00101110|00|1|Vm|10011|1|Vn|Vd"},
|
||
|
|
{"inst": "pmul Vd.16B, Vn.16B, Vm.16B" , "op": "01101110|00|1|Vm|10011|1|Vn|Vd"},
|
||
|
|
{"inst": "pmull Vd.8H, Vn.8B, Vm.8B" , "op": "00001110|00|1|Vm|11100|0|Vn|Vd"},
|
||
|
|
{"inst": "pmull Vd.1Q, Vn.1D, Vm.1D" , "op": "00001110|11|1|Vm|11100|0|Vn|Vd"},
|
||
|
|
{"inst": "pmull2 Vd.8H, Vn.16B, Vm.16B" , "op": "01001110|00|1|Vm|11100|0|Vn|Vd"},
|
||
|
|
{"inst": "pmull2 Vd.1Q, Vn.2D, Vm.2D" , "op": "01001110|11|1|Vm|11100|0|Vn|Vd"},
|
||
|
|
{"inst": "raddhn Vd.ta, Vn.tb, Vm.tb" , "op": "00101110|sz|1|Vm|01000|0|Vn|Vd" , "ta.tb": "8B.8H 4H.4S 2S.2D"},
|
||
|
|
{"inst": "raddhn2 Vx.ta, Vn.tb, Vm.tb" , "op": "01101110|sz|1|Vm|01000|0|Vn|Vx" , "ta.tb": "16B.8H 8H.4S 4S.2D"},
|
||
|
|
{"inst": "rbit Vd.8B, Vn.8B" , "op": "00101110|01|10000|00101|10|Vn|Vd"},
|
||
|
|
{"inst": "rbit Vd.16B, Vn.16B" , "op": "01101110|01|10000|00101|10|Vn|Vd"},
|
||
|
|
{"inst": "rev16 Vd.8B, Vn.8B" , "op": "00001110|sz|10000|00001|10|Vn|Vd"},
|
||
|
|
{"inst": "rev16 Vd.16B, Vn.16B" , "op": "01001110|sz|10000|00001|10|Vn|Vd"},
|
||
|
|
{"inst": "rev32 Vd.t, Vn.t" , "op": "00101110|sz|10000|00000|10|Vn|Vd" , "t": "8B 4H"},
|
||
|
|
{"inst": "rev32 Vd.t, Vn.t" , "op": "01101110|sz|10000|00000|10|Vn|Vd" , "t": "16B 8H"},
|
||
|
|
{"inst": "rev64 Vd.t, Vn.t" , "op": "00001110|sz|10000|00000|10|Vn|Vd" , "t": "8B 4H 2S"},
|
||
|
|
{"inst": "rev64 Vd.t, Vn.t" , "op": "01001110|sz|10000|00000|10|Vn|Vd" , "t": "16B 8H 4S"},
|
||
|
|
{"inst": "rshrn Vd.ta, Vn.tb, #n" , "op": "00001111|0|immh:4|immb:3|10001|1|Vn|Vd" , "imm": "ASimdShiftNImm(n, sz)", "ta.tb": "8B.8H 4H.4S 2S.2D"},
|
||
|
|
{"inst": "rshrn2 Vx.ta, Vn.tb, #n" , "op": "01001111|0|immh:4|immb:3|10001|1|Vn|Vx" , "imm": "ASimdShiftNImm(n, sz)", "ta.tb": "16B.8H 8H.4S 4S.2D"},
|
||
|
|
{"inst": "rsubhn Vd.ta, Vn.tb, Vm.tb" , "op": "00101110|sz|1|Vm|01100|0|Vn|Vd" , "ta.tb": "8B.8H 4H.4S 2S.2D"},
|
||
|
|
{"inst": "rsubhn2 Vx.ta, Vn.tb, Vm.tb" , "op": "01101110|sz|1|Vm|01100|0|Vn|Vx" , "ta.tb": "16B.8H 8H.4S 4S.2D"},
|
||
|
|
{"inst": "saba Vx.t, Vn.t, Vm.t" , "op": "00001110|sz|1|Vm|01111|1|Vn|Vx" , "t": "8B 4H 2S"},
|
||
|
|
{"inst": "saba Vx.t, Vn.t, Vm.t" , "op": "01001110|sz|1|Vm|01111|1|Vn|Vx" , "t": "16B 8H 4S"},
|
||
|
|
{"inst": "sabal Vx.ta, Vn.tb, Vm.tb" , "op": "00001110|sz|1|Vm|01010|0|Vn|Vx" , "ta.tb": "8H.8B 4S.4H 2D.2S"},
|
||
|
|
{"inst": "sabal2 Vx.ta, Vn.tb, Vm.tb" , "op": "01001110|sz|1|Vm|01010|0|Vn|Vx" , "ta.tb": "8H.16B 4S.8H 2D.4S"},
|
||
|
|
{"inst": "sabd Vd.t, Vn.t, Vm.t" , "op": "00001110|sz|1|Vm|01110|1|Vn|Vd" , "t": "8B 4H 2S"},
|
||
|
|
{"inst": "sabd Vd.t, Vn.t, Vm.t" , "op": "01001110|sz|1|Vm|01110|1|Vn|Vd" , "t": "16B 8H 4S"},
|
||
|
|
{"inst": "sabdl Vd.ta, Vn.tb, Vm.tb" , "op": "00001110|sz|1|Vm|01110|0|Vn|Vd" , "ta.tb": "8H.8B 4S.4H 2D.2S"},
|
||
|
|
{"inst": "sabdl2 Vd.ta, Vn.tb, Vm.tb" , "op": "01001110|sz|1|Vm|01110|0|Vn|Vd" , "ta.tb": "8H.16B 4S.8H 2D.4S"},
|
||
|
|
{"inst": "sadalp Vx.ta, Vn.tb" , "op": "00001110|sz|10000|00110|10|Vn|Vx" , "ta.tb": "4H.8B 2S.4H 1D.2S"},
|
||
|
|
{"inst": "sadalp Vx.ta, Vn.tb" , "op": "01001110|sz|10000|00110|10|Vn|Vx" , "ta.tb": "8H.16B 4S.8H 2D.4S"},
|
||
|
|
{"inst": "saddl Vd.ta, Vn.tb, Vm.tb" , "op": "00001110|sz|1|Vm|00000|0|Vn|Vd" , "ta.tb": "8H.8B 4S.4H 2D.2S"},
|
||
|
|
{"inst": "saddl2 Vd.ta, Vn.tb, Vm.tb" , "op": "01001110|sz|1|Vm|00000|0|Vn|Vd" , "ta.tb": "8H.16B 4S.8H 2D.4S"},
|
||
|
|
{"inst": "saddlp Vd.ta, Vn.tb" , "op": "00001110|sz|10000|00010|10|Vn|Vd" , "ta.tb": "4H.8B 2S.4H 1D.2S"},
|
||
|
|
{"inst": "saddlp Vd.ta, Vn.tb" , "op": "01001110|sz|10000|00010|10|Vn|Vd" , "ta.tb": "8H.16B 4S.8H 2D.4S"},
|
||
|
|
{"inst": "saddlv Hd, Vn.8B" , "op": "00001110|00|11000|00011|10|Vn|Vd"},
|
||
|
|
{"inst": "saddlv Hd, Vn.16B" , "op": "01001110|00|11000|00011|10|Vn|Vd"},
|
||
|
|
{"inst": "saddlv Sd, Vn.4H" , "op": "00001110|01|11000|00011|10|Vn|Vd"},
|
||
|
|
{"inst": "saddlv Sd, Vn.8H" , "op": "01001110|01|11000|00011|10|Vn|Vd"},
|
||
|
|
{"inst": "saddlv Dd, Vn.4S" , "op": "01001110|10|11000|00011|10|Vn|Vd"},
|
||
|
|
{"inst": "saddw Vd.ta, Vn.ta, Vm.tb" , "op": "00001110|sz|1|Vm|00010|0|Vn|Vd" , "ta.tb": "8H.8B 4S.4H 2D.2S"},
|
||
|
|
{"inst": "saddw2 Vd.ta, Vn.ta, Vm.tb" , "op": "01001110|sz|1|Vm|00010|0|Vn|Vd" , "ta.tb": "8H.16B 4S.8H 2D.4S"},
|
||
|
|
{"inst": "scvtf Sd, Wn" , "op": "00011110|00|1|00010|00000|0|Rn|Vd"},
|
||
|
|
{"inst": "scvtf Sd, Wn, #fbits" , "op": "00011110|00|0|00010|scale:6|Rn|Vd" , "imm": "ASimdFBitsScaleImm(fbits, 32)"},
|
||
|
|
{"inst": "scvtf Sd, Xn" , "op": "10011110|00|1|00010|00000|0|Rn|Vd"},
|
||
|
|
{"inst": "scvtf Sd, Xn, #fbits" , "op": "10011110|00|0|00010|scale:6|Rn|Vd" , "imm": "ASimdFBitsScaleImm(fbits, 64)"},
|
||
|
|
{"inst": "scvtf Sd, Sn" , "op": "01011110|00|10000|11101|10|Vn|Vd"},
|
||
|
|
{"inst": "scvtf Sd, Sn, #bits" , "op": "01011111|0|immh:4|immb:3|11100|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 32)"},
|
||
|
|
{"inst": "scvtf Dd, Wn" , "op": "00011110|01|1|00010|00000|0|Rn|Vd"},
|
||
|
|
{"inst": "scvtf Dd, Wn, #fbits" , "op": "00011110|01|0|00010|scale:6|Rn|Vd" , "imm": "ASimdFBitsScaleImm(fbits, 32)"},
|
||
|
|
{"inst": "scvtf Dd, Xn" , "op": "10011110|01|1|00010|00000|0|Rn|Vd"},
|
||
|
|
{"inst": "scvtf Dd, Xn, #fbits" , "op": "10011110|01|0|00010|scale:6|Rn|Vd" , "imm": "ASimdFBitsScaleImm(fbits, 64)"},
|
||
|
|
{"inst": "scvtf Dd, Dn" , "op": "01011110|01|10000|11101|10|Vn|Vd"},
|
||
|
|
{"inst": "scvtf Dd, Dn, #bits" , "op": "01011111|0|immh:4|immb:3|11100|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 64)"},
|
||
|
|
{"inst": "scvtf Vd.2S, Vn.2S" , "op": "00001110|00|10000|11101|10|Vn|Vd"},
|
||
|
|
{"inst": "scvtf Vd.4S, Vn.4S" , "op": "01001110|00|10000|11101|10|Vn|Vd"},
|
||
|
|
{"inst": "scvtf Vd.2D, Vn.2D" , "op": "01001110|01|10000|11101|10|Vn|Vd"},
|
||
|
|
{"inst": "scvtf Vd.2S, Vn.2S, #fbits" , "op": "00001111|0|immh:4|immb:3|11100|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 32)"},
|
||
|
|
{"inst": "scvtf Vd.4S, Vn.4S, #fbits" , "op": "01001111|0|immh:4|immb:3|11100|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 32)"},
|
||
|
|
{"inst": "scvtf Vd.2D, Vn.2D, #fbits" , "op": "01001111|0|immh:4|immb:3|11100|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 64)"},
|
||
|
|
{"inst": "shadd Vd.t, Vn.t, Vm.t" , "op": "00001110|sz|1|Vm|00000|1|Vn|Vd" , "t": "8B 4H 2S"},
|
||
|
|
{"inst": "shadd Vd.t, Vn.t, Vm.t" , "op": "01001110|sz|1|Vm|00000|1|Vn|Vd" , "t": "16B 8H 4S"},
|
||
|
|
{"inst": "shl Dd, Dn, #n" , "op": "01011111|0|immh:4|immb:3|01010|1|Vn|Vd" , "imm": "ASimdSHL(n, 3)"},
|
||
|
|
{"inst": "shl Vd.t, Vn.t, #n" , "op": "00001111|0|immh:4|immb:3|01010|1|Vn|Vd" , "imm": "ASimdSHL(n, sz)", "t": "8B 4H 2S"},
|
||
|
|
{"inst": "shl Vd.t, Vn.t, #n" , "op": "01001111|0|immh:4|immb:3|01010|1|Vn|Vd" , "imm": "ASimdSHL(n, sz)", "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "shll Vd.8H, Vn.8B, #8" , "op": "00101110|00|10000|10011|10|Vn|Vd"},
|
||
|
|
{"inst": "shll2 Vd.8H, Vn.16B, #8" , "op": "01101110|00|10000|10011|10|Vn|Vd"},
|
||
|
|
{"inst": "shll Vd.4S, Vn.4H, #16" , "op": "00101110|01|10000|10011|10|Vn|Vd"},
|
||
|
|
{"inst": "shll2 Vd.4S, Vn.8H, #16" , "op": "01101110|01|10000|10011|10|Vn|Vd"},
|
||
|
|
{"inst": "shll Vd.2D, Vn.2S, #32" , "op": "00101110|10|10000|10011|10|Vn|Vd"},
|
||
|
|
{"inst": "shll2 Vd.2D, Vn.4S, #32" , "op": "01101110|10|10000|10011|10|Vn|Vd"},
|
||
|
|
{"inst": "shrn Vd.ta, Vn.tb, #n" , "op": "00001111|0|immh:4|immb:3|100001|Vn|Vd" , "imm": "ASimdSHRN(n, sz)", "t": "8B.8H 4H.4S 2S.2D"},
|
||
|
|
{"inst": "shrn2 Vx.ta, Vn.tb, #n" , "op": "01001111|0|immh:4|immb:3|100001|Vn|Vx" , "imm": "ASimdSHRN(n, sz)", "t": "16B.8H 8H.4S 4S.2D"},
|
||
|
|
{"inst": "shsub Vd.t, Vn.t, Vm.t" , "op": "00001110|sz|1|Vm|00100|1|Vn|Vd" , "t": "8B 4H 2S"},
|
||
|
|
{"inst": "shsub Vd.t, Vn.t, Vm.t" , "op": "01001110|sz|1|Vm|00100|1|Vn|Vd" , "t": "16B 8H 4S"},
|
||
|
|
{"inst": "sli Dx, Dn, #n" , "op": "01111111|0|immh:4|immb:3|01010|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftPImm(n, 3)"},
|
||
|
|
{"inst": "sli Vx.t, Vn.t, #n" , "op": "00101111|0|immh:4|immb:3|01010|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftPImm(n, sz)", "t": "8B 4H 2S"},
|
||
|
|
{"inst": "sli Vx.t, Vn.t, #n" , "op": "01101111|0|immh:4|immb:3|01010|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftPImm(n, sz)", "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "smax Vd.t, Vn.t, Vm.t" , "op": "00001110|sz|1|Vm|01100|1|Vn|Vd" , "t": "8B 4H 2S"},
|
||
|
|
{"inst": "smax Vd.t, Vn.t, Vm.t" , "op": "01001110|sz|1|Vm|01100|1|Vn|Vd" , "t": "16B 8H 4S"},
|
||
|
|
{"inst": "smaxp Vd.t, Vn.t, Vm.t" , "op": "00001110|sz|1|Vm|10100|1|Vn|Vd" , "t": "8B 4H 2S"},
|
||
|
|
{"inst": "smaxp Vd.t, Vn.t, Vm.t" , "op": "01001110|sz|1|Vm|10100|1|Vn|Vd" , "t": "16B 8H 4S"},
|
||
|
|
{"inst": "smaxv Bd, Vn.8B" , "op": "00001110|00|11000|01010|10|Vn|Vd"},
|
||
|
|
{"inst": "smaxv Bd, Vn.16B" , "op": "01001110|00|11000|01010|10|Vn|Vd"},
|
||
|
|
{"inst": "smaxv Hd, Vn.4H" , "op": "00001110|01|11000|01010|10|Vn|Vd"},
|
||
|
|
{"inst": "smaxv Hd, Vn.8H" , "op": "01001110|01|11000|01010|10|Vn|Vd"},
|
||
|
|
{"inst": "smaxv Sd, Vn.4S" , "op": "01001110|10|11000|01010|10|Vn|Vd"},
|
||
|
|
{"inst": "smin Vd.t, Vn.t, Vm.t" , "op": "00001110|sz|1|Vm|01101|1|Vn|Vd" , "t": "8B 4H 2S"},
|
||
|
|
{"inst": "smin Vd.t, Vn.t, Vm.t" , "op": "01001110|sz|1|Vm|01101|1|Vn|Vd" , "t": "16B 8H 4S"},
|
||
|
|
{"inst": "sminp Vd.t, Vn.t, Vm.t" , "op": "00001110|sz|1|Vm|10101|1|Vn|Vd" , "t": "8B 4H 2S"},
|
||
|
|
{"inst": "sminp Vd.t, Vn.t, Vm.t" , "op": "01001110|sz|1|Vm|10101|1|Vn|Vd" , "t": "16B 8H 4S"},
|
||
|
|
{"inst": "sminv Bd, Vn.8B" , "op": "00001110|00|11000|11010|10|Vn|Vd"},
|
||
|
|
{"inst": "sminv Bd, Vn.16B" , "op": "01001110|00|11000|11010|10|Vn|Vd"},
|
||
|
|
{"inst": "sminv Hd, Vn.4H" , "op": "00001110|01|11000|11010|10|Vn|Vd"},
|
||
|
|
{"inst": "sminv Hd, Vn.8H" , "op": "01001110|01|11000|11010|10|Vn|Vd"},
|
||
|
|
{"inst": "sminv Sd, Vn.4S" , "op": "01001110|10|11000|11010|10|Vn|Vd"},
|
||
|
|
{"inst": "smlal Vd.ta, Vn.tb, Vm.tb" , "op": "00001110|sz|1|Vm|10000|0|Vn|Vd" , "t": "8H.8B 4S.4H 2D.2S"},
|
||
|
|
{"inst": "smlal2 Vd.ta, Vn.tb, Vm.tb" , "op": "01001110|sz|1|Vm|10000|0|Vn|Vd" , "t": "8H.16B 4S.8H 2D.4S"},
|
||
|
|
{"inst": "smlal Vd.4S, Vn.4H, Vm.H[#dx]" , "op": "00001111|01|idx[1:0]|Vm:4|0010|idx[2]|0|Vn|Vd"},
|
||
|
|
{"inst": "smlal2 Vd.4S, Vn.8H, Vm.H[#dx]" , "op": "01001111|01|idx[1:0]|Vm:4|0010|idx[2]|0|Vn|Vd"},
|
||
|
|
{"inst": "smlal Vd.2D, Vn.2S, Vm.S[#dx]" , "op": "00001111|10|idx[0] |Vm |0010|idx[1]|0|Vn|Vd"},
|
||
|
|
{"inst": "smlal2 Vd.2D, Vn.4S, Vm.S[#dx]" , "op": "01001111|10|idx[0] |Vm |0010|idx[1]|0|Vn|Vd"},
|
||
|
|
{"inst": "smlsl Vd.ta, Vn.tb, Vm.tb" , "op": "00001110|sz|1|Vm|10100|0|Vn|Vd" , "t": "8H.8B 4S.4H 2D.2S"},
|
||
|
|
{"inst": "smlsl2 Vd.ta, Vn.tb, Vm.tb" , "op": "01001110|sz|1|Vm|10100|0|Vn|Vd" , "t": "8H.16B 4S.8H 2D.4S"},
|
||
|
|
{"inst": "smlsl Vd.4S, Vn.4H, Vm.H[#dx]" , "op": "00001111|01|idx[1:0]|Vm:4|0110|idx[2]|0|Vn|Vd"},
|
||
|
|
{"inst": "smlsl2 Vd.4S, Vn.8H, Vm.H[#dx]" , "op": "01001111|01|idx[1:0]|Vm:4|0110|idx[2]|0|Vn|Vd"},
|
||
|
|
{"inst": "smlsl Vd.2D, Vn.2S, Vm.S[#dx]" , "op": "00001111|10|idx[0] |Vm |0110|idx[1]|0|Vn|Vd"},
|
||
|
|
{"inst": "smlsl2 Vd.2D, Vn.4S, Vm.S[#dx]" , "op": "01001111|10|idx[0] |Vm |0110|idx[1]|0|Vn|Vd"},
|
||
|
|
{"inst": "smov Wd, Vn.B[#idx]" , "op": "00001110|00|0|idx:4| 1|00101|1|Vn|Rd"},
|
||
|
|
{"inst": "smov Wd, Vn.H[#idx]" , "op": "00001110|00|0|idx:3| 10|00101|1|Vn|Rd"},
|
||
|
|
{"inst": "smov Xd, Vn.B[#idx]" , "op": "01001110|00|0|idx:4| 1|00101|1|Vn|Rd"},
|
||
|
|
{"inst": "smov Xd, Vn.H[#idx]" , "op": "01001110|00|0|idx:3| 10|00101|1|Vn|Rd"},
|
||
|
|
{"inst": "smov Xd, Vn.S[#idx]" , "op": "01001110|00|0|idx:2|100|00101|1|Vn|Rd"},
|
||
|
|
{"inst": "smull Vd.ta, Vn.tb, Vm.tb" , "op": "00001110|sz|1|Vm|11000|0|Vn|Vd" , "t": "8H.8B 4S.4H 2D.2S"},
|
||
|
|
{"inst": "smull2 Vd.ta, Vn.tb, Vm.tb" , "op": "01001110|sz|1|Vm|11000|0|Vn|Vd" , "t": "8H.16B 4S.8H 2D.4S"},
|
||
|
|
{"inst": "smull Vd.4S, Vn.4H, Vm.H[#idx]" , "op": "00001111|01|idx[1:0]|Vm:4|1010|idx[2]|0|Vn|Vd"},
|
||
|
|
{"inst": "smull2 Vd.4S, Vn.8H, Vm.H[#idx]" , "op": "01001111|01|idx[1:0]|Vm:4|1010|idx[2]|0|Vn|Vd"},
|
||
|
|
{"inst": "smull Vd.2D, Vn.2S, Vm.S[#idx]" , "op": "00001111|10|idx[0] |Vm |1010|idx[1]|0|Vn|Vd"},
|
||
|
|
{"inst": "smull2 Vd.2D, Vn.4S, Vm.S[#idx]" , "op": "01001111|10|idx[0] |Vm |1010|idx[1]|0|Vn|Vd"},
|
||
|
|
{"inst": "sqabs Bd, Bn" , "op": "01011110|sz|10000|00111|10|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqabs Hd, Hn" , "op": "01011110|sz|10000|00111|10|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqabs Sd, Sn" , "op": "01011110|sz|10000|00111|10|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqabs Dd, Dn" , "op": "01011110|sz|10000|00111|10|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqabs Vd.t, Vn.t" , "op": "00001110|sz|10000|00111|10|Vn|Vd" , "io": "QC|=SAT", "t": "16B 8H 4S"},
|
||
|
|
{"inst": "sqabs Vd.t, Vn.t" , "op": "01001110|sz|10000|00111|10|Vn|Vd" , "io": "QC|=SAT", "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "sqadd Bd, Bn, Bm" , "op": "01011110|sz|1|Vm|00001|1|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqadd Hd, Hn, Hm" , "op": "01011110|sz|1|Vm|00001|1|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqadd Sd, Sn, Sm" , "op": "01011110|sz|1|Vm|00001|1|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqadd Dd, Dn, Dm" , "op": "01011110|sz|1|Vm|00001|1|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqadd Vd.t, Vn.t, Vm.t" , "op": "00001110|sz|1|Vm|00001|1|Vn|Vd" , "io": "QC|=SAT", "t": "16B 8H 4S"},
|
||
|
|
{"inst": "sqadd Vd.t, Vn.t, Vm.t" , "op": "01001110|sz|1|Vm|00001|1|Vn|Vd" , "io": "QC|=SAT", "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "sqdmlal Sx, Hn, Hm" , "op": "01011110|01|1|Vm|10010|0|Vn|Vx" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqdmlal Dx, Sn, Sm" , "op": "01011110|10|1|Vm|10010|0|Vn|Vx" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqdmlal Sx, Hn, Vm.H[#idx]" , "op": "01011111|01|idx[1:0]|Vm:4|0011|idx[2]|0|Vn|Vx" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqdmlal Dx, Sn, Vm.S[#idx]" , "op": "01011111|10|idx[0] |Vm |0011|idx[1]|0|Vn|Vx" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqdmlal Vx.ta, Vn.tb, Vm.tb" , "op": "00001110|sz|1|Vm|10010|0|Vn|Vx" , "io": "QC|=SAT", "ta.tb": "4S.4H 2D.2S"},
|
||
|
|
{"inst": "sqdmlal2 Vx.ta, Vn.tb, Vm.tb" , "op": "01001110|sz|1|Vm|10010|0|Vn|Vx" , "io": "QC|=SAT", "ta.tb": "4S.8H 2D.4S"},
|
||
|
|
{"inst": "sqdmlal Vx.4S, Vn.4H, Vm.H[#idx]" , "op": "00011111|01|idx[1:0]|Vm:4|0011|idx[2]|0|Vn|Vx" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqdmlal2 Vx.4S, Vn.8H, Vm.H[#idx]" , "op": "01011111|01|idx[1:0]|Vm:4|0011|idx[2]|0|Vn|Vx" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqdmlal Vx.2D, Vn.2S, Vm.S[#idx]" , "op": "00011111|10|idx[0] |Vm |0011|idx[1]|0|Vn|Vx" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqdmlal2 Vx.2D, Vn.4S, Vm.S[#idx]" , "op": "01011111|10|idx[0] |Vm |0011|idx[1]|0|Vn|Vx" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqdmlsl Sx, Hn, Hm" , "op": "01011110|01|1|Vm|10110|0|Vn|Vx" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqdmlsl Dx, Sn, Sm" , "op": "01011110|10|1|Vm|10110|0|Vn|Vx" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqdmlsl Sx, Hn, Vm.H[#idx]" , "op": "01011111|01|idx[1:0]|Vm:4|0111|idx[2]|0|Vn|Vx" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqdmlsl Dx, Sn, Vm.S[#idx]" , "op": "01011111|10|idx[0] |Vm |0111|idx[1]|0|Vn|Vx" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqdmlsl Vx.ta, Vn.tb, Vm.tb" , "op": "00001110|sz|1|Vm|10110|0|Vn|Vx" , "io": "QC|=SAT", "ta.tb": "4S.4H 2D.2S"},
|
||
|
|
{"inst": "sqdmlsl2 Vx.ta, Vn.tb, Vm.tb" , "op": "01001110|sz|1|Vm|10110|0|Vn|Vx" , "io": "QC|=SAT", "ta.tb": "4S.8H 2D.4S"},
|
||
|
|
{"inst": "sqdmlsl Vx.4S, Vn.4H, Vm.H[#idx]" , "op": "00011111|01|idx[1:0]|Vm:4|0111|idx[2]|0|Vn|Vx" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqdmlsl2 Vx.4S, Vn.8H, Vm.H[#idx]" , "op": "01011111|01|idx[1:0]|Vm:4|0111|idx[2]|0|Vn|Vx" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqdmlsl Vx.2D, Vn.2S, Vm.S[#idx]" , "op": "00011111|10|idx[0] |Vm |0111|idx[1]|0|Vn|Vx" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqdmlsl2 Vx.2D, Vn.4S, Vm.S[#idx]" , "op": "01011111|10|idx[0] |Vm |0111|idx[1]|0|Vn|Vx" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqdmulh Hd, Hn, Hm" , "op": "01011110|01|1|Vm|10110|1|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqdmulh Sd, Sn, Sm" , "op": "01011110|10|1|Vm|10110|1|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqdmulh Hd, Hn, Vm.H[#idx]" , "op": "01011111|01|idx[1:0]|Vm:4|1100|idx[2]|0|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqdmulh Sd, Sn, Vm.S[#idx]" , "op": "01011111|10|idx[0] |Vm |1100|idx[1]|0|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqdmulh Vd.t, Vn.t, Vm.t" , "op": "00001110|sz|1|Vm|10110|1|Vn|Vd" , "io": "QC|=SAT", "t": "~ 4H 2S"},
|
||
|
|
{"inst": "sqdmulh Vd.t, Vn.t, Vm.t" , "op": "01001110|sz|1|Vm|10110|1|Vn|Vd" , "io": "QC|=SAT", "t": "~ 8H 4S"},
|
||
|
|
{"inst": "sqdmulh Vd.4H, Vn.4H, Vm.H[#idx]" , "op": "00001111|01|idx[1:0]|Vm:4|1100|idx[2]|0|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqdmulh Vd.8H, Vn.8H, Vm.H[#idx]" , "op": "01001111|01|idx[1:0]|Vm:4|1100|idx[2]|0|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqdmulh Vd.2S, Vn.2S, Vm.S[#idx]" , "op": "00001111|10|idx[0] |Vm |1100|idx[1]|0|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqdmulh Vd.4S, Vn.4S, Vm.S[#idx]" , "op": "01001111|10|idx[0] |Vm |1100|idx[1]|0|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqdmull Sd, Hn, Hm" , "op": "01011110|01|1|Vm|11010|0|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqdmull Dd, Sn, Sm" , "op": "01011110|10|1|Vm|11010|0|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqdmull Sd, Hn, Vm.H[#idx]" , "op": "01011111|01|idx[1:0]|Vm:4|1011|idx[2]|0|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqdmull Dd, Sn, Vm.S[#idx]" , "op": "01011111|10|idx[0] |Vm |1011|idx[1]|0|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqdmull Vd.ta, Vn.tb, Vm.tb" , "op": "00001110|sz|1|Vm|10110|1|Vn|Vd" , "io": "QC|=SAT", "ta.tb": "~ 4S.4H 2D.2S"},
|
||
|
|
{"inst": "sqdmull2 Vd.ta, Vn.tb, Vm.tb" , "op": "01001110|sz|1|Vm|10110|1|Vn|Vd" , "io": "QC|=SAT", "ta.tb": "~ 4S.8H 2D.4S"},
|
||
|
|
{"inst": "sqdmull Vd.4S, Vn.4H, Vm.H[#idx]" , "op": "00001111|01|idx[1:0]|Vm:4|1011|idx[2]|0|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqdmull2 Vd.4S, Vn.8H, Vm.H[#idx]" , "op": "01001111|01|idx[1:0]|Vm:4|1011|idx[2]|0|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqdmull Vd.2D, Vn.2S, Vm.S[#idx]" , "op": "00001111|10|idx[0] |Vm |1011|idx[1]|0|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqdmull2 Vd.2D, Vn.4S, Vm.S[#idx]" , "op": "01001111|10|idx[0] |Vm |1011|idx[1]|0|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqneg Bd, Bn" , "op": "01111110|sz|10000|00111|10|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqneg Hd, Hn" , "op": "01111110|sz|10000|00111|10|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqneg Sd, Sn" , "op": "01111110|sz|10000|00111|10|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqneg Dd, Dn" , "op": "01111110|sz|10000|00111|10|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqneg Vd.t, Vn.t" , "op": "00101110|sz|10000|00111|10|Vn|Vd" , "io": "QC|=SAT", "t": "16B 8H 4S"},
|
||
|
|
{"inst": "sqneg Vd.t, Vn.t" , "op": "01101110|sz|10000|00111|10|Vn|Vd" , "io": "QC|=SAT", "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "sqrdmulh Hd, Hn, Hm" , "op": "01111110|01|1|Vm|10110|1|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqrdmulh Sd, Sn, Sm" , "op": "01111110|10|1|Vm|10110|1|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqrdmulh Hd, Hn, Vm.H[#idx]" , "op": "01011111|01|idx[1:0]|Vm:4|1101|idx[2]|0|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqrdmulh Sd, Sn, Vm.S[#idx]" , "op": "01011111|10|idx[0] |Vm |1101|idx[1]|0|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqrdmulh Vd.t, Vn.t, Vm.t" , "op": "00101110|sz|1|Vm|10110|1|Vn|Vd" , "io": "QC|=SAT", "t": "~ 4H 2S"},
|
||
|
|
{"inst": "sqrdmulh Vd.t, Vn.t, Vm.t" , "op": "01101110|sz|1|Vm|10110|1|Vn|Vd" , "io": "QC|=SAT", "t": "~ 8H 4S"},
|
||
|
|
{"inst": "sqrdmulh Vd.4H, Vn.4H, Vm.H[#idx]" , "op": "00001111|01|idx[1:0]|Vm:4|1101|idx[2]|0|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqrdmulh Vd.2S, Vn.2S, Vm.S[#idx]" , "op": "00001111|10|idx[0] |Vm |1101|idx[1]|0|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqrdmulh Vd.8H, Vn.8H, Vm.H[#idx]" , "op": "01001111|01|idx[1:0]|Vm:4|1101|idx[2]|0|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqrdmulh Vd.4S, Vn.4S, Vm.S[#idx]" , "op": "01001111|10|idx[0] |Vm |1101|idx[1]|0|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqrshl Bd, Bn, Bm" , "op": "01011110|00|1|Vm|01011|1|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqrshl Hd, Hn, Hm" , "op": "01011110|01|1|Vm|01011|1|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqrshl Sd, Sn, Sm" , "op": "01011110|10|1|Vm|01011|1|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqrshl Dd, Dn, Dm" , "op": "01011110|11|1|Vm|01011|1|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqrshl Vd.t, Vn.t, Vm.t" , "op": "00001110|sz|1|Vm|01011|1|Vn|Vd" , "io": "QC|=SAT", "t": "8B 4H 2S"},
|
||
|
|
{"inst": "sqrshl Vd.t, Vn.t, Vm.t" , "op": "01001110|sz|1|Vm|01011|1|Vn|Vd" , "io": "QC|=SAT", "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "sqrshrn Bd, Hn, #n" , "op": "01011111|0|immh:4|immb:3|10011|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 0)"},
|
||
|
|
{"inst": "sqrshrn Hd, Sn, #n" , "op": "01011111|0|immh:4|immb:3|10011|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 1)"},
|
||
|
|
{"inst": "sqrshrn Sd, Dn, #n" , "op": "01011111|0|immh:4|immb:3|10011|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 2)"},
|
||
|
|
{"inst": "sqrshrn Vd.8B, Vn.8H, #n" , "op": "00001111|0|immh:4|immb:3|10011|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 0)"},
|
||
|
|
{"inst": "sqrshrn2 Vx.16B, Vn.8H, #n" , "op": "01001111|0|immh:4|immb:3|10011|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 0)"},
|
||
|
|
{"inst": "sqrshrn Vd.4H, Vn.4S, #n" , "op": "00001111|0|immh:4|immb:3|10011|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 1)"},
|
||
|
|
{"inst": "sqrshrn2 Vx.8H, Vn.4S, #n" , "op": "01001111|0|immh:4|immb:3|10011|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 1)"},
|
||
|
|
{"inst": "sqrshrn Vd.2S, Vn.2D, #n" , "op": "00001111|0|immh:4|immb:3|10011|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 2)"},
|
||
|
|
{"inst": "sqrshrn2 Vx.4S, Vn.2D, #n" , "op": "01001111|0|immh:4|immb:3|10011|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 2)"},
|
||
|
|
{"inst": "sqrshrun Bd, Hn, #n" , "op": "01111111|0|immh:4|immb:3|10011|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 0)"},
|
||
|
|
{"inst": "sqrshrun Hd, Sn, #n" , "op": "01111111|0|immh:4|immb:3|10011|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 1)"},
|
||
|
|
{"inst": "sqrshrun Sd, Dn, #n" , "op": "01111111|0|immh:4|immb:3|10011|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 2)"},
|
||
|
|
{"inst": "sqrshrun Vd.8B, Vn.8H, #n" , "op": "00101111|0|immh:4|immb:3|10011|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 0)"},
|
||
|
|
{"inst": "sqrshrun2 Vx.16B, Vn.8H, #n" , "op": "01101111|0|immh:4|immb:3|10011|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 0)"},
|
||
|
|
{"inst": "sqrshrun Vd.4H, Vn.4S, #n" , "op": "00101111|0|immh:4|immb:3|10011|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 1)"},
|
||
|
|
{"inst": "sqrshrun2 Vx.8H, Vn.4S, #n" , "op": "01101111|0|immh:4|immb:3|10011|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 1)"},
|
||
|
|
{"inst": "sqrshrun Vd.2S, Vn.2D, #n" , "op": "00101111|0|immh:4|immb:3|10011|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 2)"},
|
||
|
|
{"inst": "sqrshrun2 Vx.4S, Vn.2D, #n" , "op": "01101111|0|immh:4|immb:3|10011|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 2)"},
|
||
|
|
{"inst": "sqshl Bd, Bn, Bm" , "op": "01011110|00|1|Vm|01001|1|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqshl Hd, Hn, Hm" , "op": "01011110|01|1|Vm|01001|1|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqshl Sd, Sn, Sm" , "op": "01011110|10|1|Vm|01001|1|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqshl Dd, Dn, Dm" , "op": "01011110|11|1|Vm|01001|1|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqshl Bd, Bn, #n" , "op": "01011111|0|immh:4|immb:3|01110|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftPImm(n, 0)"},
|
||
|
|
{"inst": "sqshl Hd, Hn, #n" , "op": "01011111|0|immh:4|immb:3|01110|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftPImm(n, 1)"},
|
||
|
|
{"inst": "sqshl Sd, Sn, #n" , "op": "01011111|0|immh:4|immb:3|01110|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftPImm(n, 2)"},
|
||
|
|
{"inst": "sqshl Dd, Dn, #n" , "op": "01011111|0|immh:4|immb:3|01110|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftPImm(n, 3)"},
|
||
|
|
{"inst": "sqshl Vd.t, Vn.t, Vm.t" , "op": "00001110|sz|1|Vm|01001|1|Vn|Vd" , "io": "QC|=SAT", "t": "8B 4H 2S"},
|
||
|
|
{"inst": "sqshl Vd.t, Vn.t, Vm.t" , "op": "01001110|sz|1|Vm|01001|1|Vn|Vd" , "io": "QC|=SAT", "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "sqshl Vd.t, Vn.t, #n" , "op": "00001111|0|immh:4|immb:3|01110|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftPImm(n, sz)", "t": "8B 4H 2S"},
|
||
|
|
{"inst": "sqshl Vd.t, Vn.t, #n" , "op": "01001111|0|immh:4|immb:3|01110|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftPImm(n, sz)", "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "sqshlu Bd, Bn, #n" , "op": "01111111|0|immh:4|immb:3|01100|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftPImm(n, 0)"},
|
||
|
|
{"inst": "sqshlu Hd, Hn, #n" , "op": "01111111|0|immh:4|immb:3|01100|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftPImm(n, 1)"},
|
||
|
|
{"inst": "sqshlu Sd, Sn, #n" , "op": "01111111|0|immh:4|immb:3|01100|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftPImm(n, 2)"},
|
||
|
|
{"inst": "sqshlu Dd, Dn, #n" , "op": "01111111|0|immh:4|immb:3|01100|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftPImm(n, 3)"},
|
||
|
|
{"inst": "sqshlu Vd.t, Vn.t, #n" , "op": "00101111|0|immh:4|immb:3|01100|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftPImm(n, sz)", "t": "8B 4H 2S"},
|
||
|
|
{"inst": "sqshlu Vd.t, Vn.t, #n" , "op": "01101111|0|immh:4|immb:3|01100|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftPImm(n, sz)", "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "sqshrn Bd, Hn, #n" , "op": "01011111|0|immh:4|immb:3|10010|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 0)"},
|
||
|
|
{"inst": "sqshrn Hd, Sn, #n" , "op": "01011111|0|immh:4|immb:3|10010|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 1)"},
|
||
|
|
{"inst": "sqshrn Sd, Dn, #n" , "op": "01011111|0|immh:4|immb:3|10010|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 2)"},
|
||
|
|
{"inst": "sqshrn Vd.ta, Vn.tb, #n" , "op": "00001111|0|immh:4|immb:3|10010|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 0)", "ta.tb": "8B.8H 4H.4S 2S.2D"},
|
||
|
|
{"inst": "sqshrn2 Vx.ta, Vn.tb, #n" , "op": "01001111|0|immh:4|immb:3|10010|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 1)", "ta.tb": "16B.8H 8H.4S 4S.2D"},
|
||
|
|
{"inst": "sqshrun Bd, Hn, #n" , "op": "01111111|0|immh:4|immb:3|10000|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 0)"},
|
||
|
|
{"inst": "sqshrun Hd, Sn, #n" , "op": "01111111|0|immh:4|immb:3|10000|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 1)"},
|
||
|
|
{"inst": "sqshrun Sd, Dn, #n" , "op": "01111111|0|immh:4|immb:3|10000|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 2)"},
|
||
|
|
{"inst": "sqshrun Vd.8B, Vn.8H, #n" , "op": "00101111|0|immh:4|immb:3|10000|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 0)"},
|
||
|
|
{"inst": "sqshrun2 Vx.16B, Vn.8H, #n" , "op": "01101111|0|immh:4|immb:3|10000|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 0)"},
|
||
|
|
{"inst": "sqshrun Vd.4H, Vn.4S, #n" , "op": "00101111|0|immh:4|immb:3|10000|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 1)"},
|
||
|
|
{"inst": "sqshrun2 Vx.8H, Vn.4S, #n" , "op": "01101111|0|immh:4|immb:3|10000|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 1)"},
|
||
|
|
{"inst": "sqshrun Vd.2S, Vn.2D, #n" , "op": "00101111|0|immh:4|immb:3|10000|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 2)"},
|
||
|
|
{"inst": "sqshrun2 Vx.4S, Vn.2D, #n" , "op": "01101111|0|immh:4|immb:3|10000|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 2)"},
|
||
|
|
{"inst": "sqsub Bd, Bn, Bm" , "op": "01011110|00|1|Vm|00101|1|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqsub Hd, Hn, Hm" , "op": "01011110|01|1|Vm|00101|1|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqsub Sd, Sn, Sm" , "op": "01011110|10|1|Vm|00101|1|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqsub Dd, Dn, Dm" , "op": "01011110|11|1|Vm|00101|1|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqsub Vd.t, Vn.t, Vm.t" , "op": "00001110|sz|1|Vm|00101|1|Vn|Vd" , "io": "QC|=SAT", "t": "16B 8H 4S"},
|
||
|
|
{"inst": "sqsub Vd.t, Vn.t, Vm.t" , "op": "01001110|sz|1|Vm|00101|1|Vn|Vd" , "io": "QC|=SAT", "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "sqxtn Bd, Hn" , "op": "01011110|00|10000|10100|10|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqxtn Hd, Sn" , "op": "01011110|01|10000|10100|10|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqxtn Sd, Dn" , "op": "01011110|10|10000|10100|10|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqxtn Vd.ta, Vn.tb" , "op": "00001110|sz|10000|10100|10|Vn|Vd" , "io": "QC|=SAT", "ta.tb": "8B.8H 4H.4S 2S.2D"},
|
||
|
|
{"inst": "sqxtn2 Vx.ta, Vn.tb" , "op": "01001110|sz|10000|10100|10|Vn|Vx" , "io": "QC|=SAT", "ta.tb": "16B.8H 8H.4S 4S.2D"},
|
||
|
|
{"inst": "sqxtun Bd, Hn" , "op": "01011110|00|10000|10100|10|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqxtun Hd, Sn" , "op": "01011110|01|10000|10100|10|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqxtun Sd, Dn" , "op": "01011110|10|10000|10100|10|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqxtun Vd.ta, Vn.tb" , "op": "00001110|sz|10000|10100|10|Vn|Vd" , "io": "QC|=SAT", "ta.tb": "8B.8H 4H.4S 2S.2D"},
|
||
|
|
{"inst": "sqxtun2 Vx.ta, Vn.tb" , "op": "01001110|sz|10000|10100|10|Vn|Vx" , "io": "QC|=SAT", "ta.tb": "16B.8H 8H.4S 4S.2D"},
|
||
|
|
{"inst": "srhadd Vd.t, Vn.t, Vm.t" , "op": "00001110|sz|1|Vm|00010|1|Vn|Vd" , "io": "QC|=SAT", "t": "16B 8H 4S"},
|
||
|
|
{"inst": "srhadd Vd.t, Vn.t, Vm.t" , "op": "01001110|sz|1|Vm|00010|1|Vn|Vd" , "io": "QC|=SAT", "t": "16B 8H 4S"},
|
||
|
|
{"inst": "sri Dx, Dn, #n" , "op": "01111111|0|immh:4|immb:3|01000|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 3)"},
|
||
|
|
{"inst": "sri Vx.t, Vn.t, #n" , "op": "00101111|0|immh:4|immb:3|01000|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, sz)", "t": "8B 4H 2S"},
|
||
|
|
{"inst": "sri Vx.t, Vn.t, #n" , "op": "01101111|0|immh:4|immb:3|01000|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, sz)", "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "srshl Dd, Dn, Dm" , "op": "01011110|11|1|Vm|01010|1|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "srshl Vd.t, Vn.t, Vm.t" , "op": "00001110|sz|1|Vm|01010|1|Vn|Vd" , "io": "QC|=SAT", "t": "8B 4H 2S"},
|
||
|
|
{"inst": "srshl Vd.t, Vn.t, Vm.t" , "op": "01001110|sz|1|Vm|01010|1|Vn|Vd" , "io": "QC|=SAT", "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "srshr Dd, Dn, #n" , "op": "01011111|0|immh:4|immb:3|00100|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 3)"},
|
||
|
|
{"inst": "srshr Vd.t, Vn.t, #n" , "op": "00001111|0|immh:4|immb:3|00100|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, sz)", "t": "8B 4H 2S"},
|
||
|
|
{"inst": "srshr Vd.t, Vn.t, #n" , "op": "01001111|0|immh:4|immb:3|00100|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, sz)", "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "srsra Dx, Dn, #n" , "op": "01011111|0|immh:4|immb:3|00110|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 3)"},
|
||
|
|
{"inst": "srsra Vx.t, Vn.t, #n" , "op": "00001111|0|immh:4|immb:3|00110|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, sz)", "t": "8B 4H 2S"},
|
||
|
|
{"inst": "srsra Vx.t, Vn.t, #n" , "op": "01001111|0|immh:4|immb:3|00110|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, sz)", "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "sshl Dd, Dn, Dm" , "op": "01011110|11|1|Vm|01000|1|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sshl Vd.t, Vn.t, Vm.t" , "op": "00001110|sz|1|Vm|01000|1|Vn|Vd" , "io": "QC|=SAT", "t": "8B 4H 2S"},
|
||
|
|
{"inst": "sshl Vd.t, Vn.t, Vm.t" , "op": "01001110|sz|1|Vm|01000|1|Vn|Vd" , "io": "QC|=SAT", "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "sshll Vd.ta, Vn.tb, #n" , "op": "00001111|0|immh:4|immb:3|10100|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftPImm(n, sz)", "ta.tb": "8H.8B 4S.4H 2D.2S"},
|
||
|
|
{"inst": "sshll2 Vd.ta, Vn.tb, #n" , "op": "01001111|0|immh:4|immb:3|10100|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftPImm(n, sz)", "ta.tb": "8H.16B 4S.8H 2D.4S"},
|
||
|
|
{"inst": "sshr Dd, Dn, #n" , "op": "01011111|0|immh:4|immb:3|00000|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 3)"},
|
||
|
|
{"inst": "sshr Vd.t, Vn.t, #n" , "op": "00001111|0|immh:4|immb:3|00000|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, sz)", "t": "8B 4H 2S"},
|
||
|
|
{"inst": "sshr Vd.t, Vn.t, #n" , "op": "01001111|0|immh:4|immb:3|00000|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, sz)", "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "ssra Dx, Dn, #n" , "op": "01011111|0|immh:4|immb:3|00010|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 3)"},
|
||
|
|
{"inst": "ssra Vx.t, Vn.t, #n" , "op": "00001111|0|immh:4|immb:3|00010|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, sz)", "t": "8B 4H 2S"},
|
||
|
|
{"inst": "ssra Vx.t, Vn.t, #n" , "op": "01001111|0|immh:4|immb:3|00010|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, sz)", "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "ssubl Vd.ta, Vn.tb, Vm.tb" , "op": "00001110|sz|1|Vm|00100|0|Vn|Vd" , "ta.tb": "8H.8B 4S.4H 2D.2S"},
|
||
|
|
{"inst": "ssubl2 Vd.ta, Vn.tb, Vm.tb" , "op": "01001110|sz|1|Vm|00100|0|Vn|Vd" , "ta.tb": "8H.16B 4S.8H 2D.4S"},
|
||
|
|
{"inst": "ssubw Vd.ta, Vn.ta, Vm.tb" , "op": "00001110|sz|1|Vm|00110|0|Vn|Vd" , "ta.tb": "8H.8B 4S.4H 2D.2S"},
|
||
|
|
{"inst": "ssubw2 Vd.ta, Vn.ta, Vm.tb" , "op": "01001110|sz|1|Vm|00110|0|Vn|Vd" , "ta.tb": "8H.16B 4S.8H 2D.4S"},
|
||
|
|
{"inst": "st1 Vs.B[#idx], [Xn|SP]" , "op": "0|idx:1|001101|000|00000|000|idx:3 |Rn|Vs"},
|
||
|
|
{"inst": "st1 Vs.H[#idx], [Xn|SP]" , "op": "0|idx:1|001101|000|00000|010|idx:2| 0|Rn|Vs"},
|
||
|
|
{"inst": "st1 Vs.S[#idx], [Xn|SP]" , "op": "0|idx:1|001101|000|00000|100|idx:1|00|Rn|Vs"},
|
||
|
|
{"inst": "st1 Vs.D[#idx], [Xn|SP]" , "op": "0|idx:1|001101|000|00000|100| 001|Rn|Vs"},
|
||
|
|
{"inst": "st1 Vs.B[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|100|Rm |000|idx:3 |Rn|Vs"},
|
||
|
|
{"inst": "st1 Vs.H[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|100|Rm |010|idx:2| 0|Rn|Vs"},
|
||
|
|
{"inst": "st1 Vs.S[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|100|Rm |100|idx:1|00|Rn|Vs"},
|
||
|
|
{"inst": "st1 Vs.D[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|100|Rm |100| 001|Rn|Vs"},
|
||
|
|
{"inst": "st1 Vs.B[#idx], [Xn|SP, #off=1]@" , "op": "0|idx:1|001101|100|11111|000|idx:3 |Rn|Vs"},
|
||
|
|
{"inst": "st1 Vs.H[#idx], [Xn|SP, #off=2]@" , "op": "0|idx:1|001101|100|11111|010|idx:2| 0|Rn|Vs"},
|
||
|
|
{"inst": "st1 Vs.S[#idx], [Xn|SP, #off=4]@" , "op": "0|idx:1|001101|100|11111|100|idx:1|00|Rn|Vs"},
|
||
|
|
{"inst": "st1 Vs.D[#idx], [Xn|SP, #off=8]@" , "op": "0|idx:1|001101|100|11111|100| 001|Rn|Vs"},
|
||
|
|
{"inst": "st1 1x{Vs.t}, [Xn|SP]" , "op": "00001100|000|00000|0111|sz|Rn|Vs" , "t": "8B 4H 2S 1D"},
|
||
|
|
{"inst": "st1 1x{Vs.t}, [Xn|SP]" , "op": "01001100|000|00000|0111|sz|Rn|Vs" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "st1 2x{Vs.t}+, [Xn|SP]" , "op": "00001100|000|00000|1010|sz|Rn|Vs" , "t": "8B 4H 2S 1D"},
|
||
|
|
{"inst": "st1 2x{Vs.t}+, [Xn|SP]" , "op": "01001100|000|00000|1010|sz|Rn|Vs" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "st1 3x{Vs.t}+, [Xn|SP]" , "op": "00001100|000|00000|0110|sz|Rn|Vs" , "t": "8B 4H 2S 1D"},
|
||
|
|
{"inst": "st1 3x{Vs.t}+, [Xn|SP]" , "op": "01001100|000|00000|0110|sz|Rn|Vs" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "st1 4x{Vs.t}+, [Xn|SP]" , "op": "00001100|000|00000|0010|sz|Rn|Vs" , "t": "8B 4H 2S 1D"},
|
||
|
|
{"inst": "st1 4x{Vs.t}+, [Xn|SP]" , "op": "01001100|000|00000|0010|sz|Rn|Vs" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "st1 1x{Vs.t}, [Xn|SP, Xm]@" , "op": "00001100|100|Rm |0111|sz|Rn|Vs" , "t": "8B 4H 2S 1D"},
|
||
|
|
{"inst": "st1 1x{Vs.t}, [Xn|SP, Xm]@" , "op": "01001100|100|Rm |0111|sz|Rn|Vs" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "st1 2x{Vs.t}+, [Xn|SP, Xm]@" , "op": "00001100|100|Rm |1010|sz|Rn|Vs" , "t": "8B 4H 2S 1D"},
|
||
|
|
{"inst": "st1 2x{Vs.t}+, [Xn|SP, Xm]@" , "op": "01001100|100|Rm |1010|sz|Rn|Vs" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "st1 3x{Vs.t}+, [Xn|SP, Xm]@" , "op": "00001100|100|Rm |0110|sz|Rn|Vs" , "t": "8B 4H 2S 1D"},
|
||
|
|
{"inst": "st1 3x{Vs.t}+, [Xn|SP, Xm]@" , "op": "01001100|100|Rm |0110|sz|Rn|Vs" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "st1 4x{Vs.t}+, [Xn|SP, Xm]@" , "op": "00001100|100|Rm |0010|sz|Rn|Vs" , "t": "8B 4H 2S 1D"},
|
||
|
|
{"inst": "st1 4x{Vs.t}+, [Xn|SP, Xm]@" , "op": "01001100|100|Rm |0010|sz|Rn|Vs" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "st1 1x{Vs.t}, [Xn|SP, #off==8]@" , "op": "00001100|100|11111|0111|sz|Rn|Vs" , "t": "8B 4H 2S 1D"},
|
||
|
|
{"inst": "st1 1x{Vs.t}, [Xn|SP, #off==16]@" , "op": "01001100|100|11111|0111|sz|Rn|Vs" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "st1 2x{Vs.t}+, [Xn|SP, #off==16]@" , "op": "00001100|100|11111|1010|sz|Rn|Vs" , "t": "8B 4H 2S 1D"},
|
||
|
|
{"inst": "st1 2x{Vs.t}+, [Xn|SP, #off==32]@" , "op": "01001100|100|11111|1010|sz|Rn|Vs" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "st1 3x{Vs.t}+, [Xn|SP, #off==24]@" , "op": "00001100|100|11111|0110|sz|Rn|Vs" , "t": "8B 4H 2S 1D"},
|
||
|
|
{"inst": "st1 3x{Vs.t}+, [Xn|SP, #off==48]@" , "op": "01001100|100|11111|0110|sz|Rn|Vs" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "st1 4x{Vs.t}+, [Xn|SP, #off==32]@" , "op": "00001100|100|11111|0010|sz|Rn|Vs" , "t": "8B 4H 2S 1D"},
|
||
|
|
{"inst": "st1 4x{Vs.t}+, [Xn|SP, #off==64]@" , "op": "01001100|100|11111|0010|sz|Rn|Vs" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "st2 2x{Vs.B}+[#idx], [Xn|SP]" , "op": "0|idx:1|001101|001|00000|000|idx:3 |Rn|Vs"},
|
||
|
|
{"inst": "st2 2x{Vs.H}+[#idx], [Xn|SP]" , "op": "0|idx:1|001101|001|00000|010|idx:2| 0|Rn|Vs"},
|
||
|
|
{"inst": "st2 2x{Vs.S}+[#idx], [Xn|SP]" , "op": "0|idx:1|001101|001|00000|100|idx:1|00|Rn|Vs"},
|
||
|
|
{"inst": "st2 2x{Vs.D}+[#idx], [Xn|SP]" , "op": "0|idx:1|001101|001|00000|100| 001|Rn|Vs"},
|
||
|
|
{"inst": "st2 2x{Vs.B}+[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|101|Rm |000|idx:3 |Rn|Vs"},
|
||
|
|
{"inst": "st2 2x{Vs.H}+[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|101|Rm |010|idx:2| 0|Rn|Vs"},
|
||
|
|
{"inst": "st2 2x{Vs.S}+[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|101|Rm |100|idx:1|00|Rn|Vs"},
|
||
|
|
{"inst": "st2 2x{Vs.D}+[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|101|Rm |100| 001|Rn|Vs"},
|
||
|
|
{"inst": "st2 2x{Vs.B}+[#idx], [Xn|SP, #off=2]@" , "op": "0|idx:1|001101|101|11111|000|idx:3 |Rn|Vs"},
|
||
|
|
{"inst": "st2 2x{Vs.H}+[#idx], [Xn|SP, #off=4]@" , "op": "0|idx:1|001101|101|11111|010|idx:2| 0|Rn|Vs"},
|
||
|
|
{"inst": "st2 2x{Vs.S}+[#idx], [Xn|SP, #off=8]@" , "op": "0|idx:1|001101|101|11111|100|idx:1|00|Rn|Vs"},
|
||
|
|
{"inst": "st2 2x{Vs.D}+[#idx], [Xn|SP, #off=16]@" , "op": "0|idx:1|001101|101|11111|100| 001|Rn|Vs"},
|
||
|
|
{"inst": "st2 2x{Vs.t}+, [Xn|SP]" , "op": "00001100|000|00000|1000|sz|Rn|Vs" , "t": "8B 4H 2S"},
|
||
|
|
{"inst": "st2 2x{Vs.t}+, [Xn|SP]" , "op": "01001100|000|00000|1000|sz|Rn|Vs" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "st2 2x{Vs.t}+, [Xn|SP, Xm]@" , "op": "00001100|100|Rm |1000|sz|Rn|Vs" , "t": "8B 4H 2S"},
|
||
|
|
{"inst": "st2 2x{Vs.t}+, [Xn|SP, Xm]@" , "op": "01001100|100|Rm |1000|sz|Rn|Vs" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "st2 2x{Vs.t}+, [Xn|SP, #off==16]@" , "op": "00001100|100|11111|1000|sz|Rn|Vs" , "t": "8B 4H 2S"},
|
||
|
|
{"inst": "st2 2x{Vs.t}+, [Xn|SP, #off==32]@" , "op": "01001100|100|11111|1000|sz|Rn|Vs" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "st3 3x{Vs.B}+[#idx], [Xn|SP]" , "op": "0|idx:1|001101|000|00000|001|idx:3 |Rn|Vs"},
|
||
|
|
{"inst": "st3 3x{Vs.H}+[#idx], [Xn|SP]" , "op": "0|idx:1|001101|000|00000|011|idx:2| 0|Rn|Vs"},
|
||
|
|
{"inst": "st3 3x{Vs.S}+[#idx], [Xn|SP]" , "op": "0|idx:1|001101|000|00000|101|idx:1|00|Rn|Vs"},
|
||
|
|
{"inst": "st3 3x{Vs.D}+[#idx], [Xn|SP]" , "op": "0|idx:1|001101|000|00000|101| 001|Rn|Vs"},
|
||
|
|
{"inst": "st3 3x{Vs.B}+[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|100|Rm |001|idx:3 |Rn|Vs"},
|
||
|
|
{"inst": "st3 3x{Vs.H}+[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|100|Rm |011|idx:2| 0|Rn|Vs"},
|
||
|
|
{"inst": "st3 3x{Vs.S}+[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|100|Rm |101|idx:1|00|Rn|Vs"},
|
||
|
|
{"inst": "st3 3x{Vs.D}+[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|100|Rm |101| 001|Rn|Vs"},
|
||
|
|
{"inst": "st3 3x{Vs.B}+[#idx], [Xn|SP, #off=3]@" , "op": "0|idx:1|001101|100|11111|001|idx:3 |Rn|Vs"},
|
||
|
|
{"inst": "st3 3x{Vs.H}+[#idx], [Xn|SP, #off=6]@" , "op": "0|idx:1|001101|100|11111|011|idx:2| 0|Rn|Vs"},
|
||
|
|
{"inst": "st3 3x{Vs.S}+[#idx], [Xn|SP, #off=12]@" , "op": "0|idx:1|001101|100|11111|101|idx:1|00|Rn|Vs"},
|
||
|
|
{"inst": "st3 3x{Vs.D}+[#idx], [Xn|SP, #off=24]@" , "op": "0|idx:1|001101|100|11111|101| 001|Rn|Vs"},
|
||
|
|
{"inst": "st3 3x{Vs.t}+, [Xn|SP]" , "op": "00001100|000|00000|0100|sz|Rn|Vs" , "t": "8B 4H 2S"},
|
||
|
|
{"inst": "st3 3x{Vs.t}+, [Xn|SP]" , "op": "01001100|000|00000|0100|sz|Rn|Vs" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "st3 3x{Vs.t}+, [Xn|SP, Xm]@" , "op": "00001100|100|Rm |0100|sz|Rn|Vs" , "t": "8B 4H 2S"},
|
||
|
|
{"inst": "st3 3x{Vs.t}+, [Xn|SP, Xm]@" , "op": "01001100|100|Rm |0100|sz|Rn|Vs" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "st3 3x{Vs.t}+, [Xn|SP, #off==16]@" , "op": "00001100|100|11111|0100|sz|Rn|Vs" , "t": "8B 4H 2S"},
|
||
|
|
{"inst": "st3 3x{Vs.t}+, [Xn|SP, #off==32]@" , "op": "01001100|100|11111|0100|sz|Rn|Vs" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "st4 4x{Vs.B}+[#idx], [Xn|SP]" , "op": "0|idx:1|001101|001|00000|001|idx:3 |Rn|Vs"},
|
||
|
|
{"inst": "st4 4x{Vs.H}+[#idx], [Xn|SP]" , "op": "0|idx:1|001101|001|00000|011|idx:2| 0|Rn|Vs"},
|
||
|
|
{"inst": "st4 4x{Vs.S}+[#idx], [Xn|SP]" , "op": "0|idx:1|001101|001|00000|101|idx:1|00|Rn|Vs"},
|
||
|
|
{"inst": "st4 4x{Vs.D}+[#idx], [Xn|SP]" , "op": "0|idx:1|001101|001|00000|101| 001|Rn|Vs"},
|
||
|
|
{"inst": "st4 4x{Vs.B}+[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|100|Rm |001|idx:3 |Rn|Vs"},
|
||
|
|
{"inst": "st4 4x{Vs.H}+[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|100|Rm |011|idx:2| 0|Rn|Vs"},
|
||
|
|
{"inst": "st4 4x{Vs.S}+[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|100|Rm |101|idx:1|00|Rn|Vs"},
|
||
|
|
{"inst": "st4 4x{Vs.D}+[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|100|Rm |101| 001|Rn|Vs"},
|
||
|
|
{"inst": "st4 4x{Vs.B}+[#idx], [Xn|SP, #off=4]@" , "op": "0|idx:1|001101|100|11111|001|idx:3 |Rn|Vs"},
|
||
|
|
{"inst": "st4 4x{Vs.H}+[#idx], [Xn|SP, #off=8]@" , "op": "0|idx:1|001101|100|11111|011|idx:2| 0|Rn|Vs"},
|
||
|
|
{"inst": "st4 4x{Vs.S}+[#idx], [Xn|SP, #off=16]@" , "op": "0|idx:1|001101|100|11111|101|idx:1|00|Rn|Vs"},
|
||
|
|
{"inst": "st4 4x{Vs.D}+[#idx], [Xn|SP, #off=32]@" , "op": "0|idx:1|001101|100|11111|101| 001|Rn|Vs"},
|
||
|
|
{"inst": "st4 4x{Vs.t}+, [Xn|SP]" , "op": "00001100|000|00000|0000|sz|Rn|Vs" , "t": "8B 4H 2S"},
|
||
|
|
{"inst": "st4 4x{Vs.t}+, [Xn|SP]" , "op": "01001100|000|00000|0000|sz|Rn|Vs" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "st4 4x{Vs.t}+, [Xn|SP, Xm]@" , "op": "00001100|100|Rm |0000|sz|Rn|Vs" , "t": "8B 4H 2S"},
|
||
|
|
{"inst": "st4 4x{Vs.t}+, [Xn|SP, Xm]@" , "op": "01001100|100|Rm |0000|sz|Rn|Vs" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "st4 4x{Vs.t}+, [Xn|SP, #off==32]@" , "op": "00001100|100|11111|0000|sz|Rn|Vs" , "t": "8B 4H 2S"},
|
||
|
|
{"inst": "st4 4x{Vs.t}+, [Xn|SP, #off==64]@" , "op": "01001100|100|11111|0000|sz|Rn|Vs" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "stnp Sd, Sd2, [Xn|SP, #soff*4]" , "op": "00101100|00|soff:7|Vs2|Vn|Vs"},
|
||
|
|
{"inst": "stnp Dd, Dd2, [Xn|SP, #soff*8]" , "op": "01101100|00|soff:7|Vs2|Vn|Vs"},
|
||
|
|
{"inst": "stnp Qd, Qd2, [Xn|SP, #soff*16]" , "op": "10101100|00|soff:7|Vs2|Vn|Vs"},
|
||
|
|
{"inst": "stp Sd, Sd2, [Xn|SP, #soff*4]{@}{!}" , "op": "0010110|!post|W|0|soff:7|Vs2|Vn|Vs"},
|
||
|
|
{"inst": "stp Dd, Dd2, [Xn|SP, #soff*8]{@}{!}" , "op": "0110110|!post|W|0|soff:7|Vs2|Vn|Vs"},
|
||
|
|
{"inst": "stp Qd, Qd2, [Xn|SP, #soff*16]{@}{!}" , "op": "1010110|!post|W|0|soff:7|Vs2|Vn|Vs"},
|
||
|
|
{"inst": "str Bd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "00111100|001|Rm|option:3|n:1|10|Rn|Vs"},
|
||
|
|
{"inst": "str Hd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "01111100|001|Rm|option:3|n:1|10|Rn|Vs"},
|
||
|
|
{"inst": "str Sd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n*2}]" , "op": "10111100|001|Rm|option:3|n:1|10|Rn|Vs"},
|
||
|
|
{"inst": "str Dd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n*3}]" , "op": "11111100|001|Rm|option:3|n:1|10|Rn|Vs"},
|
||
|
|
{"inst": "str Qd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n*4}]" , "op": "00111100|101|Rm|option:3|n:1|10|Rn|Vs"},
|
||
|
|
{"inst": "str Bd, [Xn|SP, #zoff]" , "op": "00111101|00|zoff:12|Rn|Vs"},
|
||
|
|
{"inst": "str Hd, [Xn|SP, #zoff*2]" , "op": "01111101|00|zoff:12|Rn|Vs"},
|
||
|
|
{"inst": "str Sd, [Xn|SP, #zoff*4]" , "op": "10111101|00|zoff:12|Rn|Vs"},
|
||
|
|
{"inst": "str Dd, [Xn|SP, #zoff*8]" , "op": "11111101|00|zoff:12|Rn|Vs"},
|
||
|
|
{"inst": "str Qd, [Xn|SP, #zoff*16]" , "op": "00111101|10|zoff:12|Rn|Vs"},
|
||
|
|
{"inst": "str Bd, [Xn|SP, #soff]!" , "op": "00111100|000|soff:9|11|Rn|Vs"},
|
||
|
|
{"inst": "str Hd, [Xn|SP, #soff*2]!" , "op": "01111100|000|soff:9|11|Rn|Vs"},
|
||
|
|
{"inst": "str Sd, [Xn|SP, #soff*4]!" , "op": "10111100|000|soff:9|11|Rn|Vs"},
|
||
|
|
{"inst": "str Dd, [Xn|SP, #soff*8]!" , "op": "11111100|000|soff:9|11|Rn|Vs"},
|
||
|
|
{"inst": "str Qd, [Xn|SP, #soff*16]!" , "op": "00111100|100|soff:9|11|Rn|Vs"},
|
||
|
|
{"inst": "str Bd, [Xn|SP, #soff]@" , "op": "00111100|000|soff:9|01|Rn|Vs"},
|
||
|
|
{"inst": "str Hd, [Xn|SP, #soff*2]@" , "op": "01111100|000|soff:9|01|Rn|Vs"},
|
||
|
|
{"inst": "str Sd, [Xn|SP, #soff*4]@" , "op": "10111100|000|soff:9|01|Rn|Vs"},
|
||
|
|
{"inst": "str Dd, [Xn|SP, #soff*8]@" , "op": "11111100|000|soff:9|01|Rn|Vs"},
|
||
|
|
{"inst": "str Qd, [Xn|SP, #soff*16]@" , "op": "00111100|100|soff:9|01|Rn|Vs"},
|
||
|
|
{"inst": "stur Bd, [Xn|SP, #soff]" , "op": "00111100|000|soff:9|00|Rn|Vs"},
|
||
|
|
{"inst": "stur Hd, [Xn|SP, #soff]" , "op": "01111100|000|soff:9|00|Rn|Vs"},
|
||
|
|
{"inst": "stur Sd, [Xn|SP, #soff]" , "op": "10111100|000|soff:9|00|Rn|Vs"},
|
||
|
|
{"inst": "stur Dd, [Xn|SP, #soff]" , "op": "11111100|000|soff:9|00|Rn|Vs"},
|
||
|
|
{"inst": "stur Qd, [Xn|SP, #soff]" , "op": "00111100|100|soff:9|00|Rn|Vs"},
|
||
|
|
{"inst": "sub Dd, Dn, Dm" , "op": "01111110|11|1|Vm|10000|1|Vn|Vd"},
|
||
|
|
{"inst": "sub Vd.t, Vn.t, Vm.t" , "op": "00101110|sz|1|Vm|10000|1|Vn|Vd" , "t": "8B 4H 2S"},
|
||
|
|
{"inst": "sub Vd.t, Vn.t, Vm.t" , "op": "01101110|sz|1|Vm|10000|1|Vn|Vd" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "subhn Vd.ta, Vn.tb, Vm.tb" , "op": "00001110|sz|1|Vm|01100|0|Vn|Vd" , "ta.tb": "8B.8H 4H.4S 2S.2D"},
|
||
|
|
{"inst": "subhn2 Vx.ta, Vn.tb, Vm.tb" , "op": "01001110|sz|1|Vm|01100|0|Vn|Vx" , "ta.tb": "16B.8H 8H.4S 4S.2D"},
|
||
|
|
{"inst": "suqadd Bx, Bn" , "op": "01011110|sz|10000|00011|10|Vn|Vx" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "suqadd Hx, Hn" , "op": "01011110|sz|10000|00011|10|Vn|Vx" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "suqadd Sx, Sn" , "op": "01011110|sz|10000|00011|10|Vn|Vx" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "suqadd Dx, Dn" , "op": "01011110|sz|10000|00011|10|Vn|Vx" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "suqadd Vx.t, Vn.t" , "op": "00001110|sz|10000|00011|10|Vn|Vx" , "io": "QC|=SAT", "t": "16B 8H 4S"},
|
||
|
|
{"inst": "suqadd Vx.t, Vn.t" , "op": "01001110|sz|10000|00011|10|Vn|Vx" , "io": "QC|=SAT", "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "sxtl Vd.ta, Vn.tb" , "op": "00001111|0|immh:4|000|10100|1|Vn|Vd" , "imm": "ASimdXtlImm(sz)", "ta.tb": "8H.8B 4S.4H 2D.2S" },
|
||
|
|
{"inst": "sxtl2 Vd.ta, Vn.tb" , "op": "01001111|0|immh:4|000|10100|1|Vn|Vd" , "imm": "ASimdXtlImm(sz)", "ta.tb": "8H.16B 4S.8H 2D.4S"},
|
||
|
|
{"inst": "tbl Vd.8B, Vn.16B, Vm.8B" , "op": "00001110|00|0|Vm|0|00|000|Vn|Vd"},
|
||
|
|
{"inst": "tbl Vd.16B, Vn.16B, Vm.16B" , "op": "01001110|00|0|Vm|0|00|000|Vn|Vd"},
|
||
|
|
{"inst": "tbl Vd.8B, 2x{Vn.16B}+, Vm.8B" , "op": "00001110|00|0|Vm|0|01|000|Vn|Vd"},
|
||
|
|
{"inst": "tbl Vd.16B, 2x{Vn.16B}+, Vm.16B" , "op": "01001110|00|0|Vm|0|01|000|Vn|Vd"},
|
||
|
|
{"inst": "tbl Vd.8B, 3x{Vn.16B}+, Vm.8B" , "op": "00001110|00|0|Vm|0|10|000|Vn|Vd"},
|
||
|
|
{"inst": "tbl Vd.16B, 3x{Vn.16B}+, Vm.16B" , "op": "01001110|00|0|Vm|0|10|000|Vn|Vd"},
|
||
|
|
{"inst": "tbl Vd.8B, 4x{Vn.16B}+, Vm.8B" , "op": "00001110|00|0|Vm|0|11|000|Vn|Vd"},
|
||
|
|
{"inst": "tbl Vd.16B, 4x{Vn.16B}+, Vm.16B" , "op": "01001110|00|0|Vm|0|11|000|Vn|Vd"},
|
||
|
|
{"inst": "tbx Vx.8B, Vn.16B, Vm.8B" , "op": "00001110|00|0|Vm|0|00|100|Vn|Vx"},
|
||
|
|
{"inst": "tbx Vx.16B, Vn.16B, Vm.16B" , "op": "01001110|00|0|Vm|0|00|100|Vn|Vx"},
|
||
|
|
{"inst": "tbx Vx.8B, 2x{Vn.16B}+, Vm.8B" , "op": "00001110|00|0|Vm|0|01|100|Vn|Vx"},
|
||
|
|
{"inst": "tbx Vx.16B, 2x{Vn.16B}+, Vm.16B" , "op": "01001110|00|0|Vm|0|01|100|Vn|Vx"},
|
||
|
|
{"inst": "tbx Vx.8B, 3x{Vn.16B}+, Vm.8B" , "op": "00001110|00|0|Vm|0|10|100|Vn|Vx"},
|
||
|
|
{"inst": "tbx Vx.16B, 3x{Vn.16B}+, Vm.16B" , "op": "01001110|00|0|Vm|0|10|100|Vn|Vx"},
|
||
|
|
{"inst": "tbx Vx.8B, 4x{Vn.16B}+, Vm.8B" , "op": "00001110|00|0|Vm|0|11|100|Vn|Vx"},
|
||
|
|
{"inst": "tbx Vx.16B, 4x{Vn.16B}+, Vm.16B" , "op": "01001110|00|0|Vm|0|11|100|Vn|Vx"},
|
||
|
|
{"inst": "trn1 Vd.t, Vn.t, Vm.t" , "op": "00001110|sz|0|Vm|00101|0|Vn|Vd" , "t": "8B 4H 2S"},
|
||
|
|
{"inst": "trn1 Vd.t, Vn.t, Vm.t" , "op": "01001110|sz|0|Vm|00101|0|Vn|Vd" , "t": "16B 8H 4S"},
|
||
|
|
{"inst": "trn2 Vd.t, Vn.t, Vm.t" , "op": "00001110|sz|0|Vm|01101|0|Vn|Vd" , "t": "8B 4H 2S"},
|
||
|
|
{"inst": "trn2 Vd.t, Vn.t, Vm.t" , "op": "01001110|sz|0|Vm|01101|0|Vn|Vd" , "t": "16B 8H 4S"},
|
||
|
|
{"inst": "uaba Vx.t, Vn.t, Vm.t" , "op": "00101110|sz|1|Vm|01111|1|Vn|Vx" , "t": "8B 4H 2S"},
|
||
|
|
{"inst": "uaba Vx.t, Vn.t, Vm.t" , "op": "01101110|sz|1|Vm|01111|1|Vn|Vx" , "t": "16B 8H 4S"},
|
||
|
|
{"inst": "uabal Vx.ta, Vn.tb, Vm.tb" , "op": "00101110|sz|1|Vm|01010|0|Vn|Vx" , "ta.tb": "8H.8B 4S.4H 2D.2S"},
|
||
|
|
{"inst": "uabal2 Vx.ta, Vn.tb, Vm.tb" , "op": "01101110|sz|1|Vm|01010|0|Vn|Vx" , "ta.tb": "8H.16B 4S.8H 2D.4S"},
|
||
|
|
{"inst": "uabd Vd.t, Vn.t, Vm.t" , "op": "00101110|sz|1|Vm|01110|1|Vn|Vd" , "t": "8B 4H 2S"},
|
||
|
|
{"inst": "uabd Vd.t, Vn.t, Vm.t" , "op": "01101110|sz|1|Vm|01110|1|Vn|Vd" , "t": "16B 8H 4S"},
|
||
|
|
{"inst": "uabdl Vd.ta, Vn.tb, Vm.tb" , "op": "00101110|sz|1|Vm|01110|0|Vn|Vd" , "ta.tb": "8H.8B 4S.4H 2D.2S"},
|
||
|
|
{"inst": "uabdl2 Vd.ta, Vn.tb, Vm.tb" , "op": "01101110|sz|1|Vm|01110|0|Vn|Vd" , "ta.tb": "8H.16B 4S.8H 2D.4S"},
|
||
|
|
{"inst": "uadalp Vx.ta, Vn.tb" , "op": "00101110|sz|10000|00110|10|Vn|Vx" , "ta.tb": "4H.8B 2S.4H 1D.2S"},
|
||
|
|
{"inst": "uadalp Vx.ta, Vn.tb" , "op": "01101110|sz|10000|00110|10|Vn|Vx" , "ta.tb": "8H.16B 4S.8H 2D.4S"},
|
||
|
|
{"inst": "uaddl Vd.ta, Vn.tb, Vm.tb" , "op": "00101110|sz|1|Vm|00000|0|Vn|Vd" , "ta.tb": "8H.8B 4S.4H 2D.2S"},
|
||
|
|
{"inst": "uaddl2 Vd.ta, Vn.tb, Vm.tb" , "op": "01101110|sz|1|Vm|00000|0|Vn|Vd" , "ta.tb": "8H.16B 4S.8H 2D.4S"},
|
||
|
|
{"inst": "uaddlp Vd.ta, Vn.tb" , "op": "00101110|sz|10000|00010|10|Vn|Vd" , "ta.tb": "4H.8B 2S.4H 1D.2S"},
|
||
|
|
{"inst": "uaddlp Vd.ta, Vn.tb" , "op": "01101110|sz|10000|00010|10|Vn|Vd" , "ta.tb": "8H.16B 4S.8H 2D.4S"},
|
||
|
|
{"inst": "uaddlv Hd, Vn.8B" , "op": "00101110|00|11000|00011|10|Vn|Vd"},
|
||
|
|
{"inst": "uaddlv Hd, Vn.16B" , "op": "01101110|00|11000|00011|10|Vn|Vd"},
|
||
|
|
{"inst": "uaddlv Sd, Vn.4H" , "op": "00101110|01|11000|00011|10|Vn|Vd"},
|
||
|
|
{"inst": "uaddlv Sd, Vn.8H" , "op": "01101110|01|11000|00011|10|Vn|Vd"},
|
||
|
|
{"inst": "uaddlv Dd, Vn.4S" , "op": "01101110|10|11000|00011|10|Vn|Vd"},
|
||
|
|
{"inst": "uaddw Vd.ta, Vn.ta, Vm.tb" , "op": "00101110|sz|1|Vm|00010|0|Vn|Vd" , "ta.tb": "8H.8B 4S.4H 2D.2S"},
|
||
|
|
{"inst": "uaddw2 Vd.ta, Vn.ta, Vm.tb" , "op": "01101110|sz|1|Vm|00010|0|Vn|Vd" , "ta.tb": "8H.16B 4S.8H 2D.4S"},
|
||
|
|
{"inst": "ucvtf Sd, Wn" , "op": "00011110|00|1|00011|00000|0|Rn|Vd"},
|
||
|
|
{"inst": "ucvtf Sd, Wn, #fbits" , "op": "00011110|00|0|00011|scale:6|Rn|Vd" , "imm": "ASimdFBitsScaleImm(fbits, 32)"},
|
||
|
|
{"inst": "ucvtf Sd, Xn" , "op": "10011110|00|1|00011|00000|0|Rn|Vd"},
|
||
|
|
{"inst": "ucvtf Sd, Xn, #fbits" , "op": "10011110|00|0|00011|scale:6|Rn|Vd" , "imm": "ASimdFBitsScaleImm(fbits, 64)"},
|
||
|
|
{"inst": "ucvtf Sd, Sn" , "op": "01111110|00|10000|11101|10|Vn|Vd"},
|
||
|
|
{"inst": "ucvtf Sd, Sn, #bits" , "op": "01111111|0|immh:4|immb:3|11100|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 32)"},
|
||
|
|
{"inst": "ucvtf Dd, Wn" , "op": "00011110|01|1|00011|00000|0|Rn|Vd"},
|
||
|
|
{"inst": "ucvtf Dd, Wn, #fbits" , "op": "00011110|01|0|00011|scale:6|Rn|Vd" , "imm": "ASimdFBitsScaleImm(fbits, 32)"},
|
||
|
|
{"inst": "ucvtf Dd, Xn" , "op": "10011110|01|1|00011|00000|0|Rn|Vd"},
|
||
|
|
{"inst": "ucvtf Dd, Xn, #fbits" , "op": "10011110|01|0|00011|scale:6|Rn|Vd" , "imm": "ASimdFBitsScaleImm(fbits, 64)"},
|
||
|
|
{"inst": "ucvtf Dd, Dn" , "op": "01111110|01|10000|11101|10|Vn|Vd"},
|
||
|
|
{"inst": "ucvtf Dd, Dn, #bits" , "op": "01111111|0|immh:4|immb:3|11100|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 64)"},
|
||
|
|
{"inst": "ucvtf Vd.2S, Vn.2S" , "op": "00101110|00|10000|11101|10|Vn|Vd"},
|
||
|
|
{"inst": "ucvtf Vd.4S, Vn.4S" , "op": "01101110|00|10000|11101|10|Vn|Vd"},
|
||
|
|
{"inst": "ucvtf Vd.2D, Vn.2D" , "op": "01101110|01|10000|11101|10|Vn|Vd"},
|
||
|
|
{"inst": "ucvtf Vd.2S, Vn.2S, #fbits" , "op": "00101111|0|immh:4|immb:3|11100|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 32)"},
|
||
|
|
{"inst": "ucvtf Vd.4S, Vn.4S, #fbits" , "op": "01101111|0|immh:4|immb:3|11100|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 32)"},
|
||
|
|
{"inst": "ucvtf Vd.2D, Vn.2D, #fbits" , "op": "01101111|0|immh:4|immb:3|11100|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 64)"},
|
||
|
|
{"inst": "uhadd Vd.t, Vn.t, Vm.t" , "op": "00101110|sz|1|Vm|00000|1|Vn|Vd" , "t": "8B 4H 2S"},
|
||
|
|
{"inst": "uhadd Vd.t, Vn.t, Vm.t" , "op": "01101110|sz|1|Vm|00000|1|Vn|Vd" , "t": "16B 8H 4S"},
|
||
|
|
{"inst": "uhsub Vd.t, Vn.t, Vm.t" , "op": "00101110|sz|1|Vm|00100|1|Vn|Vd" , "t": "8B 4H 2S"},
|
||
|
|
{"inst": "uhsub Vd.t, Vn.t, Vm.t" , "op": "01101110|sz|1|Vm|00100|1|Vn|Vd" , "t": "16B 8H 4S"},
|
||
|
|
{"inst": "umax Vd.t, Vn.t, Vm.t" , "op": "00101110|sz|1|Vm|01100|1|Vn|Vd" , "t": "8B 4H 2S"},
|
||
|
|
{"inst": "umax Vd.t, Vn.t, Vm.t" , "op": "01101110|sz|1|Vm|01100|1|Vn|Vd" , "t": "16B 8H 4S"},
|
||
|
|
{"inst": "umaxp Vd.t, Vn.t, Vm.t" , "op": "00101110|sz|1|Vm|10100|1|Vn|Vd" , "t": "8B 4H 2S"},
|
||
|
|
{"inst": "umaxp Vd.t, Vn.t, Vm.t" , "op": "01101110|sz|1|Vm|10100|1|Vn|Vd" , "t": "16B 8H 4S"},
|
||
|
|
{"inst": "umaxv Bd, Vn.8B" , "op": "00101110|00|11000|01010|10|Vn|Vd"},
|
||
|
|
{"inst": "umaxv Bd, Vn.16B" , "op": "01101110|00|11000|01010|10|Vn|Vd"},
|
||
|
|
{"inst": "umaxv Hd, Vn.4H" , "op": "00101110|01|11000|01010|10|Vn|Vd"},
|
||
|
|
{"inst": "umaxv Hd, Vn.8H" , "op": "01101110|01|11000|01010|10|Vn|Vd"},
|
||
|
|
{"inst": "umaxv Sd, Vn.4S" , "op": "01101110|10|11000|01010|10|Vn|Vd"},
|
||
|
|
{"inst": "umin Vd.t, Vn.t, Vm.t" , "op": "00101110|sz|1|Vm|01101|1|Vn|Vd" , "t": "8B 4H 2S"},
|
||
|
|
{"inst": "umin Vd.t, Vn.t, Vm.t" , "op": "01101110|sz|1|Vm|01101|1|Vn|Vd" , "t": "16B 8H 4S"},
|
||
|
|
{"inst": "uminp Vd.t, Vn.t, Vm.t" , "op": "00101110|sz|1|Vm|10101|1|Vn|Vd" , "t": "8B 4H 2S"},
|
||
|
|
{"inst": "uminp Vd.t, Vn.t, Vm.t" , "op": "01101110|sz|1|Vm|10101|1|Vn|Vd" , "t": "16B 8H 4S"},
|
||
|
|
{"inst": "uminv Bd, Vn.8B" , "op": "00101110|00|11000|11010|10|Vn|Vd"},
|
||
|
|
{"inst": "uminv Bd, Vn.16B" , "op": "01101110|00|11000|11010|10|Vn|Vd"},
|
||
|
|
{"inst": "uminv Hd, Vn.4H" , "op": "00101110|01|11000|11010|10|Vn|Vd"},
|
||
|
|
{"inst": "uminv Hd, Vn.8H" , "op": "01101110|01|11000|11010|10|Vn|Vd"},
|
||
|
|
{"inst": "uminv Sd, Vn.4S" , "op": "01101110|10|11000|11010|10|Vn|Vd"},
|
||
|
|
{"inst": "umlal Vd.ta, Vn.tb, Vm.tb" , "op": "00101110|sz|1|Vm|10000|0|Vn|Vd" , "t": "8H.8B 4S.4H 2D.2S"},
|
||
|
|
{"inst": "umlal2 Vd.ta, Vn.tb, Vm.tb" , "op": "01101110|sz|1|Vm|10000|0|Vn|Vd" , "t": "8H.16B 4S.8H 2D.4S"},
|
||
|
|
{"inst": "umlal Vd.4S, Vn.4H, Vm.H[#dx]" , "op": "00101111|01|idx[1:0]|Vm:4|0010|idx[2]|0|Vn|Vd"},
|
||
|
|
{"inst": "umlal2 Vd.4S, Vn.8H, Vm.H[#dx]" , "op": "01101111|01|idx[1:0]|Vm:4|0010|idx[2]|0|Vn|Vd"},
|
||
|
|
{"inst": "umlal Vd.2D, Vn.2S, Vm.S[#dx]" , "op": "00101111|10|idx[0] |Vm |0010|idx[1]|0|Vn|Vd"},
|
||
|
|
{"inst": "umlal2 Vd.2D, Vn.4S, Vm.S[#dx]" , "op": "01101111|10|idx[0] |Vm |0010|idx[1]|0|Vn|Vd"},
|
||
|
|
{"inst": "umlsl Vd.ta, Vn.tb, Vm.tb" , "op": "00101110|sz|1|Vm|10100|0|Vn|Vd" , "t": "8H.8B 4S.4H 2D.2S"},
|
||
|
|
{"inst": "umlsl2 Vd.ta, Vn.tb, Vm.tb" , "op": "01101110|sz|1|Vm|10100|0|Vn|Vd" , "t": "8H.16B 4S.8H 2D.4S"},
|
||
|
|
{"inst": "umlsl Vd.4S, Vn.4H, Vm.H[#dx]" , "op": "00101111|01|idx[1:0]|Vm:4|0110|idx[2]|0|Vn|Vd"},
|
||
|
|
{"inst": "umlsl2 Vd.4S, Vn.8H, Vm.H[#dx]" , "op": "01101111|01|idx[1:0]|Vm:4|0110|idx[2]|0|Vn|Vd"},
|
||
|
|
{"inst": "umlsl Vd.2D, Vn.2S, Vm.S[#dx]" , "op": "00101111|10|idx[0] |Vm |0110|idx[1]|0|Vn|Vd"},
|
||
|
|
{"inst": "umlsl2 Vd.2D, Vn.4S, Vm.S[#dx]" , "op": "01101111|10|idx[0] |Vm |0110|idx[1]|0|Vn|Vd"},
|
||
|
|
{"inst": "umov Wd, Vn.B[#idx]" , "op": "00001110|00|0|idx:4| 1|00111|1|Vn|Rd"},
|
||
|
|
{"inst": "umov Wd, Vn.H[#idx]" , "op": "00001110|00|0|idx:3| 10|00111|1|Vn|Rd"},
|
||
|
|
{"inst": "umov|mov Wd, Vn.S[#idx]" , "op": "00001110|00|0|idx:2| 100|00111|1|Vn|Rd"},
|
||
|
|
{"inst": "umov|mov Xd, Vn.D[#idx]" , "op": "01001110|00|0|idx:1|1000|00111|1|Vn|Rd"},
|
||
|
|
{"inst": "umull Vd.ta, Vn.tb, Vm.tb" , "op": "00101110|sz|1|Vm|11000|0|Vn|Vd" , "t": "8H.8B 4S.4H 2D.2S"},
|
||
|
|
{"inst": "umull2 Vd.ta, Vn.tb, Vm.tb" , "op": "01101110|sz|1|Vm|11000|0|Vn|Vd" , "t": "8H.16B 4S.8H 2D.4S"},
|
||
|
|
{"inst": "umull Vd.4S, Vn.4H, Vm.H[#idx]" , "op": "00101111|01|idx[1:0]|Vm:4|1010|idx[2]|0|Vn|Vd"},
|
||
|
|
{"inst": "umull2 Vd.4S, Vn.8H, Vm.H[#idx]" , "op": "01101111|01|idx[1:0]|Vm:4|1010|idx[2]|0|Vn|Vd"},
|
||
|
|
{"inst": "umull Vd.2D, Vn.2S, Vm.S[#idx]" , "op": "00101111|10|idx[0] |Vm |1010|idx[1]|0|Vn|Vd"},
|
||
|
|
{"inst": "umull2 Vd.2D, Vn.4S, Vm.S[#idx]" , "op": "01101111|10|idx[0] |Vm |1010|idx[1]|0|Vn|Vd"},
|
||
|
|
{"inst": "uqadd Bd, Bn, Bm" , "op": "01111110|sz|1|Vm|00001|1|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "uqadd Hd, Hn, Hm" , "op": "01111110|sz|1|Vm|00001|1|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "uqadd Sd, Sn, Sm" , "op": "01111110|sz|1|Vm|00001|1|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "uqadd Dd, Dn, Dm" , "op": "01111110|sz|1|Vm|00001|1|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "uqadd Vd.t, Vn.t, Vm.t" , "op": "00101110|sz|1|Vm|00001|1|Vn|Vd" , "io": "QC|=SAT", "t": "16B 8H 4S"},
|
||
|
|
{"inst": "uqadd Vd.t, Vn.t, Vm.t" , "op": "01101110|sz|1|Vm|00001|1|Vn|Vd" , "io": "QC|=SAT", "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "uqrshl Bd, Bn, Bm" , "op": "01111110|00|1|Vm|01011|1|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "uqrshl Hd, Hn, Hm" , "op": "01111110|01|1|Vm|01011|1|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "uqrshl Sd, Sn, Sm" , "op": "01111110|10|1|Vm|01011|1|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "uqrshl Dd, Dn, Dm" , "op": "01111110|11|1|Vm|01011|1|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "uqrshl Vd.t, Vn.t, Vm.t" , "op": "00101110|sz|1|Vm|01011|1|Vn|Vd" , "io": "QC|=SAT", "t": "8B 4H 2S"},
|
||
|
|
{"inst": "uqrshl Vd.t, Vn.t, Vm.t" , "op": "01101110|sz|1|Vm|01011|1|Vn|Vd" , "io": "QC|=SAT", "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "uqrshrn Bd, Hn, #n" , "op": "01111111|0|immh:4|immb:3|10011|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 0)"},
|
||
|
|
{"inst": "uqrshrn Hd, Sn, #n" , "op": "01111111|0|immh:4|immb:3|10011|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 1)"},
|
||
|
|
{"inst": "uqrshrn Sd, Dn, #n" , "op": "01111111|0|immh:4|immb:3|10011|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 2)"},
|
||
|
|
{"inst": "uqrshrn Vd.8B, Vn.8H, #n" , "op": "00101111|0|immh:4|immb:3|10011|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 0)"},
|
||
|
|
{"inst": "uqrshrn2 Vx.16B, Vn.8H, #n" , "op": "01101111|0|immh:4|immb:3|10011|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 0)"},
|
||
|
|
{"inst": "uqrshrn Vd.4H, Vn.4S, #n" , "op": "00101111|0|immh:4|immb:3|10011|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 1)"},
|
||
|
|
{"inst": "uqrshrn2 Vx.8H, Vn.4S, #n" , "op": "01101111|0|immh:4|immb:3|10011|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 1)"},
|
||
|
|
{"inst": "uqrshrn Vd.2S, Vn.2D, #n" , "op": "00101111|0|immh:4|immb:3|10011|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 2)"},
|
||
|
|
{"inst": "uqrshrn2 Vx.4S, Vn.2D, #n" , "op": "01101111|0|immh:4|immb:3|10011|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 2)"},
|
||
|
|
{"inst": "uqshl Bd, Bn, Bm" , "op": "01111110|00|1|Vm|01001|1|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "uqshl Hd, Hn, Hm" , "op": "01111110|01|1|Vm|01001|1|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "uqshl Sd, Sn, Sm" , "op": "01111110|10|1|Vm|01001|1|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "uqshl Dd, Dn, Dm" , "op": "01111110|11|1|Vm|01001|1|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "uqshl Vd.t, Vn.t, Vm.t" , "op": "00101110|sz|1|Vm|01001|1|Vn|Vd" , "io": "QC|=SAT", "t": "8B 4H 2S"},
|
||
|
|
{"inst": "uqshl Vd.t, Vn.t, Vm.t" , "op": "01101110|sz|1|Vm|01001|1|Vn|Vd" , "io": "QC|=SAT", "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "uqshl Bd, Bn, #n" , "op": "01111111|0|immh:4|immb:3|01110|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftPImm(n, 0)"},
|
||
|
|
{"inst": "uqshl Hd, Hn, #n" , "op": "01111111|0|immh:4|immb:3|01110|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftPImm(n, 1)"},
|
||
|
|
{"inst": "uqshl Sd, Sn, #n" , "op": "01111111|0|immh:4|immb:3|01110|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftPImm(n, 2)"},
|
||
|
|
{"inst": "uqshl Dd, Dn, #n" , "op": "01111111|0|immh:4|immb:3|01110|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftPImm(n, 3)"},
|
||
|
|
{"inst": "uqshl Vd.t, Vn.t, #n" , "op": "00101111|0|immh:4|immb:3|01110|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftPImm(n, sz)", "t": "8B 4H 2S"},
|
||
|
|
{"inst": "uqshl Vd.t, Vn.t, #n" , "op": "01101111|0|immh:4|immb:3|01110|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftPImm(n, sz)", "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "uqshrn Bd, Hn, #n" , "op": "01111111|0|immh:4|immb:3|10010|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 0)"},
|
||
|
|
{"inst": "uqshrn Hd, Sn, #n" , "op": "01111111|0|immh:4|immb:3|10010|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 1)"},
|
||
|
|
{"inst": "uqshrn Sd, Dn, #n" , "op": "01111111|0|immh:4|immb:3|10010|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 2)"},
|
||
|
|
{"inst": "uqshrn Vd.ta, Vn.tb, #n" , "op": "00001111|0|immh:4|immb:3|10010|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, sz)", "ta.tb": "8B.8H 4H.4S 2S.2D"},
|
||
|
|
{"inst": "uqshrn2 Vx.ta, Vn.tb, #n" , "op": "01001111|0|immh:4|immb:3|10010|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, sz)", "ta.tb": "16B.8H 8H.4S 4S.2D"},
|
||
|
|
{"inst": "uqsub Bd, Bn, Bm" , "op": "01111110|sz|1|Vm|00101|1|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "uqsub Hd, Hn, Hm" , "op": "01111110|sz|1|Vm|00101|1|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "uqsub Sd, Sn, Sm" , "op": "01111110|sz|1|Vm|00101|1|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "uqsub Dd, Dn, Dm" , "op": "01111110|sz|1|Vm|00101|1|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "uqsub Vd.t, Vn.t, Vm.t" , "op": "00101110|sz|1|Vm|00101|1|Vn|Vd" , "io": "QC|=SAT", "t": "16B 8H 4S"},
|
||
|
|
{"inst": "uqsub Vd.t, Vn.t, Vm.t" , "op": "01101110|sz|1|Vm|00101|1|Vn|Vd" , "io": "QC|=SAT", "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "uqxtn Bd, Hn" , "op": "01111110|00|10000|10100|10|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "uqxtn Hd, Sn" , "op": "01111110|01|10000|10100|10|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "uqxtn Sd, Dn" , "op": "01111110|10|10000|10100|10|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "uqxtn Vd.ta, Vn.tb" , "op": "00101110|sz|10000|10100|10|Vn|Vd" , "io": "QC|=SAT", "ta.tb": "8B.8H 4H.4S 2S.2D"},
|
||
|
|
{"inst": "uqxtn2 Vx.ta, Vn.tb" , "op": "01101110|sz|10000|10100|10|Vn|Vx" , "io": "QC|=SAT", "ta.tb": "16B.8H 8H.4S 4S.2D"},
|
||
|
|
{"inst": "urecpe Vd.2S, Vn.2S" , "op": "00001110|10|10000|11100|10|Vn|Vd"},
|
||
|
|
{"inst": "urecpe Vd.4S, Vn.4S" , "op": "01001110|10|10000|11100|10|Vn|Vd"},
|
||
|
|
{"inst": "urhadd Vd.t, Vn.t, Vm.t" , "op": "00101110|sz|1|Vm|00010|1|Vn|Vd" , "t": "8B 4H 2S"},
|
||
|
|
{"inst": "urhadd Vd.t, Vn.t, Vm.t" , "op": "01101110|sz|1|Vm|00010|1|Vn|Vd" , "t": "16B 8H 4S"},
|
||
|
|
{"inst": "urshl Dd, Dn, Dm" , "op": "01111110|11|1|Vm|01010|1|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "urshl Vd.t, Vn.t, Vm.t" , "op": "00101110|sz|1|Vm|01010|1|Vn|Vd" , "io": "QC|=SAT", "t": "8B 4H 2S"},
|
||
|
|
{"inst": "urshl Vd.t, Vn.t, Vm.t" , "op": "01101110|sz|1|Vm|01010|1|Vn|Vd" , "io": "QC|=SAT", "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "urshr Dd, Dn, #n" , "op": "01111111|0|immh:4|immb:3|00100|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 3)"},
|
||
|
|
{"inst": "urshr Vd.t, Vn.t, #n" , "op": "00101111|0|immh:4|immb:3|00100|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, sz)", "t": "8B 4H 2S"},
|
||
|
|
{"inst": "urshr Vd.t, Vn.t, #n" , "op": "01101111|0|immh:4|immb:3|00100|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, sz)", "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "ursqrte Vd.2S, Vn.2S" , "op": "00101110|10|10000|11100|10|Vn|Vd"},
|
||
|
|
{"inst": "ursqrte Vd.4S, Vn.4S" , "op": "01101110|10|10000|11100|10|Vn|Vd"},
|
||
|
|
{"inst": "ursra Dx, Dn, #n" , "op": "01111111|0|immh:4|immb:3|00110|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 3)"},
|
||
|
|
{"inst": "ursra Vx.t, Vn.t, #n" , "op": "00101111|0|immh:4|immb:3|00110|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, sz)", "t": "8B 4H 2S"},
|
||
|
|
{"inst": "ursra Vx.t, Vn.t, #n" , "op": "01101111|0|immh:4|immb:3|00110|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, sz)", "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "ushl Dd, Dn, Dm" , "op": "01111110|11|1|Vm|01000|1|Vn|Vd" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "ushl Vd.t, Vn.t, Vm.t" , "op": "00101110|sz|1|Vm|01000|1|Vn|Vd" , "io": "QC|=SAT", "t": "8B 4H 2S"},
|
||
|
|
{"inst": "ushl Vd.t, Vn.t, Vm.t" , "op": "01101110|sz|1|Vm|01000|1|Vn|Vd" , "io": "QC|=SAT", "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "ushll Vd.ta, Vn.tb, #n" , "op": "00101111|0|immh:4|immb:3|10100|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftPImm(n, sz)", "ta.tb": "8H.8B 4S.4H 2D.2S"},
|
||
|
|
{"inst": "ushll2 Vd.ta, Vn.tb, #n" , "op": "01101111|0|immh:4|immb:3|10100|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftPImm(n, sz)", "ta.tb": "8H.16B 4S.8H 2D.4S"},
|
||
|
|
{"inst": "ushr Dd, Dn, #n" , "op": "01111111|0|immh:4|immb:3|00000|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 3)"},
|
||
|
|
{"inst": "ushr Vd.t, Vn.t, #n" , "op": "00101111|0|immh:4|immb:3|00000|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, sz)", "t": "8B 4H 2S"},
|
||
|
|
{"inst": "ushr Vd.t, Vn.t, #n" , "op": "01101111|0|immh:4|immb:3|00000|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, sz)", "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "usqadd Bx, Bn" , "op": "01111110|sz|10000|00011|10|Vn|Vx" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "usqadd Hx, Hn" , "op": "01111110|sz|10000|00011|10|Vn|Vx" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "usqadd Sx, Sn" , "op": "01111110|sz|10000|00011|10|Vn|Vx" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "usqadd Dx, Dn" , "op": "01111110|sz|10000|00011|10|Vn|Vx" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "usqadd Vx.t, Vn.t" , "op": "00101110|sz|10000|00011|10|Vn|Vx" , "io": "QC|=SAT", "t": "16B 8H 4S"},
|
||
|
|
{"inst": "usqadd Vx.t, Vn.t" , "op": "01101110|sz|10000|00011|10|Vn|Vx" , "io": "QC|=SAT", "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "usra Dx, Dn, #n" , "op": "01111111|0|immh:4|immb:3|00010|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 3)"},
|
||
|
|
{"inst": "usra Vx.t, Vn.t, #n" , "op": "00101111|0|immh:4|immb:3|00010|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, sz)", "t": "8B 4H 2S"},
|
||
|
|
{"inst": "usra Vx.t, Vn.t, #n" , "op": "01101111|0|immh:4|immb:3|00010|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, sz)", "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "usubl Vd.ta, Vn.tb, Vm.tb" , "op": "00101110|sz|1|Vm|00100|0|Vn|Vd" , "ta.tb": "8H.8B 4S.4H 2D.2S"},
|
||
|
|
{"inst": "usubl2 Vd.ta, Vn.tb, Vm.tb" , "op": "01101110|sz|1|Vm|00100|0|Vn|Vd" , "ta.tb": "8H.16B 4S.8H 2D.4S"},
|
||
|
|
{"inst": "usubw Vd.ta, Vn.ta, Vm.tb" , "op": "00101110|sz|1|Vm|00110|0|Vn|Vd" , "ta.tb": "8H.8B 4S.4H 2D.2S"},
|
||
|
|
{"inst": "usubw2 Vd.ta, Vn.ta, Vm.tb" , "op": "01101110|sz|1|Vm|00110|0|Vn|Vd" , "ta.tb": "8H.16B 4S.8H 2D.4S"},
|
||
|
|
{"inst": "uxtl Vd.ta, Vn.tb" , "op": "00101111|0|immh:4|000|10100|1|Vn|Vd" , "imm": "ASimdXtlImm(sz)", "ta.tb": "8H.8B 4S.4H 2D.2S"},
|
||
|
|
{"inst": "uxtl2 Vd.ta, Vn.tb" , "op": "01101111|0|immh:4|000|10100|1|Vn|Vd" , "imm": "ASimdXtlImm(sz)", "ta.tb": "8H.16B 4S.8H 2D.4S"},
|
||
|
|
{"inst": "uzp1 Vd.t, Vn.t, Vm.t" , "op": "00001110|sz|0|Vm|00011|0|Vn|Vd" , "t": "8B 4H 2S"},
|
||
|
|
{"inst": "uzp1 Vd.t, Vn.t, Vm.t" , "op": "01001110|sz|0|Vm|00011|0|Vn|Vd" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "uzp2 Vd.t, Vn.t, Vm.t" , "op": "00001110|sz|0|Vm|01011|0|Vn|Vd" , "t": "8B 4H 2S"},
|
||
|
|
{"inst": "uzp2 Vd.t, Vn.t, Vm.t" , "op": "01001110|sz|0|Vm|01011|0|Vn|Vd" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "xtn Vd.ta, Vn.tb" , "op": "00001110|sz|10000|10010|10|Vn|Vd" , "t": "8B.8H 4H.4S 2S.2D"},
|
||
|
|
{"inst": "xtn2 Vx.ta, Vn.tb" , "op": "01001110|sz|10000|10010|10|Vn|Vx" , "t": "16B.8H 8H.4S 4S.2D"},
|
||
|
|
{"inst": "zip1 Vd.t, Vn.t, Vm.t" , "op": "00001110|sz|0|Vm|00111|0|Vn|Vd" , "t": "8B 4H 2S"},
|
||
|
|
{"inst": "zip1 Vd.t, Vn.t, Vm.t" , "op": "01001110|sz|0|Vm|00111|0|Vn|Vd" , "t": "16B 8H 4S 2D"},
|
||
|
|
{"inst": "zip2 Vd.t, Vn.t, Vm.t" , "op": "00001110|sz|0|Vm|01111|0|Vn|Vd" , "t": "8B 4H 2S"},
|
||
|
|
{"inst": "zip2 Vd.t, Vn.t, Vm.t" , "op": "01001110|sz|0|Vm|01111|0|Vn|Vd" , "t": "16B 8H 4S 2D"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "ASIMD CRYPTO_HASH", "ext": "AES", "data": [
|
||
|
|
{"inst": "aesd Vd.16B, Vn.16B" , "op": "01001110|00|10100|00101|10|Vn|Vd"},
|
||
|
|
{"inst": "aese Vd.16B, Vn.16B" , "op": "01001110|00|10100|00100|10|Vn|Vd"},
|
||
|
|
{"inst": "aesimc Vd.16B, Vn.16B" , "op": "01001110|00|10100|00111|10|Vn|Vd"},
|
||
|
|
{"inst": "aesmc Vd.16B, Vn.16B" , "op": "01001110|00|10100|00110|10|Vn|Vd"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "ASIMD", "ext": "BF16", "data": [
|
||
|
|
{"inst": "bfcvt Hd, Sn" , "op": "00011110|01|10001|10100|00|Vn|Vd"},
|
||
|
|
{"inst": "bfcvtn Vd.4H, Vn.4S" , "op": "00001110|10|10000|10110|10|Vn|Vd"},
|
||
|
|
{"inst": "bfcvtn2 Vd.8H, Vn.4S" , "op": "01001110|10|10000|10110|10|Vn|Vd"},
|
||
|
|
{"inst": "bfdot Vx.2S, Vn.4H, Vm.4H" , "op": "00101110|01|0|Vm|11111|1|Vn|Vx"},
|
||
|
|
{"inst": "bfdot Vx.4S, Vn.8H, Vm.8H" , "op": "01101110|01|0|Vm|11111|1|Vn|Vx"},
|
||
|
|
{"inst": "bfdot Vx.2S, Vn.4H, Vm.2H[#idx]" , "op": "00001111|01|idx[0]|Vm|1111|idx[1]|0|Vn|Vx"},
|
||
|
|
{"inst": "bfdot Vx.4S, Vn.8H, Vm.2H[#idx]" , "op": "01001111|01|idx[0]|Vm|1111|idx[1]|0|Vn|Vx"},
|
||
|
|
{"inst": "bfmlalb Vx.4S, Vn.8H, Vm.8H" , "op": "00101110|11|0|Vm|11111|1|Vn|Vx"},
|
||
|
|
{"inst": "bfmlalb Vx.4S, Vn.8H, Vm.H[#idx]" , "op": "00001111|11|imm[1:0]|Vm:4|1111|imm[2]|1|Vn|Vx"},
|
||
|
|
{"inst": "bfmlalt Vx.4S, Vn.8H, Vm.8H" , "op": "01101110|11|0|Vm|11111|1|Vn|Vx"},
|
||
|
|
{"inst": "bfmlalt Vx.4S, Vn.8H, Vm.H[#idx]" , "op": "01001111|11|imm[1:0]|Vm:4|1111|imm[2]|1|Vn|Vx"},
|
||
|
|
{"inst": "bfmmla Vx.4S, Vn.8H, Vm.8H" , "op": "01101110|01|0|Vm|11101|1|Vn|Vx"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "ASIMD", "ext": "DOTPROD", "data": [
|
||
|
|
{"inst": "sdot Vx.2S, Vn.8B, Vm.8B" , "op": "00001110|10|0|Vm|10010|1|Vn|Vx"},
|
||
|
|
{"inst": "sdot Vx.4S, Vn.16B, Vm.16B" , "op": "01001110|10|0|Vm|10010|1|Vn|Vx"},
|
||
|
|
{"inst": "sdot Vx.2S, Vn.8B, Vm.4B[#idx]" , "op": "00001111|10|idx[0]|Vm|1110|idx[1]|0|Vn|Vx"},
|
||
|
|
{"inst": "sdot Vx.4S, Vn.16B, Vm.4B[#idx]" , "op": "01001111|10|idx[0]|Vm|1110|idx[1]|0|Vn|Vx"},
|
||
|
|
{"inst": "udot Vx.2S, Vn.8B, Vm.8B" , "op": "00101110|10|0|Vm|10010|1|Vn|Vx"},
|
||
|
|
{"inst": "udot Vx.4S, Vn.16B, Vm.16B" , "op": "01101110|10|0|Vm|10010|1|Vn|Vx"},
|
||
|
|
{"inst": "udot Vx.2S, Vn.8B, Vm.4B[#idx]" , "op": "00101111|10|idx[0]|Vm|1110|idx[1]|0|Vn|Vx"},
|
||
|
|
{"inst": "udot Vx.4S, Vn.16B, Vm.4B[#idx]" , "op": "01101111|10|idx[0]|Vm|1110|idx[1]|0|Vn|Vx"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "ASIMD", "ext": "FCMA", "data": [
|
||
|
|
{"inst": "fcadd Vd.t, Vn.t, Vm.t, #rotate" , "op": "00101110|sz|0|Vm|111|imm:1|01|Vn|Vd" , "imm": "ASimdRotateImm_90_270(rotate)", "t": "4H 2S"},
|
||
|
|
{"inst": "fcadd Vd.t, Vn.t, Vm.t, #rotate" , "op": "01101110|sz|0|Vm|111|imm:1|01|Vn|Vd" , "imm": "ASimdRotateImm_90_270(rotate)", "t": "8H 4S 2D"},
|
||
|
|
{"inst": "fcmla Vd.t, Vn.t, Vm.t, #rotate" , "op": "00101110|sz|0|Vm|110|imm:2|1|Vn|Vd" , "imm": "ASimdRotateImm_0_90_180_270(rotate)", "t": "4H 2S"},
|
||
|
|
{"inst": "fcmla Vd.t, Vn.t, Vm.t, #rotate" , "op": "01101110|sz|0|Vm|110|imm:2|1|Vn|Vd" , "imm": "ASimdRotateImm_0_90_180_270(rotate)", "t": "8H 4S 2D"},
|
||
|
|
{"inst": "fcmla Vd.4H, Vn.4H, Vm.H[#idx], #rotate" , "op": "00101111|01|idx[0]|Vm|1|imm:2|1|idx[1]|0|Vn|Vd" , "imm": "ASimdRotateImm_0_90_180_270(rotate)"},
|
||
|
|
{"inst": "fcmla Vd.8H, Vn.8H, Vm.H[#idx], #rotate" , "op": "01101111|01|idx[0]|Vm|1|imm:2|1|idx[1]|0|Vn|Vd" , "imm": "ASimdRotateImm_0_90_180_270(rotate)"},
|
||
|
|
{"inst": "fcmla Vd.4S, Vn.4S, Vm.S[#idx], #rotate" , "op": "01101111|10|0|Vm|1|imm:2|1|idx:1|0|Vn|Vd" , "imm": "ASimdRotateImm_0_90_180_270(rotate)"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "ASIMD", "ext": "FHM", "data": [
|
||
|
|
{"inst": "fmlal Vx.2S, Vn.2H, Vm.2H" , "op": "00001110|00|1|Vm|11101|1|Vn|Vx"},
|
||
|
|
{"inst": "fmlal Vx.4S, Vn.4H, Vm.4H" , "op": "01001110|00|1|Vm|11101|1|Vn|Vx"},
|
||
|
|
{"inst": "fmlal Vx.2S, Vn.2H, Vm.H[#idx]" , "op": "00001111|10|imm[1:0]|Vm:4|0000|imm[2]|0|Vn|Vx"},
|
||
|
|
{"inst": "fmlal Vx.4S, Vn.4H, Vm.H[#idx]" , "op": "01001111|10|imm[1:0]|Vm:4|0000|imm[2]|0|Vn|Vx"},
|
||
|
|
{"inst": "fmlal2 Vx.2S, Vn.2H, Vm.2H" , "op": "00101110|00|1|Vm|11001|1|Vn|Vx"},
|
||
|
|
{"inst": "fmlal2 Vx.4S, Vn.4H, Vm.4H" , "op": "01101110|00|1|Vm|11001|1|Vn|Vx"},
|
||
|
|
{"inst": "fmlal2 Vx.2S, Vn.2H, Vm.H[#idx]" , "op": "00101111|10|imm[1:0]|Vm:4|1000|imm[2]|0|Vn|Vx"},
|
||
|
|
{"inst": "fmlal2 Vx.4S, Vn.4H, Vm.H[#idx]" , "op": "01101111|10|imm[1:0]|Vm:4|1000|imm[2]|0|Vn|Vx"},
|
||
|
|
{"inst": "fmlsl Vx.2S, Vn.2H, Vm.2H" , "op": "00001110|10|1|Vm|11101|1|Vn|Vx"},
|
||
|
|
{"inst": "fmlsl Vx.4S, Vn.4H, Vm.4H" , "op": "01001110|10|1|Vm|11101|1|Vn|Vx"},
|
||
|
|
{"inst": "fmlsl Vx.2S, Vn.2H, Vm.H[#idx]" , "op": "00001111|10|imm[1:0]|Vm:4|0100|imm[2]|0|Vn|Vx"},
|
||
|
|
{"inst": "fmlsl Vx.4S, Vn.4H, Vm.H[#idx]" , "op": "01001111|10|imm[1:0]|Vm:4|0100|imm[2]|0|Vn|Vx"},
|
||
|
|
{"inst": "fmlsl2 Vx.2S, Vn.2H, Vm.2H" , "op": "00101110|10|1|Vm|11001|1|Vn|Vx"},
|
||
|
|
{"inst": "fmlsl2 Vx.4S, Vn.4H, Vm.4H" , "op": "01101110|10|1|Vm|11001|1|Vn|Vx"},
|
||
|
|
{"inst": "fmlsl2 Vx.2S, Vn.2H, Vm.H[#idx]" , "op": "00101111|10|imm[1:0]|Vm:4|1100|imm[2]|0|Vn|Vx"},
|
||
|
|
{"inst": "fmlsl2 Vx.4S, Vn.4H, Vm.H[#idx]" , "op": "01101111|10|imm[1:0]|Vm:4|1100|imm[2]|0|Vn|Vx"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "ASIMD", "ext": "FP16", "data": [
|
||
|
|
{"inst": "fabd Hd, Hn, Hm" , "op": "01111110|11|0|Vm|00010|1|Vn|Vd"},
|
||
|
|
{"inst": "fabd Vd.4H, Vn.4H, Vm.4H" , "op": "00101110|11|0|Vm|00010|1|Vn|Vd"},
|
||
|
|
{"inst": "fabd Vd.8H, Vn.8H, Vm.8H" , "op": "01101110|11|0|Vm|00010|1|Vn|Vd"},
|
||
|
|
{"inst": "fabs Hd, Hn" , "op": "00011110|11|10000|01100|00|Vn|Vd"},
|
||
|
|
{"inst": "fabs Vd.4H, Vn.4H" , "op": "00001110|11|11100|01111|10|Vn|Vd"},
|
||
|
|
{"inst": "fabs Vd.8H, Vn.8H" , "op": "01001110|11|11100|01111|10|Vn|Vd"},
|
||
|
|
{"inst": "facge Hd, Hn, Hm" , "op": "01111110|01|0|Vm|00101|1|Vn|Vd"},
|
||
|
|
{"inst": "facge Vd.4H, Vn.4H, Vm.4H" , "op": "00101110|01|0|Vm|00101|1|Vn|Vd"},
|
||
|
|
{"inst": "facge Vd.8H, Vn.8H, Vm.8H" , "op": "01101110|01|0|Vm|00101|1|Vn|Vd"},
|
||
|
|
{"inst": "facgt Hd, Hn, Hm" , "op": "01111110|11|0|Vm|00101|1|Vn|Vd"},
|
||
|
|
{"inst": "facgt Vd.4H, Vn.4H, Vm.4H" , "op": "00101110|11|0|Vm|00101|1|Vn|Vd"},
|
||
|
|
{"inst": "facgt Vd.8H, Vn.8H, Vm.8H" , "op": "01101110|11|0|Vm|00101|1|Vn|Vd"},
|
||
|
|
{"inst": "fadd Hd, Hn, Hm" , "op": "00011110|11|1|Vm|00101|0|Vn|Vd"},
|
||
|
|
{"inst": "fadd Vd.4H, Vn.4H, Vm.4H" , "op": "00001110|01|0|Vm|00010|1|Vn|Vd"},
|
||
|
|
{"inst": "fadd Vd.8H, Vn.8H, Vm.8H" , "op": "01001110|01|0|Vm|00010|1|Vn|Vd"},
|
||
|
|
{"inst": "faddp Hd, Vn.2H" , "op": "01011110|00|11000|01101|10|Vn|Vd"},
|
||
|
|
{"inst": "faddp Vd.4H, Vn.4H, Vm.4H" , "op": "00101110|01|0|Vm|00010|1|Vn|Vd"},
|
||
|
|
{"inst": "faddp Vd.8H, Vn.8H, Vm.8H" , "op": "01101110|01|0|Vm|00010|1|Vn|Vd"},
|
||
|
|
{"inst": "fccmp Hn, Hm, #nzcv, #cond" , "op": "00011110|11|1|Vm|cond|01|Vn|0|nzcv" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "fccmpe Hn, Hm, #nzcv, #cond" , "op": "00011110|11|1|Vm|cond|01|Vn|1|nzcv" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "fcmeq Hd, Hn, Hm" , "op": "01011110|01|0|Vm|00100|1|Vn|Vd"},
|
||
|
|
{"inst": "fcmeq Hd, Hn, #0" , "op": "01011110|11|11100|01101|10|Vn|Vd"},
|
||
|
|
{"inst": "fcmeq Vd.4H, Vn.4H, Vm.4H" , "op": "00001110|01|0|Vm|00100|1|Vn|Vd"},
|
||
|
|
{"inst": "fcmeq Vd.4H, Vn.4H, #0" , "op": "00001110|11|11100|01101|10|Vn|Vd"},
|
||
|
|
{"inst": "fcmeq Vd.8H, Vn.8H, Vm.8H" , "op": "01001110|01|0|Vm|00100|1|Vn|Vd"},
|
||
|
|
{"inst": "fcmeq Vd.8H, Vn.8H, #0" , "op": "01001110|11|11100|01101|10|Vn|Vd"},
|
||
|
|
{"inst": "fcmge Hd, Hn, Hm" , "op": "01111110|01|0|Vm|00100|1|Vn|Vd"},
|
||
|
|
{"inst": "fcmge Hd, Hn, #0" , "op": "01111110|11|11100|01100|10|Vn|Vd"},
|
||
|
|
{"inst": "fcmge Vd.4H, Vn.4H, Vm.4H" , "op": "00101110|01|0|Vm|00100|1|Vn|Vd"},
|
||
|
|
{"inst": "fcmge Vd.4H, Vn.4H, #0" , "op": "00101110|11|11100|01100|10|Vn|Vd"},
|
||
|
|
{"inst": "fcmge Vd.8H, Vn.8H, Vm.8H" , "op": "01101110|01|0|Vm|00100|1|Vn|Vd"},
|
||
|
|
{"inst": "fcmge Vd.8H, Vn.8H, #0" , "op": "01101110|11|11100|01100|10|Vn|Vd"},
|
||
|
|
{"inst": "fcmgt Hd, Hn, Hm" , "op": "01111110|11|0|Vm|00100|1|Vn|Vd"},
|
||
|
|
{"inst": "fcmgt Hd, Hn, #0" , "op": "01011110|11|11100|01100|10|Vn|Vd"},
|
||
|
|
{"inst": "fcmgt Vd.4H, Vn.4H, Vm.4H" , "op": "00101110|11|0|Vm|00100|1|Vn|Vd"},
|
||
|
|
{"inst": "fcmgt Vd.4H, Vn.4H, #0" , "op": "00001110|11|11100|01100|10|Vn|Vd"},
|
||
|
|
{"inst": "fcmgt Vd.8H, Vn.8H, Vm.8H" , "op": "01101110|11|0|Vm|00100|1|Vn|Vd"},
|
||
|
|
{"inst": "fcmgt Vd.8H, Vn.8H, #0" , "op": "01001110|11|11100|01100|10|Vn|Vd"},
|
||
|
|
{"inst": "fcmle Hd, Hn, #0" , "op": "01111110|11|11100|01101|10|Vn|Vd"},
|
||
|
|
{"inst": "fcmle Vd.4H, Vn.4H, #0" , "op": "00101110|11|11100|01101|10|Vn|Vd"},
|
||
|
|
{"inst": "fcmle Vd.8H, Vn.8H, #0" , "op": "01101110|11|11100|01101|10|Vn|Vd"},
|
||
|
|
{"inst": "fcmlt Hd, Hn, #0" , "op": "01011110|11|11100|01110|10|Vn|Vd"},
|
||
|
|
{"inst": "fcmlt Vd.4H, Vn.4H, #0" , "op": "00001110|11|11100|01110|10|Vn|Vd"},
|
||
|
|
{"inst": "fcmlt Vd.8H, Vn.8H, #0" , "op": "01001110|11|11100|01110|10|Vn|Vd"},
|
||
|
|
{"inst": "fcmp Hn, Hm" , "op": "00011110|11|1|Vm|00100|0|Vn|00000" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "fcmp Hn, #0" , "op": "00011110|11|1|00000|00100|0|Vn|01000" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "fcmpe Hn, Hm" , "op": "00011110|11|1|Vm|00100|0|Vn|10000" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "fcmpe Hn, #0" , "op": "00011110|11|1|00000|00100|0|Vn|11000" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "fcsel Hd, Hn, Hm, #cond" , "op": "00011110|11|1|Vm|cond|11|Vn|Vd" , "io": "N=R Z=R C=R V=R"},
|
||
|
|
{"inst": "fcvtas Wd, Hn" , "op": "00011110|11|10010|00000|00|Vn|Rd"},
|
||
|
|
{"inst": "fcvtas Xd, Hn" , "op": "10011110|11|10010|00000|00|Vn|Rd"},
|
||
|
|
{"inst": "fcvtas Hd, Hn" , "op": "01011110|01|11100|11100|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtas Vd.4H, Vn.4H" , "op": "00001110|01|11100|11100|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtas Vd.8H, Vn.8H" , "op": "01001110|01|11100|11100|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtau Wd, Hn" , "op": "00011110|11|10010|10000|00|Vn|Rd"},
|
||
|
|
{"inst": "fcvtau Xd, Hn" , "op": "10011110|11|10010|10000|00|Vn|Rd"},
|
||
|
|
{"inst": "fcvtau Hd, Hn" , "op": "01111110|01|11100|11100|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtau Vd.4H, Vn.4H" , "op": "00101110|01|11100|11100|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtau Vd.8H, Vn.8H" , "op": "01101110|01|11100|11100|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtms Wd, Hn" , "op": "00011110|11|11000|00000|00|Vn|Rd"},
|
||
|
|
{"inst": "fcvtms Xd, Hn" , "op": "10011110|11|11000|00000|00|Vn|Rd"},
|
||
|
|
{"inst": "fcvtms Hd, Hn" , "op": "01011110|01|11100|11011|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtms Vd.4H, Vn.4H" , "op": "00001110|01|11100|11011|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtms Vd.8H, Vn.8H" , "op": "01001110|01|11100|11011|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtmu Wd, Hn" , "op": "00011110|11|11000|10000|00|Vn|Rd"},
|
||
|
|
{"inst": "fcvtmu Xd, Hn" , "op": "10011110|11|11000|10000|00|Vn|Rd"},
|
||
|
|
{"inst": "fcvtmu Hd, Hn" , "op": "01111110|01|11100|11011|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtmu Vd.4H, Vn.4H" , "op": "00101110|01|11100|11011|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtmu Vd.8H, Vn.8H" , "op": "01101110|01|11100|11011|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtns Wd, Hn" , "op": "00011110|11|10000|00000|00|Vn|Rd"},
|
||
|
|
{"inst": "fcvtns Xd, Hn" , "op": "10011110|11|10000|00000|00|Vn|Rd"},
|
||
|
|
{"inst": "fcvtns Hd, Hn" , "op": "01011110|01|11100|11010|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtns Vd.4H, Vn.4H" , "op": "00001110|01|11100|11010|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtns Vd.8H, Vn.8H" , "op": "01001110|01|11100|11010|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtnu Wd, Hn" , "op": "00011110|11|10000|10000|00|Vn|Rd"},
|
||
|
|
{"inst": "fcvtnu Xd, Hn" , "op": "10011110|11|10000|10000|00|Vn|Rd"},
|
||
|
|
{"inst": "fcvtnu Hd, Hn" , "op": "01111110|01|11100|11010|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtnu Vd.4H, Vn.4H" , "op": "00101110|01|11100|11010|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtnu Vd.8H, Vn.8H" , "op": "01101110|01|11100|11010|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtps Wd, Hn" , "op": "00011110|11|10100|00000|00|Vn|Rd"},
|
||
|
|
{"inst": "fcvtps Xd, Hn" , "op": "10011110|11|10100|00000|00|Vn|Rd"},
|
||
|
|
{"inst": "fcvtps Hd, Hn" , "op": "01011110|11|11100|11010|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtps Vd.4H, Vn.4H" , "op": "00001110|11|11100|11010|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtps Vd.8H, Vn.8H" , "op": "01001110|11|11100|11010|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtpu Wd, Hn" , "op": "00011110|11|10100|10000|00|Vn|Rd"},
|
||
|
|
{"inst": "fcvtpu Xd, Hn" , "op": "10011110|11|10100|10000|00|Vn|Rd"},
|
||
|
|
{"inst": "fcvtpu Hd, Hn" , "op": "01111110|11|11100|11010|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtpu Vd.4H, Vn.4H" , "op": "00101110|11|11100|11010|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtpu Vd.8H, Vn.8H" , "op": "01101110|11|11100|11010|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtzs Wd, Hn" , "op": "00011110|11|11100|00000|00|Vn|Rd"},
|
||
|
|
{"inst": "fcvtzs Xd, Hn" , "op": "10011110|11|11100|00000|00|Vn|Rd"},
|
||
|
|
{"inst": "fcvtzs Hd, Hn" , "op": "01011110|11|11100|11011|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtzs Vd.4H, Vn.4H" , "op": "00001110|11|11100|11011|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtzs Vd.8H, Vn.8H" , "op": "01001110|11|11100|11011|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtzs Wd, Hn, #fbits" , "op": "00011110|11|011000|scale:6|Vn|Vd" , "imm": "ASimdFBitsScaleImm(fbits, 32)"},
|
||
|
|
{"inst": "fcvtzs Xd, Hn, #fbits" , "op": "10011110|11|011000|scale:6|Vn|Vd" , "imm": "ASimdFBitsScaleImm(fbits, 64)"},
|
||
|
|
{"inst": "fcvtzs Hd, Hn, #fbits" , "op": "01011111|0|immh:4|immb:3|11111|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 16)"},
|
||
|
|
{"inst": "fcvtzs Vd.4H, Vn.4H, #fbits" , "op": "00001111|0|immh:4|immb:3|11111|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 16)"},
|
||
|
|
{"inst": "fcvtzs Vd.8H, Vn.8H, #fbits" , "op": "01001111|0|immh:4|immb:3|11111|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 16)"},
|
||
|
|
{"inst": "fcvtzu Wd, Hn" , "op": "00011110|11|11100|10000|00|Vn|Rd"},
|
||
|
|
{"inst": "fcvtzu Xd, Hn" , "op": "10011110|11|11100|10000|00|Vn|Rd"},
|
||
|
|
{"inst": "fcvtzu Hd, Hn" , "op": "01111110|11|11100|11011|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtzu Vd.4H, Vn.4H" , "op": "00101110|11|11100|11011|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtzu Vd.8H, Vn.8H" , "op": "01101110|11|11100|11011|10|Vn|Vd"},
|
||
|
|
{"inst": "fcvtzu Wd, Hn, #fbits" , "op": "00011110|11|011001|scale:6|Vn|Vd" , "imm": "ASimdFBitsScaleImm(fbits, 32)"},
|
||
|
|
{"inst": "fcvtzu Xd, Hn, #fbits" , "op": "10011110|11|011001|scale:6|Vn|Vd" , "imm": "ASimdFBitsScaleImm(fbits, 64)"},
|
||
|
|
{"inst": "fcvtzu Hd, Hn, #fbits" , "op": "01111111|0|immh:4|immb:3|11111|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 16)"},
|
||
|
|
{"inst": "fcvtzu Vd.4H, Vn.4H, #fbits" , "op": "00101111|0|immh:4|immb:3|11111|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 16)"},
|
||
|
|
{"inst": "fcvtzu Vd.8H, Vn.8H, #fbits" , "op": "01101111|0|immh:4|immb:3|11111|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 16)"},
|
||
|
|
{"inst": "fdiv Hd, Hn, Hm" , "op": "00011110|11|1|Vm|00011|0|Vn|Vd"},
|
||
|
|
{"inst": "fdiv Vd.4H, Vn.4H, Vm.4H" , "op": "00101110|01|0|Vm|00111|1|Vn|Vd"},
|
||
|
|
{"inst": "fdiv Vd.8H, Vn.8H, Vm.8H" , "op": "01101110|01|0|Vm|00111|1|Vn|Vd"},
|
||
|
|
{"inst": "fmadd Hd, Hn, Hm, Ha" , "op": "00011111|11|0|Vm|0|Va|Vn|Vd"},
|
||
|
|
{"inst": "fmax Hd, Hn, Hm" , "op": "00011110|11|1|Vm|01001|0|Vn|Vd"},
|
||
|
|
{"inst": "fmax Vd.4H, Vn.4H, Vm.4H" , "op": "00001110|01|0|Vm|00110|1|Vn|Vd"},
|
||
|
|
{"inst": "fmax Vd.8H, Vn.8H, Vm.8H" , "op": "01001110|01|0|Vm|00110|1|Vn|Vd"},
|
||
|
|
{"inst": "fmaxnm Hd, Hn, Hm" , "op": "00011110|11|1|Vm|01101|0|Vn|Vd"},
|
||
|
|
{"inst": "fmaxnm Vd.4H, Vn.4H, Vm.4H" , "op": "00001110|01|0|Vm|00000|1|Vn|Vd"},
|
||
|
|
{"inst": "fmaxnm Vd.8H, Vn.8H, Vm.8H" , "op": "01001110|01|0|Vm|00000|1|Vn|Vd"},
|
||
|
|
{"inst": "fmaxnmp Hd, Vn.2H" , "op": "01011110|00|11000|01100|10|Vn|Vd"},
|
||
|
|
{"inst": "fmaxnmp Vd.4H, Vn.4H, Vm.4H" , "op": "00101110|01|0|Vm|00000|1|Vn|Vd"},
|
||
|
|
{"inst": "fmaxnmp Vd.8H, Vn.8H, Vm.8H" , "op": "01101110|01|0|Vm|00000|1|Vn|Vd"},
|
||
|
|
{"inst": "fmaxnmv Hd, Vn.4H" , "op": "00001110|00|11000|01100|10|Vn|Vd"},
|
||
|
|
{"inst": "fmaxnmv Hd, Vn.8H" , "op": "01001110|00|11000|01100|10|Vn|Vd"},
|
||
|
|
{"inst": "fmaxp Hd, Vn.2H" , "op": "01011110|00|11000|01111|10|Vn|Vd"},
|
||
|
|
{"inst": "fmaxp Vd.4H, Vn.4H, Vm.4H" , "op": "00101110|01|0|Vm|00110|1|Vn|Vd"},
|
||
|
|
{"inst": "fmaxp Vd.8H, Vn.8H, Vm.8H" , "op": "01101110|01|0|Vm|00110|1|Vn|Vd"},
|
||
|
|
{"inst": "fmaxv Hd, Vn.4H" , "op": "00001110|00|11000|01111|10|Vn|Vd"},
|
||
|
|
{"inst": "fmaxv Hd, Vn.8H" , "op": "01001110|00|11000|01111|10|Vn|Vd"},
|
||
|
|
{"inst": "fmin Hd, Hn, Hm" , "op": "00011110|11|1|Vm|01011|0|Vn|Vd"},
|
||
|
|
{"inst": "fmin Vd.4H, Vn.4H, Vm.4H" , "op": "00001110|11|0|Vm|00110|1|Vn|Vd"},
|
||
|
|
{"inst": "fmin Vd.8H, Vn.8H, Vm.8H" , "op": "01001110|11|0|Vm|00110|1|Vn|Vd"},
|
||
|
|
{"inst": "fminnm Hd, Hn, Hm" , "op": "00011110|11|1|Vm|01111|0|Vn|Vd"},
|
||
|
|
{"inst": "fminnm Vd.4H, Vn.4H, Vm.4H" , "op": "00001110|11|0|Vm|00000|1|Vn|Vd"},
|
||
|
|
{"inst": "fminnm Vd.8H, Vn.8H, Vm.8H" , "op": "01001110|11|0|Vm|00000|1|Vn|Vd"},
|
||
|
|
{"inst": "fminnmp Hd, Vn.2H" , "op": "01011110|10|11000|01100|10|Vn|Vd"},
|
||
|
|
{"inst": "fminnmp Vd.4H, Vn.4H, Vm.4H" , "op": "00101110|11|0|Vm|00000|1|Vn|Vd"},
|
||
|
|
{"inst": "fminnmp Vd.8H, Vn.8H, Vm.8H" , "op": "01101110|11|0|Vm|00000|1|Vn|Vd"},
|
||
|
|
{"inst": "fminnmv Hd, Vn.4H" , "op": "00001110|10|11000|01100|10|Vn|Vd"},
|
||
|
|
{"inst": "fminnmv Hd, Vn.8H" , "op": "01001110|10|11000|01100|10|Vn|Vd"},
|
||
|
|
{"inst": "fminp Hd, Vn.2H" , "op": "01011110|10|11000|01111|10|Vn|Vd"},
|
||
|
|
{"inst": "fminp Vd.4H, Vn.4H, Vm.4H" , "op": "00101110|11|0|Vm|00110|1|Vn|Vd"},
|
||
|
|
{"inst": "fminp Vd.8H, Vn.8H, Vm.8H" , "op": "01101110|11|0|Vm|00110|1|Vn|Vd"},
|
||
|
|
{"inst": "fminv Hd, Vn.4H" , "op": "00001110|10|11000|01111|10|Vn|Vd"},
|
||
|
|
{"inst": "fminv Hd, Vn.8H" , "op": "01001110|10|11000|01111|10|Vn|Vd"},
|
||
|
|
{"inst": "fmla Hx, Hn, Vm.H[#idx]" , "op": "01011111|00|idx[1:0]|Vm:4|0001|idx[2]|0|Vn|Vx"},
|
||
|
|
{"inst": "fmla Vx.4H, Vn.4H, Vm.4H" , "op": "00001110|01|0|Vm|00001|1|Vn|Vx"},
|
||
|
|
{"inst": "fmla Vx.8H, Vn.8H, Vm.8H" , "op": "01001110|01|0|Vm|00001|1|Vn|Vx"},
|
||
|
|
{"inst": "fmla Vx.4H, Vn.4H, Vm.H[#idx]" , "op": "00001111|00|idx[1:0]|Vm:4|0001|idx[2]|0|Vn|Vx"},
|
||
|
|
{"inst": "fmla Vx.8H, Vn.8H, Vm.H[#idx]" , "op": "01001111|00|idx[1:0]|Vm:4|0001|idx[2]|0|Vn|Vx"},
|
||
|
|
{"inst": "fmls Hx, Hn, Vm.H[#idx]" , "op": "01011111|00|idx[1:0]|Vm:4|0101|idx[2]|0|Vn|Vx"},
|
||
|
|
{"inst": "fmls Vx.4H, Vn.4H, Vm.4H" , "op": "00001110|11|0|Vm|00001|1|Vn|Vx"},
|
||
|
|
{"inst": "fmls Vx.8H, Vn.8H, Vm.8H" , "op": "01001110|11|0|Vm|00001|1|Vn|Vx"},
|
||
|
|
{"inst": "fmls Vx.4H, Vn.4H, Vm.H[#idx]" , "op": "00001111|00|idx[1:0]|Vm:4|0101|idx[2]|0|Vn|Vx"},
|
||
|
|
{"inst": "fmls Vx.8H, Vn.8H, Vm.H[#idx]" , "op": "01001111|00|idx[1:0]|Vm:4|0101|idx[2]|0|Vn|Vx"},
|
||
|
|
{"inst": "fmov Wd, Hn" , "op": "00011110|11|10011|00000|00|Vn|Rd"},
|
||
|
|
{"inst": "fmov Xd, Hn" , "op": "10011110|11|10011|00000|00|Vn|Rd"},
|
||
|
|
{"inst": "fmov Hd, Wn" , "op": "00011110|11|10011|10000|00|Rn|Vd"},
|
||
|
|
{"inst": "fmov Hd, Xn" , "op": "10011110|11|10011|10000|00|Rn|Vd"},
|
||
|
|
{"inst": "fmov Hd, Hn" , "op": "00011110|11|10000|00100|00|Vn|Vd"},
|
||
|
|
{"inst": "fmov Hd, #fimm" , "op": "00011110|11|1|imm:8|100|00000|Vd" , "imm": "ASimdFMovImm(fimm)"},
|
||
|
|
{"inst": "fmov Vd.4H, #fimm" , "op": "00001111|00|000|abc:3|111111|defgh:5|Vd" , "imm": "ASimdFMovImm(fimm)"},
|
||
|
|
{"inst": "fmov Vd.8H, #fimm" , "op": "01001111|00|000|abc:3|111111|defgh:5|Vd" , "imm": "ASimdFMovImm(fimm)"},
|
||
|
|
{"inst": "fmsub Hd, Hn, Hm, Ha" , "op": "00011111|11|0|Vm|1|Va|Vn|Vd"},
|
||
|
|
{"inst": "fmul Hd, Hn, Hm" , "op": "00011110|11|1|Vm|00001|0|Vn|Vd"},
|
||
|
|
{"inst": "fmul Hd, Hn, Vm.H[#idx]" , "op": "01011111|00|idx[1:0]|Vm:4|1001|idx[2]|0|Vn|Vd"},
|
||
|
|
{"inst": "fmul Vd.4H, Vn.4H, Vm.4H" , "op": "00101110|01|0|Vm|00011|1|Vn|Vd"},
|
||
|
|
{"inst": "fmul Vd.8H, Vn.8H, Vm.8H" , "op": "01101110|01|0|Vm|00011|1|Vn|Vd"},
|
||
|
|
{"inst": "fmul Vd.4H, Vn.4H, Vm.H[#idx]" , "op": "00001111|00|idx[1:0]|Vm:4|1001|idx[2]|0|Vn|Vd"},
|
||
|
|
{"inst": "fmul Vd.8H, Vn.8H, Vm.H[#idx]" , "op": "01001111|00|idx[1:0]|Vm:4|1001|idx[2]|0|Vn|Vd"},
|
||
|
|
{"inst": "fmulx Hd, Hn, Hm" , "op": "01011110|01|0|Vm|00011|1|Vn|Vd"},
|
||
|
|
{"inst": "fmulx Hd, Hn, Vm.H[#idx]" , "op": "01111111|00|idx[1:0]|Vm:4|1001|idx[2]|0|Vn|Vd"},
|
||
|
|
{"inst": "fmulx Vd.4H, Vn.4H, Vm.4H" , "op": "00001110|01|0|Vm|00011|1|Vn|Vd"},
|
||
|
|
{"inst": "fmulx Vd.8H, Vn.8H, Vm.8H" , "op": "01001110|01|0|Vm|00011|1|Vn|Vd"},
|
||
|
|
{"inst": "fmulx Vd.4H, Vn.4H, Vm.H[#idx]" , "op": "00101111|00|idx[1:0]|Vm:4|1001|idx[2]|0|Vn|Vd"},
|
||
|
|
{"inst": "fmulx Vd.8H, Vn.8H, Vm.H[#idx]" , "op": "01101111|00|idx[1:0]|Vm:4|1001|idx[2]|0|Vn|Vd"},
|
||
|
|
{"inst": "fneg Hd, Hn" , "op": "00011110|11|10000|10100|00|Vn|Vd"},
|
||
|
|
{"inst": "fneg Vd.4H, Vn.4H" , "op": "00101110|11|11100|01111|10|Vn|Vd"},
|
||
|
|
{"inst": "fneg Vd.8H, Vn.8H" , "op": "01101110|11|11100|01111|10|Vn|Vd"},
|
||
|
|
{"inst": "fnmadd Hd, Hn, Hm, Ha" , "op": "00011111|11|1|Vm|0|Va|Vn|Vd"},
|
||
|
|
{"inst": "fnmsub Hd, Hn, Hm, Ha" , "op": "00011111|11|1|Vm|1|Va|Vn|Vd"},
|
||
|
|
{"inst": "fnmul Hd, Hn, Hm" , "op": "00011110|11|1|Vm|10001|0|Vn|Vd"},
|
||
|
|
{"inst": "frecpe Hd, Hn" , "op": "01011110|11|11100|11101|10|Vn|Vd"},
|
||
|
|
{"inst": "frecpe Vd.4H, Vn.4H" , "op": "00001110|11|11100|11101|10|Vn|Vd"},
|
||
|
|
{"inst": "frecpe Vd.8H, Vn.8H" , "op": "01001110|11|11100|11101|10|Vn|Vd"},
|
||
|
|
{"inst": "frecps Hd, Hn, Hm" , "op": "01011110|01|0|Vm|00111|1|Vn|Vd"},
|
||
|
|
{"inst": "frecps Vd.4H, Vn.4H, Vm.4H" , "op": "00001110|01|0|Vm|00111|1|Vn|Vd"},
|
||
|
|
{"inst": "frecps Vd.8H, Vn.8H, Vm.8H" , "op": "01001110|01|0|Vm|00111|1|Vn|Vd"},
|
||
|
|
{"inst": "frecpx Hd, Hn, Hm" , "op": "01011110|11|11100|11111|10|Vn|Vd"},
|
||
|
|
{"inst": "frinta Hd, Hn" , "op": "00011110|11|10011|00100|00|Vn|Vd"},
|
||
|
|
{"inst": "frinta Vd.4H, Vn.4H" , "op": "00101110|01|11100|11000|10|Vn|Vd"},
|
||
|
|
{"inst": "frinta Vd.8H, Vn.8H" , "op": "01101110|01|11100|11000|10|Vn|Vd"},
|
||
|
|
{"inst": "frinti Hd, Hn" , "op": "00011110|11|10011|11100|00|Vn|Vd"},
|
||
|
|
{"inst": "frinti Vd.4H, Vn.4H" , "op": "00101110|11|11100|11001|10|Vn|Vd"},
|
||
|
|
{"inst": "frinti Vd.8H, Vn.8H" , "op": "01101110|11|11100|11001|10|Vn|Vd"},
|
||
|
|
{"inst": "frintm Hd, Hn" , "op": "00011110|11|10010|10100|00|Vn|Vd"},
|
||
|
|
{"inst": "frintm Vd.4H, Vn.4H" , "op": "00001110|01|11100|11001|10|Vn|Vd"},
|
||
|
|
{"inst": "frintm Vd.8H, Vn.8H" , "op": "01001110|01|11100|11001|10|Vn|Vd"},
|
||
|
|
{"inst": "frintn Hd, Hn" , "op": "00011110|11|10010|00100|00|Vn|Vd"},
|
||
|
|
{"inst": "frintn Vd.4H, Vn.4H" , "op": "00001110|01|11100|11000|10|Vn|Vd"},
|
||
|
|
{"inst": "frintn Vd.8H, Vn.8H" , "op": "01001110|01|11100|11000|10|Vn|Vd"},
|
||
|
|
{"inst": "frintp Hd, Hn" , "op": "00011110|11|10010|01100|00|Vn|Vd"},
|
||
|
|
{"inst": "frintp Vd.4H, Vn.4H" , "op": "00001110|11|11100|11000|10|Vn|Vd"},
|
||
|
|
{"inst": "frintp Vd.8H, Vn.8H" , "op": "01001110|11|11100|11000|10|Vn|Vd"},
|
||
|
|
{"inst": "frintx Hd, Hn" , "op": "00011110|11|10011|10100|00|Vn|Vd"},
|
||
|
|
{"inst": "frintx Vd.4H, Vn.4H" , "op": "00101110|01|11100|11001|10|Vn|Vd"},
|
||
|
|
{"inst": "frintx Vd.8H, Vn.8H" , "op": "01101110|01|11100|11001|10|Vn|Vd"},
|
||
|
|
{"inst": "frintz Hd, Hn" , "op": "00011110|11|10010|11100|00|Vn|Vd"},
|
||
|
|
{"inst": "frintz Vd.4H, Vn.4H" , "op": "00001110|11|11100|11001|10|Vn|Vd"},
|
||
|
|
{"inst": "frintz Vd.8H, Vn.8H" , "op": "01001110|11|11100|11001|10|Vn|Vd"},
|
||
|
|
{"inst": "frsqrte Hd, Hn" , "op": "01111110|11|11100|11101|10|Vn|Vd"},
|
||
|
|
{"inst": "frsqrte Vd.4H, Vn.4H" , "op": "00101110|11|11100|11101|10|Vn|Vd"},
|
||
|
|
{"inst": "frsqrte Vd.8H, Vn.8H" , "op": "01101110|11|11100|11101|10|Vn|Vd"},
|
||
|
|
{"inst": "frsqrts Hd, Hn, Hm" , "op": "01011110|11|0|Vm|00111|1|Vn|Vd"},
|
||
|
|
{"inst": "frsqrts Vd.4H, Vn.4H, Vm.4H" , "op": "00001110|11|0|Vm|00111|1|Vn|Vd"},
|
||
|
|
{"inst": "frsqrts Vd.8H, Vn.8H, Vm.8H" , "op": "01001110|11|0|Vm|00111|1|Vn|Vd"},
|
||
|
|
{"inst": "fsqrt Hd, Hn" , "op": "00011110|11|10000|11100|00|Vn|Vd"},
|
||
|
|
{"inst": "fsqrt Vd.4H, Vn.4H" , "op": "00101110|11|11100|11111|10|Vn|Vd"},
|
||
|
|
{"inst": "fsqrt Vd.8H, Vn.8H" , "op": "01101110|11|11100|11111|10|Vn|Vd"},
|
||
|
|
{"inst": "fsub Hd, Hn, Hm" , "op": "00011110|11|1|Vm|00111|0|Vn|Vd"},
|
||
|
|
{"inst": "fsub Vd.4H, Vn.4H, Vm.4H" , "op": "00001110|11|0|Vm|00010|1|Vn|Vd"},
|
||
|
|
{"inst": "fsub Vd.8H, Vn.8H, Vm.8H" , "op": "01001110|11|0|Vm|00010|1|Vn|Vd"},
|
||
|
|
{"inst": "scvtf Hd, Wn" , "op": "00011110|11|1|00010|00000|0|Rn|Vd"},
|
||
|
|
{"inst": "scvtf Hd, Wn, #fbits" , "op": "00011110|11|0|00010|scale:6|Rn|Vd" , "imm": "ASimdFBitsScaleImm(fbits, 32)"},
|
||
|
|
{"inst": "scvtf Hd, Xn" , "op": "10011110|11|1|00010|00000|0|Rn|Vd"},
|
||
|
|
{"inst": "scvtf Hd, Xn, #fbits" , "op": "10011110|11|0|00010|scale:6|Rn|Vd" , "imm": "ASimdFBitsScaleImm(fbits, 64)"},
|
||
|
|
{"inst": "scvtf Hd, Hn" , "op": "01011110|01|11100|11101|10|Vn|Vd"},
|
||
|
|
{"inst": "scvtf Hd, Hn, #bits" , "op": "01011111|0|immh:4|immb:3|11100|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 16)"},
|
||
|
|
{"inst": "scvtf Vd.4H, Vn.4H" , "op": "00001110|01|11100|11101|10|Vn|Vd"},
|
||
|
|
{"inst": "scvtf Vd.8H, Vn.8H" , "op": "01001110|01|11100|11101|10|Vn|Vd"},
|
||
|
|
{"inst": "scvtf Vd.4H, Vn.4H, #fbits" , "op": "00001111|0|immh:4|immb:3|11100|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 16)"},
|
||
|
|
{"inst": "scvtf Vd.8H, Vn.8H, #fbits" , "op": "01001111|0|immh:4|immb:3|11100|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 16)"},
|
||
|
|
{"inst": "ucvtf Hd, Wn" , "op": "00011110|11|1|00011|00000|0|Rn|Vd"},
|
||
|
|
{"inst": "ucvtf Hd, Wn, #fbits" , "op": "00011110|11|0|00011|scale:6|Rn|Vd" , "imm": "ASimdFBitsScaleImm(fbits, 32)"},
|
||
|
|
{"inst": "ucvtf Hd, Xn" , "op": "10011110|11|1|00011|00000|0|Rn|Vd"},
|
||
|
|
{"inst": "ucvtf Hd, Xn, #fbits" , "op": "10011110|11|0|00011|scale:6|Rn|Vd" , "imm": "ASimdFBitsScaleImm(fbits, 64)"},
|
||
|
|
{"inst": "ucvtf Hd, Hn" , "op": "01111110|01|11100|11101|10|Vn|Vd"},
|
||
|
|
{"inst": "ucvtf Hd, Hn, #bits" , "op": "01111111|0|immh:4|immb:3|11100|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 16)"},
|
||
|
|
{"inst": "ucvtf Vd.4H, Vn.4H" , "op": "00101110|01|11100|11101|10|Vn|Vd"},
|
||
|
|
{"inst": "ucvtf Vd.8H, Vn.8H" , "op": "01101110|01|11100|11101|10|Vn|Vd"},
|
||
|
|
{"inst": "ucvtf Vd.4H, Vn.4H, #fbits" , "op": "00101111|0|immh:4|immb:3|11100|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 16)"},
|
||
|
|
{"inst": "ucvtf Vd.8H, Vn.8H, #fbits" , "op": "01101111|0|immh:4|immb:3|11100|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 16)"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "ASIMD", "ext": "FRINTTS", "data": [
|
||
|
|
{"inst": "frint32x Sd, Sn" , "op": "00011110|00|10100|01100|00|Vn|Vd"},
|
||
|
|
{"inst": "frint32x Dd, Dn" , "op": "00011110|01|10100|01100|00|Vn|Vd"},
|
||
|
|
{"inst": "frint32x Vd.2S, Vn.2S" , "op": "00101110|00|10000|11110|10|Vn|Vd"},
|
||
|
|
{"inst": "frint32x Vd.4S, Vn.4S" , "op": "01101110|00|10000|11110|10|Vn|Vd"},
|
||
|
|
{"inst": "frint32x Vd.2D, Vn.2D" , "op": "01101110|01|10000|11110|10|Vn|Vd"},
|
||
|
|
{"inst": "frint32z Sd, Sn" , "op": "00011110|00|10100|00100|00|Vn|Vd"},
|
||
|
|
{"inst": "frint32z Dd, Dn" , "op": "00011110|01|10100|00100|00|Vn|Vd"},
|
||
|
|
{"inst": "frint32z Vd.2S, Vn.2S" , "op": "00001110|00|10000|11110|10|Vn|Vd"},
|
||
|
|
{"inst": "frint32z Vd.4S, Vn.4S" , "op": "01001110|00|10000|11110|10|Vn|Vd"},
|
||
|
|
{"inst": "frint32z Vd.2D, Vn.2D" , "op": "01001110|01|10000|11110|10|Vn|Vd"},
|
||
|
|
{"inst": "frint64x Sd, Sn" , "op": "00011110|00|10100|11100|00|Vn|Vd"},
|
||
|
|
{"inst": "frint64x Dd, Dn" , "op": "00011110|01|10100|11100|00|Vn|Vd"},
|
||
|
|
{"inst": "frint64x Vd.2S, Vn.2S" , "op": "00101110|00|10000|11111|10|Vn|Vd"},
|
||
|
|
{"inst": "frint64x Vd.4S, Vn.4S" , "op": "01101110|00|10000|11111|10|Vn|Vd"},
|
||
|
|
{"inst": "frint64x Vd.2D, Vn.2D" , "op": "01101110|01|10000|11111|10|Vn|Vd"},
|
||
|
|
{"inst": "frint64z Sd, Sn" , "op": "00011110|00|10100|10100|00|Vn|Vd"},
|
||
|
|
{"inst": "frint64z Dd, Dn" , "op": "00011110|01|10100|10100|00|Vn|Vd"},
|
||
|
|
{"inst": "frint64z Vd.2S, Vn.2S" , "op": "00001110|00|10000|11111|10|Vn|Vd"},
|
||
|
|
{"inst": "frint64z Vd.4S, Vn.4S" , "op": "01001110|00|10000|11111|10|Vn|Vd"},
|
||
|
|
{"inst": "frint64z Vd.2D, Vn.2D" , "op": "01001110|01|10000|11111|10|Vn|Vd"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "ASIMD", "ext": "I8MM", "data": [
|
||
|
|
{"inst": "smmla Vx.4S, Vn.16B, Vm.16B" , "op": "01001110|10|0|Vm|10100|1|Vn|Vx"},
|
||
|
|
{"inst": "sudot Vx.2S, Vn.8B, Vm.4B[#idx]" , "op": "00001111|00|idx[0]|Vm|1111|idx[1]|0|Vn|Vx"},
|
||
|
|
{"inst": "sudot Vx.4S, Vn.16B, Vm.4B[#idx]" , "op": "01001111|00|idx[0]|Vm|1111|idx[1]|0|Vn|Vx"},
|
||
|
|
{"inst": "ummla Vx.4S, Vn.16B, Vm.16B" , "op": "01101110|10|0|Vm|10100|1|Vn|Vx"},
|
||
|
|
{"inst": "usdot Vx.2S, Vn.8B, Vm.tb" , "op": "00001110|10|0|Vm|10011|1|Vn|Vx"},
|
||
|
|
{"inst": "usdot Vx.4S, Vn.16B, Vm.tb" , "op": "01001110|10|0|Vm|10011|1|Vn|Vx"},
|
||
|
|
{"inst": "usdot Vx.2S, Vn.8B, Vm.4B[#idx]" , "op": "00001111|10|idx[0]|Vm|1111|idx[1]|0|Vn|Vx"},
|
||
|
|
{"inst": "usdot Vx.4S, Vn.16B, Vm.4B[#idx]" , "op": "01001111|10|idx[0]|Vm|1111|idx[1]|0|Vn|Vx"},
|
||
|
|
{"inst": "usmmla Vx.4S, Vn.16B, Vm.16B" , "op": "01001110|10|0|Vm|10101|1|Vn|Vx"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "ASIMD", "ext": "JSCVT", "data": [
|
||
|
|
{"inst": "fjcvtzs Wd, Dn" , "op": "00011110|011|11110|00000|0|Vn|Vd"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "ASIMD", "ext": "ASIMD LRCPC3", "data": [
|
||
|
|
{"inst": "ldap1 Vd.D[#idx], [Xn|SP]" , "op": "0|idx:1|001101|010|00001|10000|1|Rn|Vd"},
|
||
|
|
{"inst": "ldapur Bd, [Xn|SP, #soff]" , "op": "00011101|010|soff:9|10|Rn|Vd"},
|
||
|
|
{"inst": "ldapur Hd, [Xn|SP, #soff]" , "op": "01011101|010|soff:9|10|Rn|Vd"},
|
||
|
|
{"inst": "ldapur Sd, [Xn|SP, #soff]" , "op": "10011101|010|soff:9|10|Rn|Vd"},
|
||
|
|
{"inst": "ldapur Dd, [Xn|SP, #soff]" , "op": "11011101|010|soff:9|10|Rn|Vd"},
|
||
|
|
{"inst": "ldapur Qd, [Xn|SP, #soff]" , "op": "00011101|110|soff:9|10|Rn|Vd"},
|
||
|
|
{"inst": "stl1 Vs.D[#idx], [Xn|SP]" , "op": "0|idx:1|001101|000|00001|10000|1|Rn|Vs"},
|
||
|
|
{"inst": "stlur Bs, [Xn|SP, #soff]" , "op": "00011101|000|soff:9|10|Rn|Vs"},
|
||
|
|
{"inst": "stlur Hs, [Xn|SP, #soff]" , "op": "01011101|000|soff:9|10|Rn|Vs"},
|
||
|
|
{"inst": "stlur Ss, [Xn|SP, #soff]" , "op": "10011101|000|soff:9|10|Rn|Vs"},
|
||
|
|
{"inst": "stlur Ds, [Xn|SP, #soff]" , "op": "11011101|000|soff:9|10|Rn|Vs"},
|
||
|
|
{"inst": "stlur Qs, [Xn|SP, #soff]" , "op": "00011101|100|soff:9|10|Rn|Vs"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "ASIMD", "ext": "RDM", "data": [
|
||
|
|
{"inst": "sqrdmlah Hx, Hn, Hm" , "op": "01111110|01|0|Vm|10000|1|Vn|Vx" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqrdmlah Sx, Sn, Sm" , "op": "01111110|10|0|Vm|10000|1|Vn|Vx" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqrdmlah Hx, Hn, Vn.H[#idx]" , "op": "01111111|01|imm[1:0]|Vm:4|1101|imm[2]|0|Vn|Vx" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqrdmlah Sx, Sn, Vn.S[#idx]" , "op": "01111111|10|imm[0] |Vm |1101|imm[1]|0|Vn|Vx" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqrdmlah Vx.t, Vn.t, Vm.t" , "op": "00101110|sz|0|Vm|10000|1|Vn|Vx" , "io": "QC|=SAT", "t": "~ 4H 2S"},
|
||
|
|
{"inst": "sqrdmlah Vx.t, Vn.t, Vm.t" , "op": "01101110|sz|0|Vm|10000|1|Vn|Vx" , "io": "QC|=SAT", "t": "~ 8H 4S"},
|
||
|
|
{"inst": "sqrdmlah Vx.4H, Vn.4H, Vm.H[#idx]" , "op": "00101111|01|imm[1:0]|Vm:4|1101|imm[2]|0|Vn|Vx" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqrdmlah Vx.2S, Vn.2S, Vm.S[#idx]" , "op": "00101111|10|imm[0] |Vm |1101|imm[1]|0|Vn|Vx" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqrdmlah Vx.8H, Vn.8H, Vm.H[#idx]" , "op": "01101111|01|imm[1:0]|Vm:4|1101|imm[2]|0|Vn|Vx" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqrdmlah Vx.4S, Vn.4S, Vm.S[#idx]" , "op": "01101111|10|imm[0] |Vm |1101|imm[1]|0|Vn|Vx" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqrdmlsh Hx, Hn, Hm" , "op": "01111110|01|0|Vm|10001|1|Vn|Vx" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqrdmlsh Sx, Sn, Sm" , "op": "01111110|10|0|Vm|10001|1|Vn|Vx" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqrdmlsh Hx, Hn, Vn.H[#idx]" , "op": "01111111|01|imm[1:0]|Vm:4|1111|imm[2]|0|Vn|Vx" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqrdmlsh Sx, Sn, Vn.S[#idx]" , "op": "01111111|10|imm[0] |Vm |1111|imm[1]|0|Vn|Vx" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqrdmlsh Vx.t, Vn.t, Vm.t" , "op": "00101110|sz|0|Vm|10001|1|Vn|Vx" , "io": "QC|=SAT", "t": "~ 4H 2S"},
|
||
|
|
{"inst": "sqrdmlsh Vx.t, Vn.t, Vm.t" , "op": "01101110|sz|0|Vm|10001|1|Vn|Vx" , "io": "QC|=SAT", "t": "~ 8H 4S"},
|
||
|
|
{"inst": "sqrdmlsh Vx.4H, Vn.4H, Vm.H[#idx]" , "op": "00101111|01|imm[1:0]|Vm:4|1111|imm[2]|0|Vn|Vx" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqrdmlsh Vx.2S, Vn.2S, Vm.S[#idx]" , "op": "00101111|10|imm[0] |Vm |1111|imm[1]|0|Vn|Vx" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqrdmlsh Vx.8H, Vn.8H, Vm.H[#idx]" , "op": "01101111|01|imm[1:0]|Vm:4|1111|imm[2]|0|Vn|Vx" , "io": "QC|=SAT"},
|
||
|
|
{"inst": "sqrdmlsh Vx.4S, Vn.4S, Vm.S[#idx]" , "op": "01101111|10|imm[0] |Vm |1111|imm[1]|0|Vn|Vx" , "io": "QC|=SAT"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "ASIMD CRYPTO_HASH", "ext": "SHA1", "data": [
|
||
|
|
{"inst": "sha1c Qx, Sn, Vm.4S" , "op": "01011110|00|0|Vm|00000|0|Vn|Vx"},
|
||
|
|
{"inst": "sha1h Sd, Sn" , "op": "01011110|00|10100|00000|10|Vn|Vd"},
|
||
|
|
{"inst": "sha1m Qx, Sn, Vm.4S" , "op": "01011110|00|0|Vm|00100|0|Vn|Vx"},
|
||
|
|
{"inst": "sha1p Qx, Sn, Vm.4S" , "op": "01011110|00|0|Vm|00010|0|Vn|Vx"},
|
||
|
|
{"inst": "sha1su0 Vx.4S, Vn.4S, Vm.4S" , "op": "01011110|00|0|Vm|00110|0|Vn|Vx"},
|
||
|
|
{"inst": "sha1su1 Vx.4S, Vn.4S" , "op": "01011110|00|1|01000|00011|0|Vn|Vx"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "ASIMD CRYPTO_HASH", "ext": "SHA256", "data": [
|
||
|
|
{"inst": "sha256h Qx, Qn, Vm.4S" , "op": "01011110|00|0|Vm|01000|0|Vn|Vx"},
|
||
|
|
{"inst": "sha256h2 Qx, Qn, Vm.4S" , "op": "01011110|00|0|Vm|01010|0|Vn|Vx"},
|
||
|
|
{"inst": "sha256su0 Vx.4S, Vn.4S" , "op": "01011110|00|10100|00010|10|Vn|Vx"},
|
||
|
|
{"inst": "sha256su1 Vx.4S, Vn.4S, Vm.4S" , "op": "01011110|00|0|Vm|01100|0|Vn|Vx"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "ASIMD CRYPTO_HASH", "ext": "SHA3", "data": [
|
||
|
|
{"inst": "bcax Vd.16B, Vn.16B, Vm.16B, Va.16B" , "op": "11001110|00|1|Vm|0|Va|Vn|Vd"},
|
||
|
|
{"inst": "eor3 Vd.16B, Vn.16B, Vm.16B, Va.16B" , "op": "11001110|00|0|Vm|0|Va|Vn|Vd"},
|
||
|
|
{"inst": "rax1 Vd.2D, Vn.2D, Vm.2D" , "op": "11001110|01|1|Vm|10001|1|Vn|Vd"},
|
||
|
|
{"inst": "xar Vd.2D, Vn.2D, Vm.2D, #imm" , "op": "11001110|10|0|Vm|imm:6|Vn|Vd"}
|
||
|
|
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "ASIMD CRYPTO_HASH", "ext": "SHA512", "data": [
|
||
|
|
{"inst": "sha512h Qx, Qn, Vm.2D" , "op": "11001110|01|1|Vm|10000|0|Vn|Vx"},
|
||
|
|
{"inst": "sha512h2 Qx, Qn, Vm.2D" , "op": "11001110|01|1|Vm|10000|1|Vn|Vx"},
|
||
|
|
{"inst": "sha512su0 Vx.2D, Vn.2D" , "op": "11001110|11|00000|01000|00|Vn|Vx"},
|
||
|
|
{"inst": "sha512su1 Vx.2D, Vn.2D, Vm.2D" , "op": "11001110|01|1|Vm|10001|0|Vn|Vx"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "ASIMD CRYPTO_HASH", "ext": "SM3", "data": [
|
||
|
|
{"inst": "sm3partw1 Vx.4S, Vn.4S, Vm.4S" , "op": "11001110|01|1|Vm|11000|0|Vn|Vx"},
|
||
|
|
{"inst": "sm3partw2 Vx.4S, Vn.4S, Vm.4S" , "op": "11001110|01|1|Vm|11000|1|Vn|Vx"},
|
||
|
|
{"inst": "sm3ss1 Vd.4S, Vn.4S, Vm.4S, Va.4S" , "op": "11001110|01|0|Vm|0|Va|Vn|Vd"},
|
||
|
|
{"inst": "sm3tt1a Vx.4S, Vn.4S, Vm.4[#idx]" , "op": "11001110|01|0|Vm|10|idx:2|00|Vn|Vx"},
|
||
|
|
{"inst": "sm3tt1b Vx.4S, Vn.4S, Vm.4[#idx]" , "op": "11001110|01|0|Vm|10|idx:2|01|Vn|Vx"},
|
||
|
|
{"inst": "sm3tt2a Vx.4S, Vn.4S, Vm.4[#idx]" , "op": "11001110|01|0|Vm|10|idx:2|10|Vn|Vx"},
|
||
|
|
{"inst": "sm3tt2b Vx.4S, Vn.4S, Vm.4[#idx]" , "op": "11001110|01|0|Vm|10|idx:2|11|Vn|Vx"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "ASIMD CRYPTO_HASH", "ext": "SM4", "data": [
|
||
|
|
{"inst": "sm4e Vx.4S, Vn.4S" , "op": "11001110|11|0|00000|10000|1|Vn|Vx"},
|
||
|
|
{"inst": "sm4ekey Vd.4S, Vn.4S, Vm.4S" , "op": "11001110|01|1|Vm|11001|0|Vn|Vd"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "SVE", "ext": "SVE", "data": [
|
||
|
|
{"inst": "abs Zd.t, Pg/M, Zn.t" , "op": "00000100|sz|0|10110101|Pg:3|Zn|Zd"},
|
||
|
|
{"inst": "add Zd.t, Zn.t, Zm.t" , "op": "00000100|sz|1|Zm|000000|Zn|Zd"},
|
||
|
|
{"inst": "add Zdn.t, Zdn.t, #imm, {lsl #n}" , "op": "00100101|sz|10000011|n:1|imm:8|Zdn" , "imm": "Sve8BitImm(imm)"},
|
||
|
|
{"inst": "add Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "00000100|sz|000000000|Pg:3|Zm|Zdn"},
|
||
|
|
{"inst": "addp Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|010001101|Pg:3|Zm|Zdn"},
|
||
|
|
{"inst": "addpl Xd|SP, Xn|SP, #immS" , "op": "00000100|01|1|Rn|01010|immS:6|Rd"},
|
||
|
|
{"inst": "addvl Xd|SP, Xn|SP, #immS" , "op": "00000100|00|1|Rn|01010|immS:6|Rd"},
|
||
|
|
{"inst": "adr Zd.t, [Zn.t, Zm.t, {lsl #n}]" , "op": "00000100|sz|1|Zm|1010|msz|Zn|Zd" , "t": "~~SD"},
|
||
|
|
{"inst": "adr Zd.D, [Zn.D, Zm.D, {sxtw #n}]" , "op": "00000100|00|1|Zm|1010|msz|Zn|Zd"},
|
||
|
|
{"inst": "adr Zd.D, [Zn.D, Zm.D, {uxtw #n}]" , "op": "00000100|01|1|Zm|1010|msz|Zn|Zd"},
|
||
|
|
{"inst": "and Zd.D, Zn.D, Zm.D" , "op": "00000100|00|1|Zm|001100|Zn|Zd"},
|
||
|
|
{"inst": "and Zdn.t, Zdn.t, #imm" , "op": "00000101|10|0000|imm:13|Zdn" , "imm": "SveLogicalImm(imm, 0, t)"},
|
||
|
|
{"inst": "and Pd.B, Pg/Z, Pn.B, Pm.B" , "op": "00100101|00|00|Pm|01|Pg|0|Pn|0|Pd"},
|
||
|
|
{"inst": "and Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "00000100|sz|011010000|Pg:3|Zm|Zdn"},
|
||
|
|
{"inst": "ands Pd.B, Pg/Z, Pn.B, Pm.B" , "op": "00100101|01|00|Pm|01|Pg|0|Pn|0|Pd" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "andv Vd, Pg, Zn.t" , "op": "00000100|sz|011010001|Pg:3|Zn|Vd"},
|
||
|
|
{"inst": "asr Zd.t, Zn.t, Zm.D" , "op": "00000100|sz|1|Zm|100000|Zn|Zd" , "t": "BHS~"},
|
||
|
|
{"inst": "asr Zd.t, Zn.t, #imm" , "op": "00000100|imm:2|1|imm:5|100100|Zn|Zd" , "imm": "SveShiftImm7(sz, imm)"},
|
||
|
|
{"inst": "asr Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "00000100|sz|010000100|Pg:3|Zm|Zdn"},
|
||
|
|
{"inst": "asr Zdn.t, Pg/M, Zdn.t, Zm.D" , "op": "00000100|sz|011000100|Pg:3|Zm|Zdn" , "t": "BHS~"},
|
||
|
|
{"inst": "asr Zdn.t, Pg/M, Zdn.t, #imm" , "op": "00000100|imm:2|000000100|Pg:3|imm:5|Zdn" , "imm": "SveShiftImm7(sz, imm)"},
|
||
|
|
{"inst": "asrd Zdn.t, Pg/M, Zdn.t, #imm" , "op": "00000100|imm:2|000100100|Pg:3|imm:5|Zdn" , "imm": "SveShiftImm7(sz, imm)"},
|
||
|
|
{"inst": "asrr Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "00000100|sz|010100100|Pg:3|Zm|Zdn"},
|
||
|
|
{"inst": "bic Zd.D, Zn.D, Zm.D" , "op": "00000100|11|1|Zm|001100|Zn|Zd"},
|
||
|
|
{"inst": "bic Zdn.t, Zdn.t, #imm" , "op": "00000101|10|0000|imm:13|Zdn" , "imm": "SveLogicalImm(imm, 1, t)"},
|
||
|
|
{"inst": "bic Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "00000100|sz|011010000|Pg:3|Zm|Zdn"},
|
||
|
|
{"inst": "bic Pd.B, Pg/Z, Pn.B, Pm.B" , "op": "00100101|00|00|Pm|01|Pg|0|Pn|1|Pd"},
|
||
|
|
{"inst": "bics Pd.B, Pg/Z, Pn.B, Pm.B" , "op": "00100101|01|10|Pm|01|Pg|0|Pn|1|Pd" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "brka Pd.B, Pg/MZ, Pn.B" , "op": "00100101|00|01000001|Pg|0|Pn|M|Pd"},
|
||
|
|
{"inst": "brkas Pd.B, Pg/M, Pn.B" , "op": "00100101|01|01000001|Pg|0|Pn|0|Pd" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "brkb Pd.B, Pg/MZ, Pn.B" , "op": "00100101|10|01000001|Pg|0|Pn|M|Pd"},
|
||
|
|
{"inst": "brkbs Pd.B, Pg/M, Pn.B" , "op": "00100101|11|01000001|Pg|0|Pn|0|Pd" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "brkn Pdm.B, Pg/Z, Pn.B, Pdm.B" , "op": "00100101|00|01100001|Pg|0|Pn|0|Pdm"},
|
||
|
|
{"inst": "brkns Pdm.B, Pg/Z, Pn.B, Pdm.B" , "op": "00100101|01|01100001|Pg|0|Pn|0|Pdm" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "brkpa Pd.B, Pg/Z, Pn.B, Pm.B" , "op": "00100101|00|00|Pm|11|Pg|0|Pn|0|Pd"},
|
||
|
|
{"inst": "brkpas Pd.B, Pg/Z, Pn.B, Pm.B" , "op": "00100101|01|00|Pm|11|Pg|0|Pn|0|Pd" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "brkpb Pd.B, Pg/Z, Pn.B, Pm.B" , "op": "00100101|00|00|Pm|11|Pg|0|Pn|1|Pd"},
|
||
|
|
{"inst": "brkpbs Pd.B, Pg/Z, Pn.B, Pm.B" , "op": "00100101|01|00|Pm|11|Pg|0|Pn|1|Pd" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "clasta Wdn, Pg, Wdn, Zm.t" , "op": "00000101|sz|110000101|Pg:3|Zm|Rdn" , "t": "BHS~"},
|
||
|
|
{"inst": "clasta Xdn, Pg, Xdn, Zm.D" , "op": "00000101|11|110000101|Pg:3|Zm|Rdn"},
|
||
|
|
{"inst": "clasta Bdn, Pg, Bdn, Zm.t" , "op": "00000101|00|101010100|Pg:3|Zm|Vdn"},
|
||
|
|
{"inst": "clasta Hdn, Pg, Hdn, Zm.t" , "op": "00000101|01|101010100|Pg:3|Zm|Vdn"},
|
||
|
|
{"inst": "clasta Sdn, Pg, Sdn, Zm.t" , "op": "00000101|10|101010100|Pg:3|Zm|Vdn"},
|
||
|
|
{"inst": "clasta Ddn, Pg, Ddn, Zm.t" , "op": "00000101|11|101010100|Pg:3|Zm|Vdn"},
|
||
|
|
{"inst": "clasta Zdn.t, Pg, Zdn.t, Zm.t" , "op": "00000101|sz|101000100|Pg:3|Zm|Zdn"},
|
||
|
|
{"inst": "clastb Wdn, Pg, Wdn, Zm.t" , "op": "00000101|sz|110001101|Pg:3|Zm|Rdn" , "t": "BHS~"},
|
||
|
|
{"inst": "clastb Xdn, Pg, Xdn, Zm.D" , "op": "00000101|11|110001101|Pg:3|Zm|Rdn"},
|
||
|
|
{"inst": "clastb Bdn, Pg, Bdn, Zm.t" , "op": "00000101|00|101011100|Pg:3|Zm|Vdn"},
|
||
|
|
{"inst": "clastb Hdn, Pg, Hdn, Zm.t" , "op": "00000101|01|101011100|Pg:3|Zm|Vdn"},
|
||
|
|
{"inst": "clastb Sdn, Pg, Sdn, Zm.t" , "op": "00000101|10|101011100|Pg:3|Zm|Vdn"},
|
||
|
|
{"inst": "clastb Ddn, Pg, Ddn, Zm.t" , "op": "00000101|11|101011100|Pg:3|Zm|Vdn"},
|
||
|
|
{"inst": "clastb Zdn.t, Pg, Zdn.t, Zm.t" , "op": "00000101|sz|101001100|Pg:3|Zm|Zdn"},
|
||
|
|
{"inst": "cls Zd.t, Pg/M, Zn.t" , "op": "00000100|sz|011000101|Pg:3|Zn|Zd"},
|
||
|
|
{"inst": "clz Zd.t, Pg/M, Zn.t" , "op": "00000100|sz|011001101|Pg:3|Zn|Zd"},
|
||
|
|
{"inst": "cmpeq Pd.t, Pg/Z, Zn.t, Zm.t" , "op": "00100100|sz|0|Zm|101|Pg:3|Zn|0|Pd" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "cmpeq Pd.t, Pg/Z, Zn.t, Zm.D" , "op": "00100100|sz|0|Zm|001|Pg:3|Zn|0|Pd" , "io": "N=W Z=W C=W V=W", "t": "BHS~"},
|
||
|
|
{"inst": "cmpeq Pd.t, Pg/Z, Zn.t, #immS" , "op": "00100101|sz|0|immS:5|100|Pg:3|Zn|0|Pd" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "cmpgt Pd.t, Pg/Z, Zn.t, Zm.t" , "op": "00100100|sz|0|Zm|100|Pg:3|Zn|1|Pd" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "cmpgt Pd.t, Pg/Z, Zn.t, Zm.D" , "op": "00100100|sz|0|Zm|010|Pg:3|Zn|1|Pd" , "io": "N=W Z=W C=W V=W", "t": "BHS~"},
|
||
|
|
{"inst": "cmpgt Pd.t, Pg/Z, Zn.t, #immS" , "op": "00100101|sz|0|immS:5|000|Pg:3|Zn|1|Pd" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "cmpge Pd.t, Pg/Z, Zn.t, Zm.t" , "op": "00100100|sz|0|Zm|100|Pg:3|Zn|0|Pd" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "cmpge Pd.t, Pg/Z, Zn.t, Zm.D" , "op": "00100100|sz|0|Zm|010|Pg:3|Zn|0|Pd" , "io": "N=W Z=W C=W V=W", "t": "BHS~"},
|
||
|
|
{"inst": "cmpge Pd.t, Pg/Z, Zn.t, #immS" , "op": "00100101|sz|0|immS:5|000|Pg:3|Zn|0|Pd" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "cmphi Pd.t, Pg/Z, Zn.t, Zm.t" , "op": "00100100|sz|0|Zm|000|Pg:3|Zn|1|Pd" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "cmphi Pd.t, Pg/Z, Zn.t, Zm.D" , "op": "00100100|sz|0|Zm|110|Pg:3|Zn|1|Pd" , "io": "N=W Z=W C=W V=W", "t": "BHS~"},
|
||
|
|
{"inst": "cmphi Pd.t, Pg/Z, Zn.t, #immS" , "op": "00100100|sz|1|immS:7|0|Pg:3|Zn|1|Pd" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "cmphs Pd.t, Pg/Z, Zn.t, Zm.t" , "op": "00100100|sz|0|Zm|000|Pg:3|Zn|0|Pd" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "cmphs Pd.t, Pg/Z, Zn.t, Zm.D" , "op": "00100100|sz|0|Zm|110|Pg:3|Zn|0|Pd" , "io": "N=W Z=W C=W V=W", "t": "BHS~"},
|
||
|
|
{"inst": "cmphs Pd.t, Pg/Z, Zn.t, #immS" , "op": "00100100|sz|1|immS:7|0|Pg:3|Zn|0|Pd" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "cmple Pd.t, Pg/Z, Zn.t, Zm.t" , "op": "00100100|sz|0|Zn|100|Pg:3|Zm|0|Pd" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "cmple Pd.t, Pg/Z, Zn.t, Zm.D" , "op": "00100100|sz|0|Zm|011|Pg:3|Zn|1|Pd" , "io": "N=W Z=W C=W V=W", "t": "BHS~"},
|
||
|
|
{"inst": "cmple Pd.t, Pg/Z, Zn.t, #immS" , "op": "00100101|sz|0|immS:5|001|Pg:3|Zn|1|Pd" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "cmplo Pd.t, Pg/Z, Zn.t, Zm.t" , "op": "00100100|sz|0|Zn|000|Pg:3|Zm|1|Pd" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "cmplo Pd.t, Pg/Z, Zn.t, Zm.D" , "op": "00100100|sz|0|Zm|111|Pg:3|Zn|0|Pd" , "io": "N=W Z=W C=W V=W", "t": "BHS~"},
|
||
|
|
{"inst": "cmplo Pd.t, Pg/Z, Zn.t, #immS" , "op": "00100100|sz|1|immS:7|1|Pg:3|Zn|0|Pd" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "cmpls Pd.t, Pg/Z, Zn.t, Zm.t" , "op": "00100100|sz|0|Zn|000|Pg:3|Zm|0|Pd" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "cmpls Pd.t, Pg/Z, Zn.t, Zm.D" , "op": "00100100|sz|0|Zm|111|Pg:3|Zn|1|Pd" , "io": "N=W Z=W C=W V=W", "t": "BHS~"},
|
||
|
|
{"inst": "cmpls Pd.t, Pg/Z, Zn.t, #immS" , "op": "00100100|sz|1|immS:7|1|Pg:3|Zn|1|Pd" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "cmplt Pd.t, Pg/Z, Zn.t, Zm.t" , "op": "00100100|sz|0|Zn|100|Pg:3|Zm|1|Pd" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "cmplt Pd.t, Pg/Z, Zn.t, Zm.D" , "op": "00100100|sz|0|Zm|011|Pg:3|Zn|0|Pd" , "io": "N=W Z=W C=W V=W", "t": "BHS~"},
|
||
|
|
{"inst": "cmplt Pd.t, Pg/Z, Zn.t, #immS" , "op": "00100101|sz|0|immS:5|001|Pg:3|Zn|0|Pd" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "cmpne Pd.t, Pg/Z, Zn.t, Zm.t" , "op": "00100100|sz|0|Zm|101|Pg:3|Zn|1|Pd" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "cmpne Pd.t, Pg/Z, Zn.t, Zm.D" , "op": "00100100|sz|0|Zm|001|Pg:3|Zn|1|Pd" , "io": "N=W Z=W C=W V=W", "t": "BHS~"},
|
||
|
|
{"inst": "cmpne Pd.t, Pg/Z, Zn.t, #immS" , "op": "00100101|sz|0|immS:5|100|Pg:3|Zn|1|Pd" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "cnot Zd.t, Pg/M, Zn.t" , "op": "00000100|sz|011011101|Pg:3|Zn|Zd"},
|
||
|
|
{"inst": "cnt Zd.t, Pg/M, Zn.t" , "op": "00000100|sz|011010101|Pg:3|Zn|Zd"},
|
||
|
|
{"inst": "cntb Xd, {#pattern}, {mul #imm}" , "op": "00000100|00|10|imm:4|111000|pattern:5|Rd" , "imm": "SvePatternImm(pattern, imm)"},
|
||
|
|
{"inst": "cntd Xd, {#pattern}, {mul #imm}" , "op": "00000100|11|10|imm:4|111000|pattern:5|Rd" , "imm": "SvePatternImm(pattern, imm)"},
|
||
|
|
{"inst": "cnth Xd, {#pattern}, {mul #imm}" , "op": "00000100|01|10|imm:4|111000|pattern:5|Rd" , "imm": "SvePatternImm(pattern, imm)"},
|
||
|
|
{"inst": "cntp Xd, Pg, Pn.t" , "op": "00100101|sz|10000010|Pg|0|Pn|Rd"},
|
||
|
|
{"inst": "cntw Xd, {#pattern}, {mul #imm}" , "op": "00000100|10|10|imm:4|111000|pattern:5|Rd" , "imm": "SvePatternImm(pattern, imm)"},
|
||
|
|
{"inst": "compact Zd.t, Pg, Zn.t" , "op": "00000101|sz|10000010|Pg|0|Pn|Rd" , "t": "~~SD"},
|
||
|
|
{"inst": "cpy Zd.t, Pg/M, Wn|SP" , "op": "00000101|sz|101000101|Pg:3|Rn|Zd" , "t": "BHS~"},
|
||
|
|
{"inst": "cpy Zd.D, Pg/M, Xn|SP" , "op": "00000101|11|101000101|Pg:3|Rn|Zd"},
|
||
|
|
{"inst": "cpy Zd.B, Pg/M, Bn" , "op": "00000101|00|100000100|Pg:3|Rn|Zd"},
|
||
|
|
{"inst": "cpy Zd.H, Pg/M, Hn" , "op": "00000101|01|100000100|Pg:3|Rn|Zd"},
|
||
|
|
{"inst": "cpy Zd.S, Pg/M, Sn" , "op": "00000101|10|100000100|Pg:3|Rn|Zd"},
|
||
|
|
{"inst": "cpy Zd.D, Pg/M, Dn" , "op": "00000101|11|100000100|Pg:3|Rn|Zd"},
|
||
|
|
{"inst": "cpy Zd.t, Pg/MZ, #imm, {lsl #n}" , "op": "00000101|sz|01|Pg|0|M|n:1|imm:8|Zd"},
|
||
|
|
{"inst": "ctermeq Rn, Rm" , "op": "00100101|1X|1|Rm|001000|Rn|00000"},
|
||
|
|
{"inst": "ctermne Rn, Rm" , "op": "00100101|1X|1|Rm|001000|Rn|10000"},
|
||
|
|
{"inst": "decb Xdn, {#pattern}, {mul #imm}" , "op": "00000100|00|11|imm:4|111001|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
|
||
|
|
{"inst": "decd Xdn, {#pattern}, {mul #imm}" , "op": "00000100|11|11|imm:4|111001|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
|
||
|
|
{"inst": "decd Zdn.D, {#pattern}, {mul #imm}" , "op": "00000100|11|11|imm:4|110001|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
|
||
|
|
{"inst": "dech Xdn, {#pattern}, {mul #imm}" , "op": "00000100|01|11|imm:4|111001|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
|
||
|
|
{"inst": "dech Zdn.H, {#pattern}, {mul #imm}" , "op": "00000100|01|11|imm:4|110001|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
|
||
|
|
{"inst": "decp Xdn, Pm.t" , "op": "00100101|sz|1011011000100|Pm|Rdn"},
|
||
|
|
{"inst": "decp Zdn.t, Pm.t" , "op": "00100101|sz|1011011000000|Pm|Zdn" , "t": "~HSD"},
|
||
|
|
{"inst": "decw Xdn, {#pattern}, {mul #imm}" , "op": "00000100|10|11|imm:4|111001|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
|
||
|
|
{"inst": "decw Zdn.S, {#pattern}, {mul #imm}" , "op": "00000100|10|11|imm:4|110001|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
|
||
|
|
{"inst": "dup Zd.t, Wn|SP" , "op": "00000101|sz|100000001110|Rn|Zd" , "T": "BHS~"},
|
||
|
|
{"inst": "dup Zd.t, Xn|SP" , "op": "00000101|11|100000001110|Rn|Zd"},
|
||
|
|
{"inst": "dup Zd.t, Zn.t[#idx]" , "op": "00000101|imm:2|1|imm:5|001000|Zn|Zd" , "imm": "SveDupImm(sz, idx)"},
|
||
|
|
{"inst": "dup Zd.t, #imm, {lsl #n}" , "op": "00100101|sz|11100011|n:1|imm:8|Zd"},
|
||
|
|
{"inst": "dupm Zd.t, #imm" , "op": "00000101|11|0000|imm:13|Zd" , "imm": "SveDupmImm(sz, imm)"},
|
||
|
|
{"inst": "eon Zdn.t, Zdn.t, #imm" , "op": "00000101|01|0000|imm:13|Zdn" , "imm": "SveLogicalImm(imm, 1, t)"},
|
||
|
|
{"inst": "eor Zd.D, Zn.D, Zm.D" , "op": "00000100|10|1|Zm|001100|Zn|Zd"},
|
||
|
|
{"inst": "eor Zdn.t, Zdn.t, #imm" , "op": "00000101|01|0000|imm:13|Zdn" , "imm": "SveLogicalImm(imm, 0, t)"},
|
||
|
|
{"inst": "eor Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "00000100|sz|011001000|Pg:3|Zm|Zdn"},
|
||
|
|
{"inst": "eor Pd.B, Pg/Z, Pn.B, Pm.B" , "op": "00100101|00|00|Pm|01|Pg|1|Pn|0|Pd"},
|
||
|
|
{"inst": "eors Pd.B, Pg/Z, Pn.B, Pm.B" , "op": "00100101|01|00|Pm|01|Pg|1|Pn|0|Pd" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "eorv Bd, Pg, Zn.t" , "op": "00000100|00|011001001|Pg:3|Zn|Vd"},
|
||
|
|
{"inst": "eorv Hd, Pg, Zn.t" , "op": "00000100|01|011001001|Pg:3|Zn|Vd"},
|
||
|
|
{"inst": "eorv Sd, Pg, Zn.t" , "op": "00000100|10|011001001|Pg:3|Zn|Vd"},
|
||
|
|
{"inst": "eorv Dd, Pg, Zn.t" , "op": "00000100|11|011001001|Pg:3|Zn|Vd"},
|
||
|
|
{"inst": "ext Zdn.B, Zdn.B, Zm.B, #imm" , "op": "00000101|00|1|imm:5|000|imm:3|Zm|Zdn"},
|
||
|
|
{"inst": "fabd Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01100101|sz|001000100|Pg:3|Zm|Zdn" , "t": "~HSD"},
|
||
|
|
{"inst": "fabs Zd.t, Pg/M, Zn.t" , "op": "00000100|sz|011100101|Pg:3|Zn|Zd" , "t": "~HSD"},
|
||
|
|
{"inst": "facge Pd.t, Pg/Z, Zn.t, Zm.t" , "op": "01100101|sz|0|Zm|110|Pg:3|Zn|1|Pd" , "t": "~HSD"},
|
||
|
|
{"inst": "facgt Pd.t, Pg/Z, Zn.t, Zm.t" , "op": "01100101|sz|0|Zm|111|Pg:3|Zn|1|Pd" , "t": "~HSD"},
|
||
|
|
{"inst": "facle Pd.t, Pg/Z, Zn.t, Zm.t" , "op": "01100101|sz|0|Zn|110|Pg:3|Zm|1|Pd" , "t": "~HSD"},
|
||
|
|
{"inst": "faclt Pd.t, Pg/Z, Zn.t, Zm.t" , "op": "01100101|sz|0|Zn|111|Pg:3|Zm|1|Pd" , "t": "~HSD"},
|
||
|
|
{"inst": "fadd Zd.t, Zn.t, Zm.t" , "op": "01100101|sz|0|Zm|000000|Zn|Zd" , "t": "~HSD"},
|
||
|
|
{"inst": "fadd Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01100101|sz|000000100|Pg:3|Zm|Zdn" , "t": "~HSD"},
|
||
|
|
{"inst": "fadd Zdn.t, Pg/M, Zdn.t, #immF" , "op": "01100101|sz|011000100|Pg:3|0000|imm:1|Zdn" , "t": "~HSD", "imm": "FpHalfOrOneImm(immF)"},
|
||
|
|
{"inst": "fadda Hdn, Pg, Hdn, Zm.H" , "op": "01100101|01|011000001|Pg:3|Zm|Vdn"},
|
||
|
|
{"inst": "fadda Sdn, Pg, Sdn, Zm.S" , "op": "01100101|10|011000001|Pg:3|Zm|Vdn"},
|
||
|
|
{"inst": "fadda Ddn, Pg, Ddn, Zm.D" , "op": "01100101|11|011000001|Pg:3|Zm|Vdn"},
|
||
|
|
{"inst": "faddv Hd, Pg, Zn.H" , "op": "01100101|01|000000001|Pg:3|Zn|Vd"},
|
||
|
|
{"inst": "faddv Sd, Pg, Zn.S" , "op": "01100101|10|000000001|Pg:3|Zn|Vd"},
|
||
|
|
{"inst": "faddv Dd, Pg, Zn.D" , "op": "01100101|11|000000001|Pg:3|Zn|Vd"},
|
||
|
|
{"inst": "fcadd Zdn.t, Pg/M, Zdn.t, Zm.t, #rot2" , "op": "01100100|sz|00000|imm:1|100|Pg:3|Zm|Zdn" , "t": "~HSD", "imm": "Rot1Imm(rot1)"},
|
||
|
|
{"inst": "fcmeq Pd.t, Pg/Z, Zn.t, Zm.t" , "op": "01100101|sz|0|Zm|011|Pg:3|Zn|0|Pd" , "t": "~HSD"},
|
||
|
|
{"inst": "fcmeq Pd.t, Pg/Z, Zn.t, #zero" , "op": "01100101|sz|0|10010001|Pg:3|Zn|0|Pd" , "t": "~HSD"},
|
||
|
|
{"inst": "fcmge Pd.t, Pg/Z, Zn.t, Zm.t" , "op": "01100101|sz|0|Zm|010|Pg:3|Zn|0|Pd" , "t": "~HSD"},
|
||
|
|
{"inst": "fcmge Pd.t, Pg/Z, Zn.t, #zero" , "op": "01100101|sz|0|10000001|Pg:3|Zn|0|Pd" , "t": "~HSD"},
|
||
|
|
{"inst": "fcmgt Pd.t, Pg/Z, Zn.t, Zm.t" , "op": "01100101|sz|0|Zm|010|Pg:3|Zn|1|Pd" , "t": "~HSD"},
|
||
|
|
{"inst": "fcmgt Pd.t, Pg/Z, Zn.t, #zero" , "op": "01100101|sz|0|10000001|Pg:3|Zn|1|Pd" , "t": "~HSD"},
|
||
|
|
{"inst": "fcmle Pd.t, Pg/Z, Zn.t, Zm.t" , "op": "01100101|sz|0|Zn|010|Pg:3|Zm|0|Pd" , "t": "~HSD"},
|
||
|
|
{"inst": "fcmle Pd.t, Pg/Z, Zn.t, #zero" , "op": "01100101|sz|010001001|Pg:3|Zn|1|Pd" , "t": "~HSD"},
|
||
|
|
{"inst": "fcmlt Pd.t, Pg/Z, Zn.t, Zm.t" , "op": "01100101|sz|0|Zn|010|Pg:3|Zm|1|Pd" , "t": "~HSD"},
|
||
|
|
{"inst": "fcmlt Pd.t, Pg/Z, Zn.t, #zero" , "op": "01100101|sz|010001001|Pg:3|Zn|0|Pd" , "t": "~HSD"},
|
||
|
|
{"inst": "fcmne Pd.t, Pg/Z, Zn.t, Zm.t" , "op": "01100101|sz|0|Zm|011|Pg:3|Zn|1|Pd" , "t": "~HSD"},
|
||
|
|
{"inst": "fcmne Pd.t, Pg/Z, Zn.t, #zero" , "op": "01100101|sz|010011001|Pg:3|Zn|0|Pd" , "t": "~HSD"},
|
||
|
|
{"inst": "fcmuo Pd.t, Pg/Z, Zn.t, Zm.t" , "op": "01100101|sz|0|Zm|110|Pg:3|Zn|0|Pd" , "t": "~HSD"},
|
||
|
|
{"inst": "fcpy Zd.t, Pg/M, #immVFP" , "op": "00000101|sz|01|Pg|110|imm:8|Zd" , "t": "~HSD", "imm": "VecVFPImm(immVFP)"},
|
||
|
|
{"inst": "fcvt Zd.S, Pg/M, Zn.H" , "op": "01100101|10|001001101|Pg:3|Zn|Zd"},
|
||
|
|
{"inst": "fcvt Zd.D, Pg/M, Zn.H" , "op": "01100101|11|001001101|Pg:3|Zn|Zd"},
|
||
|
|
{"inst": "fcvt Zd.H, Pg/M, Zn.S" , "op": "01100101|10|001000101|Pg:3|Zn|Zd"},
|
||
|
|
{"inst": "fcvt Zd.D, Pg/M, Zn.S" , "op": "01100101|11|001011101|Pg:3|Zn|Zd"},
|
||
|
|
{"inst": "fcvt Zd.H, Pg/M, Zn.D" , "op": "01100101|11|001000101|Pg:3|Zn|Zd"},
|
||
|
|
{"inst": "fcvt Zd.S, Pg/M, Zn.D" , "op": "01100101|11|001010101|Pg:3|Zn|Zd"},
|
||
|
|
{"inst": "fcvtzs Zd.H, Pg/M, Zn.H" , "op": "01100101|01|011010101|Pg:3|Zn|Zd"},
|
||
|
|
{"inst": "fcvtzs Zd.S, Pg/M, Zn.H" , "op": "01100101|01|011100101|Pg:3|Zn|Zd"},
|
||
|
|
{"inst": "fcvtzs Zd.D, Pg/M, Zn.H" , "op": "01100101|01|011110101|Pg:3|Zn|Zd"},
|
||
|
|
{"inst": "fcvtzs Zd.S, Pg/M, Zn.S" , "op": "01100101|10|011100101|Pg:3|Zn|Zd"},
|
||
|
|
{"inst": "fcvtzs Zd.D, Pg/M, Zn.S" , "op": "01100101|11|011100101|Pg:3|Zn|Zd"},
|
||
|
|
{"inst": "fcvtzs Zd.S, Pg/M, Zn.D" , "op": "01100101|11|011000101|Pg:3|Zn|Zd"},
|
||
|
|
{"inst": "fcvtzs Zd.D, Pg/M, Zn.D" , "op": "01100101|11|011110101|Pg:3|Zn|Zd"},
|
||
|
|
{"inst": "fcvtzu Zd.H, Pg/M, Zn.H" , "op": "01100101|01|011011101|Pg:3|Zn|Zd"},
|
||
|
|
{"inst": "fcvtzu Zd.S, Pg/M, Zn.H" , "op": "01100101|01|011101101|Pg:3|Zn|Zd"},
|
||
|
|
{"inst": "fcvtzu Zd.D, Pg/M, Zn.H" , "op": "01100101|01|011111101|Pg:3|Zn|Zd"},
|
||
|
|
{"inst": "fcvtzu Zd.S, Pg/M, Zn.S" , "op": "01100101|10|011101101|Pg:3|Zn|Zd"},
|
||
|
|
{"inst": "fcvtzu Zd.D, Pg/M, Zn.S" , "op": "01100101|11|011101101|Pg:3|Zn|Zd"},
|
||
|
|
{"inst": "fcvtzu Zd.S, Pg/M, Zn.D" , "op": "01100101|11|011001101|Pg:3|Zn|Zd"},
|
||
|
|
{"inst": "fcvtzu Zd.D, Pg/M, Zn.D" , "op": "01100101|11|011111101|Pg:3|Zn|Zd"},
|
||
|
|
{"inst": "fdiv Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01100101|sz|001101100|Pg:3|Zm|Zdn" , "t": "~HSD"},
|
||
|
|
{"inst": "fdivr Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01100101|sz|001100100|Pg:3|Zm|Zdn" , "t": "~HSD"},
|
||
|
|
{"inst": "fdup Zd.t, #immVFP" , "op": "00100101|sz|111001110|imm:8|Zd" , "t": "~HSD", "imm": "VecVFPImm(immVFP)"},
|
||
|
|
{"inst": "fexpa Zd.t, Zn.t" , "op": "00000100|sz|100000101110|Zm|Zdn" , "t": "~HSD"},
|
||
|
|
{"inst": "fmad Zdn.t, Pg/M, Zm.t, Za.t" , "op": "01100101|sz|1|Za|100|Pg:3|Zm|Zdn" , "t": "~HSD"},
|
||
|
|
{"inst": "fmax Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01100101|sz|000110100|Pg:3|Zm|Zdn" , "t": "~HSD"},
|
||
|
|
{"inst": "fmax Zdn.t, Pg/M, Zdn.t, #immF" , "op": "01100101|sz|011110100|Pg:3|0000|imm:1|Zdn" , "t": "~HSD", "imm": "FpZeroOrOneImm(immF)"},
|
||
|
|
{"inst": "fmaxnm Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01100101|sz|000100100|Pg:3|Zm|Zdn" , "t": "~HSD"},
|
||
|
|
{"inst": "fmaxnm Zdn.t, Pg/M, Zdn.t, #immF" , "op": "01100101|sz|011100100|Pg:3|0000|imm:1|Zdn" , "t": "~HSD", "imm": "FpZeroOrOneImm(immF)"},
|
||
|
|
{"inst": "fmaxnmv Hd, Pg, Zn.H" , "op": "01100101|01|000100001|Pg:3|Zm|Zd"},
|
||
|
|
{"inst": "fmaxnmv Sd, Pg, Zn.S" , "op": "01100101|10|000100001|Pg:3|Zm|Zd"},
|
||
|
|
{"inst": "fmaxnmv Dd, Pg, Zn.D" , "op": "01100101|11|000100001|Pg:3|Zm|Zd"},
|
||
|
|
{"inst": "fmaxv Hd, Pg, Zn.H" , "op": "01100101|01|000110001|Pg:3|Zm|Zd"},
|
||
|
|
{"inst": "fmaxv Sd, Pg, Zn.S" , "op": "01100101|10|000110001|Pg:3|Zm|Zd"},
|
||
|
|
{"inst": "fmaxv Dd, Pg, Zn.D" , "op": "01100101|11|000110001|Pg:3|Zm|Zd"},
|
||
|
|
{"inst": "fmin Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01100101|sz|000111100|Pg:3|Zm|Zdn" , "t": "~HSD"},
|
||
|
|
{"inst": "fmin Zdn.t, Pg/M, Zdn.t, #immF" , "op": "01100101|sz|011111100|Pg:3|0000|imm:1|Zdn" , "t": "~HSD", "imm": "FpZeroOrOneImm(immF)"},
|
||
|
|
{"inst": "fminnm Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01100101|sz|000101100|Pg:3|Zm|Zdn" , "t": "~HSD"},
|
||
|
|
{"inst": "fminnm Zdn.t, Pg/M, Zdn.t, #immF" , "op": "01100101|sz|011101100|Pg:3|0000|imm:1|Zdn" , "t": "~HSD", "imm": "FpZeroOrOneImm(immF)"},
|
||
|
|
{"inst": "fminnmv Hd, Pg, Zn.H" , "op": "01100101|01|000101001|Pg:3|Zm|Zd"},
|
||
|
|
{"inst": "fminnmv Sd, Pg, Zn.S" , "op": "01100101|10|000101001|Pg:3|Zm|Zd"},
|
||
|
|
{"inst": "fminnmv Dd, Pg, Zn.D" , "op": "01100101|11|000101001|Pg:3|Zm|Zd"},
|
||
|
|
{"inst": "fminv Hd, Pg, Zn.H" , "op": "01100101|01|000111001|Pg:3|Zm|Zd"},
|
||
|
|
{"inst": "fminv Sd, Pg, Zn.S" , "op": "01100101|10|000111001|Pg:3|Zm|Zd"},
|
||
|
|
{"inst": "fminv Dd, Pg, Zn.D" , "op": "01100101|11|000111001|Pg:3|Zm|Zd"},
|
||
|
|
{"inst": "fmla Zda.t, Pg/M, Zn.t, Zm.t" , "op": "01100101|sz|1|Zm|000|Pg:3|Zn|Zda" , "t": "~HSD"},
|
||
|
|
{"inst": "fmla Zda.H, Zn.H, Zm.H[#idx]" , "op": "01100100|0|idx:1|1|idx:2|Zm:3|000000|Zn|Zda" , "t": "~HSD"},
|
||
|
|
{"inst": "fmla Zda.S, Zn.S, Zm.S[#idx]" , "op": "01100100|10|1|idx:2|Zm:3|000000|Zn|Zda" , "t": "~HSD"},
|
||
|
|
{"inst": "fmla Zda.D, Zn.D, Zm.D[#idx]" , "op": "01100100|11|1|idx:1|Zm:4|000000|Zn|Zda" , "t": "~HSD"},
|
||
|
|
{"inst": "fmls Zda.t, Pg/M, Zn.t, Zm.t" , "op": "01100101|sz|1|Zm|001|Pg:3|Zn|Zda" , "t": "~HSD"},
|
||
|
|
{"inst": "fmls Zda.H, Zn.H, Zm.H[#idx]" , "op": "01100100|0|idx:1|1|idx:2|Zm:3|000001|Zn|Zda" , "t": "~HSD"},
|
||
|
|
{"inst": "fmls Zda.S, Zn.S, Zm.S[#idx]" , "op": "01100100|10|1|idx:2|Zm:3|000001|Zn|Zda" , "t": "~HSD"},
|
||
|
|
{"inst": "fmls Zda.D, Zn.D, Zm.D[#idx]" , "op": "01100100|11|1|idx:1|Zm:4|000001|Zn|Zda" , "t": "~HSD"},
|
||
|
|
{"inst": "fmov Zd.t, #zero" , "op": "00100101|sz|111000110|00000000|Zd" , "t": "~HSD", "aliasOf": "dup"},
|
||
|
|
{"inst": "fmov Zd.t, #immVFP" , "op": "00100101|sz|111001110|imm:8|Zd" , "t": "~HSD", "imm": "VecVFPImm(immVFP)", "aliasOf": "fdup"},
|
||
|
|
{"inst": "fmov Zd.t, Pg/M, #zero" , "op": "00000101|sz|01|Pg|010|00000000|Zd" , "t": "~HSD", "aliasOf": "cpy"},
|
||
|
|
{"inst": "fmov Zd.t, Pg/M, #immVFP" , "op": "00000101|sz|01|Pg|110|imm:8|Zd" , "t": "~HSD", "imm": "VecVFPImm(immVFP)", "aliasOf": "fcpy"},
|
||
|
|
{"inst": "fmsb Zdn.t, Pg/M, Zm.t, Za.t" , "op": "01100101|sz|1|Za|101|Pg:3|Zm|Zdn" , "t": "~HSD"},
|
||
|
|
{"inst": "fmul Zd.t, Zn.t, Zm.t" , "op": "01100101|sz|0|Zm|000010|Zn|Zd" , "t": "~HSD"},
|
||
|
|
{"inst": "fmul Zd.H, Zn.H, Zm.H[#idx]" , "op": "01100100|0|idx:1|1|idx:2|Zm:3|001000|Zn|Zda" , "t": "~HSD"},
|
||
|
|
{"inst": "fmul Zd.S, Zn.S, Zm.S[#idx]" , "op": "01100100|10|1|idx:2|Zm:3|001000|Zn|Zda" , "t": "~HSD"},
|
||
|
|
{"inst": "fmul Zd.D, Zn.D, Zm.D[#idx]" , "op": "01100100|11|1|idx:1|Zm:4|001000|Zn|Zda" , "t": "~HSD"},
|
||
|
|
{"inst": "fmul Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01100101|sz|000010100|Pg:3|Zm|Zdn" , "t": "~HSD"},
|
||
|
|
{"inst": "fmul Zdn.t, Pg/M, Zdn.t, #immF" , "op": "01100101|sz|011010100|Pg:3|0000|imm:1|Zdn" , "t": "~HSD", "imm": "FpHalfOrTwoImm(immF)"},
|
||
|
|
{"inst": "fmulx Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01100101|sz|001010100|Pg:3|Zm|Zdn" , "t": "~HSD"},
|
||
|
|
{"inst": "fneg Zd.t, Pg/M, Zn.t" , "op": "00000100|sz|011101101|Pg:3|Zm|Zdn" , "t": "~HSD"},
|
||
|
|
{"inst": "fnmad Zdn.t, Pg/M, Zm.t, Za.t" , "op": "01100101|sz|1|Za|110|Pg:3|Zm|Zdn" , "t": "~HSD"},
|
||
|
|
{"inst": "fnmla Zda.t, Pg/M, Zn.t, Zm.t" , "op": "01100101|sz|1|Zm|010|Pg:3|Zn|Zda" , "t": "~HSD"},
|
||
|
|
{"inst": "fnmls Zda.t, Pg/M, Zn.t, Zm.t" , "op": "01100101|sz|1|Zm|011|Pg:3|Zn|Zda" , "t": "~HSD"},
|
||
|
|
{"inst": "fnmsb Zdn.t, Pg/M, Zm.t, Za.t" , "op": "01100101|sz|1|Za|111|Pg:3|Zm|Zdn" , "t": "~HSD"},
|
||
|
|
{"inst": "frecpe Zd.t, Zn.t" , "op": "01100101|sz|001110001100|Zn|Zd" , "t": "~HSD"},
|
||
|
|
{"inst": "frecps Zd.t, Zn.t, Zm.t" , "op": "01100101|sz|0|Zm|000110|Zn|Zd" , "t": "~HSD"},
|
||
|
|
{"inst": "frecpx Zd.t, Pg/M, Zn.t" , "op": "01100101|sz|001100101|Pg:3|Zn|Zd" , "t": "~HSD"},
|
||
|
|
{"inst": "frinta Zd.t, Pg/M, Zn.t" , "op": "01100101|sz|000100101|Pg:3|Zn|Zd" , "t": "~HSD"},
|
||
|
|
{"inst": "frinti Zd.t, Pg/M, Zn.t" , "op": "01100101|sz|000111101|Pg:3|Zn|Zd" , "t": "~HSD"},
|
||
|
|
{"inst": "frintm Zd.t, Pg/M, Zn.t" , "op": "01100101|sz|000010101|Pg:3|Zn|Zd" , "t": "~HSD"},
|
||
|
|
{"inst": "frintn Zd.t, Pg/M, Zn.t" , "op": "01100101|sz|000000101|Pg:3|Zn|Zd" , "t": "~HSD"},
|
||
|
|
{"inst": "frintp Zd.t, Pg/M, Zn.t" , "op": "01100101|sz|000001101|Pg:3|Zn|Zd" , "t": "~HSD"},
|
||
|
|
{"inst": "frintx Zd.t, Pg/M, Zn.t" , "op": "01100101|sz|000110101|Pg:3|Zn|Zd" , "t": "~HSD"},
|
||
|
|
{"inst": "frintz Zd.t, Pg/M, Zn.t" , "op": "01100101|sz|000011101|Pg:3|Zn|Zd" , "t": "~HSD"},
|
||
|
|
{"inst": "frsqrte Zd.t, Zn.t" , "op": "01100101|sz|001111001100|Zn|Zd" , "t": "~HSD"},
|
||
|
|
{"inst": "frsqrts Zd.t, Zn.t, Zm.t" , "op": "01100101|sz|0|Zm|000111|Zn|Zd" , "t": "~HSD"},
|
||
|
|
{"inst": "fscale Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01100101|sz|001001100|Pg:3|Zm|Zdn" , "t": "~HSD"},
|
||
|
|
{"inst": "fsqrt Zd.t, Pg/M, Zn.t" , "op": "01100101|sz|001101101|Pg:3|Zn|Zd" , "t": "~HSD"},
|
||
|
|
{"inst": "fsub Zd.t, Zn.t, Zm.t" , "op": "01100101|sz|0|Zm|000001|Zn|Zd" , "t": "~HSD"},
|
||
|
|
{"inst": "fsub Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01100101|sz|000001100|Pg:3|Zm|Zdn" , "t": "~HSD"},
|
||
|
|
{"inst": "fsub Zdn.t, Pg/M, Zdn.t, #immF" , "op": "01100101|sz|011001100|Pg:3|0000|imm:1|Zdn" , "t": "~HSD", "imm": "FpHalfOrOneImm(immF)"},
|
||
|
|
{"inst": "fsubr Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01100101|sz|000011100|Pg:3|Zm|Zdn" , "t": "~HSD"},
|
||
|
|
{"inst": "fsubr Zdn.t, Pg/M, Zdn.t, #immF" , "op": "01100101|sz|011011100|Pg:3|0000|imm:1|Zdn" , "t": "~HSD", "imm": "FpHalfOrOneImm(immF)"},
|
||
|
|
{"inst": "ftmad Zdn.t, Zdn.t, Zm.t, #imm" , "op": "01100101|sz|010|imm:3|100000|Zm|Zdn" , "t": "~HSD"},
|
||
|
|
{"inst": "ftsmul Zd.t, Zn.t, Zm.t" , "op": "01100101|sz|0|Zm|000011|Zn|Zd" , "t": "~HSD"},
|
||
|
|
{"inst": "ftssel Zd.t, Zn.t, Zm.t" , "op": "00000100|sz|1|Zm|101100|Zn|Zd" , "t": "~HSD"},
|
||
|
|
{"inst": "incb Xdn, {#pattern}, {mul #imm}" , "op": "00000100|00|11|imm:4|111000|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
|
||
|
|
{"inst": "incd Xdn, {#pattern}, {mul #imm}" , "op": "00000100|11|11|imm:4|111000|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
|
||
|
|
{"inst": "incd Zdn.D, {#pattern}, {mul #imm}" , "op": "00000100|11|11|imm:4|110000|pattern:5|Zdn" , "imm": "SvePatternImm(pattern, imm)"},
|
||
|
|
{"inst": "inch Xdn, {#pattern}, {mul #imm}" , "op": "00000100|01|11|imm:4|111000|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
|
||
|
|
{"inst": "inch Zdn.H, {#pattern}, {mul #imm}" , "op": "00000100|01|11|imm:4|110000|pattern:5|Zdn" , "imm": "SvePatternImm(pattern, imm)"},
|
||
|
|
{"inst": "incp Xdn, Pm.t" , "op": "00100101|sz|1011001000100|Pm|Rdn"},
|
||
|
|
{"inst": "incp Zdn.t, Pm.t" , "op": "00100101|sz|1011001000000|Pm|Zdn" , "t": "~HSD"},
|
||
|
|
{"inst": "incw Xdn, {#pattern}, {mul #imm}" , "op": "00000100|10|11|imm:4|111000|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
|
||
|
|
{"inst": "incw Zdn.S, {#pattern}, {mul #imm}" , "op": "00000100|10|11|imm:4|110000|pattern:5|Zdn" , "imm": "SvePatternImm(pattern, imm)"},
|
||
|
|
{"inst": "index Zd.t, Wn, Wm" , "op": "00000100|sz|1|Rm|010011|Rn|Zd" , "t": "BHS~"},
|
||
|
|
{"inst": "index Zd.D, Xn, Xm" , "op": "00000100|11|1|Rm|010011|Rn|Zd"},
|
||
|
|
{"inst": "index Zd.t, Wn, #immS" , "op": "00000100|sz|1|immS:5|010001|Rn|Zd" , "t": "BHS~"},
|
||
|
|
{"inst": "index Zd.D, Xn, #immS" , "op": "00000100|11|1|immS:5|010001|Rn|Zd"},
|
||
|
|
{"inst": "index Zd.t, #immS, Wm" , "op": "00000100|sz|1|Rm|010010|immS:5|Zd" , "t": "BHS~"},
|
||
|
|
{"inst": "index Zd.D, #immS, Xm" , "op": "00000100|11|1|Rm|010010|immS:5|Zd"},
|
||
|
|
{"inst": "index Zd.t, #immSa, #immSb" , "op": "00000100|sz|1|immSb:5|010000|immSa:5|Zd"},
|
||
|
|
{"inst": "insr Zdn.t, Wm" , "op": "00000101|sz|100100001110|Rm|Zdn" , "t": "BHS~"},
|
||
|
|
{"inst": "insr Zdn.D, Xm" , "op": "00000101|11|100100001110|Rm|Zdn"},
|
||
|
|
{"inst": "insr Zdn.B, Bm" , "op": "00000101|00|110100001110|Vm|Zdn"},
|
||
|
|
{"inst": "insr Zdn.H, Hm" , "op": "00000101|01|110100001110|Vm|Zdn"},
|
||
|
|
{"inst": "insr Zdn.S, Sm" , "op": "00000101|10|110100001110|Vm|Zdn"},
|
||
|
|
{"inst": "insr Zdn.D, Dm" , "op": "00000101|11|110100001110|Vm|Zdn"},
|
||
|
|
{"inst": "lasta Wd, Pg, Zn.t" , "op": "00000101|sz|100000101|Pg:3|Zn|Rd" , "t": "BHS~"},
|
||
|
|
{"inst": "lasta Xd, Pg, Zn.D" , "op": "00000101|11|100000101|Pg:3|Zn|Rd"},
|
||
|
|
{"inst": "lasta Bd, Pg, Zn.B" , "op": "00000101|00|100010100|Pg:3|Zn|Rd"},
|
||
|
|
{"inst": "lasta Hd, Pg, Zn.H" , "op": "00000101|01|100010100|Pg:3|Zn|Rd"},
|
||
|
|
{"inst": "lasta Sd, Pg, Zn.S" , "op": "00000101|10|100010100|Pg:3|Zn|Rd"},
|
||
|
|
{"inst": "lasta Dd, Pg, Zn.D" , "op": "00000101|11|100010100|Pg:3|Zn|Rd"},
|
||
|
|
{"inst": "lastb Wd, Pg, Zn.t" , "op": "00000101|sz|100001101|Pg:3|Zn|Rd" , "t": "BHS~"},
|
||
|
|
{"inst": "lastb Xd, Pg, Zn.D" , "op": "00000101|11|100001101|Pg:3|Zn|Rd"},
|
||
|
|
{"inst": "lastb Bd, Pg, Zn.B" , "op": "00000101|00|100011100|Pg:3|Zn|Rd"},
|
||
|
|
{"inst": "lastb Hd, Pg, Zn.H" , "op": "00000101|01|100011100|Pg:3|Zn|Rd"},
|
||
|
|
{"inst": "lastb Sd, Pg, Zn.S" , "op": "00000101|10|100011100|Pg:3|Zn|Rd"},
|
||
|
|
{"inst": "lastb Dd, Pg, Zn.D" , "op": "00000101|11|100011100|Pg:3|Zn|Rd"},
|
||
|
|
|
||
|
|
{"inst": "lsl Zd.t, Zn.t, Zm.D" , "op": "00000100|sz|1|Zm|100011|Zn|Zd" , "t": "BHS~"},
|
||
|
|
{"inst": "lsl Zd.t, Zn.t, #imm" , "op": "00000100|imm:2|1|imm:5|100111|Zn|Zd" , "imm": "SveShiftImm7(sz, imm)"},
|
||
|
|
{"inst": "lsl Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "00000100|sz|010011100|Pg:3|Zm|Zdn"},
|
||
|
|
{"inst": "lsl Zdn.t, Pg/M, Zdn.t, Zm.D" , "op": "00000100|sz|011011100|Pg:3|Zm|Zdn" , "t": "BHS~"},
|
||
|
|
{"inst": "lsl Zdn.t, Pg/M, Zdn.t, #imm" , "op": "00000100|imm:2|000011100|Pg:3|imm:5|Zdn" , "imm": "SveShiftImm7(sz, imm)"},
|
||
|
|
{"inst": "lslr Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "00000100|sz|010111100|Pg:3|Zm|Zdn"},
|
||
|
|
{"inst": "lsr Zd.t, Zn.t, Zm.D" , "op": "00000100|sz|1|Zm|100001|Zn|Zd" , "t": "BHS~"},
|
||
|
|
{"inst": "lsr Zd.t, Zn.t, #imm" , "op": "00000100|imm:2|1|imm:5|100101|Zn|Zd" , "imm": "SveShiftImm7(sz, imm)"},
|
||
|
|
{"inst": "lsr Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "00000100|sz|010001100|Pg:3|Zm|Zdn"},
|
||
|
|
{"inst": "lsr Zdn.t, Pg/M, Zdn.t, Zm.D" , "op": "00000100|sz|011001100|Pg:3|Zm|Zdn" , "t": "BHS~"},
|
||
|
|
{"inst": "lsr Zdn.t, Pg/M, Zdn.t, #imm" , "op": "00000100|imm:2|000001100|Pg:3|imm:5|Zdn" , "imm": "SveShiftImm7(sz, imm)"},
|
||
|
|
{"inst": "lsrr Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "00000100|sz|010101100|Pg:3|Zm|Zdn"},
|
||
|
|
{"inst": "mad Zdn.t, Pg/M, Zm.t, Za.t" , "op": "00000100|sz|0|Zm|110|Pg:3|Za|Zdn"},
|
||
|
|
{"inst": "mla Zda.t, Pg/M, Zn.t, Zm.t" , "op": "00000100|sz|0|Zm|010|Pg:3|Za|Zdn"},
|
||
|
|
{"inst": "mls Zda.t, Pg/M, Zn.t, Zm.t" , "op": "00000100|sz|0|Zm|011|Pg:3|Za|Zdn"},
|
||
|
|
{"inst": "mov Pd.B, Pn.B" , "op": "001001011000|Pn|01|Pn|0|Pn|0|Pd" , "aliasOf": "orr"},
|
||
|
|
{"inst": "mov Zd.t, Wn|SP" , "op": "00000101|sz|100000001110|Rn|Zd" , "aliasOf": "dup", "T": "BHS~"},
|
||
|
|
{"inst": "mov Zd.t, Xn|SP" , "op": "00000101|11|100000001110|Rn|Zd" , "aliasOf": "dup"},
|
||
|
|
{"inst": "mov Zd.B, Bn" , "op": "00000101|imm:2|1|imm:5|001000|Zn|Zd" , "aliasOf": "dup", "imm": "SveDupImm(0, 0)"},
|
||
|
|
{"inst": "mov Zd.H, Hn" , "op": "00000101|imm:2|1|imm:5|001000|Zn|Zd" , "aliasOf": "dup", "imm": "SveDupImm(1, 0)"},
|
||
|
|
{"inst": "mov Zd.S, Sn" , "op": "00000101|imm:2|1|imm:5|001000|Zn|Zd" , "aliasOf": "dup", "imm": "SveDupImm(2, 0)"},
|
||
|
|
{"inst": "mov Zd.D, Dn" , "op": "00000101|imm:2|1|imm:5|001000|Zn|Zd" , "aliasOf": "dup", "imm": "SveDupImm(3, 0)"},
|
||
|
|
{"inst": "mov Zd.D, Zn.D" , "op": "00000100|01|1|Zn|001100|Zn|Zd" , "aliasOf": "orr"},
|
||
|
|
{"inst": "mov Zd.t, Zn.t[#idx]" , "op": "00000101|imm:2|1|imm:5|001000|Zn|Zd" , "aliasOf": "dup", "imm": "SveDupImm(sz, idx)"},
|
||
|
|
{"inst": "mov Zd.t, #imm" , "op": "00000101|11|0000|imm:13|Zd" , "aliasOf": "dupm", "imm": "SveDupmImm(sz, imm)"},
|
||
|
|
{"inst": "mov Zd.t, #imm, {lsl #n}" , "op": "00100101|sz|11100011|n:1|imm:8|Zd" , "aliasOf": "dup"},
|
||
|
|
{"inst": "mov Pd.B, Pg/M, Pn.B" , "op": "00100101|00|00|Pd|01|Pg|1|Pn|1|Pd" , "aliasOf": "sel"},
|
||
|
|
{"inst": "mov Pd.B, Pg/Z, Pn.B" , "op": "00100101|00|00|Pn|01|Pg|0|Pn|0|Pd" , "aliasOf": "and"},
|
||
|
|
{"inst": "mov Zd.t, Pg/M, Wn|SP" , "op": "00000101|sz|101000101|Pg:3|Rn|Zd" , "aliasOf": "cpy", "t": "BHS~"},
|
||
|
|
{"inst": "mov Zd.D, Pg/M, Xn|SP" , "op": "00000101|11|101000101|Pg:3|Rn|Zd" , "aliasOf": "cpy"},
|
||
|
|
{"inst": "mov Zd.B, Pg/M, Bn" , "op": "00000101|00|100000100|Pg:3|Rn|Zd" , "aliasOf": "cpy"},
|
||
|
|
{"inst": "mov Zd.H, Pg/M, Hn" , "op": "00000101|01|100000100|Pg:3|Rn|Zd" , "aliasOf": "cpy"},
|
||
|
|
{"inst": "mov Zd.S, Pg/M, Sn" , "op": "00000101|10|100000100|Pg:3|Rn|Zd" , "aliasOf": "cpy"},
|
||
|
|
{"inst": "mov Zd.D, Pg/M, Dn" , "op": "00000101|11|100000100|Pg:3|Rn|Zd" , "aliasOf": "cpy"},
|
||
|
|
{"inst": "mov Zd.t, Pg/M, Zn.t" , "op": "00000101|sz|1|Zd|11|Pg|Zn|Zd" , "aliasOf": "sel"},
|
||
|
|
{"inst": "mov Zd.t, Pg/MZ, #imm, {lsl #n}" , "op": "00000101|sz|01|Pg|0M|n:1|imm:8|Zd" , "aliasOf": "cpy"},
|
||
|
|
{"inst": "movprfx Zd, Zn" , "op": "00000100|00|100000101111|Zn|Zd"},
|
||
|
|
{"inst": "movprfx Zd.t, Pg/MZ, Zn.t" , "op": "00000100|sz|01000M001|Pg:3|Zn|Zd"},
|
||
|
|
{"inst": "movs Pd.B, Pn.B" , "op": "00100101|11|00|Pn|01|Pn|0|Pn|0|Pd" , "io": "N=W Z=W C=W V=W", "aliasOf": "orrs"},
|
||
|
|
{"inst": "movs Pd.B, Pg/Z, Pn.B" , "op": "00100101|01|00|Pn|01|Pg|0|Pn|0|Pd" , "io": "N=W Z=W C=W V=W", "aliasOf": "ands"},
|
||
|
|
{"inst": "msb Zdn.t, Pg/M, Zm.t, Za.t" , "op": "00000100|sz|0|Zm|111|Pg:3|Za|Zdn"},
|
||
|
|
{"inst": "mul Zdn.t, Zdn.t, #immS" , "op": "00100101|sz|110000110|immS:8|Zdn"},
|
||
|
|
{"inst": "mul Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "00000100|sz|010000000|Pg:3|Zm|Zdn"},
|
||
|
|
{"inst": "nand Pd.B, Pg/Z, Pn.B, Pm.B" , "op": "00100101|10|00|Pm|01|Pg|1|Pn|1|Pd"},
|
||
|
|
{"inst": "nands Pd.B, Pg/Z, Pn.B, Pm.B" , "op": "00100101|11|00|Pm|01|Pg|1|Pn|1|Pd" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "neg Zd.t, Pg/M, Zn.t" , "op": "00000100|sz|010111101|Pg:3|Zm|Zdn"},
|
||
|
|
{"inst": "nor Pd.B, Pg/Z, Pn.B, Pm.B" , "op": "00100101|10|00|Pm|01|Pg|1|Pn|0|Pd"},
|
||
|
|
{"inst": "nors Pd.B, Pg/Z, Pn.B, Pm.B" , "op": "00100101|11|00|Pm|01|Pg|1|Pn|0|Pd" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "not Pd.B, Pg/Z, Pn.B" , "op": "00100101|00|00|Pg|01|Pg|1|Pn|0|Pd"},
|
||
|
|
{"inst": "not Zd.t, Pg/M, Zn.t" , "op": "00000100|sz|011110101|Pg:3|Zn|Zd"},
|
||
|
|
{"inst": "nots Pd.B, Pg/Z, Pn.B" , "op": "00100101|01|00|Pg|01|Pg|1|Pn|0|Pd" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "orn Zdn.t, Zdn.t, #imm" , "op": "00000101|00|0000|imm:13|Zdn" , "imm": "SveLogicalImm(imm, 1, t)"},
|
||
|
|
{"inst": "orn Pd.B, Pg/Z, Pn.B, Pm.B" , "op": "00100101|10|00|Pm|01|Pg|0|Pn|1|Pd"},
|
||
|
|
{"inst": "orns Pd.B, Pg/Z, Pn.B, Pm.B" , "op": "00100101|11|00|Pm|01|Pg|0|Pn|1|Pd" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "orr Zd.D, Zn.D, Zm.D" , "op": "00000100|01|1|Zm|001100|Zn|Zd"},
|
||
|
|
{"inst": "orr Zdn.t, Zdn.t, #imm" , "op": "00000101|00|0000|imm:13|Zdn" , "imm": "SveLogicalImm(imm, 0, t)"},
|
||
|
|
{"inst": "orr Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "00000100|sz|011000000|Pg:3|Zm|Zdn"},
|
||
|
|
{"inst": "orr Pd.B, Pg/Z, Pn.B, Pm.B" , "op": "00100100|10|00|Pm|01|Pg|0|Pn|0|Pd"},
|
||
|
|
{"inst": "orrs Pd.B, Pg/Z, Pn.B, Pm.B" , "op": "00100101|11|00|Pm|01|Pg|0|Pn|0|Pd" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "orv Bd, Pg, Zn.B" , "op": "00000100|00|011000001|Pg:3|Zn|Vd"},
|
||
|
|
{"inst": "orv Hd, Pg, Zn.H" , "op": "00000100|01|011000001|Pg:3|Zn|Vd"},
|
||
|
|
{"inst": "orv Sd, Pg, Zn.S" , "op": "00000100|10|011000001|Pg:3|Zn|Vd"},
|
||
|
|
{"inst": "orv Dd, Pg, Zn.D" , "op": "00000100|11|011000001|Pg:3|Zn|Vd"},
|
||
|
|
{"inst": "pfalse Pd.B" , "op": "00100101|00|011000111001|000000|Pd"},
|
||
|
|
{"inst": "pfirst Pdn.B, Pg, Pdn.B" , "op": "00100101|01|0110001100000|Pg|0|Pdn"},
|
||
|
|
{"inst": "pnext Pdn.t, Pg, Pdn.t" , "op": "00100101|sz|0110011100010|Pg|0|Pdn"},
|
||
|
|
|
||
|
|
{"inst": "ptest Pg, Pn.B" , "op": "00100101|01|01000011|Pg|0|Pn|00000" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "ptrue Pd.t, {#pattern}" , "op": "00100101|sz|011000111000|pattern:5|0|Pd"},
|
||
|
|
{"inst": "ptrues Pd.t, {#pattern}" , "op": "00100101|sz|011001111000|pattern:5|0|Pd" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "punpkhi Pd.H, Pn.B" , "op": "00000101|00|1100010100000|Pn|0|Pd"},
|
||
|
|
{"inst": "punpklo Pd.H, Pn.B" , "op": "00000101|00|1100000100000|Pn|0|Pd"},
|
||
|
|
{"inst": "rbit Zd.t, Pg/M, Zn.t" , "op": "00000101|sz|100111100|Pg:3|Zn|Zd"},
|
||
|
|
{"inst": "rdffr Pd.B" , "op": "00100101|00|011001111100000000|Pd"},
|
||
|
|
{"inst": "rdffr Pd.B, Pg/Z" , "op": "00100101|00|0110001111000|Pg|0|Pd"},
|
||
|
|
{"inst": "rdffrs Pd.B, Pg/Z" , "op": "00100101|01|0110001111000|Pg|0|Pd" , "io": "N=W Z=W C=W V=W"},
|
||
|
|
{"inst": "rdvl Xd, #immS" , "op": "00000100|10|11111101010|immS:6|Rd"},
|
||
|
|
{"inst": "rev Pd.t, Pn.t" , "op": "00000101|sz|1101000100000|Pn|0|Pd"},
|
||
|
|
{"inst": "rev Zd.t, Zn.t" , "op": "00000101|sz|111000001110|Zn|Zd"},
|
||
|
|
{"inst": "revb Zd.t, Pg/M, Zn.t" , "op": "00000101|sz|100100100|Pg:3|Zn|Zd" , "t": "~HSD"},
|
||
|
|
{"inst": "revh Zd.t, Pg/M, Zn.t" , "op": "00000101|sz|100101100|Pg:3|Zn|Zd" , "t": "~~SD"},
|
||
|
|
{"inst": "revw Zd.D, Pg/M, Zn.D" , "op": "00000101|11|100110100|Pg:3|Zn|Zd"},
|
||
|
|
{"inst": "rshrnb Zd.ta, Zn.tb, #imm" , "op": "01000101|0|imm:1|1|imm:5|000110|Zn|Zd" , "imm": "SveShiftImm6(sz, imm)", "ta": "~BHS", "tb": "~HSD"},
|
||
|
|
{"inst": "rshrnt Zd.ta, Zn.tb, #imm" , "op": "01000101|0|imm:1|1|imm:5|000111|Zn|Zd" , "imm": "SveShiftImm6(sz, imm)", "ta": "~BHS", "tb": "~HSD"},
|
||
|
|
{"inst": "sabd Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "00000100|sz|0|01100000|Pg:3|Zm|Zdn"},
|
||
|
|
{"inst": "saddv Dd, Pg, Zn.t" , "op": "00000100|sz|0|00000001|Pg:3|Zn|Vd" , "t": "BHS~"},
|
||
|
|
{"inst": "scvtf Zd.H, Pg/M, Zn.H" , "op": "01100101|01|0|10010101|Pg:3|Zn|Zd"},
|
||
|
|
{"inst": "scvtf Zd.H, Pg/M, Zn.S" , "op": "01100101|01|0|10100101|Pg:3|Zn|Zd"},
|
||
|
|
{"inst": "scvtf Zd.S, Pg/M, Zn.S" , "op": "01100101|10|0|10100101|Pg:3|Zn|Zd"},
|
||
|
|
{"inst": "scvtf Zd.D, Pg/M, Zn.S" , "op": "01100101|11|0|10000101|Pg:3|Zn|Zd"},
|
||
|
|
{"inst": "scvtf Zd.H, Pg/M, Zn.D" , "op": "01100101|01|0|10110101|Pg:3|Zn|Zd"},
|
||
|
|
{"inst": "scvtf Zd.S, Pg/M, Zn.D" , "op": "01100101|11|0|10100101|Pg:3|Zn|Zd"},
|
||
|
|
{"inst": "scvtf Zd.D, Pg/M, Zn.D" , "op": "01100101|11|0|10110101|Pg:3|Zn|Zd"},
|
||
|
|
{"inst": "sdiv Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "00000100|sz|0|10100000|Pg:3|Zm|Zdn" , "t": "~~SD"},
|
||
|
|
{"inst": "sdivr Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "00000100|sz|0|10110000|Pg:3|Zm|Zdn" , "t": "~~SD"},
|
||
|
|
{"inst": "sdot Zda.ta, Zn.tb, Zm.tb" , "op": "01000100|sz|0|Zm|000000|Zn|Zda" , "ta": "~~SD", "tb": "~~BH"},
|
||
|
|
{"inst": "sdot Zda.S, Zn.B, Zm.B[#idx]" , "op": "01000100|10|1|idx:2|Zm:3|000000|Zn|Zda"},
|
||
|
|
{"inst": "sdot Zda.D, Zn.H, Zm.H[#idx]" , "op": "01000100|11|1|idx:1|Zm:4|000000|Zn|Zda"},
|
||
|
|
{"inst": "sel Pd.B, Pg, Pn.B, Pm.B" , "op": "00100101|00|00|Pm|01|Pg|1|Pn|1|Pd"},
|
||
|
|
{"inst": "sel Zd.t, Pg, Zn.t, Zm.t" , "op": "00000101|sz|1|Zm|11|Pg|Zn|Zd"},
|
||
|
|
{"inst": "setffr" , "op": "00100101|00|10|1100100100|0000000000"},
|
||
|
|
{"inst": "shrnb Zd.t, Zn.t, #imm" , "op": "01000101|0|imm:1|1|imm:5|0001|00|Zn|Zd" , "imm": "SveShiftImm6(sz, imm)", "t": "~BHS"},
|
||
|
|
{"inst": "shrnt Zd.t, Zn.t, #imm" , "op": "01000101|0|imm:1|1|imm:5|0001|01|Zn|Zd" , "imm": "SveShiftImm6(sz, imm)", "t": "~BHS"},
|
||
|
|
{"inst": "smax Zdn.t, Zdn.t, #immS" , "op": "00100101|sz|1|01000110|immS:8|Zdn"},
|
||
|
|
{"inst": "smax Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "00000100|sz|0|01000000|Pg:3|Zm|Zdn"},
|
||
|
|
{"inst": "smaxv Bd, Pg, Zn.B" , "op": "00000100|00|0|01000001|Pg:3|Zn|Vd"},
|
||
|
|
{"inst": "smaxv Hd, Pg, Zn.H" , "op": "00000100|01|0|01000001|Pg:3|Zn|Vd"},
|
||
|
|
{"inst": "smaxv Sd, Pg, Zn.S" , "op": "00000100|10|0|01000001|Pg:3|Zn|Vd"},
|
||
|
|
{"inst": "smaxv Dd, Pg, Zn.D" , "op": "00000100|11|0|01000001|Pg:3|Zn|Vd"},
|
||
|
|
{"inst": "smin Zdn.t, Zdn.t, #immS" , "op": "00100101|sz|1|01010110|immS:8|Zdn"},
|
||
|
|
{"inst": "smin Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "00000100|sz|0|01010000|Pg:3|Zm|Zdn"},
|
||
|
|
{"inst": "sminv Bd, Pg, Zn.B" , "op": "00000100|00|0|01010001|Pg:3|Zn|Vd"},
|
||
|
|
{"inst": "sminv Hd, Pg, Zn.H" , "op": "00000100|01|0|01010001|Pg:3|Zn|Vd"},
|
||
|
|
{"inst": "sminv Sd, Pg, Zn.S" , "op": "00000100|10|0|01010001|Pg:3|Zn|Vd"},
|
||
|
|
{"inst": "sminv Dd, Pg, Zn.D" , "op": "00000100|11|0|01010001|Pg:3|Zn|Vd"},
|
||
|
|
{"inst": "smulh Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "00000100|sz|0|10010000|Pg:3|Zm|Zdn"},
|
||
|
|
{"inst": "splice Zdn.t, Pg, Zdn.t, Zm.t" , "op": "00000101|sz|1|01100100|Pg:3|Zn|Zdn"},
|
||
|
|
{"inst": "sqadd Zd.t, Zn.t, Zm.t" , "op": "00000100|sz|1|Zm|000100|Zn|Zd"},
|
||
|
|
{"inst": "sqadd Zdn.t, Zdn.t, #imm, {lsl #n}" , "op": "00100101|sz|1|0010011|n:1|imm:8|Zdn" , "imm": "Sve8BitImm(imm)"},
|
||
|
|
{"inst": "sqdecb Xdn, Wdn, {#pattern}, {mul #imm}" , "op": "00000100|00|10|imm:4|111110|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
|
||
|
|
{"inst": "sqdecb Xdn, {#pattern}, {mul #imm}" , "op": "00000100|00|11|imm:4|111110|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
|
||
|
|
{"inst": "sqdecd Xdn, Wdn, {#pattern}, {mul #imm}" , "op": "00000100|11|10|imm:4|111110|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
|
||
|
|
{"inst": "sqdecd Xdn, {#pattern}, {mul #imm}" , "op": "00000100|11|11|imm:4|111110|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
|
||
|
|
{"inst": "sqdecd Zdn.D, {#pattern}, {mul #imm}" , "op": "00000100|11|10|imm:4|110010|pattern:5|Zdn" , "imm": "SvePatternImm(pattern, imm)"},
|
||
|
|
{"inst": "sqdech Xdn, Wdn, {#pattern}, {mul #imm}" , "op": "00000100|01|10|imm:4|111110|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
|
||
|
|
{"inst": "sqdech Xdn, {#pattern}, {mul #imm}" , "op": "00000100|01|11|imm:4|111110|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
|
||
|
|
{"inst": "sqdech Zdn.D, {#pattern}, {mul #imm}" , "op": "00000100|01|01|imm:4|110010|pattern:5|Zdn" , "imm": "SvePatternImm(pattern, imm)"},
|
||
|
|
{"inst": "sqdecp Xdn, Pm.t, Wdn" , "op": "00100101|sz|1|010101000100|Pm|Rdn"},
|
||
|
|
{"inst": "sqdecp Xdn, Pm.t" , "op": "00100101|sz|1|010101000110|Pm|Rdn"},
|
||
|
|
{"inst": "sqdecp Zdn.t, Pm.t" , "op": "00100101|sz|1|010101000000|Pm|Zdn" , "t": "~HSD"},
|
||
|
|
{"inst": "sqdecw Xdn, Wdn, {#pattern}, {mul #imm}" , "op": "00000100|10|10|imm:4|111110|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
|
||
|
|
{"inst": "sqdecw Xdn, {#pattern}, {mul #imm}" , "op": "00000100|10|11|imm:4|111110|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
|
||
|
|
{"inst": "sqdecw Zdn.D, {#pattern}, {mul #imm}" , "op": "00000100|10|10|imm:4|110010|pattern:5|Zdn" , "imm": "SvePatternImm(pattern, imm)"},
|
||
|
|
{"inst": "sqincb Xdn, Wdn, {#pattern}, {mul #imm}" , "op": "00000100|00|10|imm:4|111100|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
|
||
|
|
{"inst": "sqincb Xdn, {#pattern}, {mul #imm}" , "op": "00000100|00|11|imm:4|111100|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
|
||
|
|
{"inst": "sqincd Xdn, Wdn, {#pattern}, {mul #imm}" , "op": "00000100|11|10|imm:4|111100|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
|
||
|
|
{"inst": "sqincd Xdn, {#pattern}, {mul #imm}" , "op": "00000100|11|11|imm:4|111100|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
|
||
|
|
{"inst": "sqincd Zdn.D, {#pattern}, {mul #imm}" , "op": "00000100|11|10|imm:4|110000|pattern:5|Zdn" , "imm": "SvePatternImm(pattern, imm)"},
|
||
|
|
{"inst": "sqinch Xdn, Wdn, {#pattern}, {mul #imm}" , "op": "00000100|01|10|imm:4|111100|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
|
||
|
|
{"inst": "sqinch Xdn, {#pattern}, {mul #imm}" , "op": "00000100|01|11|imm:4|111100|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
|
||
|
|
{"inst": "sqinch Zdn.D, {#pattern}, {mul #imm}" , "op": "00000100|01|01|imm:4|110000|pattern:5|Zdn" , "imm": "SvePatternImm(pattern, imm)"},
|
||
|
|
{"inst": "sqincp Xdn, Pm.t, Wdn" , "op": "00100101|sz|1010001000100|Pm|Rdn"},
|
||
|
|
{"inst": "sqincp Xdn, Pm.t" , "op": "00100101|sz|1010001000110|Pm|Rdn"},
|
||
|
|
{"inst": "sqincp Zdn.t, Pm.t" , "op": "00100101|sz|1010001000000|Pm|Zdn" , "t": "~HSD"},
|
||
|
|
{"inst": "sqincw Xdn, Wdn, {#pattern}, {mul #imm}" , "op": "00000100|10|10|imm:4|111100|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
|
||
|
|
{"inst": "sqincw Xdn, {#pattern}, {mul #imm}" , "op": "00000100|10|11|imm:4|111100|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
|
||
|
|
{"inst": "sqincw Zdn.D, {#pattern}, {mul #imm}" , "op": "00000100|10|10|imm:4|110000|pattern:5|Zdn" , "imm": "SvePatternImm(pattern, imm)"},
|
||
|
|
|
||
|
|
{"inst": "sqsub Zd.t, Zn.t, Zm.t" , "op": "00000100|sz|1|Zm|000110|Zn|Zd"},
|
||
|
|
{"inst": "sqsub Zdn.t, Zdn.t, #imm, {lsl #n}" , "op": "00100101|sz|10011011|n:1|imm:8|Zdn" , "imm": "Sve8BitImm(imm)"},
|
||
|
|
|
||
|
|
{"inst": "sub Zd.t, Zn.t, Zm.t" , "op": "00000100|sz|1|Zm|000001|Zn|Zd"},
|
||
|
|
{"inst": "sub Zdn.t, Zdn.t, #imm, {lsl #n}" , "op": "00100101|sz|10000111|n:1|imm:8|Zdn" , "imm": "Sve8BitImm(imm)"},
|
||
|
|
{"inst": "sub Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "00000100|sz|000001000|Pg:3|Zm|Zdn"},
|
||
|
|
{"inst": "subr Zdn.t, Zdn.t, #imm, {lsl #n}" , "op": "00100101|sz|10001111|n:1|imm:8|Zdn" , "imm": "Sve8BitImm(imm)"},
|
||
|
|
{"inst": "subr Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "00000100|sz|000011000|Pg:3|Zm|Zdn"},
|
||
|
|
{"inst": "sunpkhi Zd.t, Zn.tb" , "op": "00000101|sz|110001001110|Zn|Zd"},
|
||
|
|
{"inst": "sunpklo Zd.t, Zn.tb" , "op": "00000101|sz|110000001110|Zn|Zd"},
|
||
|
|
{"inst": "sxtb Zd.t, Pg/M, Zn.t" , "op": "00000100|sz|010000101|Pg:3|Zn|Zd" , "t": "~HSD"},
|
||
|
|
{"inst": "sxth Zd.t, Pg/M, Zn.t" , "op": "00000100|sz|010010101|Pg:3|Zn|Zd" , "t": "~~SD"},
|
||
|
|
{"inst": "sxtw Zd.D, Pg/M, Zn.D" , "op": "00000100|11|010100101|Pg:3|Zn|Zd"},
|
||
|
|
{"inst": "tbl Zd.t, Zn.t, Zm.t" , "op": "00000101|sz|1|Zm|001100|Zn|Zd"},
|
||
|
|
{"inst": "trn1 Zd.t, Zn.t, Zm.t" , "op": "00000101|sz|1|Zm|011100|Zn|Zd"},
|
||
|
|
{"inst": "trn1 Pd.t, Pn.t, Pm.t" , "op": "00000101|sz|10|Pm|0101000|Pn|0|Pd"},
|
||
|
|
{"inst": "trn2 Zd.t, Zn.t, Zm.t" , "op": "00000101|sz|1|Zm|011101|Zn|Zd"},
|
||
|
|
{"inst": "trn2 Pd.t, Pn.t, Pm.t" , "op": "00000101|sz|10|Pm|0101010|Pn|0|Pd"},
|
||
|
|
{"inst": "uabd Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "00000100|sz|001101000|Pg:3|Zm|Zdn"},
|
||
|
|
{"inst": "uaddv Dd, Pg, Zn.t" , "op": "00000100|sz|000001001|Pg:3|Zn|Vd" , "t": "BHS~"},
|
||
|
|
{"inst": "ucvtf Zd.H, Pg/M, Zn.H" , "op": "01100101|01|010011101|Pg:3|Zn|Zd"},
|
||
|
|
{"inst": "ucvtf Zd.H, Pg/M, Zn.S" , "op": "01100101|01|010101101|Pg:3|Zn|Zd"},
|
||
|
|
{"inst": "ucvtf Zd.S, Pg/M, Zn.S" , "op": "01100101|10|010101101|Pg:3|Zn|Zd"},
|
||
|
|
{"inst": "ucvtf Zd.D, Pg/M, Zn.S" , "op": "01100101|11|010001101|Pg:3|Zn|Zd"},
|
||
|
|
{"inst": "ucvtf Zd.H, Pg/M, Zn.D" , "op": "01100101|01|010111101|Pg:3|Zn|Zd"},
|
||
|
|
{"inst": "ucvtf Zd.S, Pg/M, Zn.D" , "op": "01100101|11|010101101|Pg:3|Zn|Zd"},
|
||
|
|
{"inst": "ucvtf Zd.D, Pg/M, Zn.D" , "op": "01100101|11|010111101|Pg:3|Zn|Zd"},
|
||
|
|
{"inst": "udiv Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "00000100|sz|010101000|Pg:3|Zm|Zdn" , "t": "~~SD"},
|
||
|
|
{"inst": "udivr Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "00000100|sz|010111000|Pg:3|Zm|Zdn" , "t": "~~SD"},
|
||
|
|
{"inst": "udot Zda.ta, Zn.tb, Zm.tb" , "op": "01000100|sz|0|Zm|000001|Zn|Zda" , "ta": "~~SD", "tb": "~~BH"},
|
||
|
|
{"inst": "udot Zda.S, Zn.B, Zm.B[#idx]" , "op": "01000100|10|1|idx:2|Zm:3|000001|Zn|Zda"},
|
||
|
|
{"inst": "udot Zda.D, Zn.H, Zm.H[#idx]" , "op": "01000100|11|1|idx:1|Zm:4|000001|Zn|Zda"},
|
||
|
|
{"inst": "umax Zdn.t, Zdn.t, #immZ" , "op": "00100101|sz|101001110|immZ:8|Zdn"},
|
||
|
|
{"inst": "umax Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "00000100|sz|001001000|Pg:3|Zm|Zdn"},
|
||
|
|
{"inst": "umaxv Bd, Pg, Zn.B" , "op": "00000100|00|001001001|Pg:3|Zn|Vd"},
|
||
|
|
{"inst": "umaxv Hd, Pg, Zn.H" , "op": "00000100|01|001001001|Pg:3|Zn|Vd"},
|
||
|
|
{"inst": "umaxv Sd, Pg, Zn.S" , "op": "00000100|10|001001001|Pg:3|Zn|Vd"},
|
||
|
|
{"inst": "umaxv Dd, Pg, Zn.D" , "op": "00000100|11|001001001|Pg:3|Zn|Vd"},
|
||
|
|
{"inst": "umin Zdn.t, Zdn.t, #immS" , "op": "00100101|sz|101011110|immS:8|Zdn"},
|
||
|
|
{"inst": "umin Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "00000100|sz|001011000|Pg:3|Zm|Zdn"},
|
||
|
|
{"inst": "uminv Bd, Pg, Zn.B" , "op": "00000100|00|001011001|Pg:3|Zn|Vd"},
|
||
|
|
{"inst": "uminv Hd, Pg, Zn.H" , "op": "00000100|01|001011001|Pg:3|Zn|Vd"},
|
||
|
|
{"inst": "uminv Sd, Pg, Zn.S" , "op": "00000100|10|001011001|Pg:3|Zn|Vd"},
|
||
|
|
{"inst": "uminv Dd, Pg, Zn.D" , "op": "00000100|11|001011001|Pg:3|Zn|Vd"},
|
||
|
|
{"inst": "umulh Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "00000100|sz|010011000|Pg:3|Zm|Zdn"},
|
||
|
|
{"inst": "uqadd Zd.t, Zn.t, Zm.t" , "op": "00000100|sz|1|Zm|000101|Zn|Zd"},
|
||
|
|
{"inst": "uqadd Zdn.t, Zdn.t, #imm, {lsl #n}" , "op": "00100101|sz|10010111|n:1|imm:8|Zdn" , "imm": "Sve8BitImm(imm)"},
|
||
|
|
{"inst": "uqdecb Xdn, Wdn, {#pattern}, {mul #imm}" , "op": "00000100|00|10|imm:4|111111|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
|
||
|
|
{"inst": "uqdecb Xdn, {#pattern}, {mul #imm}" , "op": "00000100|00|11|imm:4|111111|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
|
||
|
|
{"inst": "uqdecd Xdn, Wdn, {#pattern}, {mul #imm}" , "op": "00000100|11|10|imm:4|111111|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
|
||
|
|
{"inst": "uqdecd Xdn, {#pattern}, {mul #imm}" , "op": "00000100|11|11|imm:4|111111|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
|
||
|
|
{"inst": "uqdecd Zdn.D, {#pattern}, {mul #imm}" , "op": "00000100|11|10|imm:4|110011|pattern:5|Zdn" , "imm": "SvePatternImm(pattern, imm)"},
|
||
|
|
{"inst": "uqdech Xdn, Wdn, {#pattern}, {mul #imm}" , "op": "00000100|01|10|imm:4|111111|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
|
||
|
|
{"inst": "uqdech Xdn, {#pattern}, {mul #imm}" , "op": "00000100|01|11|imm:4|111111|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
|
||
|
|
{"inst": "uqdech Zdn.D, {#pattern}, {mul #imm}" , "op": "00000100|01|01|imm:4|110011|pattern:5|Zdn" , "imm": "SvePatternImm(pattern, imm)"},
|
||
|
|
{"inst": "uqdecp Xdn, Pm.t" , "op": "00100101|sz|1010111000100|Pm|Rdn"},
|
||
|
|
{"inst": "uqdecp Xdn, Pm.t" , "op": "00100101|sz|1010111000110|Pm|Rdn"},
|
||
|
|
{"inst": "uqdecp Zdn.t, Pm.t" , "op": "00100101|sz|1010111000000|Pm|Zdn" , "t": "~HSD"},
|
||
|
|
{"inst": "uqdecw Xdn, Wdn, {#pattern}, {mul #imm}" , "op": "00000100|10|10|imm:4|111111|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
|
||
|
|
{"inst": "uqdecw Xdn, {#pattern}, {mul #imm}" , "op": "00000100|10|11|imm:4|111111|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
|
||
|
|
{"inst": "uqdecw Zdn.D, {#pattern}, {mul #imm}" , "op": "00000100|10|10|imm:4|110011|pattern:5|Zdn" , "imm": "SvePatternImm(pattern, imm)"},
|
||
|
|
{"inst": "uqincb Xdn, Wdn, {#pattern}, {mul #imm}" , "op": "00000100|00|10|imm:4|111101|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
|
||
|
|
{"inst": "uqincb Xdn, {#pattern}, {mul #imm}" , "op": "00000100|00|11|imm:4|111101|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
|
||
|
|
{"inst": "uqincd Xdn, Wdn, {#pattern}, {mul #imm}" , "op": "00000100|11|10|imm:4|111101|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
|
||
|
|
{"inst": "uqincd Xdn, {#pattern}, {mul #imm}" , "op": "00000100|11|11|imm:4|111101|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
|
||
|
|
{"inst": "uqincd Zdn.D, {#pattern}, {mul #imm}" , "op": "00000100|11|10|imm:4|110001|pattern:5|Zdn" , "imm": "SvePatternImm(pattern, imm)"},
|
||
|
|
{"inst": "uqinch Xdn, Wdn, {#pattern}, {mul #imm}" , "op": "00000100|01|10|imm:4|111101|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
|
||
|
|
{"inst": "uqinch Xdn, {#pattern}, {mul #imm}" , "op": "00000100|01|11|imm:4|111101|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
|
||
|
|
{"inst": "uqinch Zdn.D, {#pattern}, {mul #imm}" , "op": "00000100|01|01|imm:4|110001|pattern:5|Zdn" , "imm": "SvePatternImm(pattern, imm)"},
|
||
|
|
{"inst": "uqincp Xdn, Pm.t" , "op": "00100101|sz|1010011000100|Pm|Rdn"},
|
||
|
|
{"inst": "uqincp Xdn, Pm.t" , "op": "00100101|sz|1010011000110|Pm|Rdn"},
|
||
|
|
{"inst": "uqincp Zdn.t, Pm.t" , "op": "00100101|sz|1010011000000|Pm|Zdn" , "t": "~HSD"},
|
||
|
|
{"inst": "uqincw Xdn, Wdn, {#pattern}, {mul #imm}" , "op": "00000100|10|10|imm:4|111101|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
|
||
|
|
{"inst": "uqincw Xdn, {#pattern}, {mul #imm}" , "op": "00000100|10|11|imm:4|111101|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
|
||
|
|
{"inst": "uqincw Zdn.D, {#pattern}, {mul #imm}" , "op": "00000100|10|10|imm:4|110001|pattern:5|Zdn" , "imm": "SvePatternImm(pattern, imm)"},
|
||
|
|
{"inst": "uqsub Zd.t, Zn.t, Zm.t" , "op": "00000100|sz|1|Zm|000111|Zn|Zd"},
|
||
|
|
{"inst": "uqsub Zdn.t, Zdn.t, #imm, {lsl #n}" , "op": "00100101|sz|10011111|n:1|imm:8|Zdn" , "imm": "Sve8BitImm(imm)"},
|
||
|
|
{"inst": "uunpkhi Zd.t, Zn.tb" , "op": "00000101|sz|110011001110|Zn|Zd"},
|
||
|
|
{"inst": "uunpklo Zd.t, Zn.tb" , "op": "00000101|sz|110010001110|Zn|Zd"},
|
||
|
|
{"inst": "uxtb Zd.t, Pg/M, Zn.t" , "op": "00000100|sz|010001101|Pg:3|Zn|Zd" , "t": "~HSD"},
|
||
|
|
{"inst": "uxth Zd.t, Pg/M, Zn.t" , "op": "00000100|sz|010011101|Pg:3|Zn|Zd" , "t": "~~SD"},
|
||
|
|
{"inst": "uxtw Zd.D, Pg/M, Zn.D" , "op": "00000100|11|010101101|Pg:3|Zn|Zd"},
|
||
|
|
{"inst": "uzp1 Pd.t, Pn.t, Pm.t" , "op": "00000101|sz|10|Pm|0100100|Pn|0|Pd"},
|
||
|
|
{"inst": "uzp1 Zd.t, Zn.t, Zm.t" , "op": "00000101|sz|1|Zm|011010|Zn|Zd"},
|
||
|
|
{"inst": "uzp2 Pd.t, Pn.t, Pm.t" , "op": "00000101|sz|10|Pm|0100110|Pn|0|Pd"},
|
||
|
|
{"inst": "uzp2 Zd.t, Zn.t, Zm.t" , "op": "00000101|sz|1|Zm|011011|Zn|Zd"},
|
||
|
|
{"inst": "whilege Pd.t, Rn, Rm" , "op": "00100101|sz|1|Rm|000X00|Rn|0|Pd"},
|
||
|
|
{"inst": "whilegt Pd.t, Rn, Rm" , "op": "00100101|sz|1|Rm|000X00|Rn|1|Pd"},
|
||
|
|
{"inst": "whilehi Pd.t, Rn, Rm" , "op": "00100101|sz|1|Rm|000X10|Rn|1|Pd"},
|
||
|
|
{"inst": "whilehs Pd.t, Rn, Rm" , "op": "00100101|sz|1|Rm|000X10|Rn|0|Pd"},
|
||
|
|
{"inst": "whilele Pd.t, Rn, Rm" , "op": "00100101|sz|1|Rm|000X01|Rn|1|Pd"},
|
||
|
|
{"inst": "whilelo Pd.t, Rn, Rm" , "op": "00100101|sz|1|Rm|000X11|Rn|0|Pd"},
|
||
|
|
{"inst": "whilels Pd.t, Rn, Rm" , "op": "00100101|sz|1|Rm|000X11|Rn|1|Pd"},
|
||
|
|
{"inst": "whilelt Pd.t, Rn, Rm" , "op": "00100101|sz|1|Rm|000X01|Rn|0|Pd"},
|
||
|
|
{"inst": "wrffr Pn.B" , "op": "00100101|00|1010001001000|Pn|00000"},
|
||
|
|
{"inst": "zip1 Pd.t, Pn.t, Pm.t" , "op": "00000101|sz|10|Pm|0100000|Pn|0|Pd"},
|
||
|
|
{"inst": "zip1 Zd.t, Zn.t, Zm.t" , "op": "00000101|sz|1|Zm|011000|Zn|Zd"},
|
||
|
|
{"inst": "zip2 Pd.t, Pn.t, Pm.t" , "op": "00000101|sz|10|Pm|0100010|Pn|0|Pd"},
|
||
|
|
{"inst": "zip2 Zd.t, Zn.t, Zm.t" , "op": "00000101|sz|1|Zm|011001|Zn|Zd"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "SVE", "ext": "SVE_BF16", "data": [
|
||
|
|
{"inst": "bfcvt Zd.H, Pg/M, Zn.S" , "op": "01100101|10|001010101|Pg:3|Zn|Zd"},
|
||
|
|
{"inst": "bfcvtnt Zd.H, Pg/M, Zn.S" , "op": "01100100|10|001010101|Pg:3|Zn|Zd"},
|
||
|
|
{"inst": "bfdot Zda.S, Zn.H, Zm.H" , "op": "01100100|01|1|Zm|100000|Zn|Zda"},
|
||
|
|
{"inst": "bfdot Zda.S, Zn.H, Zm.H[#idx]" , "op": "01100100|01|1|idx:2|Zm:3|010000|Zn|Zda"},
|
||
|
|
{"inst": "bfmlalb Zda.S, Zn.H, Zm.H" , "op": "01100100|11|1|Zm|100000|Zn|Zda"},
|
||
|
|
{"inst": "bfmlalb Zda.S, Zn.H, Zm.H[#idx]" , "op": "01100100|11|1|idx:2|Zm:3|0100|idx:1|0|Zn|Zda"},
|
||
|
|
{"inst": "bfmlalt Zda.S, Zn.H, Zm.H" , "op": "01100100|11|1|Zm|100001|Zn|Zda"},
|
||
|
|
{"inst": "bfmlalt Zda.S, Zn.H, Zm.H[#idx]" , "op": "01100100|11|1|idx:2|Zm:3|0100|idx:1|1|Zn|Zda"},
|
||
|
|
{"inst": "bfmmla Zda.S, Zn.H, Zm.H" , "op": "01100100|01|1|Zm|111001|Zn|Zda"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "SVE", "ext": "SVE_F32MM", "data": [
|
||
|
|
{"inst": "fmmla Zda.S, Zn.S, Zm.S" , "op": "01100100|10|1|Zm|111001|Zn|Zda", "t": "~~SD"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "SVE", "ext": "SVE_F64MM", "data": [
|
||
|
|
{"inst": "fmmla Zda.D, Zn.D, Zm.D" , "op": "01100100|11|1|Zm|111001|Zn|Zda", "t": "~~SD"},
|
||
|
|
{"inst": "trn1 Zd.Q, Zn.Q, Zm.Q" , "op": "00000101|10|1|Zm|000110|Zn|Zd"},
|
||
|
|
{"inst": "trn2 Zd.Q, Zn.Q, Zm.Q" , "op": "00000101|10|1|Zm|000111|Zn|Zd"},
|
||
|
|
{"inst": "uzp1 Zd.Q, Zn.Q, Zm.Q" , "op": "00000101|10|1|Zm|000010|Zn|Zd"},
|
||
|
|
{"inst": "uzp2 Zd.Q, Zn.Q, Zm.Q" , "op": "00000101|10|1|Zm|000011|Zn|Zd"},
|
||
|
|
{"inst": "zip1 Zd.Q, Zn.Q, Zm.Q" , "op": "00000101|10|1|Zm|000000|Zn|Zd"},
|
||
|
|
{"inst": "zip2 Zd.Q, Zn.Q, Zm.Q" , "op": "00000101|10|1|Zm|000001|Zn|Zd"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "SVE", "ext": "SVE_I8MM", "data": [
|
||
|
|
{"inst": "smmla Zda.S, Zn.B, Zm.B" , "op": "01000101|00|0|Zm|100110|Zn|Zda"},
|
||
|
|
{"inst": "sudot Zda.S, Zn.B, Zm.B[#idx]" , "op": "01000100|10|1|idx:2|Zm:3|000111|Zn|Zda"},
|
||
|
|
{"inst": "ummla Zda.S, Zn.B, Zm.B" , "op": "01000101|11|0|Zm|100110|Zn|Zda"},
|
||
|
|
{"inst": "usdot Zda.S, Zn.B, Zm.B" , "op": "01000100|10|0|Zm|011110|Zn|Zda"},
|
||
|
|
{"inst": "usdot Zda.S, Zn.B, Zm.B[#idx]" , "op": "01000100|10|1|idx:2|Zm:3|000110|Zn|Zda"},
|
||
|
|
{"inst": "usmmla Zda.S, Zn.B, Zm.B" , "op": "01000101|10|0|Zm|100110|Zn|Zda"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "SVE", "ext": "SVE2", "data": [
|
||
|
|
{"inst": "adclb Zda.t, Pg/M, Zn.t" , "op": "01000101|0|sz[0]|0|Zm|110100|Zn|Zda" , "t": "~~SD"},
|
||
|
|
{"inst": "adclt Zda.t, Pg/M, Zn.t" , "op": "01000101|0|sz[0]|0|Zm|110101|Zn|Zda" , "t": "~~SD"},
|
||
|
|
{"inst": "addhnb Zd.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|1|Zm|011000|Zn|Zd" , "ta": "~BHS", "tb": "~HSD"},
|
||
|
|
{"inst": "addhnt Zd.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|1|Zm|011001|Zn|Zd" , "ta": "~BHS", "tb": "~HSD"},
|
||
|
|
{"inst": "bcax Zdn.D, Zdn.D, Zm.D, Zk.D" , "op": "00000100|01|1|Zm|001110|Zk|Zdn"},
|
||
|
|
{"inst": "bsl Zdn.D, Zdn.D, Zm.D, Zk.D" , "op": "00000100|00|1|Zm|001111|Zk|Zdn"},
|
||
|
|
{"inst": "bsl1n Zdn.D, Zdn.D, Zm.D, Zk.D" , "op": "00000100|01|1|Zm|001111|Zk|Zdn"},
|
||
|
|
{"inst": "bsl2n Zdn.D, Zdn.D, Zm.D, Zk.D" , "op": "00000100|10|1|Zm|001111|Zk|Zdn"},
|
||
|
|
{"inst": "cadd Zdn.t, Zdn.t, Zm.t, #rot1" , "op": "01000101|sz|0|00000110|11|imm:1|Zm|Zdn" , "imm": "Rot1Imm(rot1)"},
|
||
|
|
{"inst": "cdot Zda.ta, Zn.tb, Zm.tb, #rot2" , "op": "01000100|sz|0|Zm|0001|imm:2|Zn|Zda" , "imm": "Rot2Imm(rot2)", "ta": "~~SD", "tb": "~~BH"},
|
||
|
|
{"inst": "cdot Zda.S, Zn.B, Zm.B[#idx], #rot2" , "op": "01000100|10|1|idx:2|Zm:3|0100|imm:2|Zn|Zda" , "imm": "Rot2Imm(rot2)"},
|
||
|
|
{"inst": "cdot Zda.D, Zn.H, Zm.H[#idx], #rot2" , "op": "01000100|11|1|idx:1|Zm:4|0100|imm:2|Zn|Zda" , "imm": "Rot2Imm(rot2)"},
|
||
|
|
{"inst": "cmla Zda.t, Zn.t, Zm.t, #rot2" , "op": "01000100|sz|0|Zm|0010|imm:2|Zn|Zda" , "imm": "Rot2Imm(rot2)"},
|
||
|
|
{"inst": "cmla Zda.H, Zn.H, Zm.H[#idx], #rot2" , "op": "01000100|10|1|idx:2|Zm:3|0110|imm:2|Zn|Zda" , "imm": "Rot2Imm(rot2)"},
|
||
|
|
{"inst": "cmla Zda.S, Zn.S, Zm.S[#idx], #rot2" , "op": "01000100|11|1|idx:1|Zm:4|0110|imm:2|Zn|Zda" , "imm": "Rot2Imm(rot2)"},
|
||
|
|
{"inst": "eor3 Zdn.D, Zdn.D, Zm.D, Zk.D" , "op": "00000100|00|1|Zm|001110|Zk|Zdn"},
|
||
|
|
{"inst": "ext Zd.B, 2x{Zn.B}+, #imm" , "op": "00000101|01|1|imm:5|000|imm:3|Zn|Zd"},
|
||
|
|
{"inst": "faddp Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01100100|sz|010000100|Pg:3|Zm|Zdn" , "t": "~HSD"},
|
||
|
|
{"inst": "fcmla Zda.t, Pg/M, Zn.t, Zm.t, #rot2" , "op": "01100100|sz|0|Zm|0|imm:2|Pg:3|Zn|Zda" , "t": "~HSD", "imm": "Rot2Imm(rot2)"},
|
||
|
|
{"inst": "fcmla Zda.H, Zn.H, Zm.H[#idx], #rot2" , "op": "01100100|10|1|idx:2|Zm:3|0001|imm:2|Zn|Zda" , "imm": "Rot2Imm(rot2)"},
|
||
|
|
{"inst": "fcmla Zda.S, Zn.S, Zm.S[#idx], #rot2" , "op": "01100100|11|1|idx:1|Zm:4|0001|imm:2|Zn|Zda" , "imm": "Rot2Imm(rot2)"},
|
||
|
|
{"inst": "fcvtlt Zd.S, Pg/M, Zn.H" , "op": "01100100|10|001001101|Pg:3|Zn|Zd"},
|
||
|
|
{"inst": "fcvtlt Zd.D, Pg/M, Zn.S" , "op": "01100100|11|001011101|Pg:3|Zn|Zd"},
|
||
|
|
{"inst": "fcvtnt Zd.H, Pg/M, Zn.S" , "op": "01100100|10|001000101|Pg:3|Zn|Zd"},
|
||
|
|
{"inst": "fcvtnt Zd.S, Pg/M, Zn.D" , "op": "01100100|11|001010101|Pg:3|Zn|Zd"},
|
||
|
|
{"inst": "fcvtx Zd.S, Pg/M, Zn.D" , "op": "01100101|00|001010101|Pg:3|Zn|Zd"},
|
||
|
|
{"inst": "fcvtxnt Zd.S, Pg/M, Zn.D" , "op": "01100100|00|001010101|Pg:3|Zn|Zd"},
|
||
|
|
{"inst": "flogb Zd.t, Pg/M, Zn.t" , "op": "01100101|00|011|sz|0101|Pg:3|Zn|Zd" , "t": "~HSD"},
|
||
|
|
{"inst": "fmaxnmp Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01100100|sz|010100100|Pg:3|Zm|Zdn" , "t": "~HSD"},
|
||
|
|
{"inst": "fmaxp Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01100100|sz|010110100|Pg:3|Zm|Zdn" , "t": "~HSD"},
|
||
|
|
{"inst": "fminnmp Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01100100|sz|010101100|Pg:3|Zm|Zdn" , "t": "~HSD"},
|
||
|
|
{"inst": "fminp Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01100100|sz|010111100|Pg:3|Zm|Zdn" , "t": "~HSD"},
|
||
|
|
{"inst": "fmlalb Zda.S, Zn.H, Zm.H" , "op": "01100100|10|1|Zm|100000|Zn|Zda" , "t": "~HSD"},
|
||
|
|
{"inst": "fmlalb Zda.S, Zn.H, Zm.H[#idx]" , "op": "01100100|10|1|idx:2|Zm:3|0100|idx:1|0|Zn|Zda" , "t": "~HSD"},
|
||
|
|
{"inst": "fmlalt Zda.S, Zn.H, Zm.H" , "op": "01100100|10|1|Zm|100001|Zn|Zda" , "t": "~HSD"},
|
||
|
|
{"inst": "fmlalt Zda.S, Zn.H, Zm.H[#idx]" , "op": "01100100|10|1|idx:2|Zm:3|0100|idx:1|1|Zn|Zda" , "t": "~HSD"},
|
||
|
|
{"inst": "fmlslb Zda.S, Zn.H, Zm.H" , "op": "01100100|10|1|Zm|101000|Zn|Zda" , "t": "~HSD"},
|
||
|
|
{"inst": "fmlslb Zda.S, Zn.H, Zm.H[#idx]" , "op": "01100100|10|1|idx:2|Zm:3|0110|idx:1|0|Zn|Zda" , "t": "~HSD"},
|
||
|
|
{"inst": "fmlslt Zda.S, Zn.H, Zm.H" , "op": "01100100|10|1|Zm|101001|Zn|Zda" , "t": "~HSD"},
|
||
|
|
{"inst": "fmlslt Zda.S, Zn.H, Zm.H[#idx]" , "op": "01100100|10|1|idx:2|Zm:3|0110|idx:1|1|Zn|Zda" , "t": "~HSD"},
|
||
|
|
{"inst": "histcnt Zd.t, Pg/Z, Zn.t, Zm.t" , "op": "01000101|sz|1|Zm|110|Pg:3|Zn|Zd" , "t": "~~SD"},
|
||
|
|
{"inst": "histseg Zd.B, Zn.B, Zm.B" , "op": "01000101|00|1|Zm|101000|Zn|Zd"},
|
||
|
|
{"inst": "match Pd.t, Pg/Z, Zn.t, Zm.t" , "op": "01000101|sz|1|Zm|100|Pg:3|Zn|0|Pd" , "io": "N=W Z=W C=W V=W", "t": "BH~~"},
|
||
|
|
{"inst": "mla Zda.H, Zn.H, Zm.H[#idx]" , "op": "01000100|0|idx:1|1|idx:2|Zm:3|000010|Zn|Zda"},
|
||
|
|
{"inst": "mla Zda.S, Zn.S, Zm.S[#idx]" , "op": "01000100|10|1|idx:2|Zm:3|000010|Zn|Zda"},
|
||
|
|
{"inst": "mla Zda.D, Zn.D, Zm.D[#idx]" , "op": "01000100|11|1|idx:1|Zm:4|000010|Zn|Zda"},
|
||
|
|
{"inst": "mls Zda.H, Zn.H, Zm.H[#idx]" , "op": "01000100|0|idx:1|1|idx:2|Zm:3|000011|Zn|Zda"},
|
||
|
|
{"inst": "mls Zda.S, Zn.S, Zm.S[#idx]" , "op": "01000100|10|1|idx:2|Zm:3|000011|Zn|Zda"},
|
||
|
|
{"inst": "mls Zda.D, Zn.D, Zm.D[#idx]" , "op": "01000100|11|1|idx:1|Zm:4|000011|Zn|Zda"},
|
||
|
|
{"inst": "mul Zd.t, Zn.t, Zm.t" , "op": "00000100|sz|1|Zm|011000|Zn|Zd"},
|
||
|
|
{"inst": "mul Zd.H, Zn.H, Zm.H[#idx]" , "op": "01000100|0|idx:1|1|idx:2|Zm:3|111110|Zn|Zd"},
|
||
|
|
{"inst": "mul Zd.S, Zn.S, Zm.S[#idx]" , "op": "01000100|10|1|idx:2|Zm:3|111110|Zn|Zd"},
|
||
|
|
{"inst": "mul Zd.D, Zn.D, Zm.D[#idx]" , "op": "01000100|11|1|idx:1|Zm:4|111110|Zn|Zd"},
|
||
|
|
{"inst": "nbsl Zdn.D, Zdn.D, Zm.D, Zk.D" , "op": "00000100|11|1|Zm|001111|Zk|Zdn"},
|
||
|
|
{"inst": "nmatch Pd.t, Pg/Z, Zn.t, Zm.t" , "op": "01000101|sz|1|Zm|100|Pg:3|Zn|1|Pd" , "io": "N=W Z=W C=W V=W", "t": "BH~~"},
|
||
|
|
{"inst": "pmul Zd.B, Zn.B, Zm.B" , "op": "00000100|00|1|Zm|011001|Zn|Zd"},
|
||
|
|
{"inst": "pmullb Zd.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|0|Zm|011010|Zn|Zd" , "ta": "QH~D", "tb": "DB~S"},
|
||
|
|
{"inst": "pmullt Zd.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|0|Zm|011011|Zn|Zd" , "ta": "QH~D", "tb": "DB~S"},
|
||
|
|
{"inst": "raddhnb Zd.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|1|Zm|011010|Zn|Zd" , "ta": "~BHS", "tb": "~HSD"},
|
||
|
|
{"inst": "raddhnt Zd.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|1|Zm|011011|Zn|Zd" , "ta": "~BHS", "tb": "~HSD"},
|
||
|
|
{"inst": "rsubhnb Zd.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|1|Zm|011110|Zn|Zd" , "ta": "~BHS", "tb": "~HSD"},
|
||
|
|
{"inst": "rsubhnt Zd.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|1|Zm|011111|Zn|Zd" , "ta": "~BHS", "tb": "~HSD"},
|
||
|
|
{"inst": "saba Zda.t, Zn.t, Zm.t" , "op": "01000101|sz|0|Zm|111110|Zn|Zd"},
|
||
|
|
{"inst": "sabalb Zda.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|0|Zm|110000|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
|
||
|
|
{"inst": "sabalt Zda.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|0|Zm|110001|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
|
||
|
|
{"inst": "sabdlb Zd.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|0|Zm|001100|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
|
||
|
|
{"inst": "sabdlt Zd.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|0|Zm|001101|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
|
||
|
|
{"inst": "sadalp Zda.ta, Pg/M, Zn.tb" , "op": "01000100|sz|0|00100101|Pg:3|Zn|Zda" , "ta": "~HSD", "tb": "~BHS"},
|
||
|
|
{"inst": "saddlb Zd.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|0|Zm|000000|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
|
||
|
|
{"inst": "saddlbt Zd.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|0|Zm|100000|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
|
||
|
|
{"inst": "saddlt Zd.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|0|Zm|000001|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
|
||
|
|
{"inst": "saddwb Zd.ta, Zn.t, Zm.tb" , "op": "01000101|sz|0|Zm|010000|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
|
||
|
|
{"inst": "saddwt Zd.ta, Zn.t, Zm.tb" , "op": "01000101|sz|0|Zm|010001|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
|
||
|
|
{"inst": "sbclb Zda.t, Zn.t, Zm.t" , "op": "01000101|sz|0|Zm|110100|Zn|Zda" , "t": "~~SD"},
|
||
|
|
{"inst": "sbclt Zda.t, Zn.t, Zm.t" , "op": "01000101|sz|0|Zm|110101|Zn|Zda" , "t": "~~SD"},
|
||
|
|
{"inst": "shadd Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|0|10000100|Pg:3|Zm|Zdn"},
|
||
|
|
{"inst": "shsub Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|0|10010100|Pg:3|Zm|Zdn"},
|
||
|
|
{"inst": "shsubr Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|0|10110100|Pg:3|Zm|Zdn"},
|
||
|
|
{"inst": "sli Zd.t, Zn.t, #idxmm" , "op": "01000101|imm:2|0|imm:5|111101|Zn|Zd" , "imm": "SveShiftImm7(sz, imm)"},
|
||
|
|
{"inst": "smaxp Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|0|10100101|Pg:3|Zm|Zdn"},
|
||
|
|
{"inst": "sminp Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|0|10110101|Pg:3|Zm|Zdn"},
|
||
|
|
{"inst": "smlalb Zda.ta, Zn.tb, Zm.tb" , "op": "01000100|sz|0|Zm|010000|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
|
||
|
|
{"inst": "smlalb Zda.S, Zn.H, Zm.H[#idx]" , "op": "01000100|10|1|idx:2|Zm:3|1000|idx:1|0|Zn|Zda"},
|
||
|
|
{"inst": "smlalb Zda.D, Zn.S, Zm.S[#idx]" , "op": "01000100|11|1|idx:2|Zm:3|1000|idx:1|0|Zn|Zda"},
|
||
|
|
{"inst": "smlalt Zda.ta, Zn.tb, Zm.tb" , "op": "01000100|sz|0|Zm|010001|Zn|Zda" , "ta": "~HSD", "tb": "~BHS"},
|
||
|
|
{"inst": "smlalt Zda.S, Zn.H, Zm.H[#idx]" , "op": "01000100|10|1|idx:2|Zm:3|1000|idx:1|1|Zn|Zda"},
|
||
|
|
{"inst": "smlalt Zda.D, Zn.S, Zm.S[#idx]" , "op": "01000100|11|1|idx:2|Zm:3|1000|idx:1|1|Zn|Zda"},
|
||
|
|
{"inst": "smlslb Zda.ta, Zn.tb, Zm.tb" , "op": "01000100|sz|0|Zm|010100|Zn|Zda" , "ta": "~HSD", "tb": "~BHS"},
|
||
|
|
{"inst": "smlslb Zda.S, Zn.H, Zm.H[#idx]" , "op": "01000100|10|1|idx:2|Zm:3|1010|idx:1|0|Zn|Zda"},
|
||
|
|
{"inst": "smlslb Zda.D, Zn.S, Zm.S[#idx]" , "op": "01000100|11|1|idx:2|Zm:3|1010|idx:1|0|Zn|Zda"},
|
||
|
|
{"inst": "smlslt Zda.ta, Zn.tb, Zm.tb" , "op": "01000100|sz|0|Zm|010101|Zn|Zda" , "ta": "~HSD", "tb": "~BHS"},
|
||
|
|
{"inst": "smlslt Zda.S, Zn.H, Zm.H[#idx]" , "op": "01000100|10|1|idx:2|Zm:3|1010|idx:1|1|Zn|Zda"},
|
||
|
|
{"inst": "smlslt Zda.D, Zn.S, Zm.S[#idx]" , "op": "01000100|11|1|idx:2|Zm:3|1010|idx:1|1|Zn|Zda"},
|
||
|
|
{"inst": "smulh Zd.t, Zn.t, Zm.t" , "op": "00000100|sz|1|Zm|011010|Zn|Zd"},
|
||
|
|
{"inst": "smullb Zd.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|0|Zm|011100|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
|
||
|
|
{"inst": "smullb Zda.S, Zn.H, Zm.H[#idx]" , "op": "01000100|10|1|idx:2|Zm:3|1100|idx:1|0|Zn|Zda"},
|
||
|
|
{"inst": "smullb Zda.D, Zn.S, Zm.S[#idx]" , "op": "01000100|11|1|idx:2|Zm:3|1100|idx:1|0|Zn|Zda"},
|
||
|
|
{"inst": "smullt Zd.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|0|Zm|011101|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
|
||
|
|
{"inst": "smullt Zda.S, Zn.H, Zm.H[#idx]" , "op": "01000100|10|1|idx:2|Zm:3|1100|idx:1|1|Zn|Zda"},
|
||
|
|
{"inst": "smullt Zda.D, Zn.S, Zm.S[#idx]" , "op": "01000100|11|1|idx:2|Zm:3|1100|idx:1|1|Zn|Zda"},
|
||
|
|
{"inst": "splice Zd.t, Pg, 2x{Zn.t}+" , "op": "00000101|sz|1|01101100|Pg:3|Zn|Zd"},
|
||
|
|
{"inst": "sqabs Zd.t, Pg/M, Zn.t" , "op": "01000100|sz|0|01000101|Pg:3|Zn|Zd"},
|
||
|
|
{"inst": "sqadd Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|0|11000100|Pg:3|Zm|Zdn"},
|
||
|
|
{"inst": "sqcadd Zdn.t, Zdn.t, Zm.t, #rot1" , "op": "01000101|sz|0|0000111011|imm:1|Zm|Zdn" , "imm": "Rot1Imm(rot1)"},
|
||
|
|
{"inst": "sqdmlalb Zda.ta, Zn.tb, Zm.tb" , "op": "01000100|sz|0|Zm|011000|Zn|Zda" , "ta": "~HSD", "tb": "~BHS"},
|
||
|
|
{"inst": "sqdmlalb Zda.S, Zn.H, Zm.H[#idx]" , "op": "01000100|10|1|idx:2|Zm:3|0010|idx:1|0|Zn|Zda"},
|
||
|
|
{"inst": "sqdmlalb Zda.D, Zn.S, Zm.S[#idx]" , "op": "01000100|11|1|idx:2|Zm:3|0010|idx:1|0|Zn|Zda"},
|
||
|
|
{"inst": "sqdmlalbt Zda.ta, Zn.tb, Zm.tb" , "op": "01000100|sz|0|Zm|000010|Zn|Zda" , "ta": "~HSD", "tb": "~BHS"},
|
||
|
|
{"inst": "sqdmlalt Zda.ta, Zn.tb, Zm.tb" , "op": "01000100|sz|0|Zm|011001|Zn|Zda" , "ta": "~HSD", "tb": "~BHS"},
|
||
|
|
{"inst": "sqdmlalt Zda.S, Zn.H, Zm.H[#idx]" , "op": "01000100|10|1|idx:2|Zm:3|0010|idx:1|1|Zn|Zda"},
|
||
|
|
{"inst": "sqdmlalt Zda.D, Zn.S, Zm.S[#idx]" , "op": "01000100|11|1|idx:2|Zm:3|0010|idx:1|1|Zn|Zda"},
|
||
|
|
{"inst": "sqdmlslb Zda.ta, Zn.tb, Zm.tb" , "op": "01000100|sz|0|Zm|011010|Zn|Zda" , "ta": "~HSD", "tb": "~BHS"},
|
||
|
|
{"inst": "sqdmlslb Zda.S, Zn.H, Zm.H[#idx]" , "op": "01000100|10|1|idx:2|Zm:3|0011|idx:1|0|Zn|Zda"},
|
||
|
|
{"inst": "sqdmlslb Zda.D, Zn.S, Zm.S[#idx]" , "op": "01000100|11|1|idx:2|Zm:3|0011|idx:1|0|Zn|Zda"},
|
||
|
|
{"inst": "sqdmlslbt Zda.ta, Zn.tb, Zm.tb" , "op": "01000100|sz|0|Zm|000011|Zn|Zda" , "ta": "~HSD", "tb": "~BHS"},
|
||
|
|
{"inst": "sqdmlslt Zda.ta, Zn.tb, Zm.tb" , "op": "01000100|sz|0|Zm|011011|Zn|Zda" , "ta": "~HSD", "tb": "~BHS"},
|
||
|
|
{"inst": "sqdmlslt Zda.S, Zn.H, Zm.H[#idx]" , "op": "01000100|10|1|idx:2|Zm:3|0011|idx:1|1|Zn|Zda"},
|
||
|
|
{"inst": "sqdmlslt Zda.D, Zn.S, Zm.S[#idx]" , "op": "01000100|11|1|idx:2|Zm:3|0011|idx:1|1|Zn|Zda"},
|
||
|
|
{"inst": "sqdmulh Zd.t, Zn.t, Zm.t" , "op": "00000100|sz|1|Zm|011100|Zn|Zd" , "t": "~HSD"},
|
||
|
|
{"inst": "sqdmulh Zd.H, Zn.H, Zm.H[#idx]" , "op": "01000100|0|idx:1|1|idx:2|Zm:3|111100|Zn|Zd"},
|
||
|
|
{"inst": "sqdmulh Zd.S, Zn.S, Zm.S[#idx]" , "op": "01000100|10|1|idx:2|Zm:3|111100|Zn|Zd"},
|
||
|
|
{"inst": "sqdmulh Zd.D, Zn.D, Zm.D[#idx]" , "op": "01000100|11|1|idx:1|Zm:4|111100|Zn|Zd"},
|
||
|
|
{"inst": "sqdmullb Zd.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|0|Zm|011000|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
|
||
|
|
{"inst": "sqdmullb Zd.S, Zn.S, Zm.S[#idx]" , "op": "01000100|10|1|idx:2|Zm:3|1110|idx:1|0|Zn|Zd"},
|
||
|
|
{"inst": "sqdmullb Zd.D, Zn.D, Zm.D[#idx]" , "op": "01000100|11|1|idx:1|Zm:4|1110|idx:1|0|Zn|Zd"},
|
||
|
|
{"inst": "sqdmullt Zd.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|0|Zm|011001|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
|
||
|
|
{"inst": "sqdmullt Zd.S, Zn.S, Zm.S[#idx]" , "op": "01000100|10|1|idx:2|Zm:3|1110|idx:1|1|Zn|Zd"},
|
||
|
|
{"inst": "sqdmullt Zd.D, Zn.D, Zm.D[#idx]" , "op": "01000100|11|1|idx:1|Zm:4|1110|idx:1|1|Zn|Zd"},
|
||
|
|
{"inst": "sqneg Zd.t, Pg/M, Zn.t" , "op": "01000100|sz|001001101|Pg:3|Zm|Zdn"},
|
||
|
|
{"inst": "sqrdcmlah Zda.t, Zn.t, Zm.t, #rot2" , "op": "01000100|sz|0|Zm|0011|imm:2|Zn|Zda" , "imm": "Rot2Imm(rot2)"},
|
||
|
|
{"inst": "sqrdcmlah Zda.H, Zn.H, Zm.H[#idx], #rot2" , "op": "01000100|10|1|idx:2|Zm:3|0111|imm:2|Zn|Zda" , "imm": "Rot2Imm(rot2)"},
|
||
|
|
{"inst": "sqrdcmlah Zda.S, Zn.S, Zm.S[#idx], #rot2" , "op": "01000100|11|1|idx:1|Zm:4|0111|imm:2|Zn|Zda" , "imm": "Rot2Imm(rot2)"},
|
||
|
|
{"inst": "sqrdmlah Zda.t, Zn.t, Zm.t" , "op": "01000100|sz|0|Zm|011100|Zn|Zda"},
|
||
|
|
{"inst": "sqrdmlah Zda.H, Zn.H, Zm.H[#idx]" , "op": "01000100|0|idx:1|1|idx:2|Zm:3|000100|Zn|Zda"},
|
||
|
|
{"inst": "sqrdmlah Zda.S, Zn.S, Zm.S[#idx]" , "op": "01000100|10|1|idx:2|Zm:3|000100|Zn|Zda"},
|
||
|
|
{"inst": "sqrdmlah Zda.D, Zn.D, Zm.D[#idx]" , "op": "01000100|11|1|idx:1|Zm:4|000100|Zn|Zda"},
|
||
|
|
{"inst": "sqrdmlsh Zda.t, Zn.t, Zm.t" , "op": "01000100|sz|0|Zm|011101|Zn|Zda"},
|
||
|
|
{"inst": "sqrdmlsh Zda.H, Zn.H, Zm.H[#idx]" , "op": "01000100|0|idx:1|1|idx:2|Zm:3|000101|Zn|Zda"},
|
||
|
|
{"inst": "sqrdmlsh Zda.S, Zn.S, Zm.S[#idx]" , "op": "01000100|10|1|idx:2|Zm:3|000101|Zn|Zda"},
|
||
|
|
{"inst": "sqrdmlsh Zda.D, Zn.D, Zm.D[#idx]" , "op": "01000100|11|1|idx:1|Zm:4|000101|Zn|Zda"},
|
||
|
|
{"inst": "sqrdmulh Zd.t, Zn.t, Zm.t" , "op": "00000100|sz|1|Zm|011101|Zn|Zd"},
|
||
|
|
{"inst": "sqrdmulh Zd.H, Zn.H, Zm.H[#idx]" , "op": "01000100|0|idx:1|1|idx:2|Zm:3|111101|Zn|Zd"},
|
||
|
|
{"inst": "sqrdmulh Zd.S, Zn.S, Zm.S[#idx]" , "op": "01000100|10|1|idx:2|Zm:3|111101|Zn|Zd"},
|
||
|
|
{"inst": "sqrdmulh Zd.D, Zn.D, Zm.D[#idx]" , "op": "01000100|11|1|idx:1|Zm:4|111101|Zn|Zd"},
|
||
|
|
{"inst": "sqrshl Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|001010100|Pg:3|Zm|Zdn"},
|
||
|
|
{"inst": "sqrshlr Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|001110100|Pg:3|Zm|Zdn"},
|
||
|
|
{"inst": "sqrshrnb Zd.ta, Zd.tb, #imm" , "op": "01000101|0|imm:1|1|imm:5|001010|Zn|Zd" , "imm": "SveShiftImm6(sz, imm)", "ta": "~BHS", "tb": "~HSD"},
|
||
|
|
{"inst": "sqrshrnt Zd.ta, Zd.tb, #imm" , "op": "01000101|0|imm:1|1|imm:5|001011|Zn|Zd" , "imm": "SveShiftImm6(sz, imm)", "ta": "~BHS", "tb": "~HSD"},
|
||
|
|
{"inst": "sqrshrunb Zd.ta, Zd.tb, #imm" , "op": "01000101|0|imm:1|1|imm:5|000010|Zn|Zd" , "imm": "SveShiftImm6(sz, imm)", "ta": "~BHS", "tb": "~HSD"},
|
||
|
|
{"inst": "sqrshrunt Zd.ta, Zd.tb, #imm" , "op": "01000101|0|imm:1|1|imm:5|000011|Zn|Zd" , "imm": "SveShiftImm6(sz, imm)", "ta": "~BHS", "tb": "~HSD"},
|
||
|
|
{"inst": "sqshl Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|001000100|Pg:3|Zm|Zdn"},
|
||
|
|
{"inst": "sqshl Zdn.t, Pg/M, Zdn.t, #imm" , "op": "00000100|imm:2|000110100|Pg:3|imm:5|Zdn" , "imm": "SveShiftImm7(sz, imm)"},
|
||
|
|
{"inst": "sqshlr Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|001100100|Pg:3|Zm|Zdn"},
|
||
|
|
{"inst": "sqshlu Zdn.t, Pg/M, Zdn.t, #imm" , "op": "00000100|imm:2|001111100|Pg:3|imm:5|Zdn" , "imm": "SveShiftImm7(sz, imm)"},
|
||
|
|
{"inst": "sqshrnb Zd.t, Zn.tb, #imm" , "op": "01000101|0|imm:1|1|imm:5|001000|Zn|Zd" , "imm": "SveShiftImm6(sz, imm)"},
|
||
|
|
{"inst": "sqshrnt Zd.t, Zn.tb, #imm" , "op": "01000101|0|imm:1|1|imm:5|001001|Zn|Zd" , "imm": "SveShiftImm6(sz, imm)"},
|
||
|
|
{"inst": "sqshrunb Zd.t, Zn.tb, #imm" , "op": "01000101|0|imm:1|1|imm:5|000000|Zn|Zd" , "imm": "SveShiftImm6(sz, imm)"},
|
||
|
|
{"inst": "sqshrunt Zd.t, Zn.tb, #imm" , "op": "01000101|0|imm:1|1|imm:5|000000|Zn|Zd" , "imm": "SveShiftImm6(sz, imm)"},
|
||
|
|
{"inst": "sqsub Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|011010100|Pg:3|Zm|Zdn"},
|
||
|
|
{"inst": "sqsubr Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|011110100|Pg:3|Zm|Zdn"},
|
||
|
|
{"inst": "sqxtnb Zd.ta, Zn.tb" , "op": "01000101|0|imm:1|1|imm:2|000010000|Zn|Zd" , "imm": "SveXtImm(sz)", "ta": "~BHS", "tb": "~HSD"},
|
||
|
|
{"inst": "sqxtnt Zd.ta, Zn.tb" , "op": "01000101|0|imm:1|1|imm:2|000010001|Zn|Zd" , "imm": "SveXtImm(sz)", "ta": "~BHS", "tb": "~HSD"},
|
||
|
|
{"inst": "sqxtunb Zd.ta, Zn.tb" , "op": "01000101|0|imm:1|1|imm:2|000010100|Zn|Zd" , "imm": "SveXtImm(sz)", "ta": "~BHS", "tb": "~HSD"},
|
||
|
|
{"inst": "sqxtunt Zd.ta, Zn.tb" , "op": "01000101|0|imm:1|1|imm:2|000010101|Zn|Zd" , "imm": "SveXtImm(sz)", "ta": "~BHS", "tb": "~HSD"},
|
||
|
|
{"inst": "srhadd Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|010100100|Pg:3|Zm|Zdn"},
|
||
|
|
{"inst": "sri Zd.t, Zn.t, #imm" , "op": "01000101|imm:2|0|imm:5|111100|Zn|Zd" , "imm": "SveShiftImm7(sz, imm)"},
|
||
|
|
{"inst": "srshl Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|000010100|Pg:3|Zm|Zdn"},
|
||
|
|
{"inst": "srshlr Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|000110100|Pg:3|Zm|Zdn"},
|
||
|
|
{"inst": "srshr Zdn.t, Pg/M, Zdn.t, #imm" , "op": "00000100|imm:2|001100100|Pg:3|imm:5|Zdn" , "imm": "SveShiftImm7(sz, imm)"},
|
||
|
|
{"inst": "srsra Zda.t, Zn.t, #imm" , "op": "01000101|imm:2|0|imm:5|111010|Zn|Zda" , "imm": "SveShiftImm7(sz, imm)"},
|
||
|
|
{"inst": "sshllb Zd.t, Zn.t, #imm" , "op": "01000101|0|imm:1|0|imm:5|101000|Zn|Zd" , "imm": "SveShiftImm6(sz, imm)"},
|
||
|
|
{"inst": "sshllt Zd.t, Zn.t, #imm" , "op": "01000101|0|imm:1|0|imm:5|101001|Zn|Zd" , "imm": "SveShiftImm6(sz, imm)"},
|
||
|
|
{"inst": "ssra Zda.t, Zn.t, #imm" , "op": "01000101|imm:2|0|imm:5|111000|Zn|Zda" , "imm": "SveShiftImm7(sz, imm)"},
|
||
|
|
{"inst": "ssublb Zd.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|0|Zm|000100|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
|
||
|
|
{"inst": "ssublbt Zd.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|0|Zm|100010|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
|
||
|
|
{"inst": "ssublt Zd.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|0|Zm|000101|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
|
||
|
|
{"inst": "ssubltb Zd.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|0|Zm|100011|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
|
||
|
|
{"inst": "ssubwb Zd.ta, Zn.t, Zm.tb" , "op": "01000101|sz|0|Zm|010100|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
|
||
|
|
{"inst": "ssubwt Zd.ta, Zn.t, Zm.tb" , "op": "01000101|sz|0|Zm|010101|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
|
||
|
|
{"inst": "subhnb Zd.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|1|Zm|011100|Zn|Zd" , "ta": "~BHS", "tb": "~HSD"},
|
||
|
|
{"inst": "subhnt Zd.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|1|Zm|011101|Zn|Zd" , "ta": "~BHS", "tb": "~HSD"},
|
||
|
|
{"inst": "suqadd Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|011100100|Pg:3|Zm|Zdn"},
|
||
|
|
{"inst": "tbl Zd.t, 2x{Zn.t}+, Zm.t" , "op": "00000101|sz|1|Zm|001010|Zn|Zd"},
|
||
|
|
{"inst": "tbx Zd.t, Zn.t, Zm.t" , "op": "00000101|sz|1|Zm|001011|Zn|Zd"},
|
||
|
|
{"inst": "uaba Zda.t, Zn.t, Zm.t" , "op": "01000101|sz|0|Zm|111111|Zn|Zd"},
|
||
|
|
{"inst": "uabalb Zda.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|0|Zm|110010|Zn|Zd" , "TODO": "ta.tb?"},
|
||
|
|
{"inst": "uabalt Zda.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|0|Zm|110011|Zn|Zd" , "TODO": "ta.tb?"},
|
||
|
|
{"inst": "uabdlb Zd.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|0|Zm|001110|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
|
||
|
|
{"inst": "uabdlt Zd.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|0|Zm|001111|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
|
||
|
|
{"inst": "uadalp Zda.ta, Pg/M, Zn.tb" , "op": "01000100|sz|000101101|Pg:3|Zn|Zda" , "ta": "~HSD", "tb": "~BHS"},
|
||
|
|
{"inst": "uaddlb Zd.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|0|Zm|000010|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
|
||
|
|
{"inst": "uaddlt Zd.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|0|Zm|000011|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
|
||
|
|
{"inst": "uaddwb Zd.ta, Zn.ta, Zm.tb" , "op": "01000101|sz|0|Zm|010010|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
|
||
|
|
{"inst": "uaddwt Zd.ta, Zn.ta, Zm.tb" , "op": "01000101|sz|0|Zm|010011|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
|
||
|
|
{"inst": "uhadd Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|010001100|Pg:3|Zm|Zdn"},
|
||
|
|
{"inst": "uhsub Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|010011100|Pg:3|Zm|Zdn"},
|
||
|
|
{"inst": "uhsubr Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|010111100|Pg:3|Zm|Zdn"},
|
||
|
|
{"inst": "umaxp Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|010101101|Pg:3|Zm|Zdn"},
|
||
|
|
{"inst": "uminp Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|010111101|Pg:3|Zm|Zdn"},
|
||
|
|
{"inst": "umlalb Zda.ta, Zn.tb, Zm.tb" , "op": "01000100|sz|0|Zm|010010|Zn|Zda" , "ta": "~HSD", "tb": "~BHS"},
|
||
|
|
{"inst": "umlalb Zda.S, Zn.H, Zm.H[#idx]" , "op": "01000100|10|1|idx:2|Zm:3|1001|idx:1|0|Zn|Zda"},
|
||
|
|
{"inst": "umlalb Zda.D, Zn.S, Zm.S[#idx]" , "op": "01000100|11|1|idx:2|Zm:3|1001|idx:1|0|Zn|Zda"},
|
||
|
|
{"inst": "umlalt Zda.ta, Zn.tb, Zm.tb" , "op": "01000100|sz|0|Zm|010011|Zn|Zda" , "ta": "~HSD", "tb": "~BHS"},
|
||
|
|
{"inst": "umlalt Zda.S, Zn.H, Zm.H[#idx]" , "op": "01000100|10|1|idx:2|Zm:3|1001|idx:1|1|Zn|Zda"},
|
||
|
|
{"inst": "umlalt Zda.D, Zn.S, Zm.S[#idx]" , "op": "01000100|11|1|idx:2|Zm:3|1001|idx:1|1|Zn|Zda"},
|
||
|
|
{"inst": "umlslb Zda.ta, Zn.tb, Zm.tb" , "op": "01000100|sz|0|Zm|010110|Zn|Zda" , "ta": "~HSD", "tb": "~BHS"},
|
||
|
|
{"inst": "umlslb Zda.S, Zn.H, Zm.H[#idx]" , "op": "01000100|10|1|idx:2|Zm:3|1011|idx:1|0|Zn|Zda"},
|
||
|
|
{"inst": "umlslb Zda.D, Zn.S, Zm.S[#idx]" , "op": "01000100|11|1|idx:2|Zm:3|1011|idx:1|0|Zn|Zda"},
|
||
|
|
{"inst": "umlslt Zda.ta, Zn.tb, Zm.tb" , "op": "01000100|sz|0|Zm|010111|Zn|Zda" , "ta": "~HSD", "tb": "~BHS"},
|
||
|
|
{"inst": "umlslt Zda.S, Zn.H, Zm.H[#idx]" , "op": "01000100|10|1|idx:2|Zm:3|1011|idx:1|1|Zn|Zda"},
|
||
|
|
{"inst": "umlslt Zda.D, Zn.S, Zm.S[#idx]" , "op": "01000100|11|1|idx:2|Zm:3|1011|idx:1|1|Zn|Zda"},
|
||
|
|
{"inst": "umulh Zd.t, Zn.t, Zm.t" , "op": "00000100|sz|1|Zm|011011|Zn|Zd"},
|
||
|
|
{"inst": "umullb Zd.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|0|Zm|011110|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
|
||
|
|
{"inst": "umullb Zda.S, Zn.H, Zm.H[#idx]" , "op": "01000100|10|1|idx:2|Zm:3|1101|idx:1|0|Zn|Zda"},
|
||
|
|
{"inst": "umullb Zda.D, Zn.S, Zm.S[#idx]" , "op": "01000100|11|1|idx:2|Zm:3|1101|idx:1|0|Zn|Zda"},
|
||
|
|
{"inst": "umullt Zd.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|0|Zm|011111|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
|
||
|
|
{"inst": "umullt Zda.S, Zn.H, Zm.H[#idx]" , "op": "01000100|10|1|idx:2|Zm:3|1101|idx:1|1|Zn|Zda"},
|
||
|
|
{"inst": "umullt Zda.D, Zn.S, Zm.S[#idx]" , "op": "01000100|11|1|idx:2|Zm:3|1101|idx:1|1|Zn|Zda"},
|
||
|
|
{"inst": "uqadd Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|011001100|Pg:3|Zm|Zdn"},
|
||
|
|
{"inst": "uqrshl Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|001011100|Pg:3|Zm|Zdn"},
|
||
|
|
{"inst": "uqrshlr Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|001111100|Pg:3|Zm|Zdn"},
|
||
|
|
{"inst": "uqrshrnb Zd.ta, Zd.tb, #idxmm" , "op": "01000101|0|imm:1|1|imm:5|001110|Zn|Zd" , "imm": "SveShiftImm6(sz, imm)", "ta": "~BHS", "tb": "~HSD"},
|
||
|
|
{"inst": "uqrshrnt Zd.ta, Zd.tb, #imm" , "op": "01000101|0|imm:1|1|imm:5|001111|Zn|Zd" , "imm": "SveShiftImm6(sz, imm)", "ta": "~BHS", "tb": "~HSD"},
|
||
|
|
{"inst": "uqshl Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|001001100|Pg:3|Zm|Zdn"},
|
||
|
|
{"inst": "uqshl Zdn.t, Pg/M, Zdn.t, #imm" , "op": "00000100|imm:2|000111100|Pg:3|imm:5|Zdn" , "imm": "SveShiftImm7(sz, imm)"},
|
||
|
|
{"inst": "uqshlr Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|001101100|Pg:3|Zm|Zdn"},
|
||
|
|
{"inst": "uqshrnb Zd.t, Zn.tb, #imm" , "op": "01000101|0|imm:1|1|imm:5|001100|Zn|Zd" , "imm": "SveShiftImm6(sz, imm)"},
|
||
|
|
{"inst": "uqshrnt Zd.t, Zn.tb, #imm" , "op": "01000101|0|imm:1|1|imm:5|001101|Zn|Zd" , "imm": "SveShiftImm6(sz, imm)"},
|
||
|
|
{"inst": "uqsub Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|011011100|Pg:3|Zm|Zdn"},
|
||
|
|
{"inst": "uqsubr Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|011111100|Pg:3|Zm|Zdn"},
|
||
|
|
{"inst": "uqxtnb Zd.ta, Zn.tb" , "op": "01000101|0|imm:1|1|imm:2|000010010|Zn|Zd" , "imm": "SveXtImm(sz)", "ta": "~BHS", "tb": "~HSD"},
|
||
|
|
{"inst": "uqxtnt Zd.ta, Zn.tb" , "op": "01000101|0|imm:1|1|imm:2|000010011|Zn|Zd" , "imm": "SveXtImm(sz)", "ta": "~BHS", "tb": "~HSD"},
|
||
|
|
{"inst": "urecpe Zd.S, Pg/M, Zn.S" , "op": "01000100|10|000000101|Pg:3|Zn|Zd"},
|
||
|
|
{"inst": "urhadd Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|010101100|Pg:3|Zm|Zdn"},
|
||
|
|
{"inst": "urshl Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|000011100|Pg:3|Zm|Zdn"},
|
||
|
|
{"inst": "urshlr Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|000111100|Pg:3|Zm|Zdn"},
|
||
|
|
{"inst": "urshr Zdn.t, Pg/M, Zdn.t, #imm" , "op": "00000100|imm:2|001101100|Pg:3|imm:5|Zdn" , "imm": "SveShiftImm7(sz, imm)"},
|
||
|
|
{"inst": "ursqrte Zd.S, Pg/M, Zn.S" , "op": "01000100|10|000001101|Pg:3|Zn|Zd"},
|
||
|
|
{"inst": "ursra Zda.t, Zn.t, #imm" , "op": "01000101|imm:2|0|imm:5|111011|Zn|Zda" , "imm": "SveShiftImm7(sz, imm)"},
|
||
|
|
{"inst": "ushllb Zd.t, Zn.t, #imm" , "op": "01000101|0|imm:1|0|imm:5|101010|Zn|Zd" , "imm": "SveShiftImm6(sz, imm)"},
|
||
|
|
{"inst": "ushllt Zd.t, Zn.t, #imm" , "op": "01000101|0|imm:1|0|imm:5|101011|Zn|Zd" , "imm": "SveShiftImm6(sz, imm)"},
|
||
|
|
{"inst": "usqadd Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|011101100|Pg:3|Zm|Zdn"},
|
||
|
|
{"inst": "usra Zda.t, Zn.t, #imm" , "op": "01000101|imm:2|0|imm:5|111001|Zn|Zda" , "imm": "SveShiftImm7(sz, imm)"},
|
||
|
|
{"inst": "usublb Zd.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|0|Zm|000110|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
|
||
|
|
{"inst": "usublt Zd.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|0|Zm|000111|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
|
||
|
|
{"inst": "usubwb Zd.ta, Zn.ta, Zm.tb" , "op": "01000101|sz|0|Zm|010110|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
|
||
|
|
{"inst": "usubwt Zd.ta, Zn.ta, Zm.tb" , "op": "01000101|sz|0|Zm|010111|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
|
||
|
|
{"inst": "whilerw Pd.t, Xn, Xm" , "op": "00100101|sz|1|Rm|001100|Rn|1|Pd"},
|
||
|
|
{"inst": "whilewr Pd.t, Xn, Xm" , "op": "00100101|sz|1|Rm|001100|Rn|0|Pd"},
|
||
|
|
{"inst": "xar Zdn.t, Zdn.t, Zm.t, #imm" , "op": "00000100|imm:2|1|imm:5|001101|Zm|Zdn" , "imm": "SveShiftImm7(sz, imm)"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "SVE CRYPTO_HASH", "ext": "SVE2_AES", "data": [
|
||
|
|
{"inst": "aesd Zdn.B, Zdn.B, Zm.B" , "op": "01000101|00|100010111|001|Zm|Zdn"},
|
||
|
|
{"inst": "aese Zdn.B, Zdn.B, Zm.B" , "op": "01000101|00|100010111|000|Zm|Zdn"},
|
||
|
|
{"inst": "aesimc Zdn.B, Zdn.B" , "op": "01000101|00|100000111|001|00000|Zdn"},
|
||
|
|
{"inst": "aesmc Zdn.B, Zdn.B" , "op": "01000101|00|100000111|000|00000|Zdn"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "SVE", "ext": "SVE2_BITPERM", "data": [
|
||
|
|
{"inst": "bdep Zd.t, Zn.t, Zm.t" , "op": "01000101|sz|0|Zm|101101|Zn|Zd"},
|
||
|
|
{"inst": "bext Zd.t, Zn.t, Zm.t" , "op": "01000101|sz|0|Zm|101100|Zn|Zd"},
|
||
|
|
{"inst": "bgrp Zd.t, Zn.t, Zm.t" , "op": "01000101|sz|0|Zm|101110|Zn|Zd"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "SVE CRYPTO_HASH", "ext": "SVE2_SHA3", "data": [
|
||
|
|
{"inst": "rax1 Zd.D, Zn.D, Zm.D" , "op": "01000101|00|1|Zm|111101|Zn|Zd"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "SVE CRYPTO_HASH", "ext": "SVE2_SM4", "data": [
|
||
|
|
{"inst": "sm4e Zdn.S, Zdn.S, Zm.S" , "op": "01000101|00|1|00011111000|Zm|Zdn"},
|
||
|
|
{"inst": "sm4ekey Zd.S, Zn.S, Zm.S" , "op": "01000101|00|1|Zm|111100|Zn|Zd"}
|
||
|
|
]},
|
||
|
|
|
||
|
|
{"category": "SME", "ext": "SME", "data": [
|
||
|
|
{"inst": "smstart {#sme_mode=1}" , "op": "11010101|00|000011|0100|0|op:2|1|011|11111" , "imm": "ImmSMEMode(sme_mode)"},
|
||
|
|
{"inst": "smstop {#sme_mode=1}" , "op": "11010101|00|000011|0100|0|op:2|0|011|11111" , "imm": "ImmSMEMode(sme_mode)"}
|
||
|
|
]}
|
||
|
|
]
|
||
|
|
}
|