878 lines
21 KiB
C++
878 lines
21 KiB
C++
// This file is part of AsmJit project <https://asmjit.com>
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//
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// See asmjit.h or LICENSE.md for license and copyright information
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// SPDX-License-Identifier: Zlib
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#ifndef ASMJIT_ARM_A64INSTDB_H_P_INCLUDED
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#define ASMJIT_ARM_A64INSTDB_H_P_INCLUDED
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#include "../core/codeholder.h"
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#include "../arm/a64instdb.h"
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#include "../arm/a64operand.h"
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ASMJIT_BEGIN_SUB_NAMESPACE(a64)
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//! \cond INTERNAL
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//! \addtogroup asmjit_a64
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//! \{
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namespace InstDB {
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// a64::InstDB - Constants Used by Instructions
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// ============================================
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// GP register types supported by base instructions.
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static constexpr uint32_t kW = 0x1;
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static constexpr uint32_t kX = 0x2;
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static constexpr uint32_t kWX = 0x3;
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// GP high register IDs supported by the instruction.
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static constexpr uint32_t kZR = Gp::kIdZr;
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static constexpr uint32_t kSP = Gp::kIdSp;
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// a64::InstDB - RWInfo
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// ====================
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enum RWInfoType : uint32_t {
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kRWI_R,
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kRWI_RW,
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kRWI_RX,
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kRWI_RRW,
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kRWI_RWX,
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kRWI_W,
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kRWI_WRW,
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kRWI_WRX,
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kRWI_WRRW,
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kRWI_WRRX,
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kRWI_WW,
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kRWI_X,
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kRWI_XRX,
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kRWI_XXRRX,
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kRWI_LDn,
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kRWI_STn,
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kRWI_SpecialStart = kRWI_LDn
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};
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// a64::InstDB - ElementType
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// =========================
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enum ElementType : uint8_t {
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kET_None = Vec::kElementTypeNone,
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kET_B = Vec::kElementTypeB,
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kET_H = Vec::kElementTypeH,
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kET_S = Vec::kElementTypeS,
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kET_D = Vec::kElementTypeD,
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kET_2H = Vec::kElementTypeH2,
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kET_4B = Vec::kElementTypeB4
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};
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// a64::InstDB - GpType
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// ====================
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enum GpType : uint8_t {
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kGp_W,
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kGp_X,
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kGp_X_SP
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};
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// a64::InstDB - OPSig
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// ===================
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enum kOpSignature : uint32_t {
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kOp_GpW = GpW::kSignature,
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kOp_GpX = GpX::kSignature,
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kOp_B = VecB::kSignature,
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kOp_H = VecH::kSignature,
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kOp_S = VecS::kSignature,
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kOp_D = VecD::kSignature,
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kOp_Q = VecV::kSignature,
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kOp_V8B = VecD::kSignature | Vec::kSignatureElementB,
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kOp_V4H = VecD::kSignature | Vec::kSignatureElementH,
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kOp_V2S = VecD::kSignature | Vec::kSignatureElementS,
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kOp_V16B = VecV::kSignature | Vec::kSignatureElementB,
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kOp_V8H = VecV::kSignature | Vec::kSignatureElementH,
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kOp_V4S = VecV::kSignature | Vec::kSignatureElementS,
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kOp_V2D = VecV::kSignature | Vec::kSignatureElementD
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};
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// a64::InstDB - HFConv
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// ====================
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enum kHFConv : uint32_t {
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//! FP16 version of the instruction is not available.
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kHF_N,
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//! Doesn't do any change to the opcode.
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kHF_0,
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kHF_A,
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kHF_B,
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kHF_C,
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kHF_D,
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kHF_Count
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};
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// a64::InstDB - VOType
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// ====================
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//! Vector operand type combinations used by FP&SIMD instructions.
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enum VOType : uint32_t {
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kVO_V_B,
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kVO_V_BH,
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kVO_V_BH_4S,
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kVO_V_BHS,
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kVO_V_BHS_D2,
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kVO_V_HS,
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kVO_V_S,
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kVO_V_B8H4,
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kVO_V_B8H4S2,
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kVO_V_B8D1,
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kVO_V_H4S2,
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kVO_V_B16,
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kVO_V_B16H8,
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kVO_V_B16H8S4,
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kVO_V_B16D2,
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kVO_V_H8S4,
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kVO_V_S4,
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kVO_V_D2,
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kVO_SV_BHS,
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kVO_SV_B8H4S2,
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kVO_SV_HS,
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kVO_V_Any,
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kVO_SV_Any,
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kVO_Count
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};
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// a64::InstDB - EncodingId
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// ========================
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// ${EncodingId:Begin}
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// ------------------- Automatically generated, do not edit -------------------
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enum EncodingId : uint32_t {
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kEncodingNone = 0,
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kEncodingBaseAddSub,
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kEncodingBaseAdr,
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kEncodingBaseAtDcIcTlbi,
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kEncodingBaseAtomicCasp,
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kEncodingBaseAtomicOp,
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kEncodingBaseAtomicSt,
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kEncodingBaseBfc,
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kEncodingBaseBfi,
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kEncodingBaseBfm,
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kEncodingBaseBfx,
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kEncodingBaseBranchCmp,
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kEncodingBaseBranchReg,
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kEncodingBaseBranchRel,
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kEncodingBaseBranchTst,
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kEncodingBaseCCmp,
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kEncodingBaseCInc,
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kEncodingBaseCSel,
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kEncodingBaseCSet,
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kEncodingBaseCmpCmn,
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kEncodingBaseExtend,
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kEncodingBaseExtract,
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kEncodingBaseLdSt,
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kEncodingBaseLdpStp,
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kEncodingBaseLdxp,
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kEncodingBaseLogical,
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kEncodingBaseMov,
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kEncodingBaseMovKNZ,
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kEncodingBaseMrs,
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kEncodingBaseMsr,
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kEncodingBaseMvnNeg,
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kEncodingBaseOp,
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kEncodingBaseOpImm,
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kEncodingBaseR,
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kEncodingBaseRM_NoImm,
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kEncodingBaseRM_SImm10,
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kEncodingBaseRM_SImm9,
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kEncodingBaseRR,
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kEncodingBaseRRII,
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kEncodingBaseRRR,
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kEncodingBaseRRRR,
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kEncodingBaseRev,
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kEncodingBaseShift,
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kEncodingBaseStx,
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kEncodingBaseStxp,
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kEncodingBaseSys,
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kEncodingBaseTst,
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kEncodingFSimdPair,
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kEncodingFSimdSV,
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kEncodingFSimdVV,
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kEncodingFSimdVVV,
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kEncodingFSimdVVVV,
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kEncodingFSimdVVVe,
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kEncodingISimdPair,
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kEncodingISimdSV,
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kEncodingISimdVV,
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kEncodingISimdVVV,
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kEncodingISimdVVVI,
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kEncodingISimdVVVV,
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kEncodingISimdVVVVx,
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kEncodingISimdVVVe,
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kEncodingISimdVVVx,
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kEncodingISimdVVx,
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kEncodingISimdWWV,
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kEncodingSimdBicOrr,
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kEncodingSimdCmp,
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kEncodingSimdDot,
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kEncodingSimdDup,
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kEncodingSimdFcadd,
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kEncodingSimdFccmpFccmpe,
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kEncodingSimdFcm,
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kEncodingSimdFcmla,
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kEncodingSimdFcmpFcmpe,
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kEncodingSimdFcsel,
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kEncodingSimdFcvt,
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kEncodingSimdFcvtLN,
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kEncodingSimdFcvtSV,
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kEncodingSimdFmlal,
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kEncodingSimdFmov,
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kEncodingSimdIns,
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kEncodingSimdLdNStN,
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kEncodingSimdLdSt,
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kEncodingSimdLdpStp,
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kEncodingSimdLdurStur,
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kEncodingSimdMov,
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kEncodingSimdMoviMvni,
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kEncodingSimdShift,
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kEncodingSimdShiftES,
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kEncodingSimdSm3tt,
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kEncodingSimdSmovUmov,
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kEncodingSimdSxtlUxtl,
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kEncodingSimdTblTbx
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};
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// ----------------------------------------------------------------------------
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// ${EncodingId:End}
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// a64::InstDB::EncodingData
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// =========================
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namespace EncodingData {
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#define M_OPCODE(field, bits) \
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uint32_t _##field : bits; \
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inline constexpr uint32_t field() const noexcept { return uint32_t(_##field) << (32 - bits); }
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struct BaseOp {
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uint32_t opcode;
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};
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struct BaseOpImm {
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uint32_t opcode;
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uint16_t immBits;
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uint16_t immOffset;
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};
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struct BaseR {
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uint32_t opcode;
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uint32_t rType : 8;
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uint32_t rHiId : 8;
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uint32_t rShift : 8;
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};
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struct BaseRR {
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uint32_t opcode;
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uint32_t aType : 2;
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uint32_t aHiId : 6;
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uint32_t aShift : 5;
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uint32_t bType : 2;
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uint32_t bHiId : 6;
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uint32_t bShift : 5;
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uint32_t uniform : 1;
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};
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struct BaseRRR {
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M_OPCODE(opcode, 22)
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uint32_t aType : 2;
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uint32_t aHiId : 6;
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uint32_t bType : 2;
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uint32_t bHiId : 6;
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uint32_t cType : 2;
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uint32_t cHiId : 6;
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uint32_t uniform : 1;
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};
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struct BaseRRRR {
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M_OPCODE(opcode, 22)
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uint32_t aType : 2;
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uint32_t aHiId : 6;
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uint32_t bType : 2;
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uint32_t bHiId : 6;
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uint32_t cType : 2;
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uint32_t cHiId : 6;
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uint32_t dType : 2;
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uint32_t dHiId : 6;
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uint32_t uniform : 1;
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};
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struct BaseRRII {
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M_OPCODE(opcode, 22)
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uint32_t aType : 2;
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uint32_t aHiId : 6;
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uint32_t bType : 2;
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uint32_t bHiId : 6;
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uint32_t aImmSize : 6;
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uint32_t aImmDiscardLsb : 5;
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uint32_t aImmOffset : 5;
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uint32_t bImmSize : 6;
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uint32_t bImmDiscardLsb : 5;
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uint32_t bImmOffset : 5;
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};
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struct BaseAtDcIcTlbi {
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uint32_t immVerifyMask : 14;
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uint32_t immVerifyData : 14;
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uint32_t mandatoryReg : 1;
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};
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struct BaseAdcSbc {
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uint32_t opcode;
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};
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struct BaseAddSub {
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uint32_t shiftedOp : 10; // sf|.......|Sh|.|Rm| Imm:6 |Rn|Rd|
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uint32_t extendedOp : 10; // sf|.......|..|.|Rm|Opt|Imm3|Rn|Rd|
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uint32_t immediateOp: 10; // sf|.......|Sh| Imm:12 |Rn|Rd|
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};
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struct BaseAdr {
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M_OPCODE(opcode, 22)
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OffsetType offsetType : 8;
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};
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struct BaseBfm {
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uint32_t opcode; // sf|........|N|ImmR:6|ImmS:6|Rn|Rd|
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};
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struct BaseCmpCmn {
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uint32_t shiftedOp : 10; // sf|.......|Sh|.|Rm| Imm:6 |Rn|11111|
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uint32_t extendedOp : 10; // sf|.......|..|.|Rm|Opt|Imm3|Rn|11111|
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uint32_t immediateOp: 10; // sf|.......|Sh| Imm:12 |Rn|11111|
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};
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struct BaseExtend {
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M_OPCODE(opcode, 22) // sf|........|N|......|......|Rn|Rd|
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uint32_t rType : 2;
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uint32_t u : 1;
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};
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struct BaseLogical {
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uint32_t shiftedOp : 10; // sf|.......|Sh|.|Rm| Imm:6 |Rn|Rd|
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uint32_t immediateOp: 10; // sf|........|N|ImmR:6|ImmS:6|Rn|Rd|
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uint32_t negateImm : 1 ; // True if this is an operation that must negate IMM.
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};
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struct BaseMvnNeg {
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uint32_t opcode;
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};
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struct BaseShift {
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M_OPCODE(registerOp, 22)
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M_OPCODE(immediateOp, 22)
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uint32_t ror : 2;
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};
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struct BaseTst {
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uint32_t shiftedOp : 10; // sf|.......|Sh|.|Rm| Imm:6 |Rn|11111|
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uint32_t immediateOp: 10; // sf|........|N|ImmR:6|ImmS:6|Rn|11111|
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};
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struct BaseRM_NoImm {
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M_OPCODE(opcode, 22)
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uint32_t rType : 2;
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uint32_t rHiId : 6;
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uint32_t xOffset : 5;
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};
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struct BaseRM_SImm9 {
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M_OPCODE(offsetOp, 22)
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M_OPCODE(prePostOp, 22)
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uint32_t rType : 2;
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uint32_t rHiId : 6;
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uint32_t xOffset : 5;
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uint32_t immShift : 4;
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};
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struct BaseRM_SImm10 {
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M_OPCODE(opcode, 22)
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uint32_t rType : 2;
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uint32_t rHiId : 6;
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uint32_t xOffset : 5;
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uint32_t immShift : 4;
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};
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struct BaseLdSt {
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uint32_t uOffsetOp : 10;
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uint32_t prePostOp : 11;
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uint32_t registerOp : 11;
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uint32_t literalOp : 8;
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uint32_t rType : 2;
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uint32_t xOffset : 5;
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uint32_t uOffsetShift : 3;
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uint32_t uAltInstId : 14;
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};
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struct BaseLdpStp {
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uint32_t offsetOp : 10;
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uint32_t prePostOp : 10;
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uint32_t rType : 2;
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uint32_t xOffset : 5;
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uint32_t offsetShift : 3;
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};
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struct BaseStx {
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M_OPCODE(opcode, 22)
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uint32_t rType : 2;
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uint32_t xOffset : 5;
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};
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struct BaseLdxp {
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M_OPCODE(opcode, 22)
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uint32_t rType : 2;
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uint32_t xOffset : 5;
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};
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struct BaseStxp {
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M_OPCODE(opcode, 22)
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uint32_t rType : 2;
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uint32_t xOffset : 5;
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};
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struct BaseAtomicOp {
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M_OPCODE(opcode, 22)
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uint32_t rType : 2;
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uint32_t xOffset : 5;
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uint32_t zr : 1;
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};
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struct BaseAtomicSt {
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M_OPCODE(opcode, 22)
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uint32_t rType : 2;
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uint32_t xOffset : 5;
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};
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struct BaseAtomicCasp {
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M_OPCODE(opcode, 22)
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uint32_t rType : 2;
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uint32_t xOffset : 5;
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};
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typedef BaseOp BaseBranchReg;
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typedef BaseOp BaseBranchRel;
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typedef BaseOp BaseBranchCmp;
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typedef BaseOp BaseBranchTst;
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typedef BaseOp BaseExtract;
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typedef BaseOp BaseBfc;
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typedef BaseOp BaseBfi;
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typedef BaseOp BaseBfx;
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typedef BaseOp BaseCCmp;
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typedef BaseOp BaseCInc;
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typedef BaseOp BaseCSet;
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typedef BaseOp BaseCSel;
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typedef BaseOp BaseMovKNZ;
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typedef BaseOp BaseMull;
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struct FSimdGeneric {
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uint32_t _scalarOp : 28;
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uint32_t _scalarHf : 4;
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uint32_t _vectorOp : 28;
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uint32_t _vectorHf : 4;
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constexpr uint32_t scalarOp() const noexcept { return uint32_t(_scalarOp) << 10; }
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constexpr uint32_t vectorOp() const noexcept { return uint32_t(_vectorOp) << 10; }
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constexpr uint32_t scalarHf() const noexcept { return uint32_t(_scalarHf); }
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constexpr uint32_t vectorHf() const noexcept { return uint32_t(_vectorHf); }
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};
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typedef FSimdGeneric FSimdVV;
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typedef FSimdGeneric FSimdVVV;
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typedef FSimdGeneric FSimdVVVV;
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struct FSimdSV {
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uint32_t opcode;
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};
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struct FSimdVVVe {
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uint32_t _scalarOp : 28;
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uint32_t _scalarHf : 4;
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uint32_t _vectorOp;
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uint32_t _elementOp;
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constexpr uint32_t scalarOp() const noexcept { return uint32_t(_scalarOp) << 10; }
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constexpr uint32_t scalarHf() const noexcept { return uint32_t(_scalarHf); };
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constexpr uint32_t vectorOp() const noexcept { return uint32_t(_vectorOp) << 10; }
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constexpr uint32_t vectorHf() const noexcept { return kHF_C; }
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constexpr uint32_t elementScalarOp() const noexcept { return (uint32_t(_elementOp) << 10) | (0x5u << 28); }
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constexpr uint32_t elementVectorOp() const noexcept { return (uint32_t(_elementOp) << 10); }
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};
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struct SimdFcadd {
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uint32_t _opcode;
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constexpr uint32_t opcode() const noexcept { return _opcode << 10; }
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};
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struct SimdFcmla {
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uint32_t _regularOp;
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uint32_t _elementOp;
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constexpr uint32_t regularOp() const noexcept { return uint32_t(_regularOp) << 10; }
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constexpr uint32_t elementOp() const noexcept { return (uint32_t(_elementOp) << 10); }
|
|
};
|
|
|
|
struct SimdFccmpFccmpe {
|
|
uint32_t _opcode;
|
|
constexpr uint32_t opcode() const noexcept { return _opcode; }
|
|
};
|
|
|
|
struct SimdFcm {
|
|
uint32_t _registerOp : 28;
|
|
uint32_t _registerHf : 4;
|
|
|
|
uint32_t _zeroOp : 28;
|
|
|
|
constexpr bool hasRegisterOp() const noexcept { return _registerOp != 0; }
|
|
constexpr bool hasZeroOp() const noexcept { return _zeroOp != 0; }
|
|
|
|
constexpr uint32_t registerScalarOp() const noexcept { return (uint32_t(_registerOp) << 10) | (0x5u << 28); }
|
|
constexpr uint32_t registerVectorOp() const noexcept { return uint32_t(_registerOp) << 10; }
|
|
constexpr uint32_t registerScalarHf() const noexcept { return uint32_t(_registerHf); }
|
|
constexpr uint32_t registerVectorHf() const noexcept { return uint32_t(_registerHf); }
|
|
|
|
constexpr uint32_t zeroScalarOp() const noexcept { return (uint32_t(_zeroOp) << 10) | (0x5u << 28); }
|
|
constexpr uint32_t zeroVectorOp() const noexcept { return (uint32_t(_zeroOp) << 10); }
|
|
};
|
|
|
|
struct SimdFcmpFcmpe {
|
|
uint32_t _opcode;
|
|
constexpr uint32_t opcode() const noexcept { return _opcode; }
|
|
};
|
|
|
|
struct SimdFcvtLN {
|
|
uint32_t _opcode : 22;
|
|
uint32_t _isCvtxn : 1;
|
|
uint32_t _hasScalar : 1;
|
|
|
|
constexpr uint32_t scalarOp() const noexcept { return (uint32_t(_opcode) << 10) | (0x5u << 28); }
|
|
constexpr uint32_t vectorOp() const noexcept { return (uint32_t(_opcode) << 10); }
|
|
|
|
constexpr uint32_t isCvtxn() const noexcept { return _isCvtxn; }
|
|
constexpr uint32_t hasScalar() const noexcept { return _hasScalar; }
|
|
};
|
|
|
|
struct SimdFcvtSV {
|
|
uint32_t _vectorIntOp;
|
|
uint32_t _vectorFpOp;
|
|
uint32_t _generalOp : 31;
|
|
uint32_t _isFloatToInt : 1;
|
|
|
|
constexpr uint32_t scalarIntOp() const noexcept { return (uint32_t(_vectorIntOp) << 10) | (0x5u << 28); }
|
|
constexpr uint32_t vectorIntOp() const noexcept { return uint32_t(_vectorIntOp) << 10; }
|
|
constexpr uint32_t scalarFpOp() const noexcept { return (uint32_t(_vectorFpOp) << 10) | (0x5u << 28); }
|
|
constexpr uint32_t vectorFpOp() const noexcept { return uint32_t(_vectorFpOp) << 10; }
|
|
constexpr uint32_t generalOp() const noexcept { return (uint32_t(_generalOp) << 10); }
|
|
|
|
constexpr uint32_t isFloatToInt() const noexcept { return _isFloatToInt; }
|
|
constexpr uint32_t isFixedPoint() const noexcept { return _vectorFpOp != 0; }
|
|
};
|
|
|
|
struct SimdFmlal {
|
|
uint32_t _vectorOp;
|
|
uint32_t _elementOp;
|
|
uint8_t _optionalQ;
|
|
uint8_t tA;
|
|
uint8_t tB;
|
|
uint8_t tElement;
|
|
|
|
constexpr uint32_t vectorOp() const noexcept { return uint32_t(_vectorOp) << 10; }
|
|
constexpr uint32_t elementOp() const noexcept { return uint32_t(_elementOp) << 10; }
|
|
constexpr uint32_t optionalQ() const noexcept { return _optionalQ; }
|
|
};
|
|
|
|
struct FSimdPair {
|
|
uint32_t _scalarOp;
|
|
uint32_t _vectorOp;
|
|
|
|
constexpr uint32_t scalarOp() const noexcept { return uint32_t(_scalarOp) << 10; }
|
|
constexpr uint32_t vectorOp() const noexcept { return uint32_t(_vectorOp) << 10; }
|
|
};
|
|
|
|
struct ISimdVV {
|
|
M_OPCODE(opcode, 22)
|
|
uint32_t vecOpType : 6;
|
|
};
|
|
|
|
struct ISimdVVx {
|
|
M_OPCODE(opcode, 22)
|
|
uint32_t op0Signature;
|
|
uint32_t op1Signature;
|
|
};
|
|
|
|
struct ISimdSV {
|
|
M_OPCODE(opcode, 22)
|
|
uint32_t vecOpType : 6;
|
|
};
|
|
|
|
struct ISimdVVV {
|
|
M_OPCODE(opcode, 22)
|
|
uint32_t vecOpType : 6;
|
|
};
|
|
|
|
struct ISimdVVVx {
|
|
M_OPCODE(opcode, 22)
|
|
uint32_t op0Signature;
|
|
uint32_t op1Signature;
|
|
uint32_t op2Signature;
|
|
};
|
|
|
|
struct ISimdWWV {
|
|
M_OPCODE(opcode, 22)
|
|
uint32_t vecOpType : 6;
|
|
};
|
|
|
|
struct ISimdVVVe {
|
|
uint32_t regularOp : 26; // 22 bits used.
|
|
uint32_t regularVecType : 6;
|
|
uint32_t elementOp : 26; // 22 bits used.
|
|
uint32_t elementVecType : 6;
|
|
};
|
|
|
|
struct ISimdVVVI {
|
|
M_OPCODE(opcode, 22)
|
|
uint32_t vecOpType : 6;
|
|
uint32_t immSize : 4;
|
|
uint32_t immShift : 4;
|
|
uint32_t imm64HasOneBitLess : 1;
|
|
};
|
|
|
|
struct ISimdVVVV {
|
|
uint32_t opcode : 22;
|
|
uint32_t vecOpType : 6;
|
|
};
|
|
|
|
struct ISimdVVVVx {
|
|
uint32_t opcode;
|
|
uint32_t op0Signature;
|
|
uint32_t op1Signature;
|
|
uint32_t op2Signature;
|
|
uint32_t op3Signature;
|
|
};
|
|
|
|
struct SimdBicOrr {
|
|
uint32_t registerOp; // 22 bits used.
|
|
uint32_t immediateOp; // 22 bits used.
|
|
};
|
|
|
|
struct SimdCmp {
|
|
uint32_t regOp;
|
|
uint32_t zeroOp : 22;
|
|
uint32_t vecOpType : 6;
|
|
};
|
|
|
|
struct SimdDot {
|
|
uint32_t vectorOp; // 22 bits used.
|
|
uint32_t elementOp; // 22 bits used.
|
|
uint8_t tA; // Element-type of the first operand.
|
|
uint8_t tB; // Element-type of the second and third operands.
|
|
uint8_t tElement; // Element-type of the element index[] operand.
|
|
};
|
|
|
|
struct SimdMoviMvni {
|
|
uint32_t opcode : 31;
|
|
uint32_t inverted : 1;
|
|
};
|
|
|
|
struct SimdLdSt {
|
|
uint32_t uOffsetOp : 10;
|
|
uint32_t prePostOp : 11;
|
|
uint32_t registerOp : 11;
|
|
uint32_t literalOp : 8;
|
|
uint32_t uAltInstId : 16;
|
|
};
|
|
|
|
struct SimdLdNStN {
|
|
uint32_t singleOp;
|
|
uint32_t multipleOp : 22;
|
|
uint32_t n : 3;
|
|
uint32_t replicate : 1;
|
|
};
|
|
|
|
struct SimdLdpStp {
|
|
uint32_t offsetOp : 10;
|
|
uint32_t prePostOp : 10;
|
|
};
|
|
|
|
struct SimdLdurStur {
|
|
uint32_t opcode;
|
|
};
|
|
|
|
struct ISimdPair {
|
|
uint32_t opcode2; // 22 bits used.
|
|
uint32_t opcode3 : 26; // 22 bits used.
|
|
uint32_t opType3 : 6;
|
|
};
|
|
|
|
struct SimdShift {
|
|
uint32_t registerOp; // 22 bits used.
|
|
uint32_t immediateOp : 22; // 22 bits used.
|
|
uint32_t invertedImm : 1;
|
|
uint32_t vecOpType : 6;
|
|
};
|
|
|
|
struct SimdShiftES {
|
|
uint32_t opcode : 22;
|
|
uint32_t vecOpType : 6;
|
|
};
|
|
|
|
struct SimdSm3tt {
|
|
uint32_t opcode;
|
|
};
|
|
|
|
struct SimdSmovUmov {
|
|
uint32_t opcode : 22;
|
|
uint32_t vecOpType : 6;
|
|
uint32_t isSigned : 1;
|
|
};
|
|
|
|
struct SimdSxtlUxtl {
|
|
uint32_t opcode : 22;
|
|
uint32_t vecOpType : 6;
|
|
};
|
|
|
|
struct SimdTblTbx {
|
|
uint32_t opcode;
|
|
};
|
|
|
|
#undef M_OPCODE
|
|
|
|
// ${EncodingDataForward:Begin}
|
|
// ------------------- Automatically generated, do not edit -------------------
|
|
extern const BaseAddSub baseAddSub[4];
|
|
extern const BaseAdr baseAdr[2];
|
|
extern const BaseAtDcIcTlbi baseAtDcIcTlbi[4];
|
|
extern const BaseAtomicCasp baseAtomicCasp[4];
|
|
extern const BaseAtomicOp baseAtomicOp[123];
|
|
extern const BaseAtomicSt baseAtomicSt[48];
|
|
extern const BaseBfc baseBfc[1];
|
|
extern const BaseBfi baseBfi[3];
|
|
extern const BaseBfm baseBfm[3];
|
|
extern const BaseBfx baseBfx[3];
|
|
extern const BaseBranchCmp baseBranchCmp[2];
|
|
extern const BaseBranchReg baseBranchReg[3];
|
|
extern const BaseBranchRel baseBranchRel[2];
|
|
extern const BaseBranchTst baseBranchTst[2];
|
|
extern const BaseCCmp baseCCmp[2];
|
|
extern const BaseCInc baseCInc[3];
|
|
extern const BaseCSel baseCSel[4];
|
|
extern const BaseCSet baseCSet[2];
|
|
extern const BaseCmpCmn baseCmpCmn[2];
|
|
extern const BaseExtend baseExtend[5];
|
|
extern const BaseExtract baseExtract[1];
|
|
extern const BaseLdSt baseLdSt[9];
|
|
extern const BaseLdpStp baseLdpStp[6];
|
|
extern const BaseLdxp baseLdxp[2];
|
|
extern const BaseLogical baseLogical[8];
|
|
extern const BaseMovKNZ baseMovKNZ[3];
|
|
extern const BaseMvnNeg baseMvnNeg[3];
|
|
extern const BaseOp baseOp[23];
|
|
extern const BaseOpImm baseOpImm[14];
|
|
extern const BaseR baseR[10];
|
|
extern const BaseRM_NoImm baseRM_NoImm[21];
|
|
extern const BaseRM_SImm10 baseRM_SImm10[2];
|
|
extern const BaseRM_SImm9 baseRM_SImm9[23];
|
|
extern const BaseRR baseRR[15];
|
|
extern const BaseRRII baseRRII[2];
|
|
extern const BaseRRR baseRRR[26];
|
|
extern const BaseRRRR baseRRRR[6];
|
|
extern const BaseShift baseShift[8];
|
|
extern const BaseStx baseStx[3];
|
|
extern const BaseStxp baseStxp[2];
|
|
extern const BaseTst baseTst[1];
|
|
extern const FSimdPair fSimdPair[5];
|
|
extern const FSimdSV fSimdSV[4];
|
|
extern const FSimdVV fSimdVV[17];
|
|
extern const FSimdVVV fSimdVVV[13];
|
|
extern const FSimdVVVV fSimdVVVV[4];
|
|
extern const FSimdVVVe fSimdVVVe[4];
|
|
extern const ISimdPair iSimdPair[1];
|
|
extern const ISimdSV iSimdSV[7];
|
|
extern const ISimdVV iSimdVV[29];
|
|
extern const ISimdVVV iSimdVVV[65];
|
|
extern const ISimdVVVI iSimdVVVI[2];
|
|
extern const ISimdVVVV iSimdVVVV[2];
|
|
extern const ISimdVVVVx iSimdVVVVx[1];
|
|
extern const ISimdVVVe iSimdVVVe[25];
|
|
extern const ISimdVVVx iSimdVVVx[17];
|
|
extern const ISimdVVx iSimdVVx[13];
|
|
extern const ISimdWWV iSimdWWV[8];
|
|
extern const SimdBicOrr simdBicOrr[2];
|
|
extern const SimdCmp simdCmp[7];
|
|
extern const SimdDot simdDot[5];
|
|
extern const SimdFcadd simdFcadd[1];
|
|
extern const SimdFccmpFccmpe simdFccmpFccmpe[2];
|
|
extern const SimdFcm simdFcm[5];
|
|
extern const SimdFcmla simdFcmla[1];
|
|
extern const SimdFcmpFcmpe simdFcmpFcmpe[2];
|
|
extern const SimdFcvtLN simdFcvtLN[6];
|
|
extern const SimdFcvtSV simdFcvtSV[12];
|
|
extern const SimdFmlal simdFmlal[6];
|
|
extern const SimdLdNStN simdLdNStN[12];
|
|
extern const SimdLdSt simdLdSt[2];
|
|
extern const SimdLdpStp simdLdpStp[4];
|
|
extern const SimdLdurStur simdLdurStur[2];
|
|
extern const SimdMoviMvni simdMoviMvni[2];
|
|
extern const SimdShift simdShift[40];
|
|
extern const SimdShiftES simdShiftES[2];
|
|
extern const SimdSm3tt simdSm3tt[4];
|
|
extern const SimdSmovUmov simdSmovUmov[2];
|
|
extern const SimdSxtlUxtl simdSxtlUxtl[4];
|
|
extern const SimdTblTbx simdTblTbx[2];
|
|
// ----------------------------------------------------------------------------
|
|
// ${EncodingDataForward:End}
|
|
|
|
} // {EncodingData}
|
|
|
|
// a64::InstDB - InstNameIndex
|
|
// ===========================
|
|
|
|
// ${NameLimits:Begin}
|
|
// ------------------- Automatically generated, do not edit -------------------
|
|
enum : uint32_t { kMaxNameSize = 9 };
|
|
// ----------------------------------------------------------------------------
|
|
// ${NameLimits:End}
|
|
|
|
struct InstNameIndex {
|
|
uint16_t start;
|
|
uint16_t end;
|
|
};
|
|
|
|
// a64::InstDB - Tables
|
|
// ====================
|
|
|
|
#ifndef ASMJIT_NO_TEXT
|
|
extern const uint32_t _instNameIndexTable[];
|
|
extern const char _instNameStringTable[];
|
|
extern const InstNameIndex instNameIndex[26];
|
|
#endif // !ASMJIT_NO_TEXT
|
|
|
|
} // {InstDB}
|
|
|
|
//! \}
|
|
//! \endcond
|
|
|
|
ASMJIT_END_SUB_NAMESPACE
|
|
|
|
#endif // ASMJIT_A64_ARMINSTDB_H_P_INCLUDED
|
|
|