1167 lines
41 KiB
C++
1167 lines
41 KiB
C++
// This file is part of AsmJit project <https://asmjit.com>
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//
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// See asmjit.h or LICENSE.md for license and copyright information
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// SPDX-License-Identifier: Zlib
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#include "../core/api-build_p.h"
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#ifndef ASMJIT_NO_COMPILER
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#include "../core/ralocal_p.h"
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#include "../core/support.h"
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ASMJIT_BEGIN_NAMESPACE
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// RALocalAllocator - Utilities
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// ============================
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static ASMJIT_FORCE_INLINE RATiedReg* RALocal_findTiedRegByWorkId(RATiedReg* tiedRegs, size_t count, uint32_t workId) noexcept {
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for (size_t i = 0; i < count; i++)
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if (tiedRegs[i].workId() == workId)
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return &tiedRegs[i];
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return nullptr;
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}
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// RALocalAllocator - Init & Reset
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// ===============================
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Error RALocalAllocator::init() noexcept {
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PhysToWorkMap* physToWorkMap;
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WorkToPhysMap* workToPhysMap;
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physToWorkMap = _pass->newPhysToWorkMap();
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workToPhysMap = _pass->newWorkToPhysMap();
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if (!physToWorkMap || !workToPhysMap)
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return DebugUtils::errored(kErrorOutOfMemory);
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_curAssignment.initLayout(_pass->_physRegCount, _pass->workRegs());
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_curAssignment.initMaps(physToWorkMap, workToPhysMap);
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physToWorkMap = _pass->newPhysToWorkMap();
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workToPhysMap = _pass->newWorkToPhysMap();
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_tmpWorkToPhysMap = _pass->newWorkToPhysMap();
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if (!physToWorkMap || !workToPhysMap || !_tmpWorkToPhysMap)
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return DebugUtils::errored(kErrorOutOfMemory);
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_tmpAssignment.initLayout(_pass->_physRegCount, _pass->workRegs());
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_tmpAssignment.initMaps(physToWorkMap, workToPhysMap);
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return kErrorOk;
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}
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// RALocalAllocator - Assignment
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// =============================
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Error RALocalAllocator::makeInitialAssignment() noexcept {
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FuncNode* func = _pass->func();
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RABlock* entry = _pass->entryBlock();
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ZoneBitVector& liveIn = entry->liveIn();
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uint32_t argCount = func->argCount();
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uint32_t numIter = 1;
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for (uint32_t iter = 0; iter < numIter; iter++) {
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for (uint32_t argIndex = 0; argIndex < argCount; argIndex++) {
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for (uint32_t valueIndex = 0; valueIndex < Globals::kMaxValuePack; valueIndex++) {
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// Unassigned argument.
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const RegOnly& regArg = func->argPack(argIndex)[valueIndex];
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if (!regArg.isReg() || !_cc->isVirtIdValid(regArg.id()))
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continue;
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VirtReg* virtReg = _cc->virtRegById(regArg.id());
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// Unreferenced argument.
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RAWorkReg* workReg = virtReg->workReg();
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if (!workReg)
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continue;
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// Overwritten argument.
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uint32_t workId = workReg->workId();
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if (!liveIn.bitAt(workId))
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continue;
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RegGroup group = workReg->group();
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if (_curAssignment.workToPhysId(group, workId) != RAAssignment::kPhysNone)
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continue;
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RegMask allocableRegs = _availableRegs[group] & ~_curAssignment.assigned(group);
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if (iter == 0) {
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// First iteration: Try to allocate to home RegId.
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if (workReg->hasHomeRegId()) {
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uint32_t physId = workReg->homeRegId();
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if (Support::bitTest(allocableRegs, physId)) {
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_curAssignment.assign(group, workId, physId, true);
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_pass->_argsAssignment.assignRegInPack(argIndex, valueIndex, workReg->type(), physId, workReg->typeId());
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continue;
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}
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}
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numIter = 2;
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}
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else {
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// Second iteration: Pick any other register if the is an unassigned one or assign to stack.
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if (allocableRegs) {
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uint32_t physId = Support::ctz(allocableRegs);
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_curAssignment.assign(group, workId, physId, true);
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_pass->_argsAssignment.assignRegInPack(argIndex, valueIndex, workReg->type(), physId, workReg->typeId());
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}
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else {
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// This register will definitely need stack, create the slot now and assign also `argIndex`
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// to it. We will patch `_argsAssignment` later after RAStackAllocator finishes.
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RAStackSlot* slot = _pass->getOrCreateStackSlot(workReg);
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if (ASMJIT_UNLIKELY(!slot))
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return DebugUtils::errored(kErrorOutOfMemory);
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// This means STACK_ARG may be moved to STACK.
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workReg->addFlags(RAWorkRegFlags::kStackArgToStack);
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_pass->_numStackArgsToStackSlots++;
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}
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}
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}
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}
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}
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return kErrorOk;
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}
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Error RALocalAllocator::replaceAssignment(const PhysToWorkMap* physToWorkMap) noexcept {
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_curAssignment.copyFrom(physToWorkMap);
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return kErrorOk;
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}
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Error RALocalAllocator::switchToAssignment(PhysToWorkMap* dstPhysToWorkMap, const ZoneBitVector& liveIn, bool dstReadOnly, bool tryMode) noexcept {
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RAAssignment dst;
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RAAssignment& cur = _curAssignment;
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dst.initLayout(_pass->_physRegCount, _pass->workRegs());
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dst.initMaps(dstPhysToWorkMap, _tmpWorkToPhysMap);
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dst.assignWorkIdsFromPhysIds();
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if (tryMode)
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return kErrorOk;
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for (RegGroup group : RegGroupVirtValues{}) {
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// STEP 1
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// ------
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//
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// - KILL all registers that are not live at `dst`,
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// - SPILL all registers that are not assigned at `dst`.
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if (!tryMode) {
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Support::BitWordIterator<RegMask> it(cur.assigned(group));
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while (it.hasNext()) {
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uint32_t physId = it.next();
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uint32_t workId = cur.physToWorkId(group, physId);
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// Must be true as we iterate over assigned registers.
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ASMJIT_ASSERT(workId != RAAssignment::kWorkNone);
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// KILL if it's not live on entry.
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if (!liveIn.bitAt(workId)) {
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onKillReg(group, workId, physId);
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continue;
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}
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// SPILL if it's not assigned on entry.
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uint32_t altId = dst.workToPhysId(group, workId);
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if (altId == RAAssignment::kPhysNone) {
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ASMJIT_PROPAGATE(onSpillReg(group, workId, physId));
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}
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}
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}
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// STEP 2
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// ------
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//
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// - MOVE and SWAP registers from their current assignments into their DST assignments.
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// - Build `willLoadRegs` mask of registers scheduled for `onLoadReg()`.
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// Current run-id (1 means more aggressive decisions).
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int32_t runId = -1;
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// Remaining registers scheduled for `onLoadReg()`.
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RegMask willLoadRegs = 0;
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// Remaining registers to be allocated in this loop.
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RegMask affectedRegs = dst.assigned(group);
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while (affectedRegs) {
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if (++runId == 2) {
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if (!tryMode)
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return DebugUtils::errored(kErrorInvalidState);
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// Stop in `tryMode` if we haven't done anything in past two rounds.
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break;
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}
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Support::BitWordIterator<RegMask> it(affectedRegs);
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while (it.hasNext()) {
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uint32_t physId = it.next();
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RegMask physMask = Support::bitMask<RegMask>(physId);
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uint32_t curWorkId = cur.physToWorkId(group, physId);
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uint32_t dstWorkId = dst.physToWorkId(group, physId);
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// The register must have assigned `dstWorkId` as we only iterate over assigned regs.
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ASMJIT_ASSERT(dstWorkId != RAAssignment::kWorkNone);
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if (curWorkId != RAAssignment::kWorkNone) {
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// Both assigned.
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if (curWorkId != dstWorkId) {
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// Wait a bit if this is the first run, we may avoid this if `curWorkId` moves out.
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if (runId <= 0)
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continue;
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uint32_t altPhysId = cur.workToPhysId(group, dstWorkId);
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if (altPhysId == RAAssignment::kPhysNone)
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continue;
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// Reset as we will do some changes to the current assignment.
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runId = -1;
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if (_archTraits->hasInstRegSwap(group)) {
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ASMJIT_PROPAGATE(onSwapReg(group, curWorkId, physId, dstWorkId, altPhysId));
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}
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else {
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// SPILL the reg if it's not dirty in DST, otherwise try to MOVE.
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if (!cur.isPhysDirty(group, physId)) {
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ASMJIT_PROPAGATE(onKillReg(group, curWorkId, physId));
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}
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else {
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RegMask allocableRegs = _pass->_availableRegs[group] & ~cur.assigned(group);
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// If possible don't conflict with assigned regs at DST.
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if (allocableRegs & ~dst.assigned(group))
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allocableRegs &= ~dst.assigned(group);
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if (allocableRegs) {
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// MOVE is possible, thus preferred.
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uint32_t tmpPhysId = Support::ctz(allocableRegs);
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ASMJIT_PROPAGATE(onMoveReg(group, curWorkId, tmpPhysId, physId));
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_pass->_clobberedRegs[group] |= Support::bitMask(tmpPhysId);
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}
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else {
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// MOVE is impossible, must SPILL.
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ASMJIT_PROPAGATE(onSpillReg(group, curWorkId, physId));
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}
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}
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goto Cleared;
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}
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}
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}
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else {
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Cleared:
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// DST assigned, CUR unassigned.
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uint32_t altPhysId = cur.workToPhysId(group, dstWorkId);
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if (altPhysId == RAAssignment::kPhysNone) {
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if (liveIn.bitAt(dstWorkId))
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willLoadRegs |= physMask; // Scheduled for `onLoadReg()`.
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affectedRegs &= ~physMask; // Unaffected from now.
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continue;
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}
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ASMJIT_PROPAGATE(onMoveReg(group, dstWorkId, physId, altPhysId));
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}
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// Both DST and CUR assigned to the same reg or CUR just moved to DST.
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if ((dst.dirty(group) & physMask) != (cur.dirty(group) & physMask)) {
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if ((dst.dirty(group) & physMask) == 0) {
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// CUR dirty, DST not dirty (the assert is just to visualize the condition).
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ASMJIT_ASSERT(!dst.isPhysDirty(group, physId) && cur.isPhysDirty(group, physId));
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// If `dstReadOnly` is true it means that that block was already processed and we cannot change from
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// CLEAN to DIRTY. In that case the register has to be saved as it cannot enter the block DIRTY.
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if (dstReadOnly)
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ASMJIT_PROPAGATE(onSaveReg(group, dstWorkId, physId));
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else
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dst.makeDirty(group, dstWorkId, physId);
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}
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else {
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// DST dirty, CUR not dirty (the assert is just to visualize the condition).
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ASMJIT_ASSERT(dst.isPhysDirty(group, physId) && !cur.isPhysDirty(group, physId));
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cur.makeDirty(group, dstWorkId, physId);
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}
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}
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// Must match now...
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ASMJIT_ASSERT(dst.physToWorkId(group, physId) == cur.physToWorkId(group, physId));
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ASMJIT_ASSERT(dst.isPhysDirty(group, physId) == cur.isPhysDirty(group, physId));
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runId = -1;
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affectedRegs &= ~physMask;
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}
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}
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// STEP 3
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// ------
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//
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// - Load registers specified by `willLoadRegs`.
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{
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Support::BitWordIterator<RegMask> it(willLoadRegs);
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while (it.hasNext()) {
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uint32_t physId = it.next();
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if (!cur.isPhysAssigned(group, physId)) {
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uint32_t workId = dst.physToWorkId(group, physId);
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// The algorithm is broken if it tries to load a register that is not in LIVE-IN.
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ASMJIT_ASSERT(liveIn.bitAt(workId) == true);
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ASMJIT_PROPAGATE(onLoadReg(group, workId, physId));
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if (dst.isPhysDirty(group, physId))
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cur.makeDirty(group, workId, physId);
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ASMJIT_ASSERT(dst.isPhysDirty(group, physId) == cur.isPhysDirty(group, physId));
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}
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else {
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// Not possible otherwise.
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ASMJIT_ASSERT(tryMode == true);
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}
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}
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}
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}
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if (!tryMode) {
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// Here is a code that dumps the conflicting part if something fails here:
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// if (!dst.equals(cur)) {
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// uint32_t physTotal = dst._layout.physTotal;
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// uint32_t workCount = dst._layout.workCount;
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//
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// fprintf(stderr, "Dirty DST=0x%08X CUR=0x%08X\n", dst.dirty(RegGroup::kGp), cur.dirty(RegGroup::kGp));
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// fprintf(stderr, "Assigned DST=0x%08X CUR=0x%08X\n", dst.assigned(RegGroup::kGp), cur.assigned(RegGroup::kGp));
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//
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// for (uint32_t physId = 0; physId < physTotal; physId++) {
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// uint32_t dstWorkId = dst._physToWorkMap->workIds[physId];
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// uint32_t curWorkId = cur._physToWorkMap->workIds[physId];
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// if (dstWorkId != curWorkId)
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// fprintf(stderr, "[PhysIdWork] PhysId=%u WorkId[DST(%u) != CUR(%u)]\n", physId, dstWorkId, curWorkId);
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// }
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//
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// for (uint32_t workId = 0; workId < workCount; workId++) {
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// uint32_t dstPhysId = dst._workToPhysMap->physIds[workId];
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// uint32_t curPhysId = cur._workToPhysMap->physIds[workId];
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// if (dstPhysId != curPhysId)
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// fprintf(stderr, "[WorkToPhys] WorkId=%u PhysId[DST(%u) != CUR(%u)]\n", workId, dstPhysId, curPhysId);
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// }
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// }
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ASMJIT_ASSERT(dst.equals(cur));
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}
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return kErrorOk;
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}
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Error RALocalAllocator::spillScratchGpRegsBeforeEntry(RegMask scratchRegs) noexcept {
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RegGroup group = RegGroup::kGp;
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Support::BitWordIterator<RegMask> it(scratchRegs);
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while (it.hasNext()) {
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uint32_t physId = it.next();
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if (_curAssignment.isPhysAssigned(group, physId)) {
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uint32_t workId = _curAssignment.physToWorkId(group, physId);
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ASMJIT_PROPAGATE(onSpillReg(group, workId, physId));
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}
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}
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return kErrorOk;
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}
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// RALocalAllocator - Allocation
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// =============================
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Error RALocalAllocator::allocInst(InstNode* node) noexcept {
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RAInst* raInst = node->passData<RAInst>();
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RATiedReg* outTiedRegs[Globals::kMaxPhysRegs];
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RATiedReg* dupTiedRegs[Globals::kMaxPhysRegs];
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RATiedReg* consecutiveRegs[kMaxConsecutiveRegs];
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// The cursor must point to the previous instruction for a possible instruction insertion.
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_cc->_setCursor(node->prev());
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_node = node;
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_raInst = raInst;
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_tiedTotal = raInst->_tiedTotal;
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_tiedCount = raInst->_tiedCount;
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// Whether we already replaced register operand with memory operand.
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bool rmAllocated = false;
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for (RegGroup group : RegGroupVirtValues{}) {
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uint32_t i, count = this->tiedCount(group);
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RATiedReg* tiedRegs = this->tiedRegs(group);
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RegMask willUse = _raInst->_usedRegs[group];
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RegMask willOut = _raInst->_clobberedRegs[group];
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RegMask willFree = 0;
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uint32_t usePending = count;
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uint32_t outTiedCount = 0;
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uint32_t dupTiedCount = 0;
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uint32_t consecutiveMask = 0;
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// STEP 1
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// ------
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//
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// Calculate `willUse` and `willFree` masks based on tied registers we have. In addition, aggregate information
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// regarding consecutive registers used by this instruction. We need that to make USE/OUT assignments.
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//
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// We don't do any assignment decisions at this stage as we just need to collect some information first. Then,
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// after we populate all masks needed we can finally make some decisions in the second loop. The main reason
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// for this is that we really need `willFree` to make assignment decisions for `willUse`, because if we mark
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// some registers that will be freed, we can consider them in decision making afterwards.
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for (i = 0; i < count; i++) {
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RATiedReg* tiedReg = &tiedRegs[i];
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if (tiedReg->hasAnyConsecutiveFlag()) {
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uint32_t consecutiveOffset = tiedReg->isLeadConsecutive() ? uint32_t(0) : tiedReg->consecutiveData();
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if (ASMJIT_UNLIKELY(Support::bitTest(consecutiveMask, consecutiveOffset)))
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return DebugUtils::errored(kErrorInvalidState);
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consecutiveMask |= Support::bitMask(consecutiveOffset);
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consecutiveRegs[consecutiveOffset] = tiedReg;
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}
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// Add OUT and KILL to `outPending` for CLOBBERing and/or OUT assignment.
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if (tiedReg->isOutOrKill())
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outTiedRegs[outTiedCount++] = tiedReg;
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if (tiedReg->isDuplicate())
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dupTiedRegs[dupTiedCount++] = tiedReg;
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if (!tiedReg->isUse()) {
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tiedReg->markUseDone();
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usePending--;
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continue;
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}
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// Don't assign anything here if this is a consecutive USE - we will handle this in STEP 2 instead.
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if (tiedReg->isUseConsecutive())
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continue;
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uint32_t workId = tiedReg->workId();
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uint32_t assignedId = _curAssignment.workToPhysId(group, workId);
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if (tiedReg->hasUseId()) {
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// If the register has `useId` it means it can only be allocated in that register.
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RegMask useMask = Support::bitMask(tiedReg->useId());
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// RAInstBuilder must have collected `usedRegs` on-the-fly.
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ASMJIT_ASSERT((willUse & useMask) != 0);
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if (assignedId == tiedReg->useId()) {
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// If the register is already allocated in this one, mark it done and continue.
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tiedReg->markUseDone();
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if (tiedReg->isWrite())
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_curAssignment.makeDirty(group, workId, assignedId);
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usePending--;
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willUse |= useMask;
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}
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else {
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willFree |= useMask & _curAssignment.assigned(group);
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}
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}
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else {
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// Check if the register must be moved to `allocableRegs`.
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RegMask allocableRegs = tiedReg->useRegMask();
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if (assignedId != RAAssignment::kPhysNone) {
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RegMask assignedMask = Support::bitMask(assignedId);
|
|
if ((allocableRegs & ~willUse) & assignedMask) {
|
|
tiedReg->setUseId(assignedId);
|
|
tiedReg->markUseDone();
|
|
if (tiedReg->isWrite())
|
|
_curAssignment.makeDirty(group, workId, assignedId);
|
|
usePending--;
|
|
willUse |= assignedMask;
|
|
}
|
|
else {
|
|
willFree |= assignedMask;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
// STEP 2
|
|
// ------
|
|
//
|
|
// Verify that all the consecutive registers are really consecutive. Terminate if there is a gap. In addition,
|
|
// decide which USE ids will be used in case that this consecutive sequence is USE (OUT registers are allocated
|
|
// in a different step).
|
|
uint32_t consecutiveCount = 0;
|
|
|
|
if (consecutiveMask) {
|
|
if ((consecutiveMask & (consecutiveMask + 1u)) != 0)
|
|
return DebugUtils::errored(kErrorInvalidState);
|
|
|
|
// Count of trailing ones is the count of consecutive registers. There cannot be gap.
|
|
consecutiveCount = Support::ctz(~consecutiveMask);
|
|
|
|
// Prioritize allocation that would result in least moves even when moving registers away from their homes.
|
|
RATiedReg* lead = consecutiveRegs[0];
|
|
|
|
// Assign the best possible USE Ids to all consecutives.
|
|
if (lead->isUseConsecutive()) {
|
|
uint32_t bestScore = 0;
|
|
uint32_t bestLeadReg = 0xFFFFFFFF;
|
|
RegMask allocableRegs = (_availableRegs[group] | willFree) & ~willUse;
|
|
|
|
uint32_t assignments[kMaxConsecutiveRegs];
|
|
|
|
for (i = 0; i < consecutiveCount; i++)
|
|
assignments[i] = _curAssignment.workToPhysId(group, consecutiveRegs[i]->workId());
|
|
|
|
Support::BitWordIterator<uint32_t> it(lead->useRegMask());
|
|
while (it.hasNext()) {
|
|
uint32_t regIndex = it.next();
|
|
if (Support::bitTest(lead->useRegMask(), regIndex)) {
|
|
uint32_t score = 15;
|
|
|
|
for (i = 0; i < consecutiveCount; i++) {
|
|
uint32_t consecutiveIndex = regIndex + i;
|
|
if (!Support::bitTest(allocableRegs, consecutiveIndex)) {
|
|
score = 0;
|
|
break;
|
|
}
|
|
|
|
RAWorkReg* workReg = workRegById(consecutiveRegs[i]->workId());
|
|
score += uint32_t(workReg->homeRegId() == consecutiveIndex);
|
|
score += uint32_t(assignments[i] == consecutiveIndex) * 2;
|
|
}
|
|
|
|
if (score > bestScore) {
|
|
bestScore = score;
|
|
bestLeadReg = regIndex;
|
|
}
|
|
}
|
|
}
|
|
|
|
if (bestLeadReg == 0xFFFFFFFF)
|
|
return DebugUtils::errored(kErrorConsecutiveRegsAllocation);
|
|
|
|
for (i = 0; i < consecutiveCount; i++) {
|
|
uint32_t consecutiveIndex = bestLeadReg + i;
|
|
|
|
RATiedReg* tiedReg = consecutiveRegs[i];
|
|
RegMask useMask = Support::bitMask(consecutiveIndex);
|
|
|
|
uint32_t workId = tiedReg->workId();
|
|
uint32_t assignedId = _curAssignment.workToPhysId(group, workId);
|
|
|
|
tiedReg->setUseId(consecutiveIndex);
|
|
|
|
if (assignedId == consecutiveIndex) {
|
|
// If the register is already allocated in this one, mark it done and continue.
|
|
tiedReg->markUseDone();
|
|
if (tiedReg->isWrite())
|
|
_curAssignment.makeDirty(group, workId, assignedId);
|
|
usePending--;
|
|
willUse |= useMask;
|
|
}
|
|
else {
|
|
willUse |= useMask;
|
|
willFree |= useMask & _curAssignment.assigned(group);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
// STEP 3
|
|
// ------
|
|
//
|
|
// Do some decision making to find the best candidates of registers that need to be assigned, moved, and/or
|
|
// spilled. Only USE registers are considered here, OUT will be decided later after all CLOBBERed and OUT
|
|
// registers are unassigned.
|
|
|
|
if (usePending) {
|
|
// TODO: Not sure `liveRegs` should be used, maybe willUse and willFree would be enough and much more clear.
|
|
|
|
// All registers that are currently alive without registers that will be freed.
|
|
RegMask liveRegs = _curAssignment.assigned(group) & ~willFree;
|
|
|
|
for (i = 0; i < count; i++) {
|
|
RATiedReg* tiedReg = &tiedRegs[i];
|
|
if (tiedReg->isUseDone())
|
|
continue;
|
|
|
|
uint32_t workId = tiedReg->workId();
|
|
uint32_t assignedId = _curAssignment.workToPhysId(group, workId);
|
|
|
|
// REG/MEM: Patch register operand to memory operand if not allocated.
|
|
if (!rmAllocated && tiedReg->hasUseRM()) {
|
|
if (assignedId == RAAssignment::kPhysNone && Support::isPowerOf2(tiedReg->useRewriteMask())) {
|
|
RAWorkReg* workReg = workRegById(tiedReg->workId());
|
|
uint32_t opIndex = Support::ctz(tiedReg->useRewriteMask()) / uint32_t(sizeof(Operand) / sizeof(uint32_t));
|
|
uint32_t rmSize = tiedReg->rmSize();
|
|
|
|
if (rmSize <= workReg->virtReg()->virtSize()) {
|
|
Operand& op = node->operands()[opIndex];
|
|
op = _pass->workRegAsMem(workReg);
|
|
op.as<BaseMem>().setSize(rmSize);
|
|
tiedReg->_useRewriteMask = 0;
|
|
|
|
tiedReg->markUseDone();
|
|
usePending--;
|
|
|
|
rmAllocated = true;
|
|
continue;
|
|
}
|
|
}
|
|
}
|
|
|
|
if (!tiedReg->hasUseId()) {
|
|
// DECIDE where to assign the USE register.
|
|
RegMask allocableRegs = tiedReg->useRegMask() & ~(willFree | willUse);
|
|
uint32_t useId = decideOnAssignment(group, workId, assignedId, allocableRegs);
|
|
|
|
RegMask useMask = Support::bitMask(useId);
|
|
willUse |= useMask;
|
|
willFree |= useMask & liveRegs;
|
|
tiedReg->setUseId(useId);
|
|
|
|
if (assignedId != RAAssignment::kPhysNone) {
|
|
RegMask assignedMask = Support::bitMask(assignedId);
|
|
|
|
willFree |= assignedMask;
|
|
liveRegs &= ~assignedMask;
|
|
|
|
// OPTIMIZATION: Assign the USE register here if it's possible.
|
|
if (!(liveRegs & useMask)) {
|
|
ASMJIT_PROPAGATE(onMoveReg(group, workId, useId, assignedId));
|
|
tiedReg->markUseDone();
|
|
if (tiedReg->isWrite())
|
|
_curAssignment.makeDirty(group, workId, useId);
|
|
usePending--;
|
|
}
|
|
}
|
|
else {
|
|
// OPTIMIZATION: Assign the USE register here if it's possible.
|
|
if (!(liveRegs & useMask)) {
|
|
ASMJIT_PROPAGATE(onLoadReg(group, workId, useId));
|
|
tiedReg->markUseDone();
|
|
if (tiedReg->isWrite())
|
|
_curAssignment.makeDirty(group, workId, useId);
|
|
usePending--;
|
|
}
|
|
}
|
|
|
|
liveRegs |= useMask;
|
|
}
|
|
}
|
|
}
|
|
|
|
// Initially all used regs will be marked as clobbered.
|
|
RegMask clobberedByInst = willUse | willOut;
|
|
|
|
// STEP 4
|
|
// ------
|
|
//
|
|
// Free all registers that we marked as `willFree`. Only registers that are not USEd by the instruction are
|
|
// considered as we don't want to free regs we need.
|
|
|
|
if (willFree) {
|
|
RegMask allocableRegs = _availableRegs[group] & ~(_curAssignment.assigned(group) | willFree | willUse | willOut);
|
|
Support::BitWordIterator<RegMask> it(willFree);
|
|
|
|
do {
|
|
uint32_t assignedId = it.next();
|
|
if (_curAssignment.isPhysAssigned(group, assignedId)) {
|
|
uint32_t workId = _curAssignment.physToWorkId(group, assignedId);
|
|
|
|
// DECIDE whether to MOVE or SPILL.
|
|
if (allocableRegs) {
|
|
uint32_t reassignedId = decideOnReassignment(group, workId, assignedId, allocableRegs);
|
|
if (reassignedId != RAAssignment::kPhysNone) {
|
|
ASMJIT_PROPAGATE(onMoveReg(group, workId, reassignedId, assignedId));
|
|
allocableRegs ^= Support::bitMask(reassignedId);
|
|
continue;
|
|
}
|
|
}
|
|
|
|
ASMJIT_PROPAGATE(onSpillReg(group, workId, assignedId));
|
|
}
|
|
} while (it.hasNext());
|
|
}
|
|
|
|
// STEP 5
|
|
// ------
|
|
//
|
|
// ALLOCATE / SHUFFLE all registers that we marked as `willUse` and weren't allocated yet. This is a bit
|
|
// complicated as the allocation is iterative. In some cases we have to wait before allocating a particual
|
|
// physical register as it's still occupied by some other one, which we need to move before we can use it.
|
|
// In this case we skip it and allocate another some other instead (making it free for another iteration).
|
|
//
|
|
// NOTE: Iterations are mostly important for complicated allocations like function calls, where there can
|
|
// be up to N registers used at once. Asm instructions won't run the loop more than once in 99.9% of cases
|
|
// as they use 2..3 registers in average.
|
|
|
|
if (usePending) {
|
|
bool mustSwap = false;
|
|
do {
|
|
uint32_t oldPending = usePending;
|
|
|
|
for (i = 0; i < count; i++) {
|
|
RATiedReg* thisTiedReg = &tiedRegs[i];
|
|
if (thisTiedReg->isUseDone())
|
|
continue;
|
|
|
|
uint32_t thisWorkId = thisTiedReg->workId();
|
|
uint32_t thisPhysId = _curAssignment.workToPhysId(group, thisWorkId);
|
|
|
|
// This would be a bug, fatal one!
|
|
uint32_t targetPhysId = thisTiedReg->useId();
|
|
ASMJIT_ASSERT(targetPhysId != thisPhysId);
|
|
|
|
uint32_t targetWorkId = _curAssignment.physToWorkId(group, targetPhysId);
|
|
if (targetWorkId != RAAssignment::kWorkNone) {
|
|
RAWorkReg* targetWorkReg = workRegById(targetWorkId);
|
|
|
|
// Swapping two registers can solve two allocation tasks by emitting just a single instruction. However,
|
|
// swap is only available on few architectures and it's definitely not available for each register group.
|
|
// Calling `onSwapReg()` before checking these would be fatal.
|
|
if (_archTraits->hasInstRegSwap(group) && thisPhysId != RAAssignment::kPhysNone) {
|
|
ASMJIT_PROPAGATE(onSwapReg(group, thisWorkId, thisPhysId, targetWorkId, targetPhysId));
|
|
|
|
thisTiedReg->markUseDone();
|
|
if (thisTiedReg->isWrite())
|
|
_curAssignment.makeDirty(group, thisWorkId, targetPhysId);
|
|
usePending--;
|
|
|
|
// Double-hit.
|
|
RATiedReg* targetTiedReg = RALocal_findTiedRegByWorkId(tiedRegs, count, targetWorkReg->workId());
|
|
if (targetTiedReg && targetTiedReg->useId() == thisPhysId) {
|
|
targetTiedReg->markUseDone();
|
|
if (targetTiedReg->isWrite())
|
|
_curAssignment.makeDirty(group, targetWorkId, thisPhysId);
|
|
usePending--;
|
|
}
|
|
continue;
|
|
}
|
|
|
|
if (!mustSwap)
|
|
continue;
|
|
|
|
// Only branched here if the previous iteration did nothing. This is essentially a SWAP operation without
|
|
// having a dedicated instruction for that purpose (vector registers, etc). The simplest way to handle
|
|
// such case is to SPILL the target register.
|
|
ASMJIT_PROPAGATE(onSpillReg(group, targetWorkId, targetPhysId));
|
|
}
|
|
|
|
if (thisPhysId != RAAssignment::kPhysNone) {
|
|
ASMJIT_PROPAGATE(onMoveReg(group, thisWorkId, targetPhysId, thisPhysId));
|
|
|
|
thisTiedReg->markUseDone();
|
|
if (thisTiedReg->isWrite())
|
|
_curAssignment.makeDirty(group, thisWorkId, targetPhysId);
|
|
usePending--;
|
|
}
|
|
else {
|
|
ASMJIT_PROPAGATE(onLoadReg(group, thisWorkId, targetPhysId));
|
|
|
|
thisTiedReg->markUseDone();
|
|
if (thisTiedReg->isWrite())
|
|
_curAssignment.makeDirty(group, thisWorkId, targetPhysId);
|
|
usePending--;
|
|
}
|
|
}
|
|
|
|
mustSwap = (oldPending == usePending);
|
|
} while (usePending);
|
|
}
|
|
|
|
// STEP 6
|
|
// ------
|
|
//
|
|
// KILL registers marked as KILL/OUT.
|
|
|
|
uint32_t outPending = outTiedCount;
|
|
if (outTiedCount) {
|
|
for (i = 0; i < outTiedCount; i++) {
|
|
RATiedReg* tiedReg = outTiedRegs[i];
|
|
|
|
uint32_t workId = tiedReg->workId();
|
|
uint32_t physId = _curAssignment.workToPhysId(group, workId);
|
|
|
|
// Must check if it's allocated as KILL can be related to OUT (like KILL immediately after OUT, which could
|
|
// mean the register is not assigned).
|
|
if (physId != RAAssignment::kPhysNone) {
|
|
ASMJIT_PROPAGATE(onKillReg(group, workId, physId));
|
|
willOut &= ~Support::bitMask(physId);
|
|
}
|
|
|
|
// We still maintain number of pending registers for OUT assignment. So, if this is only KILL, not OUT, we
|
|
// can safely decrement it.
|
|
outPending -= !tiedReg->isOut();
|
|
}
|
|
}
|
|
|
|
// STEP 7
|
|
// ------
|
|
//
|
|
// SPILL registers that will be CLOBBERed. Since OUT and KILL were already processed this is used mostly to
|
|
// handle function CALLs.
|
|
|
|
if (willOut) {
|
|
Support::BitWordIterator<RegMask> it(willOut);
|
|
do {
|
|
uint32_t physId = it.next();
|
|
uint32_t workId = _curAssignment.physToWorkId(group, physId);
|
|
|
|
if (workId == RAAssignment::kWorkNone)
|
|
continue;
|
|
|
|
ASMJIT_PROPAGATE(onSpillReg(group, workId, physId));
|
|
} while (it.hasNext());
|
|
}
|
|
|
|
// STEP 8
|
|
// ------
|
|
//
|
|
// Duplication.
|
|
|
|
for (i = 0; i < dupTiedCount; i++) {
|
|
RATiedReg* tiedReg = dupTiedRegs[i];
|
|
uint32_t workId = tiedReg->workId();
|
|
uint32_t srcId = tiedReg->useId();
|
|
|
|
Support::BitWordIterator<RegMask> it(tiedReg->useRegMask());
|
|
while (it.hasNext()) {
|
|
uint32_t dstId = it.next();
|
|
if (dstId == srcId)
|
|
continue;
|
|
_pass->emitMove(workId, dstId, srcId);
|
|
}
|
|
}
|
|
|
|
// STEP 9
|
|
// ------
|
|
//
|
|
// Vector registers can be cloberred partially by invoke - find if that's the case and clobber when necessary.
|
|
|
|
if (node->isInvoke() && group == RegGroup::kVec) {
|
|
const InvokeNode* invokeNode = node->as<InvokeNode>();
|
|
|
|
RegMask maybeClobberedRegs = invokeNode->detail().callConv().preservedRegs(group) & _curAssignment.assigned(group);
|
|
if (maybeClobberedRegs) {
|
|
uint32_t saveRestoreVecSize = invokeNode->detail().callConv().saveRestoreRegSize(group);
|
|
Support::BitWordIterator<RegMask> it(maybeClobberedRegs);
|
|
|
|
do {
|
|
uint32_t physId = it.next();
|
|
uint32_t workId = _curAssignment.physToWorkId(group, physId);
|
|
|
|
RAWorkReg* workReg = workRegById(workId);
|
|
uint32_t virtSize = workReg->virtReg()->virtSize();
|
|
|
|
if (virtSize > saveRestoreVecSize) {
|
|
ASMJIT_PROPAGATE(onSpillReg(group, workId, physId));
|
|
}
|
|
|
|
} while (it.hasNext());
|
|
}
|
|
}
|
|
|
|
// STEP 10
|
|
// -------
|
|
//
|
|
// Assign OUT registers.
|
|
|
|
if (outPending) {
|
|
// Live registers, we need a separate register (outside of `_curAssignment) to hold these because of KILLed
|
|
// registers. If we KILL a register here it will go out from `_curAssignment`, but we cannot assign to it in
|
|
// here.
|
|
RegMask liveRegs = _curAssignment.assigned(group);
|
|
|
|
// Must avoid as they have been already OUTed (added during the loop).
|
|
RegMask outRegs = 0;
|
|
|
|
// Must avoid as they collide with already allocated ones.
|
|
RegMask avoidRegs = willUse & ~clobberedByInst;
|
|
|
|
// Assign the best possible OUT ids of all consecutives.
|
|
if (consecutiveCount) {
|
|
RATiedReg* lead = consecutiveRegs[0];
|
|
if (lead->isOutConsecutive()) {
|
|
uint32_t bestScore = 0;
|
|
uint32_t bestLeadReg = 0xFFFFFFFF;
|
|
RegMask allocableRegs = _availableRegs[group] & ~(outRegs | avoidRegs);
|
|
|
|
Support::BitWordIterator<uint32_t> it(lead->outRegMask());
|
|
while (it.hasNext()) {
|
|
uint32_t regIndex = it.next();
|
|
if (Support::bitTest(lead->outRegMask(), regIndex)) {
|
|
uint32_t score = 15;
|
|
|
|
for (i = 0; i < consecutiveCount; i++) {
|
|
uint32_t consecutiveIndex = regIndex + i;
|
|
if (!Support::bitTest(allocableRegs, consecutiveIndex)) {
|
|
score = 0;
|
|
break;
|
|
}
|
|
|
|
RAWorkReg* workReg = workRegById(consecutiveRegs[i]->workId());
|
|
score += uint32_t(workReg->homeRegId() == consecutiveIndex);
|
|
}
|
|
|
|
if (score > bestScore) {
|
|
bestScore = score;
|
|
bestLeadReg = regIndex;
|
|
}
|
|
}
|
|
}
|
|
|
|
if (bestLeadReg == 0xFFFFFFFF)
|
|
return DebugUtils::errored(kErrorConsecutiveRegsAllocation);
|
|
|
|
for (i = 0; i < consecutiveCount; i++) {
|
|
uint32_t consecutiveIndex = bestLeadReg + i;
|
|
RATiedReg* tiedReg = consecutiveRegs[i];
|
|
tiedReg->setOutId(consecutiveIndex);
|
|
}
|
|
}
|
|
}
|
|
|
|
// Allocate OUT registers.
|
|
for (i = 0; i < outTiedCount; i++) {
|
|
RATiedReg* tiedReg = outTiedRegs[i];
|
|
if (!tiedReg->isOut())
|
|
continue;
|
|
|
|
uint32_t workId = tiedReg->workId();
|
|
uint32_t assignedId = _curAssignment.workToPhysId(group, workId);
|
|
|
|
if (assignedId != RAAssignment::kPhysNone)
|
|
ASMJIT_PROPAGATE(onKillReg(group, workId, assignedId));
|
|
|
|
uint32_t physId = tiedReg->outId();
|
|
if (physId == RAAssignment::kPhysNone) {
|
|
RegMask allocableRegs = tiedReg->outRegMask() & ~(outRegs | avoidRegs);
|
|
|
|
if (!(allocableRegs & ~liveRegs)) {
|
|
// There are no more registers, decide which one to spill.
|
|
uint32_t spillWorkId;
|
|
physId = decideOnSpillFor(group, workId, allocableRegs & liveRegs, &spillWorkId);
|
|
ASMJIT_PROPAGATE(onSpillReg(group, spillWorkId, physId));
|
|
}
|
|
else {
|
|
physId = decideOnAssignment(group, workId, RAAssignment::kPhysNone, allocableRegs & ~liveRegs);
|
|
}
|
|
}
|
|
|
|
// OUTs are CLOBBERed thus cannot be ASSIGNed right now.
|
|
ASMJIT_ASSERT(!_curAssignment.isPhysAssigned(group, physId));
|
|
|
|
if (!tiedReg->isKill())
|
|
ASMJIT_PROPAGATE(onAssignReg(group, workId, physId, true));
|
|
|
|
tiedReg->setOutId(physId);
|
|
tiedReg->markOutDone();
|
|
|
|
outRegs |= Support::bitMask(physId);
|
|
liveRegs &= ~Support::bitMask(physId);
|
|
outPending--;
|
|
}
|
|
|
|
clobberedByInst |= outRegs;
|
|
ASMJIT_ASSERT(outPending == 0);
|
|
}
|
|
|
|
_clobberedRegs[group] |= clobberedByInst;
|
|
}
|
|
|
|
return kErrorOk;
|
|
}
|
|
|
|
Error RALocalAllocator::spillAfterAllocation(InstNode* node) noexcept {
|
|
// This is experimental feature that would spill registers that don't have home-id and are last in this basic block.
|
|
// This prevents saving these regs in other basic blocks and then restoring them (mostly relevant for loops).
|
|
RAInst* raInst = node->passData<RAInst>();
|
|
uint32_t count = raInst->tiedCount();
|
|
|
|
for (uint32_t i = 0; i < count; i++) {
|
|
RATiedReg* tiedReg = raInst->tiedAt(i);
|
|
if (tiedReg->isLast()) {
|
|
uint32_t workId = tiedReg->workId();
|
|
RAWorkReg* workReg = workRegById(workId);
|
|
if (!workReg->hasHomeRegId()) {
|
|
RegGroup group = workReg->group();
|
|
uint32_t assignedId = _curAssignment.workToPhysId(group, workId);
|
|
if (assignedId != RAAssignment::kPhysNone) {
|
|
_cc->_setCursor(node);
|
|
ASMJIT_PROPAGATE(onSpillReg(group, workId, assignedId));
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
return kErrorOk;
|
|
}
|
|
|
|
Error RALocalAllocator::allocBranch(InstNode* node, RABlock* target, RABlock* cont) noexcept {
|
|
// TODO: This should be used to make the branch allocation better.
|
|
DebugUtils::unused(cont);
|
|
|
|
// The cursor must point to the previous instruction for a possible instruction insertion.
|
|
_cc->_setCursor(node->prev());
|
|
|
|
// Use TryMode of `switchToAssignment()` if possible.
|
|
if (target->hasEntryAssignment()) {
|
|
ASMJIT_PROPAGATE(switchToAssignment(target->entryPhysToWorkMap(), target->liveIn(), target->isAllocated(), true));
|
|
}
|
|
|
|
ASMJIT_PROPAGATE(allocInst(node));
|
|
ASMJIT_PROPAGATE(spillRegsBeforeEntry(target));
|
|
|
|
if (target->hasEntryAssignment()) {
|
|
BaseNode* injectionPoint = _pass->extraBlock()->prev();
|
|
BaseNode* prevCursor = _cc->setCursor(injectionPoint);
|
|
|
|
_tmpAssignment.copyFrom(_curAssignment);
|
|
ASMJIT_PROPAGATE(switchToAssignment(target->entryPhysToWorkMap(), target->liveIn(), target->isAllocated(), false));
|
|
|
|
BaseNode* curCursor = _cc->cursor();
|
|
if (curCursor != injectionPoint) {
|
|
// Additional instructions emitted to switch from the current state to the `target` state. This means
|
|
// that we have to move these instructions into an independent code block and patch the jump location.
|
|
Operand& targetOp = node->op(node->opCount() - 1);
|
|
if (ASMJIT_UNLIKELY(!targetOp.isLabel()))
|
|
return DebugUtils::errored(kErrorInvalidState);
|
|
|
|
Label trampoline = _cc->newLabel();
|
|
Label savedTarget = targetOp.as<Label>();
|
|
|
|
// Patch `target` to point to the `trampoline` we just created.
|
|
targetOp = trampoline;
|
|
|
|
// Clear a possible SHORT form as we have no clue now if the SHORT form would be encodable after patching
|
|
// the target to `trampoline` (X86 specific).
|
|
node->clearOptions(InstOptions::kShortForm);
|
|
|
|
// Finalize the switch assignment sequence.
|
|
ASMJIT_PROPAGATE(_pass->emitJump(savedTarget));
|
|
_cc->_setCursor(injectionPoint);
|
|
_cc->bind(trampoline);
|
|
}
|
|
|
|
_cc->_setCursor(prevCursor);
|
|
_curAssignment.swap(_tmpAssignment);
|
|
}
|
|
else {
|
|
ASMJIT_PROPAGATE(_pass->setBlockEntryAssignment(target, block(), _curAssignment));
|
|
}
|
|
|
|
return kErrorOk;
|
|
}
|
|
|
|
Error RALocalAllocator::allocJumpTable(InstNode* node, const RABlocks& targets, RABlock* cont) noexcept {
|
|
// TODO: Do we really need to use `cont`?
|
|
DebugUtils::unused(cont);
|
|
|
|
if (targets.empty())
|
|
return DebugUtils::errored(kErrorInvalidState);
|
|
|
|
// The cursor must point to the previous instruction for a possible instruction insertion.
|
|
_cc->_setCursor(node->prev());
|
|
|
|
// All `targets` should have the same sharedAssignmentId, we just read the first.
|
|
RABlock* anyTarget = targets[0];
|
|
if (!anyTarget->hasSharedAssignmentId())
|
|
return DebugUtils::errored(kErrorInvalidState);
|
|
|
|
RASharedAssignment& sharedAssignment = _pass->_sharedAssignments[anyTarget->sharedAssignmentId()];
|
|
|
|
ASMJIT_PROPAGATE(allocInst(node));
|
|
|
|
if (!sharedAssignment.empty()) {
|
|
ASMJIT_PROPAGATE(switchToAssignment(
|
|
sharedAssignment.physToWorkMap(),
|
|
sharedAssignment.liveIn(),
|
|
true, // Read-only.
|
|
false // Try-mode.
|
|
));
|
|
}
|
|
|
|
ASMJIT_PROPAGATE(spillRegsBeforeEntry(anyTarget));
|
|
|
|
if (sharedAssignment.empty()) {
|
|
ASMJIT_PROPAGATE(_pass->setBlockEntryAssignment(anyTarget, block(), _curAssignment));
|
|
}
|
|
|
|
return kErrorOk;
|
|
}
|
|
|
|
// RALocalAllocator - Decision Making
|
|
// ==================================
|
|
|
|
uint32_t RALocalAllocator::decideOnAssignment(RegGroup group, uint32_t workId, uint32_t physId, RegMask allocableRegs) const noexcept {
|
|
ASMJIT_ASSERT(allocableRegs != 0);
|
|
DebugUtils::unused(group, physId);
|
|
|
|
RAWorkReg* workReg = workRegById(workId);
|
|
|
|
// Prefer home register id, if possible.
|
|
if (workReg->hasHomeRegId()) {
|
|
uint32_t homeId = workReg->homeRegId();
|
|
if (Support::bitTest(allocableRegs, homeId))
|
|
return homeId;
|
|
}
|
|
|
|
// Prefer registers used upon block entries.
|
|
RegMask previouslyAssignedRegs = workReg->allocatedMask();
|
|
if (allocableRegs & previouslyAssignedRegs)
|
|
allocableRegs &= previouslyAssignedRegs;
|
|
|
|
return Support::ctz(allocableRegs);
|
|
}
|
|
|
|
uint32_t RALocalAllocator::decideOnReassignment(RegGroup group, uint32_t workId, uint32_t physId, RegMask allocableRegs) const noexcept {
|
|
ASMJIT_ASSERT(allocableRegs != 0);
|
|
DebugUtils::unused(group, physId);
|
|
|
|
RAWorkReg* workReg = workRegById(workId);
|
|
|
|
// Prefer allocating back to HomeId, if possible.
|
|
if (workReg->hasHomeRegId()) {
|
|
if (Support::bitTest(allocableRegs, workReg->homeRegId()))
|
|
return workReg->homeRegId();
|
|
}
|
|
|
|
// TODO: [Register Allocator] This could be improved.
|
|
|
|
// Decided to SPILL.
|
|
return RAAssignment::kPhysNone;
|
|
}
|
|
|
|
uint32_t RALocalAllocator::decideOnSpillFor(RegGroup group, uint32_t workId, RegMask spillableRegs, uint32_t* spillWorkId) const noexcept {
|
|
// May be used in the future to decide which register would be best to spill so `workId` can be assigned.
|
|
DebugUtils::unused(workId);
|
|
ASMJIT_ASSERT(spillableRegs != 0);
|
|
|
|
Support::BitWordIterator<RegMask> it(spillableRegs);
|
|
uint32_t bestPhysId = it.next();
|
|
uint32_t bestWorkId = _curAssignment.physToWorkId(group, bestPhysId);
|
|
|
|
// Avoid calculating the cost model if there is only one spillable register.
|
|
if (it.hasNext()) {
|
|
uint32_t bestCost = calculateSpillCost(group, bestWorkId, bestPhysId);
|
|
do {
|
|
uint32_t localPhysId = it.next();
|
|
uint32_t localWorkId = _curAssignment.physToWorkId(group, localPhysId);
|
|
uint32_t localCost = calculateSpillCost(group, localWorkId, localPhysId);
|
|
|
|
if (localCost < bestCost) {
|
|
bestCost = localCost;
|
|
bestPhysId = localPhysId;
|
|
bestWorkId = localWorkId;
|
|
}
|
|
} while (it.hasNext());
|
|
}
|
|
|
|
*spillWorkId = bestWorkId;
|
|
return bestPhysId;
|
|
}
|
|
|
|
ASMJIT_END_NAMESPACE
|
|
|
|
#endif // !ASMJIT_NO_COMPILER
|