564 lines
28 KiB
C++
564 lines
28 KiB
C++
// This file is part of AsmJit project <https://asmjit.com>
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//
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// See asmjit.h or LICENSE.md for license and copyright information
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// SPDX-License-Identifier: Zlib
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#ifndef ASMJIT_X86_X86INSTDB_H_INCLUDED
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#define ASMJIT_X86_X86INSTDB_H_INCLUDED
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#include "../x86/x86globals.h"
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ASMJIT_BEGIN_SUB_NAMESPACE(x86)
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//! \addtogroup asmjit_x86
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//! \{
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//! Instruction database (X86).
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namespace InstDB {
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//! Describes which operation mode is supported by an instruction.
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enum class Mode : uint8_t {
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//! Invalid mode.
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kNone = 0x00u,
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//! X86 mode supported.
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kX86 = 0x01u,
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//! X64 mode supported.
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kX64 = 0x02u,
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//! Both X86 and X64 modes supported.
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kAny = 0x03u
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};
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ASMJIT_DEFINE_ENUM_FLAGS(Mode)
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//! Converts architecture to operation mode, see \ref Mode.
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static constexpr Mode modeFromArch(Arch arch) noexcept {
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return arch == Arch::kX86 ? Mode::kX86 :
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arch == Arch::kX64 ? Mode::kX64 : Mode::kNone;
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}
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//! Operand signature flags used by \ref OpSignature.
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enum class OpFlags : uint64_t {
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//! No operand flags.
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kNone = 0u,
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kRegGpbLo = 0x0000000000000001u, //!< Operand can be low 8-bit GPB register.
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kRegGpbHi = 0x0000000000000002u, //!< Operand can be high 8-bit GPB register.
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kRegGpw = 0x0000000000000004u, //!< Operand can be 16-bit GPW register.
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kRegGpd = 0x0000000000000008u, //!< Operand can be 32-bit GPD register.
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kRegGpq = 0x0000000000000010u, //!< Operand can be 64-bit GPQ register.
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kRegXmm = 0x0000000000000020u, //!< Operand can be 128-bit XMM register.
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kRegYmm = 0x0000000000000040u, //!< Operand can be 256-bit YMM register.
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kRegZmm = 0x0000000000000080u, //!< Operand can be 512-bit ZMM register.
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kRegMm = 0x0000000000000100u, //!< Operand can be 64-bit MM register.
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kRegKReg = 0x0000000000000200u, //!< Operand can be 64-bit K register.
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kRegSReg = 0x0000000000000400u, //!< Operand can be SReg (segment register).
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kRegCReg = 0x0000000000000800u, //!< Operand can be CReg (control register).
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kRegDReg = 0x0000000000001000u, //!< Operand can be DReg (debug register).
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kRegSt = 0x0000000000002000u, //!< Operand can be 80-bit ST register (X87).
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kRegBnd = 0x0000000000004000u, //!< Operand can be 128-bit BND register.
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kRegTmm = 0x0000000000008000u, //!< Operand can be 0..8192-bit TMM register.
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kRegMask = 0x000000000000FFFFu, //!< Mask of all possible register types.
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kMemUnspecified = 0x0000000000040000u, //!< Operand can be a scalar memory pointer without size.
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kMem8 = 0x0000000000080000u, //!< Operand can be an 8-bit memory pointer.
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kMem16 = 0x0000000000100000u, //!< Operand can be a 16-bit memory pointer.
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kMem32 = 0x0000000000200000u, //!< Operand can be a 32-bit memory pointer.
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kMem48 = 0x0000000000400000u, //!< Operand can be a 48-bit memory pointer (FAR pointers only).
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kMem64 = 0x0000000000800000u, //!< Operand can be a 64-bit memory pointer.
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kMem80 = 0x0000000001000000u, //!< Operand can be an 80-bit memory pointer.
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kMem128 = 0x0000000002000000u, //!< Operand can be a 128-bit memory pointer.
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kMem256 = 0x0000000004000000u, //!< Operand can be a 256-bit memory pointer.
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kMem512 = 0x0000000008000000u, //!< Operand can be a 512-bit memory pointer.
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kMem1024 = 0x0000000010000000u, //!< Operand can be a 1024-bit memory pointer.
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kMemMask = 0x000000001FFC0000u, //!< Mask of all possible scalar memory types.
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kVm32x = 0x0000000040000000u, //!< Operand can be a vm32x (vector) pointer.
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kVm32y = 0x0000000080000000u, //!< Operand can be a vm32y (vector) pointer.
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kVm32z = 0x0000000100000000u, //!< Operand can be a vm32z (vector) pointer.
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kVm64x = 0x0000000200000000u, //!< Operand can be a vm64x (vector) pointer.
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kVm64y = 0x0000000400000000u, //!< Operand can be a vm64y (vector) pointer.
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kVm64z = 0x0000000800000000u, //!< Operand can be a vm64z (vector) pointer.
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kVmMask = 0x0000000FC0000000u, //!< Mask of all possible vector memory types.
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kImmI4 = 0x0000001000000000u, //!< Operand can be signed 4-bit immediate.
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kImmU4 = 0x0000002000000000u, //!< Operand can be unsigned 4-bit immediate.
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kImmI8 = 0x0000004000000000u, //!< Operand can be signed 8-bit immediate.
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kImmU8 = 0x0000008000000000u, //!< Operand can be unsigned 8-bit immediate.
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kImmI16 = 0x0000010000000000u, //!< Operand can be signed 16-bit immediate.
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kImmU16 = 0x0000020000000000u, //!< Operand can be unsigned 16-bit immediate.
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kImmI32 = 0x0000040000000000u, //!< Operand can be signed 32-bit immediate.
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kImmU32 = 0x0000080000000000u, //!< Operand can be unsigned 32-bit immediate.
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kImmI64 = 0x0000100000000000u, //!< Operand can be signed 64-bit immediate.
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kImmU64 = 0x0000200000000000u, //!< Operand can be unsigned 64-bit immediate.
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kImmMask = 0x00003FF000000000u, //!< Mask of all immediate types.
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kRel8 = 0x0000400000000000u, //!< Operand can be relative 8-bit displacement.
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kRel32 = 0x0000800000000000u, //!< Operand can be relative 32-bit displacement.
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kRelMask = 0x0000C00000000000u, //!< Mask of all relative displacement types.
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kFlagMemBase = 0x0001000000000000u, //!< Flag: Only memory base is allowed (no index, no offset).
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kFlagMemDs = 0x0002000000000000u, //!< Flag: Implicit memory operand's DS segment.
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kFlagMemEs = 0x0004000000000000u, //!< Flag: Implicit memory operand's ES segment.
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kFlagMib = 0x0008000000000000u, //!< Flag: Operand is MIB (base+index) pointer.
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kFlagTMem = 0x0010000000000000u, //!< Flag: Operand is TMEM (sib_mem), AMX memory pointer.
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kFlagImplicit = 0x0080000000000000u, //!< Flag: Operand is implicit.
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kFlagMask = 0x009F000000000000u, //!< Mask of all flags.
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//! Contains mask of all registers, memory operands, immediate operands, and displacement operands.
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kOpMask = kRegMask | kMemMask | kVmMask | kImmMask | kRelMask
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};
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ASMJIT_DEFINE_ENUM_FLAGS(OpFlags)
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//! Operand signature.
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//!
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//! Contains all possible operand combinations, memory size information, and a fixed register id (or `BaseReg::kIdBad`
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//! if fixed id isn't required).
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struct OpSignature {
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//! \name Members
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//! \{
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uint64_t _flags : 56;
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uint64_t _regMask : 8;
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//! \}
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//! \name Accessors
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//! \{
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//! Returns operand signature flags.
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inline OpFlags flags() const noexcept { return (OpFlags)_flags; }
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//! Tests whether the given `flag` is set.
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inline bool hasFlag(OpFlags flag) const noexcept { return (_flags & uint64_t(flag)) != 0; }
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//! Tests whether this signature contains at least one register operand of any type.
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inline bool hasReg() const noexcept { return hasFlag(OpFlags::kRegMask); }
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//! Tests whether this signature contains at least one scalar memory operand of any type.
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inline bool hasMem() const noexcept { return hasFlag(OpFlags::kMemMask); }
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//! Tests whether this signature contains at least one vector memory operand of any type.
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inline bool hasVm() const noexcept { return hasFlag(OpFlags::kVmMask); }
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//! Tests whether this signature contains at least one immediate operand of any type.
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inline bool hasImm() const noexcept { return hasFlag(OpFlags::kImmMask); }
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//! Tests whether this signature contains at least one relative displacement operand of any type.
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inline bool hasRel() const noexcept { return hasFlag(OpFlags::kRelMask); }
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//! Tests whether the operand is implicit.
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inline bool isImplicit() const noexcept { return hasFlag(OpFlags::kFlagImplicit); }
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//! Returns a physical register mask.
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inline RegMask regMask() const noexcept { return _regMask; }
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//! \}
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};
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ASMJIT_VARAPI const OpSignature _opSignatureTable[];
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//! Instruction signature.
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//!
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//! Contains a sequence of operands' combinations and other metadata that defines a single instruction. This data is
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//! used by instruction validator.
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struct InstSignature {
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//! \name Members
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//! \{
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//! Count of operands in `opIndex` (0..6).
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uint8_t _opCount : 3;
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//! Architecture modes supported (X86 / X64).
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uint8_t _mode : 2;
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//! Number of implicit operands.
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uint8_t _implicitOpCount : 3;
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//! Reserved for future use.
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uint8_t _reserved;
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//! Indexes to `OpSignature` table.
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uint8_t _opSignatureIndexes[Globals::kMaxOpCount];
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//! \}
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//! \name Accessors
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//! \{
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//! Returns instruction operation mode.
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inline Mode mode() const noexcept { return (Mode)_mode; }
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//! Tests whether the instruction supports the given operating mode.
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inline bool supportsMode(Mode mode) const noexcept { return (uint8_t(_mode) & uint8_t(mode)) != 0; }
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//! Returns the number of operands of this signature.
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inline uint32_t opCount() const noexcept { return _opCount; }
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//! Returns the number of implicit operands this signature has.
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inline uint32_t implicitOpCount() const noexcept { return _implicitOpCount; }
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//! Tests whether this instruction signature has at least one implicit operand.
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inline bool hasImplicitOperands() const noexcept { return _implicitOpCount != 0; }
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//! Returns indexes to \ref _opSignatureTable for each operand of the instruction.
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//!
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//! \note The returned array always provides indexes for all operands (see \ref Globals::kMaxOpCount) even if the
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//! instruction provides less operands. Undefined operands have always index of zero.
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inline const uint8_t* opSignatureIndexes() const noexcept { return _opSignatureIndexes; }
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//! Returns index to \ref _opSignatureTable, corresponding to the requested operand `index` of the instruction.
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inline uint8_t opSignatureIndex(size_t index) const noexcept {
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ASMJIT_ASSERT(index < Globals::kMaxOpCount);
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return _opSignatureIndexes[index];
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}
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//! Returns \ref OpSignature corresponding to the requested operand `index` of the instruction.
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inline const OpSignature& opSignature(size_t index) const noexcept {
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ASMJIT_ASSERT(index < Globals::kMaxOpCount);
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return _opSignatureTable[_opSignatureIndexes[index]];
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}
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//! \}
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};
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ASMJIT_VARAPI const InstSignature _instSignatureTable[];
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//! Instruction flags.
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//!
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//! Details about instruction encoding, operation, features, and some limitations.
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enum class InstFlags : uint32_t {
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//! No flags.
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kNone = 0x00000000u,
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// Instruction Family
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// ------------------
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//
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// Instruction family information.
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//! Instruction that accesses FPU registers.
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kFpu = 0x00000100u,
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//! Instruction that accesses MMX registers (including 3DNOW and GEODE) and EMMS.
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kMmx = 0x00000200u,
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//! Instruction that accesses XMM registers (SSE, AVX, AVX512).
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kVec = 0x00000400u,
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// FPU Flags
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// ---------
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//
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// Used to tell the encoder which memory operand sizes are encodable.
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//! FPU instruction can address `word_ptr` (shared with M80).
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kFpuM16 = 0x00000800u,
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//! FPU instruction can address `dword_ptr`.
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kFpuM32 = 0x00001000u,
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//! FPU instruction can address `qword_ptr`.
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kFpuM64 = 0x00002000u,
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//! FPU instruction can address `tword_ptr` (shared with M16).
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kFpuM80 = 0x00000800u,
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// Prefixes and Encoding Flags
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// ---------------------------
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//
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// These describe optional X86 prefixes that can be used to change the instruction's operation.
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//! Instruction can be prefixed with using the REP(REPE) or REPNE prefix.
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kRep = 0x00004000u,
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//! Rep prefix is accepted, but it has no effect other than being emitted with the instruction (as an extra byte).
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kRepIgnored = 0x00008000u,
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//! Instruction can be prefixed with using the LOCK prefix.
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kLock = 0x00010000u,
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//! Instruction can be prefixed with using the XACQUIRE prefix.
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kXAcquire = 0x00020000u,
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//! Instruction can be prefixed with using the XRELEASE prefix.
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kXRelease = 0x00040000u,
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//! Instruction uses MIB (BNDLDX|BNDSTX) to encode two registers.
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kMib = 0x00080000u,
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//! Instruction uses VSIB instead of legacy SIB.
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kVsib = 0x00100000u,
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//! Instruction uses TSIB (or SIB_MEM) encoding (MODRM followed by SIB).
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kTsib = 0x00200000u,
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// If both `kPrefixVex` and `kPrefixEvex` flags are specified it means that the instructions can be encoded
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// by either VEX or EVEX prefix. In that case AsmJit checks global options and also instruction options to decide
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// whether to emit VEX or EVEX prefix.
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//! Instruction can be encoded by VEX|XOP (AVX|AVX2|BMI|XOP|...).
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kVex = 0x00400000u,
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//! Instruction can be encoded by EVEX (AVX512).
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kEvex = 0x00800000u,
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//! EVEX encoding is preferred over VEX encoding (AVX515_VNNI vs AVX_VNNI).
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kPreferEvex = 0x01000000u,
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//! EVEX and VEX signatures are compatible.
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kEvexCompat = 0x02000000u,
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//! EVEX instruction requires K register in the first operand (compare instructions).
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kEvexKReg = 0x04000000u,
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//! EVEX instruction requires two operands and K register as a selector (gather instructions).
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kEvexTwoOp = 0x08000000u,
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//! VEX instruction that can be transformed to a compatible EVEX instruction.
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kEvexTransformable = 0x10000000u,
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// Other Flags
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// -----------
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//! Instruction uses consecutive registers.
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//!
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//! Used by V4FMADDPS, V4FMADDSS, V4FNMADDPS, V4FNMADDSS, VP4DPWSSD, VP4DPWSSDS, VP2INTERSECTD, and VP2INTERSECTQ
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//! instructions
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kConsecutiveRegs = 0x20000000u
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};
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ASMJIT_DEFINE_ENUM_FLAGS(InstFlags)
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//! AVX-512 flags.
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enum class Avx512Flags : uint32_t {
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//! No AVX-512 flags.
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kNone = 0,
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//! Internally used in tables, has no meaning.
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k_ = 0x00000000u,
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//! Supports masking {k1..k7}.
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kK = 0x00000001u,
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//! Supports zeroing {z}, must be used together with `kAvx512k`.
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kZ = 0x00000002u,
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//! Supports 'embedded-rounding' {er} with implicit {sae},
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kER = 0x00000004u,
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//! Supports 'suppress-all-exceptions' {sae}.
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kSAE = 0x00000008u,
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//! Supports 16-bit broadcast 'b16'.
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kB16 = 0x00000010u,
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//! Supports 32-bit broadcast 'b32'.
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kB32 = 0x00000020u,
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//! Supports 64-bit broadcast 'b64'.
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kB64 = 0x00000040u,
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//! Operates on a vector of consecutive registers (AVX512_4FMAPS and AVX512_4VNNIW).
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kT4X = 0x00000080u,
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//! Implicit zeroing if {k} masking is used. Using {z} is not valid in this case as it's implicit.
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kImplicitZ = 0x00000100,
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};
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ASMJIT_DEFINE_ENUM_FLAGS(Avx512Flags)
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//! Instruction common information.
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//!
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//! Aggregated information shared across one or more instruction.
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struct CommonInfo {
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//! Instruction flags.
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uint32_t _flags;
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//! Reserved for future use.
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uint32_t _avx512Flags : 11;
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//! First `InstSignature` entry in the database.
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uint32_t _iSignatureIndex : 11;
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//! Number of relevant `ISignature` entries.
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uint32_t _iSignatureCount : 5;
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//! Instruction control flow category, see \ref InstControlFlow.
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uint32_t _controlFlow : 3;
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//! Specifies what happens if all source operands share the same register.
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uint32_t _sameRegHint : 2;
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//! \name Accessors
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//! \{
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//! Returns instruction flags.
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inline InstFlags flags() const noexcept { return (InstFlags)_flags; }
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//! Tests whether the instruction has a `flag`.
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inline bool hasFlag(InstFlags flag) const noexcept { return Support::test(_flags, flag); }
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//! Returns instruction AVX-512 flags.
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inline Avx512Flags avx512Flags() const noexcept { return (Avx512Flags)_avx512Flags; }
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//! Tests whether the instruction has an AVX-512 `flag`.
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inline bool hasAvx512Flag(Avx512Flags flag) const noexcept { return Support::test(_avx512Flags, flag); }
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//! Tests whether the instruction is FPU instruction.
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inline bool isFpu() const noexcept { return hasFlag(InstFlags::kFpu); }
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//! Tests whether the instruction is MMX/3DNOW instruction that accesses MMX registers (includes EMMS and FEMMS).
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inline bool isMmx() const noexcept { return hasFlag(InstFlags::kMmx); }
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//! Tests whether the instruction is SSE|AVX|AVX512 instruction that accesses XMM|YMM|ZMM registers.
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inline bool isVec() const noexcept { return hasFlag(InstFlags::kVec); }
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//! Tests whether the instruction is SSE+ (SSE4.2, AES, SHA included) instruction that accesses XMM registers.
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inline bool isSse() const noexcept { return (flags() & (InstFlags::kVec | InstFlags::kVex | InstFlags::kEvex)) == InstFlags::kVec; }
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//! Tests whether the instruction is AVX+ (FMA included) instruction that accesses XMM|YMM|ZMM registers.
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inline bool isAvx() const noexcept { return isVec() && isVexOrEvex(); }
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//! Tests whether the instruction can be prefixed with LOCK prefix.
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inline bool hasLockPrefix() const noexcept { return hasFlag(InstFlags::kLock); }
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//! Tests whether the instruction can be prefixed with REP (REPE|REPZ) prefix.
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inline bool hasRepPrefix() const noexcept { return hasFlag(InstFlags::kRep); }
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//! Tests whether the instruction can be prefixed with XACQUIRE prefix.
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inline bool hasXAcquirePrefix() const noexcept { return hasFlag(InstFlags::kXAcquire); }
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//! Tests whether the instruction can be prefixed with XRELEASE prefix.
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inline bool hasXReleasePrefix() const noexcept { return hasFlag(InstFlags::kXRelease); }
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//! Tests whether the rep prefix is supported by the instruction, but ignored (has no effect).
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inline bool isRepIgnored() const noexcept { return hasFlag(InstFlags::kRepIgnored); }
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//! Tests whether the instruction uses MIB.
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inline bool isMibOp() const noexcept { return hasFlag(InstFlags::kMib); }
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//! Tests whether the instruction uses VSIB.
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inline bool isVsibOp() const noexcept { return hasFlag(InstFlags::kVsib); }
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//! Tests whether the instruction uses TSIB (AMX, instruction requires MOD+SIB).
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inline bool isTsibOp() const noexcept { return hasFlag(InstFlags::kTsib); }
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//! Tests whether the instruction uses VEX (can be set together with EVEX if both are encodable).
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inline bool isVex() const noexcept { return hasFlag(InstFlags::kVex); }
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//! Tests whether the instruction uses EVEX (can be set together with VEX if both are encodable).
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inline bool isEvex() const noexcept { return hasFlag(InstFlags::kEvex); }
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//! Tests whether the instruction uses EVEX (can be set together with VEX if both are encodable).
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inline bool isVexOrEvex() const noexcept { return hasFlag(InstFlags::kVex | InstFlags::kEvex); }
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//! Tests whether the instruction should prefer EVEX prefix instead of VEX prefix.
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inline bool preferEvex() const noexcept { return hasFlag(InstFlags::kPreferEvex); }
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inline bool isEvexCompatible() const noexcept { return hasFlag(InstFlags::kEvexCompat); }
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inline bool isEvexKRegOnly() const noexcept { return hasFlag(InstFlags::kEvexKReg); }
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inline bool isEvexTwoOpOnly() const noexcept { return hasFlag(InstFlags::kEvexTwoOp); }
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inline bool isEvexTransformable() const noexcept { return hasFlag(InstFlags::kEvexTransformable); }
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//! Tests whether the instruction supports AVX512 masking {k}.
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inline bool hasAvx512K() const noexcept { return hasAvx512Flag(Avx512Flags::kK); }
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//! Tests whether the instruction supports AVX512 zeroing {k}{z}.
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inline bool hasAvx512Z() const noexcept { return hasAvx512Flag(Avx512Flags::kZ); }
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//! Tests whether the instruction supports AVX512 embedded-rounding {er}.
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inline bool hasAvx512ER() const noexcept { return hasAvx512Flag(Avx512Flags::kER); }
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//! Tests whether the instruction supports AVX512 suppress-all-exceptions {sae}.
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inline bool hasAvx512SAE() const noexcept { return hasAvx512Flag(Avx512Flags::kSAE); }
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//! Tests whether the instruction supports AVX512 broadcast (either 32-bit or 64-bit).
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|
inline bool hasAvx512B() const noexcept { return hasAvx512Flag(Avx512Flags::kB16 | Avx512Flags::kB32 | Avx512Flags::kB64); }
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//! Tests whether the instruction supports AVX512 broadcast (16-bit).
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inline bool hasAvx512B16() const noexcept { return hasAvx512Flag(Avx512Flags::kB16); }
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//! Tests whether the instruction supports AVX512 broadcast (32-bit).
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inline bool hasAvx512B32() const noexcept { return hasAvx512Flag(Avx512Flags::kB32); }
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//! Tests whether the instruction supports AVX512 broadcast (64-bit).
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|
inline bool hasAvx512B64() const noexcept { return hasAvx512Flag(Avx512Flags::kB64); }
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|
|
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// Returns the size of the broadcast - either 2, 4, or 8, or 0 if broadcast is not supported.
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|
inline uint32_t broadcastSize() const noexcept {
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|
constexpr uint32_t kShift = Support::ConstCTZ<uint32_t(Avx512Flags::kB16)>::value;
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|
return (uint32_t(_avx512Flags) & uint32_t(Avx512Flags::kB16 | Avx512Flags::kB32 | Avx512Flags::kB64)) >> (kShift - 1);
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}
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inline uint32_t signatureIndex() const noexcept { return _iSignatureIndex; }
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inline uint32_t signatureCount() const noexcept { return _iSignatureCount; }
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inline const InstSignature* signatureData() const noexcept { return _instSignatureTable + _iSignatureIndex; }
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inline const InstSignature* signatureEnd() const noexcept { return _instSignatureTable + _iSignatureIndex + _iSignatureCount; }
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//! Returns a control flow category of the instruction.
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|
inline InstControlFlow controlFlow() const noexcept { return (InstControlFlow)_controlFlow; }
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//! Returns a hint that can be used when both inputs are the same register.
|
|
inline InstSameRegHint sameRegHint() const noexcept { return (InstSameRegHint)_sameRegHint; }
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|
|
|
//! \}
|
|
};
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ASMJIT_VARAPI const CommonInfo _commonInfoTable[];
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|
|
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//! Instruction information.
|
|
struct InstInfo {
|
|
//! Reserved for future use.
|
|
uint32_t _reserved : 14;
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|
//! Index to \ref _commonInfoTable.
|
|
uint32_t _commonInfoIndex : 10;
|
|
//! Index to \ref _additionalInfoTable.
|
|
uint32_t _additionalInfoIndex : 8;
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|
|
//! Instruction encoding (internal encoding identifier used by \ref Assembler).
|
|
uint8_t _encoding;
|
|
//! Main opcode value (0..255).
|
|
uint8_t _mainOpcodeValue;
|
|
//! Index to \ref _mainOpcodeTable` that is combined with \ref _mainOpcodeValue to form the final opcode.
|
|
uint8_t _mainOpcodeIndex;
|
|
//! Index to \ref _altOpcodeTable that contains a full alternative opcode.
|
|
uint8_t _altOpcodeIndex;
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|
|
|
//! \name Accessors
|
|
//! \{
|
|
|
|
//! Returns common information, see \ref CommonInfo.
|
|
inline const CommonInfo& commonInfo() const noexcept { return _commonInfoTable[_commonInfoIndex]; }
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|
|
|
//! Returns instruction flags, see \ref Flags.
|
|
inline InstFlags flags() const noexcept { return commonInfo().flags(); }
|
|
//! Tests whether the instruction has flag `flag`, see \ref Flags.
|
|
inline bool hasFlag(InstFlags flag) const noexcept { return commonInfo().hasFlag(flag); }
|
|
|
|
//! Returns instruction AVX-512 flags, see \ref Avx512Flags.
|
|
inline Avx512Flags avx512Flags() const noexcept { return commonInfo().avx512Flags(); }
|
|
//! Tests whether the instruction has an AVX-512 `flag`, see \ref Avx512Flags.
|
|
inline bool hasAvx512Flag(Avx512Flags flag) const noexcept { return commonInfo().hasAvx512Flag(flag); }
|
|
|
|
//! Tests whether the instruction is FPU instruction.
|
|
inline bool isFpu() const noexcept { return commonInfo().isFpu(); }
|
|
//! Tests whether the instruction is MMX/3DNOW instruction that accesses MMX registers (includes EMMS and FEMMS).
|
|
inline bool isMmx() const noexcept { return commonInfo().isMmx(); }
|
|
//! Tests whether the instruction is SSE|AVX|AVX512 instruction that accesses XMM|YMM|ZMM registers.
|
|
inline bool isVec() const noexcept { return commonInfo().isVec(); }
|
|
//! Tests whether the instruction is SSE+ (SSE4.2, AES, SHA included) instruction that accesses XMM registers.
|
|
inline bool isSse() const noexcept { return commonInfo().isSse(); }
|
|
//! Tests whether the instruction is AVX+ (FMA included) instruction that accesses XMM|YMM|ZMM registers.
|
|
inline bool isAvx() const noexcept { return commonInfo().isAvx(); }
|
|
|
|
//! Tests whether the instruction can be prefixed with LOCK prefix.
|
|
inline bool hasLockPrefix() const noexcept { return commonInfo().hasLockPrefix(); }
|
|
//! Tests whether the instruction can be prefixed with REP (REPE|REPZ) prefix.
|
|
inline bool hasRepPrefix() const noexcept { return commonInfo().hasRepPrefix(); }
|
|
//! Tests whether the instruction can be prefixed with XACQUIRE prefix.
|
|
inline bool hasXAcquirePrefix() const noexcept { return commonInfo().hasXAcquirePrefix(); }
|
|
//! Tests whether the instruction can be prefixed with XRELEASE prefix.
|
|
inline bool hasXReleasePrefix() const noexcept { return commonInfo().hasXReleasePrefix(); }
|
|
|
|
//! Tests whether the rep prefix is supported by the instruction, but ignored (has no effect).
|
|
inline bool isRepIgnored() const noexcept { return commonInfo().isRepIgnored(); }
|
|
//! Tests whether the instruction uses MIB.
|
|
inline bool isMibOp() const noexcept { return hasFlag(InstFlags::kMib); }
|
|
//! Tests whether the instruction uses VSIB.
|
|
inline bool isVsibOp() const noexcept { return hasFlag(InstFlags::kVsib); }
|
|
//! Tests whether the instruction uses VEX (can be set together with EVEX if both are encodable).
|
|
inline bool isVex() const noexcept { return hasFlag(InstFlags::kVex); }
|
|
//! Tests whether the instruction uses EVEX (can be set together with VEX if both are encodable).
|
|
inline bool isEvex() const noexcept { return hasFlag(InstFlags::kEvex); }
|
|
//! Tests whether the instruction uses EVEX (can be set together with VEX if both are encodable).
|
|
inline bool isVexOrEvex() const noexcept { return hasFlag(InstFlags::kVex | InstFlags::kEvex); }
|
|
|
|
inline bool isEvexCompatible() const noexcept { return hasFlag(InstFlags::kEvexCompat); }
|
|
inline bool isEvexKRegOnly() const noexcept { return hasFlag(InstFlags::kEvexKReg); }
|
|
inline bool isEvexTwoOpOnly() const noexcept { return hasFlag(InstFlags::kEvexTwoOp); }
|
|
inline bool isEvexTransformable() const noexcept { return hasFlag(InstFlags::kEvexTransformable); }
|
|
|
|
//! Tests whether the instruction supports AVX512 masking {k}.
|
|
inline bool hasAvx512K() const noexcept { return hasAvx512Flag(Avx512Flags::kK); }
|
|
//! Tests whether the instruction supports AVX512 zeroing {k}{z}.
|
|
inline bool hasAvx512Z() const noexcept { return hasAvx512Flag(Avx512Flags::kZ); }
|
|
//! Tests whether the instruction supports AVX512 embedded-rounding {er}.
|
|
inline bool hasAvx512ER() const noexcept { return hasAvx512Flag(Avx512Flags::kER); }
|
|
//! Tests whether the instruction supports AVX512 suppress-all-exceptions {sae}.
|
|
inline bool hasAvx512SAE() const noexcept { return hasAvx512Flag(Avx512Flags::kSAE); }
|
|
//! Tests whether the instruction supports AVX512 broadcast (either 32-bit or 64-bit).
|
|
inline bool hasAvx512B() const noexcept { return hasAvx512Flag(Avx512Flags::kB16 | Avx512Flags::kB32 | Avx512Flags::kB64); }
|
|
//! Tests whether the instruction supports AVX512 broadcast (16-bit).
|
|
inline bool hasAvx512B16() const noexcept { return hasAvx512Flag(Avx512Flags::kB16); }
|
|
//! Tests whether the instruction supports AVX512 broadcast (32-bit).
|
|
inline bool hasAvx512B32() const noexcept { return hasAvx512Flag(Avx512Flags::kB32); }
|
|
//! Tests whether the instruction supports AVX512 broadcast (64-bit).
|
|
inline bool hasAvx512B64() const noexcept { return hasAvx512Flag(Avx512Flags::kB64); }
|
|
|
|
//! Returns a control flow category of the instruction.
|
|
inline InstControlFlow controlFlow() const noexcept { return commonInfo().controlFlow(); }
|
|
//! Returns a hint that can be used when both inputs are the same register.
|
|
inline InstSameRegHint sameRegHint() const noexcept { return commonInfo().sameRegHint(); }
|
|
|
|
inline uint32_t signatureIndex() const noexcept { return commonInfo().signatureIndex(); }
|
|
inline uint32_t signatureCount() const noexcept { return commonInfo().signatureCount(); }
|
|
|
|
inline const InstSignature* signatureData() const noexcept { return commonInfo().signatureData(); }
|
|
inline const InstSignature* signatureEnd() const noexcept { return commonInfo().signatureEnd(); }
|
|
|
|
//! \}
|
|
};
|
|
|
|
ASMJIT_VARAPI const InstInfo _instInfoTable[];
|
|
|
|
static inline const InstInfo& infoById(InstId instId) noexcept {
|
|
ASMJIT_ASSERT(Inst::isDefinedId(instId));
|
|
return _instInfoTable[instId];
|
|
}
|
|
|
|
//! \cond INTERNAL
|
|
static_assert(sizeof(OpSignature) == 8, "InstDB::OpSignature must be 8 bytes long");
|
|
//! \endcond
|
|
|
|
} // {InstDB}
|
|
|
|
//! \}
|
|
|
|
ASMJIT_END_SUB_NAMESPACE
|
|
|
|
#endif // ASMJIT_X86_X86INSTDB_H_INCLUDED
|