190 lines
6.0 KiB
C++
190 lines
6.0 KiB
C++
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// This file is part of AsmJit project <https://asmjit.com>
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//
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// See asmjit.h or LICENSE.md for license and copyright information
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// SPDX-License-Identifier: Zlib
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#include "../core/api-build_p.h"
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#if !defined(ASMJIT_NO_AARCH64)
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#include "../arm/a64func_p.h"
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#include "../arm/a64operand.h"
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ASMJIT_BEGIN_SUB_NAMESPACE(a64)
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namespace FuncInternal {
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static inline bool shouldThreatAsCDecl(CallConvId ccId) noexcept {
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return ccId == CallConvId::kCDecl ||
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ccId == CallConvId::kStdCall ||
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ccId == CallConvId::kFastCall ||
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ccId == CallConvId::kVectorCall ||
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ccId == CallConvId::kThisCall ||
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ccId == CallConvId::kRegParm1 ||
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ccId == CallConvId::kRegParm2 ||
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ccId == CallConvId::kRegParm3;
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}
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static RegType regTypeFromFpOrVecTypeId(TypeId typeId) noexcept {
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if (typeId == TypeId::kFloat32)
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return RegType::kARM_VecS;
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else if (typeId == TypeId::kFloat64)
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return RegType::kARM_VecD;
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else if (TypeUtils::isVec32(typeId))
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return RegType::kARM_VecS;
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else if (TypeUtils::isVec64(typeId))
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return RegType::kARM_VecD;
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else if (TypeUtils::isVec128(typeId))
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return RegType::kARM_VecV;
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else
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return RegType::kNone;
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}
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ASMJIT_FAVOR_SIZE Error initCallConv(CallConv& cc, CallConvId ccId, const Environment& environment) noexcept {
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cc.setArch(environment.arch());
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cc.setSaveRestoreRegSize(RegGroup::kGp, 8);
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cc.setSaveRestoreRegSize(RegGroup::kVec, 8);
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cc.setSaveRestoreAlignment(RegGroup::kGp, 16);
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cc.setSaveRestoreAlignment(RegGroup::kVec, 16);
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cc.setSaveRestoreAlignment(RegGroup::kExtraVirt2, 1);
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cc.setSaveRestoreAlignment(RegGroup::kExtraVirt3, 1);
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cc.setPassedOrder(RegGroup::kGp, 0, 1, 2, 3, 4, 5, 6, 7);
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cc.setPassedOrder(RegGroup::kVec, 0, 1, 2, 3, 4, 5, 6, 7);
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cc.setNaturalStackAlignment(16);
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if (shouldThreatAsCDecl(ccId)) {
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// ARM doesn't have that many calling conventions as we can find in X86 world, treat most conventions as __cdecl.
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cc.setId(CallConvId::kCDecl);
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cc.setPreservedRegs(RegGroup::kGp, Support::bitMask(Gp::kIdOs, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30));
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cc.setPreservedRegs(RegGroup::kVec, Support::bitMask(8, 9, 10, 11, 12, 13, 14, 15));
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}
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else {
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cc.setId(ccId);
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cc.setSaveRestoreRegSize(RegGroup::kVec, 16);
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cc.setPreservedRegs(RegGroup::kGp, Support::bitMask(4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30));
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cc.setPreservedRegs(RegGroup::kVec, Support::bitMask(4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31));
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}
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return kErrorOk;
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}
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ASMJIT_FAVOR_SIZE Error initFuncDetail(FuncDetail& func, const FuncSignature& signature, uint32_t registerSize) noexcept {
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DebugUtils::unused(signature);
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const CallConv& cc = func.callConv();
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uint32_t stackOffset = 0;
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uint32_t i;
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uint32_t argCount = func.argCount();
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if (func.hasRet()) {
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for (uint32_t valueIndex = 0; valueIndex < Globals::kMaxValuePack; valueIndex++) {
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TypeId typeId = func._rets[valueIndex].typeId();
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// Terminate at the first void type (end of the pack).
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if (typeId == TypeId::kVoid)
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break;
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switch (typeId) {
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case TypeId::kInt8:
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case TypeId::kInt16:
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case TypeId::kInt32: {
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func._rets[valueIndex].initReg(RegType::kARM_GpW, valueIndex, TypeId::kInt32);
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break;
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}
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case TypeId::kUInt8:
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case TypeId::kUInt16:
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case TypeId::kUInt32: {
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func._rets[valueIndex].initReg(RegType::kARM_GpW, valueIndex, TypeId::kUInt32);
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break;
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}
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case TypeId::kInt64:
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case TypeId::kUInt64: {
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func._rets[valueIndex].initReg(RegType::kARM_GpX, valueIndex, typeId);
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break;
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}
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default: {
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RegType regType = regTypeFromFpOrVecTypeId(typeId);
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if (regType == RegType::kNone)
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return DebugUtils::errored(kErrorInvalidRegType);
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func._rets[valueIndex].initReg(regType, valueIndex, typeId);
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break;
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}
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}
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}
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}
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switch (cc.strategy()) {
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case CallConvStrategy::kDefault: {
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uint32_t gpzPos = 0;
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uint32_t vecPos = 0;
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for (i = 0; i < argCount; i++) {
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FuncValue& arg = func._args[i][0];
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TypeId typeId = arg.typeId();
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if (TypeUtils::isInt(typeId)) {
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uint32_t regId = BaseReg::kIdBad;
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if (gpzPos < CallConv::kMaxRegArgsPerGroup)
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regId = cc._passedOrder[RegGroup::kGp].id[gpzPos];
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if (regId != BaseReg::kIdBad) {
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RegType regType = typeId <= TypeId::kUInt32 ? RegType::kARM_GpW : RegType::kARM_GpX;
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arg.assignRegData(regType, regId);
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func.addUsedRegs(RegGroup::kGp, Support::bitMask(regId));
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gpzPos++;
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}
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else {
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uint32_t size = Support::max<uint32_t>(TypeUtils::sizeOf(typeId), registerSize);
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arg.assignStackOffset(int32_t(stackOffset));
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stackOffset += size;
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}
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continue;
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}
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if (TypeUtils::isFloat(typeId) || TypeUtils::isVec(typeId)) {
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uint32_t regId = BaseReg::kIdBad;
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if (vecPos < CallConv::kMaxRegArgsPerGroup)
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regId = cc._passedOrder[RegGroup::kVec].id[vecPos];
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if (regId != BaseReg::kIdBad) {
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RegType regType = regTypeFromFpOrVecTypeId(typeId);
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if (regType == RegType::kNone)
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return DebugUtils::errored(kErrorInvalidRegType);
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arg.initTypeId(typeId);
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arg.assignRegData(regType, regId);
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func.addUsedRegs(RegGroup::kVec, Support::bitMask(regId));
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vecPos++;
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}
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else {
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uint32_t size = TypeUtils::sizeOf(typeId);
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arg.assignStackOffset(int32_t(stackOffset));
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stackOffset += size;
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}
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continue;
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}
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}
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break;
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}
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default:
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return DebugUtils::errored(kErrorInvalidState);
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}
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func._argStackSize = stackOffset;
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return kErrorOk;
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}
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} // {FuncInternal}
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ASMJIT_END_SUB_NAMESPACE
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#endif // !ASMJIT_NO_AARCH64
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