622 lines
29 KiB
C
622 lines
29 KiB
C
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// This file is part of AsmJit project <https://asmjit.com>
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//
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// See asmjit.h or LICENSE.md for license and copyright information
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// SPDX-License-Identifier: Zlib
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#ifndef ASMJIT_ARM_ARMOPERAND_H_INCLUDED
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#define ASMJIT_ARM_ARMOPERAND_H_INCLUDED
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#include "../core/archtraits.h"
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#include "../core/operand.h"
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#include "../core/type.h"
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#include "../arm/armglobals.h"
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ASMJIT_BEGIN_SUB_NAMESPACE(arm)
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//! \addtogroup asmjit_arm
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//! \{
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class Reg;
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class Mem;
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class Gp;
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class GpW;
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class GpX;
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class Vec;
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class VecB;
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class VecH;
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class VecS;
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class VecD;
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class VecV;
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//! Register traits (ARM/AArch64).
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//!
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//! Register traits contains information about a particular register type. It's used by asmjit to setup register
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//! information on-the-fly and to populate tables that contain register information (this way it's possible to
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//! change register types and groups without having to reorder these tables).
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template<RegType kRegType>
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struct RegTraits : public BaseRegTraits {};
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//! \cond
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// <--------------------+-----+-------------------------+------------------------+---+---+------------------+
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// | Reg | Reg-Type | Reg-Group |Sz |Cnt| TypeId |
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// <--------------------+-----+-------------------------+------------------------+---+---+------------------+
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ASMJIT_DEFINE_REG_TRAITS(GpW , RegType::kARM_GpW , RegGroup::kGp , 4 , 32, TypeId::kInt32 );
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ASMJIT_DEFINE_REG_TRAITS(GpX , RegType::kARM_GpX , RegGroup::kGp , 8 , 32, TypeId::kInt64 );
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ASMJIT_DEFINE_REG_TRAITS(VecB , RegType::kARM_VecB , RegGroup::kVec , 1 , 32, TypeId::kVoid );
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ASMJIT_DEFINE_REG_TRAITS(VecH , RegType::kARM_VecH , RegGroup::kVec , 2 , 32, TypeId::kVoid );
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ASMJIT_DEFINE_REG_TRAITS(VecS , RegType::kARM_VecS , RegGroup::kVec , 4 , 32, TypeId::kInt32x1 );
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ASMJIT_DEFINE_REG_TRAITS(VecD , RegType::kARM_VecD , RegGroup::kVec , 8 , 32, TypeId::kInt32x2 );
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ASMJIT_DEFINE_REG_TRAITS(VecV , RegType::kARM_VecV , RegGroup::kVec , 16, 32, TypeId::kInt32x4 );
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//! \endcond
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//! Register (ARM).
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class Reg : public BaseReg {
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public:
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ASMJIT_DEFINE_ABSTRACT_REG(Reg, BaseReg)
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//! Gets whether the register is a `R|W` register (32-bit).
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inline constexpr bool isGpW() const noexcept { return baseSignature() == RegTraits<RegType::kARM_GpW>::kSignature; }
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//! Gets whether the register is an `X` register (64-bit).
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inline constexpr bool isGpX() const noexcept { return baseSignature() == RegTraits<RegType::kARM_GpX>::kSignature; }
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//! Gets whether the register is a VEC-B register (8-bit).
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inline constexpr bool isVecB() const noexcept { return baseSignature() == RegTraits<RegType::kARM_VecB>::kSignature; }
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//! Gets whether the register is a VEC-H register (16-bit).
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inline constexpr bool isVecH() const noexcept { return baseSignature() == RegTraits<RegType::kARM_VecH>::kSignature; }
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//! Gets whether the register is a VEC-S register (32-bit).
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inline constexpr bool isVecS() const noexcept { return baseSignature() == RegTraits<RegType::kARM_VecS>::kSignature; }
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//! Gets whether the register is a VEC-D register (64-bit).
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inline constexpr bool isVecD() const noexcept { return baseSignature() == RegTraits<RegType::kARM_VecD>::kSignature; }
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//! Gets whether the register is a VEC-Q register (128-bit).
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inline constexpr bool isVecQ() const noexcept { return baseSignature() == RegTraits<RegType::kARM_VecV>::kSignature; }
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//! Gets whether the register is either VEC-D (64-bit) or VEC-Q (128-bit).
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inline constexpr bool isVecDOrQ() const noexcept { return uint32_t(type()) - uint32_t(RegType::kARM_VecD) <= 1u; }
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//! Gets whether the register is a VEC-V register (128-bit).
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inline constexpr bool isVecV() const noexcept { return baseSignature() == RegTraits<RegType::kARM_VecV>::kSignature; }
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template<RegType kRegType>
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inline void setRegT(uint32_t id) noexcept {
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setSignature(RegTraits<kRegType>::kSignature);
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setId(id);
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}
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inline void setTypeAndId(RegType type, uint32_t id) noexcept {
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setSignature(signatureOf(type));
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setId(id);
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}
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static inline RegGroup groupOf(RegType type) noexcept { return ArchTraits::byArch(Arch::kAArch64).regTypeToGroup(type); }
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static inline TypeId typeIdOf(RegType type) noexcept { return ArchTraits::byArch(Arch::kAArch64).regTypeToTypeId(type); }
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static inline OperandSignature signatureOf(RegType type) noexcept { return ArchTraits::byArch(Arch::kAArch64).regTypeToSignature(type); }
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template<RegType kRegType>
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static inline RegGroup groupOfT() noexcept { return RegTraits<kRegType>::kGroup; }
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template<RegType kRegType>
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static inline TypeId typeIdOfT() noexcept { return RegTraits<kRegType>::kTypeId; }
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template<RegType kRegType>
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static inline OperandSignature signatureOfT() noexcept { return RegTraits<kRegType>::kSignature; }
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static inline bool isGpW(const Operand_& op) noexcept { return op.as<Reg>().isGpW(); }
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static inline bool isGpX(const Operand_& op) noexcept { return op.as<Reg>().isGpX(); }
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static inline bool isVecB(const Operand_& op) noexcept { return op.as<Reg>().isVecB(); }
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static inline bool isVecH(const Operand_& op) noexcept { return op.as<Reg>().isVecH(); }
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static inline bool isVecS(const Operand_& op) noexcept { return op.as<Reg>().isVecS(); }
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static inline bool isVecD(const Operand_& op) noexcept { return op.as<Reg>().isVecD(); }
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static inline bool isVecQ(const Operand_& op) noexcept { return op.as<Reg>().isVecQ(); }
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static inline bool isVecV(const Operand_& op) noexcept { return op.as<Reg>().isVecV(); }
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static inline bool isGpW(const Operand_& op, uint32_t id) noexcept { return bool(unsigned(isGpW(op)) & unsigned(op.id() == id)); }
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static inline bool isGpX(const Operand_& op, uint32_t id) noexcept { return bool(unsigned(isGpX(op)) & unsigned(op.id() == id)); }
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static inline bool isVecB(const Operand_& op, uint32_t id) noexcept { return bool(unsigned(isVecB(op)) & unsigned(op.id() == id)); }
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static inline bool isVecH(const Operand_& op, uint32_t id) noexcept { return bool(unsigned(isVecH(op)) & unsigned(op.id() == id)); }
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static inline bool isVecS(const Operand_& op, uint32_t id) noexcept { return bool(unsigned(isVecS(op)) & unsigned(op.id() == id)); }
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static inline bool isVecD(const Operand_& op, uint32_t id) noexcept { return bool(unsigned(isVecD(op)) & unsigned(op.id() == id)); }
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static inline bool isVecQ(const Operand_& op, uint32_t id) noexcept { return bool(unsigned(isVecQ(op)) & unsigned(op.id() == id)); }
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static inline bool isVecV(const Operand_& op, uint32_t id) noexcept { return bool(unsigned(isVecV(op)) & unsigned(op.id() == id)); }
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};
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//! General purpose register (ARM).
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class Gp : public Reg {
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public:
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ASMJIT_DEFINE_ABSTRACT_REG(Gp, Reg)
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//! Special register id.
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enum Id : uint32_t {
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//! Register that depends on OS, could be used as TLS offset.
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kIdOs = 18,
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//! Frame pointer.
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kIdFp = 29,
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//! Link register.
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kIdLr = 30,
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//! Stack register id.
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kIdSp = 31,
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//! Zero register id.
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//!
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//! Although zero register has the same id as stack register it has a special treatment, because we need to be
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//! able to distinguish between these two at API level. Some intructions were designed to be used with SP and
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//! some other with ZR - so we need a way to distinguish these two to make sure we emit the right thing.
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//!
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//! The number 63 is not random, when you perform `id & 31` you would always get 31 for both SP and ZR inputs,
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//! which is the identifier used by AArch64 ISA to encode either SP or ZR depending on the instruction.
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kIdZr = 63
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};
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inline constexpr bool isZR() const noexcept { return id() == kIdZr; }
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inline constexpr bool isSP() const noexcept { return id() == kIdSp; }
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//! Cast this register to a 32-bit R|W.
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inline GpW w() const noexcept;
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//! Cast this register to a 64-bit X.
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inline GpX x() const noexcept;
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};
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//! Vector register (ARM).
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class Vec : public Reg {
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public:
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ASMJIT_DEFINE_ABSTRACT_REG(Vec, Reg)
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//! Additional signature bits used by arm::Vec.
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enum AdditionalBits : uint32_t {
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// Register element type (3 bits).
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// |........|........|.XXX....|........|
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kSignatureRegElementTypeShift = 12,
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kSignatureRegElementTypeMask = 0x07 << kSignatureRegElementTypeShift,
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// Register has element index (1 bit).
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// |........|........|X.......|........|
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kSignatureRegElementFlagShift = 15,
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kSignatureRegElementFlagMask = 0x01 << kSignatureRegElementFlagShift,
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// Register element index (4 bits).
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// |........|....XXXX|........|........|
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kSignatureRegElementIndexShift = 16,
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kSignatureRegElementIndexMask = 0x0F << kSignatureRegElementIndexShift
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};
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//! Element type.
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enum ElementType : uint32_t {
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//! No element type specified.
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kElementTypeNone = 0,
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//! Byte elements (B8 or B16).
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kElementTypeB,
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//! Halfword elements (H4 or H8).
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kElementTypeH,
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//! Singleword elements (S2 or S4).
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kElementTypeS,
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//! Doubleword elements (D2).
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kElementTypeD,
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//! Byte elements grouped by 4 bytes (B4).
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//!
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//! \note This element-type is only used by few instructions.
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kElementTypeB4,
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//! Halfword elements grouped by 2 halfwords (H2).
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//!
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//! \note This element-type is only used by few instructions.
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kElementTypeH2,
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//! Count of element types.
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kElementTypeCount
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};
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//! \cond
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//! Shortcuts.
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enum SignatureReg : uint32_t {
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kSignatureElementB = kElementTypeB << kSignatureRegElementTypeShift,
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kSignatureElementH = kElementTypeH << kSignatureRegElementTypeShift,
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kSignatureElementS = kElementTypeS << kSignatureRegElementTypeShift,
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kSignatureElementD = kElementTypeD << kSignatureRegElementTypeShift,
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kSignatureElementB4 = kElementTypeB4 << kSignatureRegElementTypeShift,
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kSignatureElementH2 = kElementTypeH2 << kSignatureRegElementTypeShift
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};
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//! \endcond
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//! Returns whether the register has associated an element type.
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inline constexpr bool hasElementType() const noexcept { return _signature.hasField<kSignatureRegElementTypeMask>(); }
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//! Returns whether the register has element index (it's an element index access).
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inline constexpr bool hasElementIndex() const noexcept { return _signature.hasField<kSignatureRegElementFlagMask>(); }
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//! Returns whether the reggister has element type or element index (or both).
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inline constexpr bool hasElementTypeOrIndex() const noexcept { return _signature.hasField<kSignatureRegElementTypeMask | kSignatureRegElementFlagMask>(); }
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//! Returns element type of the register.
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inline constexpr uint32_t elementType() const noexcept { return _signature.getField<kSignatureRegElementTypeMask>(); }
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//! Sets element type of the register to `elementType`.
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inline void setElementType(uint32_t elementType) noexcept { _signature.setField<kSignatureRegElementTypeMask>(elementType); }
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//! Resets element type to none.
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inline void resetElementType() noexcept { _signature.setField<kSignatureRegElementTypeMask>(0); }
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//! Returns element index of the register.
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inline constexpr uint32_t elementIndex() const noexcept { return _signature.getField<kSignatureRegElementIndexMask>(); }
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//! Sets element index of the register to `elementType`.
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inline void setElementIndex(uint32_t elementIndex) noexcept {
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_signature |= kSignatureRegElementFlagMask;
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_signature.setField<kSignatureRegElementIndexMask>(elementIndex);
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}
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//! Resets element index of the register.
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inline void resetElementIndex() noexcept {
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_signature &= ~(kSignatureRegElementFlagMask | kSignatureRegElementIndexMask);
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}
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inline constexpr bool isVecB8() const noexcept { return _signature.subset(kBaseSignatureMask | kSignatureRegElementTypeMask) == (RegTraits<RegType::kARM_VecD>::kSignature | kSignatureElementB); }
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inline constexpr bool isVecH4() const noexcept { return _signature.subset(kBaseSignatureMask | kSignatureRegElementTypeMask) == (RegTraits<RegType::kARM_VecD>::kSignature | kSignatureElementH); }
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inline constexpr bool isVecS2() const noexcept { return _signature.subset(kBaseSignatureMask | kSignatureRegElementTypeMask) == (RegTraits<RegType::kARM_VecD>::kSignature | kSignatureElementS); }
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inline constexpr bool isVecD1() const noexcept { return _signature.subset(kBaseSignatureMask | kSignatureRegElementTypeMask) == (RegTraits<RegType::kARM_VecD>::kSignature); }
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inline constexpr bool isVecB16() const noexcept { return _signature.subset(kBaseSignatureMask | kSignatureRegElementTypeMask) == (RegTraits<RegType::kARM_VecV>::kSignature | kSignatureElementB); }
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inline constexpr bool isVecH8() const noexcept { return _signature.subset(kBaseSignatureMask | kSignatureRegElementTypeMask) == (RegTraits<RegType::kARM_VecV>::kSignature | kSignatureElementH); }
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inline constexpr bool isVecS4() const noexcept { return _signature.subset(kBaseSignatureMask | kSignatureRegElementTypeMask) == (RegTraits<RegType::kARM_VecV>::kSignature | kSignatureElementS); }
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inline constexpr bool isVecD2() const noexcept { return _signature.subset(kBaseSignatureMask | kSignatureRegElementTypeMask) == (RegTraits<RegType::kARM_VecV>::kSignature | kSignatureElementD); }
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inline constexpr bool isVecB4x4() const noexcept { return _signature.subset(kBaseSignatureMask | kSignatureRegElementTypeMask) == (RegTraits<RegType::kARM_VecV>::kSignature | kSignatureElementB4); }
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inline constexpr bool isVecH2x4() const noexcept { return _signature.subset(kBaseSignatureMask | kSignatureRegElementTypeMask) == (RegTraits<RegType::kARM_VecV>::kSignature | kSignatureElementH2); }
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//! Creates a cloned register with element access.
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inline Vec at(uint32_t elementIndex) const noexcept {
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return Vec((signature() & ~kSignatureRegElementIndexMask) | (elementIndex << kSignatureRegElementIndexShift) | kSignatureRegElementFlagMask, id());
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}
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//! Cast this register to an 8-bit B register (scalar).
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inline VecB b() const noexcept;
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//! Cast this register to a 16-bit H register (scalar).
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inline VecH h() const noexcept;
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//! Cast this register to a 32-bit S register (scalar).
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inline VecS s() const noexcept;
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//! Cast this register to a 64-bit D register (scalar).
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inline VecD d() const noexcept;
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//! Cast this register to a 128-bit Q register (scalar).
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inline VecV q() const noexcept;
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//! Cast this register to a 128-bit V register.
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inline VecV v() const noexcept;
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//! Cast this register to a 128-bit V.B[elementIndex] register.
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inline VecV b(uint32_t elementIndex) const noexcept;
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//! Cast this register to a 128-bit V.H[elementIndex] register.
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inline VecV h(uint32_t elementIndex) const noexcept;
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//! Cast this register to a 128-bit V.S[elementIndex] register.
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inline VecV s(uint32_t elementIndex) const noexcept;
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//! Cast this register to a 128-bit V.D[elementIndex] register.
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inline VecV d(uint32_t elementIndex) const noexcept;
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//! Cast this register to a 128-bit V.H2[elementIndex] register.
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inline VecV h2(uint32_t elementIndex) const noexcept;
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//! Cast this register to a 128-bit V.B4[elementIndex] register.
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inline VecV b4(uint32_t elementIndex) const noexcept;
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//! Cast this register to V.8B.
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inline VecD b8() const noexcept;
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//! Cast this register to V.16B.
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inline VecV b16() const noexcept;
|
||
|
|
//! Cast this register to V.2H.
|
||
|
|
inline VecS h2() const noexcept;
|
||
|
|
//! Cast this register to V.4H.
|
||
|
|
inline VecD h4() const noexcept;
|
||
|
|
//! Cast this register to V.8H.
|
||
|
|
inline VecV h8() const noexcept;
|
||
|
|
//! Cast this register to V.2S.
|
||
|
|
inline VecD s2() const noexcept;
|
||
|
|
//! Cast this register to V.4S.
|
||
|
|
inline VecV s4() const noexcept;
|
||
|
|
//! Cast this register to V.2D.
|
||
|
|
inline VecV d2() const noexcept;
|
||
|
|
|
||
|
|
static inline constexpr OperandSignature _makeElementAccessSignature(uint32_t elementType, uint32_t elementIndex) noexcept {
|
||
|
|
return OperandSignature{
|
||
|
|
uint32_t(RegTraits<RegType::kARM_VecV>::kSignature) |
|
||
|
|
uint32_t(kSignatureRegElementFlagMask) |
|
||
|
|
uint32_t(elementType << kSignatureRegElementTypeShift) |
|
||
|
|
uint32_t(elementIndex << kSignatureRegElementIndexShift)};
|
||
|
|
}
|
||
|
|
};
|
||
|
|
|
||
|
|
//! 32-bit GPW (AArch64) and/or GPR (ARM/AArch32) register.
|
||
|
|
class GpW : public Gp { ASMJIT_DEFINE_FINAL_REG(GpW, Gp, RegTraits<RegType::kARM_GpW>) };
|
||
|
|
//! 64-bit GPX (AArch64) register.
|
||
|
|
class GpX : public Gp { ASMJIT_DEFINE_FINAL_REG(GpX, Gp, RegTraits<RegType::kARM_GpX>) };
|
||
|
|
|
||
|
|
//! 8-bit view (S) of VFP/SIMD register.
|
||
|
|
class VecB : public Vec { ASMJIT_DEFINE_FINAL_REG(VecB, Vec, RegTraits<RegType::kARM_VecB>) };
|
||
|
|
//! 16-bit view (S) of VFP/SIMD register.
|
||
|
|
class VecH : public Vec { ASMJIT_DEFINE_FINAL_REG(VecH, Vec, RegTraits<RegType::kARM_VecH>) };
|
||
|
|
//! 32-bit view (S) of VFP/SIMD register.
|
||
|
|
class VecS : public Vec { ASMJIT_DEFINE_FINAL_REG(VecS, Vec, RegTraits<RegType::kARM_VecS>) };
|
||
|
|
//! 64-bit view (D) of VFP/SIMD register.
|
||
|
|
class VecD : public Vec { ASMJIT_DEFINE_FINAL_REG(VecD, Vec, RegTraits<RegType::kARM_VecD>) };
|
||
|
|
//! 128-bit vector register (Q or V).
|
||
|
|
class VecV : public Vec { ASMJIT_DEFINE_FINAL_REG(VecV, Vec, RegTraits<RegType::kARM_VecV>) };
|
||
|
|
|
||
|
|
inline GpW Gp::w() const noexcept { return GpW(id()); }
|
||
|
|
inline GpX Gp::x() const noexcept { return GpX(id()); }
|
||
|
|
|
||
|
|
inline VecB Vec::b() const noexcept { return VecB(id()); }
|
||
|
|
inline VecH Vec::h() const noexcept { return VecH(id()); }
|
||
|
|
inline VecS Vec::s() const noexcept { return VecS(id()); }
|
||
|
|
inline VecD Vec::d() const noexcept { return VecD(id()); }
|
||
|
|
inline VecV Vec::q() const noexcept { return VecV(id()); }
|
||
|
|
inline VecV Vec::v() const noexcept { return VecV(id()); }
|
||
|
|
|
||
|
|
inline VecV Vec::b(uint32_t elementIndex) const noexcept { return VecV(_makeElementAccessSignature(kElementTypeB, elementIndex), id()); }
|
||
|
|
inline VecV Vec::h(uint32_t elementIndex) const noexcept { return VecV(_makeElementAccessSignature(kElementTypeH, elementIndex), id()); }
|
||
|
|
inline VecV Vec::s(uint32_t elementIndex) const noexcept { return VecV(_makeElementAccessSignature(kElementTypeS, elementIndex), id()); }
|
||
|
|
inline VecV Vec::d(uint32_t elementIndex) const noexcept { return VecV(_makeElementAccessSignature(kElementTypeD, elementIndex), id()); }
|
||
|
|
inline VecV Vec::h2(uint32_t elementIndex) const noexcept { return VecV(_makeElementAccessSignature(kElementTypeH2, elementIndex), id()); }
|
||
|
|
inline VecV Vec::b4(uint32_t elementIndex) const noexcept { return VecV(_makeElementAccessSignature(kElementTypeB4, elementIndex), id()); }
|
||
|
|
|
||
|
|
inline VecD Vec::b8() const noexcept { return VecD(OperandSignature{VecD::kSignature | kSignatureElementB}, id()); }
|
||
|
|
inline VecS Vec::h2() const noexcept { return VecS(OperandSignature{VecS::kSignature | kSignatureElementH}, id()); }
|
||
|
|
inline VecD Vec::h4() const noexcept { return VecD(OperandSignature{VecD::kSignature | kSignatureElementH}, id()); }
|
||
|
|
inline VecD Vec::s2() const noexcept { return VecD(OperandSignature{VecD::kSignature | kSignatureElementS}, id()); }
|
||
|
|
inline VecV Vec::b16() const noexcept { return VecV(OperandSignature{VecV::kSignature | kSignatureElementB}, id()); }
|
||
|
|
inline VecV Vec::h8() const noexcept { return VecV(OperandSignature{VecV::kSignature | kSignatureElementH}, id()); }
|
||
|
|
inline VecV Vec::s4() const noexcept { return VecV(OperandSignature{VecV::kSignature | kSignatureElementS}, id()); }
|
||
|
|
inline VecV Vec::d2() const noexcept { return VecV(OperandSignature{VecV::kSignature | kSignatureElementD}, id()); }
|
||
|
|
|
||
|
|
#ifndef _DOXYGEN
|
||
|
|
namespace regs {
|
||
|
|
#endif
|
||
|
|
|
||
|
|
//! Creates a 32-bit W register operand (ARM/AArch64).
|
||
|
|
static inline constexpr GpW w(uint32_t id) noexcept { return GpW(id); }
|
||
|
|
//! Creates a 64-bit X register operand (AArch64).
|
||
|
|
static inline constexpr GpX x(uint32_t id) noexcept { return GpX(id); }
|
||
|
|
//! Creates a 32-bit S register operand (ARM/AArch64).
|
||
|
|
static inline constexpr VecS s(uint32_t id) noexcept { return VecS(id); }
|
||
|
|
//! Creates a 64-bit D register operand (ARM/AArch64).
|
||
|
|
static inline constexpr VecD d(uint32_t id) noexcept { return VecD(id); }
|
||
|
|
//! Creates a 1282-bit V register operand (ARM/AArch64).
|
||
|
|
static inline constexpr VecV v(uint32_t id) noexcept { return VecV(id); }
|
||
|
|
|
||
|
|
#ifndef _DOXYGEN
|
||
|
|
} // {regs}
|
||
|
|
|
||
|
|
// Make `arm::regs` accessible through `arm` namespace as well.
|
||
|
|
using namespace regs;
|
||
|
|
#endif
|
||
|
|
|
||
|
|
//! Memory operand (ARM).
|
||
|
|
class Mem : public BaseMem {
|
||
|
|
public:
|
||
|
|
//! \cond INTERNAL
|
||
|
|
//! Additional bits of operand's signature used by `arm::Mem`.
|
||
|
|
enum AdditionalBits : uint32_t {
|
||
|
|
// Index shift value (5 bits).
|
||
|
|
// |........|.....XXX|XX......|........|
|
||
|
|
kSignatureMemShiftValueShift = 14,
|
||
|
|
kSignatureMemShiftValueMask = 0x1Fu << kSignatureMemShiftValueShift,
|
||
|
|
|
||
|
|
// Shift operation type (4 bits).
|
||
|
|
// |........|XXXX....|........|........|
|
||
|
|
kSignatureMemPredicateShift = 20,
|
||
|
|
kSignatureMemPredicateMask = 0x0Fu << kSignatureMemPredicateShift
|
||
|
|
};
|
||
|
|
//! \endcond
|
||
|
|
|
||
|
|
//! Memory offset mode.
|
||
|
|
//!
|
||
|
|
//! Additional constants that can be used with the `predicate`.
|
||
|
|
enum OffsetMode : uint32_t {
|
||
|
|
//! Pre-index "[BASE, #Offset {, <shift>}]!" with write-back.
|
||
|
|
kOffsetPreIndex = 0xE,
|
||
|
|
//! Post-index "[BASE], #Offset {, <shift>}" with write-back.
|
||
|
|
kOffsetPostIndex = 0xF
|
||
|
|
};
|
||
|
|
|
||
|
|
//! \name Construction & Destruction
|
||
|
|
//! \{
|
||
|
|
|
||
|
|
//! Construct a default `Mem` operand, that points to [0].
|
||
|
|
inline constexpr Mem() noexcept
|
||
|
|
: BaseMem() {}
|
||
|
|
|
||
|
|
inline constexpr Mem(const Mem& other) noexcept
|
||
|
|
: BaseMem(other) {}
|
||
|
|
|
||
|
|
inline explicit Mem(Globals::NoInit_) noexcept
|
||
|
|
: BaseMem(Globals::NoInit) {}
|
||
|
|
|
||
|
|
inline constexpr Mem(const Signature& signature, uint32_t baseId, uint32_t indexId, int32_t offset) noexcept
|
||
|
|
: BaseMem(signature, baseId, indexId, offset) {}
|
||
|
|
|
||
|
|
inline constexpr explicit Mem(const Label& base, int32_t off = 0, Signature signature = Signature{0}) noexcept
|
||
|
|
: BaseMem(Signature::fromOpType(OperandType::kMem) |
|
||
|
|
Signature::fromMemBaseType(RegType::kLabelTag) |
|
||
|
|
signature, base.id(), 0, off) {}
|
||
|
|
|
||
|
|
inline constexpr explicit Mem(const BaseReg& base, int32_t off = 0, Signature signature = Signature{0}) noexcept
|
||
|
|
: BaseMem(Signature::fromOpType(OperandType::kMem) |
|
||
|
|
Signature::fromMemBaseType(base.type()) |
|
||
|
|
signature, base.id(), 0, off) {}
|
||
|
|
|
||
|
|
inline constexpr Mem(const BaseReg& base, const BaseReg& index, Signature signature = Signature{0}) noexcept
|
||
|
|
: BaseMem(Signature::fromOpType(OperandType::kMem) |
|
||
|
|
Signature::fromMemBaseType(base.type()) |
|
||
|
|
Signature::fromMemIndexType(index.type()) |
|
||
|
|
signature, base.id(), index.id(), 0) {}
|
||
|
|
|
||
|
|
inline constexpr Mem(const BaseReg& base, const BaseReg& index, const Shift& shift, Signature signature = Signature{0}) noexcept
|
||
|
|
: BaseMem(Signature::fromOpType(OperandType::kMem) |
|
||
|
|
Signature::fromMemBaseType(base.type()) |
|
||
|
|
Signature::fromMemIndexType(index.type()) |
|
||
|
|
Signature::fromValue<kSignatureMemPredicateMask>(uint32_t(shift.op())) |
|
||
|
|
Signature::fromValue<kSignatureMemShiftValueMask>(shift.value()) |
|
||
|
|
signature, base.id(), index.id(), 0) {}
|
||
|
|
|
||
|
|
inline constexpr Mem(uint64_t base, Signature signature = Signature{0}) noexcept
|
||
|
|
: BaseMem(Signature::fromOpType(OperandType::kMem) |
|
||
|
|
signature, uint32_t(base >> 32), 0, int32_t(uint32_t(base & 0xFFFFFFFFu))) {}
|
||
|
|
|
||
|
|
//! \}
|
||
|
|
|
||
|
|
//! \name Overloaded Operators
|
||
|
|
//! \{
|
||
|
|
|
||
|
|
inline Mem& operator=(const Mem& other) noexcept = default;
|
||
|
|
|
||
|
|
//! \}
|
||
|
|
|
||
|
|
//! \name Clone
|
||
|
|
//! \{
|
||
|
|
|
||
|
|
//! Clones the memory operand.
|
||
|
|
inline constexpr Mem clone() const noexcept { return Mem(*this); }
|
||
|
|
|
||
|
|
//! Gets new memory operand adjusted by `off`.
|
||
|
|
inline Mem cloneAdjusted(int64_t off) const noexcept {
|
||
|
|
Mem result(*this);
|
||
|
|
result.addOffset(off);
|
||
|
|
return result;
|
||
|
|
}
|
||
|
|
|
||
|
|
//! Clones the memory operand and makes it pre-index.
|
||
|
|
inline Mem pre() const noexcept {
|
||
|
|
Mem result(*this);
|
||
|
|
result.setPredicate(kOffsetPreIndex);
|
||
|
|
return result;
|
||
|
|
}
|
||
|
|
|
||
|
|
//! Clones the memory operand, applies a given offset `off` and makes it pre-index.
|
||
|
|
inline Mem pre(int64_t off) const noexcept {
|
||
|
|
Mem result(*this);
|
||
|
|
result.setPredicate(kOffsetPreIndex);
|
||
|
|
result.addOffset(off);
|
||
|
|
return result;
|
||
|
|
}
|
||
|
|
|
||
|
|
//! Clones the memory operand and makes it post-index.
|
||
|
|
inline Mem post() const noexcept {
|
||
|
|
Mem result(*this);
|
||
|
|
result.setPredicate(kOffsetPostIndex);
|
||
|
|
return result;
|
||
|
|
}
|
||
|
|
|
||
|
|
//! Clones the memory operand, applies a given offset `off` and makes it post-index.
|
||
|
|
inline Mem post(int64_t off) const noexcept {
|
||
|
|
Mem result(*this);
|
||
|
|
result.setPredicate(kOffsetPostIndex);
|
||
|
|
result.addOffset(off);
|
||
|
|
return result;
|
||
|
|
}
|
||
|
|
|
||
|
|
//! \}
|
||
|
|
|
||
|
|
//! \name Base & Index
|
||
|
|
//! \{
|
||
|
|
|
||
|
|
//! Converts memory `baseType` and `baseId` to `arm::Reg` instance.
|
||
|
|
//!
|
||
|
|
//! The memory must have a valid base register otherwise the result will be wrong.
|
||
|
|
inline Reg baseReg() const noexcept { return Reg::fromTypeAndId(baseType(), baseId()); }
|
||
|
|
|
||
|
|
//! Converts memory `indexType` and `indexId` to `arm::Reg` instance.
|
||
|
|
//!
|
||
|
|
//! The memory must have a valid index register otherwise the result will be wrong.
|
||
|
|
inline Reg indexReg() const noexcept { return Reg::fromTypeAndId(indexType(), indexId()); }
|
||
|
|
|
||
|
|
using BaseMem::setIndex;
|
||
|
|
|
||
|
|
inline void setIndex(const BaseReg& index, uint32_t shift) noexcept {
|
||
|
|
setIndex(index);
|
||
|
|
setShift(shift);
|
||
|
|
}
|
||
|
|
|
||
|
|
//! \}
|
||
|
|
|
||
|
|
//! \name ARM Specific Features
|
||
|
|
//! \{
|
||
|
|
|
||
|
|
//! Gets whether the memory operand has shift (aka scale) constant.
|
||
|
|
inline constexpr bool hasShift() const noexcept { return _signature.hasField<kSignatureMemShiftValueMask>(); }
|
||
|
|
//! Gets the memory operand's shift (aka scale) constant.
|
||
|
|
inline constexpr uint32_t shift() const noexcept { return _signature.getField<kSignatureMemShiftValueMask>(); }
|
||
|
|
//! Sets the memory operand's shift (aka scale) constant.
|
||
|
|
inline void setShift(uint32_t shift) noexcept { _signature.setField<kSignatureMemShiftValueMask>(shift); }
|
||
|
|
//! Resets the memory operand's shift (aka scale) constant to zero.
|
||
|
|
inline void resetShift() noexcept { _signature.setField<kSignatureMemShiftValueMask>(0); }
|
||
|
|
|
||
|
|
//! Gets memory predicate (shift mode or offset mode), see \ref ShiftOp and \ref OffsetMode.
|
||
|
|
inline constexpr uint32_t predicate() const noexcept { return _signature.getField<kSignatureMemPredicateMask>(); }
|
||
|
|
//! Sets memory predicate to `predicate`, see `Mem::ShiftOp`.
|
||
|
|
inline void setPredicate(uint32_t predicate) noexcept { _signature.setField<kSignatureMemPredicateMask>(predicate); }
|
||
|
|
//! Resets shift mode to LSL (default).
|
||
|
|
inline void resetPredicate() noexcept { _signature.setField<kSignatureMemPredicateMask>(0); }
|
||
|
|
|
||
|
|
inline constexpr bool isFixedOffset() const noexcept { return predicate() < kOffsetPreIndex; }
|
||
|
|
inline constexpr bool isPreOrPost() const noexcept { return predicate() >= kOffsetPreIndex; }
|
||
|
|
inline constexpr bool isPreIndex() const noexcept { return predicate() == kOffsetPreIndex; }
|
||
|
|
inline constexpr bool isPostIndex() const noexcept { return predicate() == kOffsetPostIndex; }
|
||
|
|
|
||
|
|
inline void resetToFixedOffset() noexcept { resetPredicate(); }
|
||
|
|
inline void makePreIndex() noexcept { setPredicate(kOffsetPreIndex); }
|
||
|
|
inline void makePostIndex() noexcept { setPredicate(kOffsetPostIndex); }
|
||
|
|
|
||
|
|
//! \}
|
||
|
|
};
|
||
|
|
|
||
|
|
//! Creates `[base.reg, offset]` memory operand (offset mode).
|
||
|
|
static inline constexpr Mem ptr(const Gp& base, int32_t offset = 0) noexcept {
|
||
|
|
return Mem(base, offset);
|
||
|
|
}
|
||
|
|
|
||
|
|
//! Creates `[base.reg, offset]!` memory operand (pre-index mode).
|
||
|
|
static inline constexpr Mem ptr_pre(const Gp& base, int32_t offset = 0) noexcept {
|
||
|
|
return Mem(base, offset, OperandSignature::fromValue<Mem::kSignatureMemPredicateMask>(Mem::kOffsetPreIndex));
|
||
|
|
}
|
||
|
|
|
||
|
|
//! Creates `[base.reg], offset` memory operand (post-index mode).
|
||
|
|
static inline constexpr Mem ptr_post(const Gp& base, int32_t offset = 0) noexcept {
|
||
|
|
return Mem(base, offset, OperandSignature::fromValue<Mem::kSignatureMemPredicateMask>(Mem::kOffsetPostIndex));
|
||
|
|
}
|
||
|
|
|
||
|
|
//! Creates `[base.reg, index]` memory operand.
|
||
|
|
static inline constexpr Mem ptr(const Gp& base, const Gp& index) noexcept {
|
||
|
|
return Mem(base, index);
|
||
|
|
}
|
||
|
|
|
||
|
|
//! Creates `[base.reg], index` memory operand (post-index mode).
|
||
|
|
static inline constexpr Mem ptr_post(const Gp& base, const Gp& index) noexcept {
|
||
|
|
return Mem(base, index, OperandSignature::fromValue<Mem::kSignatureMemPredicateMask>(Mem::kOffsetPostIndex));
|
||
|
|
}
|
||
|
|
|
||
|
|
//! Creates `[base.reg, index, SHIFT_OP #shift]` memory operand.
|
||
|
|
static inline constexpr Mem ptr(const Gp& base, const Gp& index, const Shift& shift) noexcept {
|
||
|
|
return Mem(base, index, shift);
|
||
|
|
}
|
||
|
|
|
||
|
|
//! Creates `[base + offset]` memory operand.
|
||
|
|
static inline constexpr Mem ptr(const Label& base, int32_t offset = 0) noexcept {
|
||
|
|
return Mem(base, offset);
|
||
|
|
}
|
||
|
|
|
||
|
|
// TODO: [ARM] PC + offset address.
|
||
|
|
#if 0
|
||
|
|
//! Creates `[PC + offset]` (relative) memory operand.
|
||
|
|
static inline constexpr Mem ptr(const PC& pc, int32_t offset = 0) noexcept {
|
||
|
|
return Mem(pc, offset);
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
//! Creates `[base]` absolute memory operand.
|
||
|
|
//!
|
||
|
|
//! \note The concept of absolute memory operands doesn't exist on ARM, the ISA only provides PC relative addressing.
|
||
|
|
//! Absolute memory operands can only be used if it's known that the PC relative offset is encodable and that it
|
||
|
|
//! would be within the limits. Absolute address is also often output from disassemblers, so AsmJit support it so it
|
||
|
|
//! can assemble it back.
|
||
|
|
static inline constexpr Mem ptr(uint64_t base) noexcept { return Mem(base); }
|
||
|
|
|
||
|
|
//! \}
|
||
|
|
|
||
|
|
ASMJIT_END_SUB_NAMESPACE
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||
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//! \cond INTERNAL
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ASMJIT_BEGIN_NAMESPACE
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||
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ASMJIT_DEFINE_TYPE_ID(arm::GpW, TypeId::kInt32);
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||
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ASMJIT_DEFINE_TYPE_ID(arm::GpX, TypeId::kInt64);
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||
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ASMJIT_DEFINE_TYPE_ID(arm::VecS, TypeId::kFloat32x1);
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ASMJIT_DEFINE_TYPE_ID(arm::VecD, TypeId::kFloat64x1);
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ASMJIT_DEFINE_TYPE_ID(arm::VecV, TypeId::kInt32x4);
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||
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ASMJIT_END_NAMESPACE
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||
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//! \endcond
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#endif // ASMJIT_ARM_ARMOPERAND_H_INCLUDED
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